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* [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+
@ 2020-05-13  9:38 Stanislav Lisovskiy
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
                   ` (8 more replies)
  0 siblings, 9 replies; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

v25: Rebased patch series as part was merged already
v26: Had to resend the whole series as one more mid patch was added
v27: Patches 2,3,7 were pushed, have to resend the series to prevent
     build failure.
v28: PCode patch was merged, one patch was added, sent new series.

Stanislav Lisovskiy (6):
  drm/i915: Introduce skl_plane_wm_level accessor.
  drm/i915: Extract skl SAGV checking
  drm/i915: Make active_pipes check skl specific
  drm/i915: Add TGL+ SAGV support
  drm/i915: Restrict qgv points which don't have enough bandwidth.
  drm/i915: Enable SAGV support for Gen12

 drivers/gpu/drm/i915/display/intel_bw.c       | 137 +++++++++---
 drivers/gpu/drm/i915/display/intel_bw.h       |   9 +
 drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
 .../drm/i915/display/intel_display_types.h    |   5 +
 drivers/gpu/drm/i915/intel_pm.c               | 202 +++++++++++++++---
 drivers/gpu/drm/i915/intel_pm.h               |   5 +-
 6 files changed, 302 insertions(+), 64 deletions(-)

-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v29 1/6] drm/i915: Introduce skl_plane_wm_level accessor.
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
@ 2020-05-13  9:38 ` Stanislav Lisovskiy
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 2/6] drm/i915: Extract skl SAGV checking Stanislav Lisovskiy
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.

So this accessor will give additional flexibility
to do that.

Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.

v2: - plane_id -> plane->id(Ville Syrjälä)
    - Moved wm_level var to have more local scope
      (Ville Syrjälä)
    - Renamed yuv to color_plane(Ville Syrjälä) in
      skl_plane_wm_level

v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
    - Changed colorplane id type from boolean to int as index
      (Ville Syrjälä)
    - Moved crtc_state param so that it is first now
      (Ville Syrjälä)
    - Moved wm_level declaration to tigher scope in
      skl_write_plane_wm(Ville Syrjälä)

v4: - Started to use enum values for color plane
    - Do sizeof for a type what we are memset'ing
    - Zero out wm_uv as well(Ville Syrjälä)

v5: - Fixed rebase conflict caused by COLOR_PLANE_*
      enum removal

v6: - Do not use skl_plane_wm_level accessor in skl_allocate_pipe_ddb

v7: - Get rid of wm_uv, which is not used in skl_plane_write_wm(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 416cb1a1e7cb..9be2d1bea4c3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4632,6 +4632,17 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	return total_data_rate;
 }
 
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+		   enum plane_id plane_id,
+		   int level)
+{
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+
+	return &wm->wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
@@ -5439,8 +5450,12 @@ void skl_write_plane_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
+		const struct skl_wm_level *wm_level;
+
+		wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
+
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
@@ -5473,8 +5488,12 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 
 	for (level = 0; level <= max_level; level++) {
+		const struct skl_wm_level *wm_level;
+
+		wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
+
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v29 2/6] drm/i915: Extract skl SAGV checking
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-05-13  9:38 ` Stanislav Lisovskiy
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 3/6] drm/i915: Make active_pipes check skl specific Stanislav Lisovskiy
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.

This is preparation to adding TGL support, which
requires different way of SAGV checking.

v2, v3, v4, v5, v6: Fix rebase conflict

v7: - Nuke icl specific function, use skl
      for icl as well, gen specific active_pipes
      check to be added in the next patch(Ville)

v8: - Use more generic intel_crtc_can_enable_sagv
      for checking(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9be2d1bea4c3..6a212d47aec8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3804,7 +3804,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 		intel_enable_sagv(dev_priv);
 }
 
-static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -3853,6 +3853,11 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
 	return true;
 }
 
+static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+	return skl_crtc_can_enable_sagv(crtc_state);
+}
+
 bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
 {
 	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
@@ -3865,7 +3870,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 {
 	int ret;
 	struct intel_crtc *crtc;
-	struct intel_crtc_state *new_crtc_state;
+	const struct intel_crtc_state *new_crtc_state;
 	struct intel_bw_state *new_bw_state = NULL;
 	const struct intel_bw_state *old_bw_state = NULL;
 	int i;
@@ -3889,6 +3894,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 
 	new_bw_state->active_pipes =
 		intel_calc_active_pipes(state, old_bw_state->active_pipes);
+
 	if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
 		ret = intel_atomic_lock_global_state(&new_bw_state->base);
 		if (ret)
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v29 3/6] drm/i915: Make active_pipes check skl specific
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 2/6] drm/i915: Extract skl SAGV checking Stanislav Lisovskiy
@ 2020-05-13  9:38 ` Stanislav Lisovskiy
  2020-05-13 13:34   ` Ville Syrjälä
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 4/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

Seems that only skl needs to have SAGV turned off
for multipipe scenarios, so lets do it this way.

If anything blows up - we can always revert this patch.

v2: Changed if condition to look better (Ville).

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++-----
 drivers/gpu/drm/i915/intel_pm.h |  3 ++-
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6a212d47aec8..de0f8cede59c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3777,7 +3777,7 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (!intel_can_enable_sagv(new_bw_state))
+	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
 		intel_disable_sagv(dev_priv);
 }
 
@@ -3800,7 +3800,7 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (intel_can_enable_sagv(new_bw_state))
+	if (intel_can_enable_sagv(dev_priv, new_bw_state))
 		intel_enable_sagv(dev_priv);
 }
 
@@ -3858,9 +3858,11 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
 	return skl_crtc_can_enable_sagv(crtc_state);
 }
 
-bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
+			   const struct intel_bw_state *bw_state)
 {
-	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
+	if (INTEL_GEN(dev_priv) < 11 &&
+	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
 		return false;
 
 	return bw_state->pipe_sagv_reject == 0;
@@ -3868,6 +3870,7 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
 
 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 {
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int ret;
 	struct intel_crtc *crtc;
 	const struct intel_crtc_state *new_crtc_state;
@@ -3901,7 +3904,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 			return ret;
 	}
 
-	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
+	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
 		if (ret)
 			return ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index fd1dc422e6c5..614ac7f8d4cc 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			      struct skl_pipe_wm *out);
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
+bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
+			   const struct intel_bw_state *bw_state);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v29 4/6] drm/i915: Add TGL+ SAGV support
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
                   ` (2 preceding siblings ...)
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 3/6] drm/i915: Make active_pipes check skl specific Stanislav Lisovskiy
@ 2020-05-13  9:38 ` Stanislav Lisovskiy
  2020-05-13 13:41   ` Ville Syrjälä
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.

v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5, v6: Fixed rebase conflict
v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
    - Removed sagv_uv_wm0(Ville)
    - can_sagv->use_sagv_wm(Ville)

v8: - Moved tgl_crtc_can_enable_sagv function up(Ville)
    - Changed comment regarding pipe_wm usage(Ville)
    - Call intel_can_enable_sagv and tgl_compute_sagv_wm only
      for Gen12(Ville)
    - Some sagv debugs removed(Ville)
    - skl_print_wm_changes improvements(Ville)
    - Do assignment instead of memcpy in
      skl_pipe_wm_get_hw_state(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/intel_pm.c               | 112 +++++++++++++++---
 3 files changed, 103 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fd6d63b03489..be5741cb7595 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+							       &sw_plane_wm->sagv_wm0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
@@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+							       &sw_plane_wm->sagv_wm0)))
 				continue;
 
 			drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9488449e4b94..8cede29c9562 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,13 @@ struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
+	struct skl_wm_level sagv_wm0;
 	bool is_planar;
 };
 
 struct skl_pipe_wm {
 	struct skl_plane_wm planes[I915_MAX_PLANES];
+	bool use_sagv_wm;
 };
 
 enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de0f8cede59c..1f253db3b7c0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3853,9 +3853,39 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
+static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum plane_id plane_id;
+
+	if (!crtc_state->hw.active)
+		return true;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		const struct skl_ddb_entry *plane_alloc =
+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
+		const struct skl_plane_wm *wm =
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+
+		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+			return false;
+	}
+
+	return true;
+}
+
 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
-	return skl_crtc_can_enable_sagv(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	bool can_sagv;
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		can_sagv = tgl_crtc_can_enable_sagv(crtc_state);
+	else
+		can_sagv = skl_crtc_can_enable_sagv(crtc_state);
+
+	return can_sagv;
 }
 
 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
@@ -3873,7 +3903,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int ret;
 	struct intel_crtc *crtc;
-	const struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc_state *new_crtc_state;
 	struct intel_bw_state *new_bw_state = NULL;
 	const struct intel_bw_state *old_bw_state = NULL;
 	int i;
@@ -3904,6 +3934,20 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 			return ret;
 	}
 
+	for_each_new_intel_crtc_in_state(state, crtc,
+					 new_crtc_state, i) {
+		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+		/*
+		 * We store use_sagv_wm in the crtc state rather than relying on
+		 * that bw state since we have no convenient way to get at the
+		 * latter from the plane commit hooks (especially in the legacy
+		 * cursor case)
+		 */
+		pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
+				       intel_can_enable_sagv(dev_priv, new_bw_state);
+	}
+
 	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
 		if (ret)
@@ -4646,8 +4690,11 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
 		   enum plane_id plane_id,
 		   int level)
 {
-	const struct skl_plane_wm *wm =
-		&crtc_state->wm.skl.optimal.planes[plane_id];
+	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+	if (level == 0 && pipe_wm->use_sagv_wm)
+		return &wm->sagv_wm0;
 
 	return &wm->wm[level];
 }
@@ -4688,7 +4735,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 							 plane_data_rate,
 							 uv_plane_data_rate);
 
-
 	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
 					   alloc, &num_active);
 	alloc_size = skl_ddb_entry_size(alloc);
@@ -5223,6 +5269,22 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 	}
 }
 
+static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+				const struct skl_wm_params *wm_params,
+				struct skl_plane_wm *plane_wm)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
+	struct skl_wm_level *levels = plane_wm->wm;
+
+	u32 latency = dev_priv->wm.skl_latency[0];
+
+	latency += dev_priv->sagv_block_time_us;
+	skl_compute_plane_wm(crtc_state, 0, latency,
+			     wm_params, &levels[0],
+			     sagv_wm);
+}
+
 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
 				      const struct skl_wm_params *wp,
 				      struct skl_plane_wm *wm)
@@ -5290,6 +5352,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 				     const struct intel_plane_state *plane_state,
 				     enum plane_id plane_id, int color_plane)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
 	struct skl_wm_params wm_params;
 	int ret;
@@ -5300,6 +5364,10 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 		return ret;
 
 	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
+
 	skl_compute_transition_wm(crtc_state, &wm_params, wm);
 
 	return 0;
@@ -5666,23 +5734,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				continue;
 
 			drm_dbg_kms(&dev_priv->drm,
-				    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
-				    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
+				    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm"
+				    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm\n",
 				    plane->base.base.id, plane->base.name,
 				    enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
 				    enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
 				    enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
 				    enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
 				    enast(old_wm->trans_wm.plane_en),
+				    enast(old_wm->sagv_wm0.plane_en),
 				    enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
 				    enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
 				    enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
 				    enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
-				    enast(new_wm->trans_wm.plane_en));
+				    enast(new_wm->trans_wm.plane_en),
+				    enast(new_wm->sagv_wm0.plane_en));
 
 			drm_dbg_kms(&dev_priv->drm,
-				    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
-				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
+				    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
+				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
 				    plane->base.base.id, plane->base.name,
 				    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
 				    enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
@@ -5693,6 +5763,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
 				    enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
 				    enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
+				    enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,
 
 				    enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
 				    enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
@@ -5702,37 +5773,42 @@ skl_print_wm_changes(struct intel_atomic_state *state)
 				    enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
 				    enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
 				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
-				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
+				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
+				    enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);
 
 			drm_dbg_kms(&dev_priv->drm,
-				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
-				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
+				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
+				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
 				    plane->base.base.id, plane->base.name,
 				    old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
 				    old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
 				    old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
 				    old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
 				    old_wm->trans_wm.plane_res_b,
+				    old_wm->sagv_wm0.plane_res_b,
 				    new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
 				    new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
 				    new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
 				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
-				    new_wm->trans_wm.plane_res_b);
+				    new_wm->trans_wm.plane_res_b,
+				    new_wm->sagv_wm0.plane_res_b);
 
 			drm_dbg_kms(&dev_priv->drm,
-				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
-				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
+				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
+				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
 				    plane->base.base.id, plane->base.name,
 				    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
 				    old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
 				    old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
 				    old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
 				    old_wm->trans_wm.min_ddb_alloc,
+				    old_wm->sagv_wm0.min_ddb_alloc,
 				    new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
 				    new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
 				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
 				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
-				    new_wm->trans_wm.min_ddb_alloc);
+				    new_wm->trans_wm.min_ddb_alloc,
+				    new_wm->sagv_wm0.min_ddb_alloc);
 		}
 	}
 }
@@ -6025,6 +6101,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
 		}
 
+		wm->sagv_wm0 = wm->wm[0];
+
 		if (plane_id != PLANE_CURSOR)
 			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
 		else
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v29 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth.
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
                   ` (3 preceding siblings ...)
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 4/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-05-13  9:38 ` Stanislav Lisovskiy
  2020-05-13 13:44   ` Ville Syrjälä
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
    values.

v3: Forbid simultaneous legacy SAGV PCode requests and
    restricting qgv points. Put the actual restriction
    to commit function, added serialization(thanks to Ville)
    to prevent commit being applied out of order in case of
    nonblocking and/or nomodeset commits.

v4:
    - Minor code refactoring, fixed few typos(thanks to James Ausmus)
    - Change the naming of qgv point
      masking/unmasking functions(James Ausmus).
    - Simplify the masking/unmasking operation itself,
      as we don't need to mask only single point per request(James Ausmus)
    - Reject and stick to highest bandwidth point if SAGV
      can't be enabled(BSpec)

v5:
    - Add new mailbox reply codes, which seems to happen during boot
      time for TGL and indicate that QGV setting is not yet available.

v6:
    - Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
    - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
      can be disabled by BIOS, which is completely legal. So don't
      make CI panic. Instead if we detect that there is only 1 QGV
      point accessible just analyze if we can fit the required bandwidth
      requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
      simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
       without modeset, which caused copying of non-calculated cdclk
       to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
     - Remove unneeded intel_qgv_info qi struct from bw check and zero
       out the needed one(Matthew Roper)
     - Changed QGV error message to have more clear meaning(Matthew Roper)
     - Use state->modeset_set instead of any_ms(Matthew Roper)
     - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
     - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
     - Moved unrelated changes to other patch(using latency as parameter
       for plane wm calculation, moved to SAGV refactoring patch)

v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
     - Remove unnecessary mask being zero check when unmasking
       qgv points as this is completely legal(Matt Roper)
     - Check if we are setting the same mask as already being set
       in hardware to prevent error from PCode.
     - Fix error message when restricting/unrestricting qgv points
       to "mask/unmask" which sounds more accurate(Matt Roper)
     - Move sagv status setting to icl_get_bw_info from atomic check
       as this should be calculated only once.(Matt Roper)
     - Edited comments for the case when we can't enable SAGV and
       use only 1 QGV point with highest bandwidth to be more
       understandable.(Matt Roper)

v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
     - Changed comment for zero new_mask in qgv points masking function
       to better reflect reality(Ville Syrjälä)
     - Simplified bit mask operation in qgv points masking function
       (Ville Syrjälä)
     - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
       however this still can't be under modeset condition(Ville Syrjälä)
     - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
       (Ville Syrjälä)
     - Extracted PCode changes to separate patch.(Ville Syrjälä)
     - Now treat num_planes 0 same as 1 to avoid confusion and
       returning max_bw as 0, which would prevent choosing QGV
       point having max bandwidth in case if SAGV is not allowed,
       as per BSpec(Ville Syrjälä)
     - Do the actual qgv_points_mask swap in the same place as
       all other global state parts like cdclk are swapped.
       In the next patch, this all will be moved to bw state as
       global state, once new global state patch series from Ville
       lands

v14: - Now using global state to serialize access to qgv points
     - Added global state locking back, otherwise we seem to read
       bw state in a wrong way.

v15: - Added TODO comment for near atomic global state locking in
       bw code.

v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
       with Jani Nikula.
     - Take bw_state_changed flag into use.

v17: - Moved qgv point related manipulations next to SAGV code, as
       those are semantically related(Ville Syrjälä)
     - Renamed those into intel_sagv_(pre)|(post)_plane_update
       (Ville Syrjälä)

v18: - Move sagv related calls from commit tail into
       intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)

v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
       for commit tail stage.

v20: - Return max bandwidth for 0 planes(Ville)
     - Constify old_bw_state in bw_atomic_check(Ville)
     - Removed some debugs(Ville)
     - Added data rate to debug print when no QGV points(Ville)
     - Removed some comments(Ville)

v21, v22, v23: - Fixed rebase conflict

v24: - Changed PCode mask to use ICL_ prefix
v25: - Resolved rebase conflict

v26: - Removed redundant NULL checks(Ville)
     - Removed redundant error prints(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 137 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_bw.h       |   9 ++
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/intel_pm.c               |  54 ++++++-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 5 files changed, 167 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..d28ca4d0b1c4 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
 #include "intel_bw.h"
 #include "intel_display_types.h"
 #include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
 
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask)
+{
+	int ret;
+
+	/* bspec says to keep retrying for at least 1 ms */
+	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+				points_mask,
+				ICL_PCODE_POINTS_RESTRICTED_MASK,
+				ICL_PCODE_POINTS_RESTRICTED,
+				1);
+
+	if (ret < 0) {
+		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 			      struct intel_qgv_info *qi)
 {
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
 			break;
 	}
 
+	/*
+	 * In case if SAGV is disabled in BIOS, we always get 1
+	 * SAGV point, but we can't send PCode commands to restrict it
+	 * as it will fail and pointless anyway.
+	 */
+	if (qi.num_points == 1)
+		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+	else
+		dev_priv->sagv_status = I915_SAGV_ENABLED;
+
 	return 0;
 }
 
@@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 {
 	int i;
 
+	/*
+	 * Let's return max bw for 0 planes
+	 */
+	num_planes = max(1, num_planes);
+
 	for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
 		const struct intel_bw_info *bi =
 			&dev_priv->max_bw[i];
@@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
 }
 
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
-					int num_planes)
-{
-	if (INTEL_GEN(dev_priv) >= 11) {
-		/*
-		 * Any bw group has same amount of QGV points
-		 */
-		const struct intel_bw_info *bi =
-			&dev_priv->max_bw[0];
-		unsigned int min_bw = UINT_MAX;
-		int i;
-
-		/*
-		 * FIXME with SAGV disabled maybe we can assume
-		 * point 1 will always be used? Seems to match
-		 * the behaviour observed in the wild.
-		 */
-		for (i = 0; i < bi->num_qgv_points; i++) {
-			unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
-			min_bw = min(bw, min_bw);
-		}
-		return min_bw;
-	} else {
-		return UINT_MAX;
-	}
-}
-
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
 {
 	/*
@@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_bw_state *new_bw_state = NULL;
-	unsigned int data_rate, max_data_rate;
+	const struct intel_bw_state *old_bw_state = NULL;
+	unsigned int data_rate;
 	unsigned int num_active_planes;
 	struct intel_crtc *crtc;
 	int i, ret;
+	u32 allowed_points = 0;
+	unsigned int max_bw_point = 0, max_bw = 0;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	u32 mask = (1 << num_qgv_points) - 1;
 
 	/* FIXME earlier gens need some checks too */
 	if (INTEL_GEN(dev_priv) < 11)
@@ -465,19 +480,71 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 		return ret;
 
 	data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+	data_rate = DIV_ROUND_UP(data_rate, 1000);
+
 	num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
 
-	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+	for (i = 0; i < num_qgv_points; i++) {
+		unsigned int max_data_rate;
 
-	data_rate = DIV_ROUND_UP(data_rate, 1000);
+		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+		if (max_data_rate >= data_rate)
+			allowed_points |= BIT(i);
+		drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
+			    i, max_data_rate, data_rate);
+	}
 
-	if (data_rate > max_data_rate) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
-			    data_rate, max_data_rate, num_active_planes);
+	/*
+	 * BSpec states that we always should have at least one allowed point
+	 * left, so if we couldn't - simply reject the configuration for obvious
+	 * reasons.
+	 */
+	if (allowed_points == 0) {
+		drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
+			      " bandwidth %d for display configuration(%d active planes).\n",
+			      data_rate, num_active_planes);
 		return -EINVAL;
 	}
 
+	/*
+	 * Leave only single point with highest bandwidth, if
+	 * we can't enable SAGV due to the increased memory latency it may
+	 * cause.
+	 */
+	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
+		allowed_points = BIT(max_bw_point);
+		drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
+			      max_bw_point);
+	}
+	/*
+	 * We store the ones which need to be masked as that is what PCode
+	 * actually accepts as a parameter.
+	 */
+	new_bw_state->qgv_points_mask = ~allowed_points & mask;
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	/*
+	 * If the actual mask had changed we need to make sure that
+	 * the commits are serialized(in case this is a nomodeset, nonblocking)
+	 */
+	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 898b4a85ccab..bbcaaa73ec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
 	 */
 	u8 pipe_sagv_reject;
 
+	/*
+	 * Current QGV points mask, which restricts
+	 * some particular SAGV states, not to confuse
+	 * with pipe_sagv_mask.
+	 */
+	u8 qgv_points_mask;
+
 	unsigned int data_rate[I915_MAX_PIPES];
 	u8 num_active_planes[I915_MAX_PIPES];
 
@@ -47,5 +54,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8cede29c9562..6edf0844f8ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -692,6 +692,9 @@ struct skl_plane_wm {
 	bool is_planar;
 };
 
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
 struct skl_pipe_wm {
 	struct skl_plane_wm planes[I915_MAX_PLANES];
 	bool use_sagv_wm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f253db3b7c0..ce5a5262471d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3762,6 +3762,8 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	const struct intel_bw_state *new_bw_state;
+	const struct intel_bw_state *old_bw_state;
+	u32 new_mask = 0;
 
 	/*
 	 * Just return if we can't control SAGV or don't have it.
@@ -3777,15 +3779,42 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (!intel_can_enable_sagv(dev_priv, new_bw_state))
+	if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
 		intel_disable_sagv(dev_priv);
+		return;
+	}
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	/*
+	 * Nothing to mask
+	 */
+	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+		return;
+
+	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+	/*
+	 * If new mask is zero - means there is nothing to mask,
+	 * we can only unmask, which should be done in unmask.
+	 */
+	if (!new_mask)
+		return;
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	icl_pcode_restrict_qgv_points(dev_priv, new_mask);
 }
 
 void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	const struct intel_bw_state *new_bw_state;
-
+	const struct intel_bw_state *old_bw_state;
+	u32 new_mask = 0;
 	/*
 	 * Just return if we can't control SAGV or don't have it.
 	 * This is different from situation when we have SAGV but just can't
@@ -3800,8 +3829,27 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (intel_can_enable_sagv(dev_priv, new_bw_state))
+	if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
 		intel_enable_sagv(dev_priv);
+		return;
+	}
+
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+	/*
+	 * Nothing to unmask
+	 */
+	if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+		return;
+
+	new_mask = new_bw_state->qgv_points_mask;
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	icl_pcode_restrict_qgv_points(dev_priv, new_mask);
 }
 
 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 614ac7f8d4cc..528aba6267da 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -44,6 +44,8 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH v29 6/6] drm/i915: Enable SAGV support for Gen12
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
                   ` (4 preceding siblings ...)
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-05-13  9:38 ` Stanislav Lisovskiy
  2020-05-13 10:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev37) Patchwork
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 13+ messages in thread
From: Stanislav Lisovskiy @ 2020-05-13  9:38 UTC (permalink / raw)
  To: intel-gfx

Flip the switch and enable SAGV support
for Gen12 also.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ce5a5262471d..cb70db0cb58b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	/* HACK! */
-	if (IS_GEN(dev_priv, 12))
-		return false;
-
 	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
 		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
-- 
2.24.1.485.gad05a3d8e5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev37)
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
                   ` (5 preceding siblings ...)
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
@ 2020-05-13 10:09 ` Patchwork
  2020-05-13 10:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2020-05-13 11:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  8 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2020-05-13 10:09 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: SAGV support for Gen12+ (rev37)
URL   : https://patchwork.freedesktop.org/series/75129/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1a28a5c25a7d drm/i915: Introduce skl_plane_wm_level accessor.
c93186da4f39 drm/i915: Extract skl SAGV checking
197c503f86b0 drm/i915: Make active_pipes check skl specific
-:64: WARNING:LONG_LINE: line over 100 characters
#64: FILE: drivers/gpu/drm/i915/intel_pm.c:3907:
+	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {

total: 0 errors, 1 warnings, 0 checks, 53 lines checked
452bb4194c02 drm/i915: Add TGL+ SAGV support
-:247: WARNING:LONG_LINE: line over 100 characters
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:5767:
+				    enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,

-:256: WARNING:LONG_LINE: line over 100 characters
#256: FILE: drivers/gpu/drm/i915/intel_pm.c:5777:
+				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,

-:257: WARNING:LONG_LINE: line over 100 characters
#257: FILE: drivers/gpu/drm/i915/intel_pm.c:5778:
+				    enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);

total: 0 errors, 3 warnings, 0 checks, 255 lines checked
60649b3d025e drm/i915: Restrict qgv points which don't have enough bandwidth.
-:319: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#319: FILE: drivers/gpu/drm/i915/display/intel_bw.c:529:
+		drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
+			      max_bw_point);

total: 0 errors, 0 warnings, 1 checks, 306 lines checked
dcde82c42f62 drm/i915: Enable SAGV support for Gen12

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev37)
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
                   ` (6 preceding siblings ...)
  2020-05-13 10:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev37) Patchwork
@ 2020-05-13 10:35 ` Patchwork
  2020-05-13 11:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  8 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2020-05-13 10:35 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: SAGV support for Gen12+ (rev37)
URL   : https://patchwork.freedesktop.org/series/75129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8471 -> Patchwork_17641
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/index.html

Known issues
------------

  Here are the changes found in Patchwork_17641 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@active:
    - fi-bwr-2160:        [PASS][1] -> [INCOMPLETE][2] ([i915#489])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/fi-bwr-2160/igt@i915_selftest@live@active.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/fi-bwr-2160/igt@i915_selftest@live@active.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u2:          [{ABORT}][3] ([i915#1814]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/fi-icl-u2/igt@debugfs_test@read_all_entries.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [SKIP][5] ([fdo#109271]) -> [FAIL][6] ([i915#62] / [i915#95])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1803]: https://gitlab.freedesktop.org/drm/intel/issues/1803
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (49 -> 35)
------------------------------

  Missing    (14): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-ilk-650 fi-kbl-7500u fi-kbl-8809g fi-elk-e7500 fi-tgl-y fi-byt-clapper fi-bsw-nick fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8471 -> Patchwork_17641

  CI-20190529: 20190529
  CI_DRM_8471: 3c84a88ed50e99b200fac400a9b817a23d399c01 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5651: e54e2642f1967ca3c488db32264607df670d1dfb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17641: dcde82c42f62fc0bec3264ae2caf4cf67e345f5e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

dcde82c42f62 drm/i915: Enable SAGV support for Gen12
60649b3d025e drm/i915: Restrict qgv points which don't have enough bandwidth.
452bb4194c02 drm/i915: Add TGL+ SAGV support
197c503f86b0 drm/i915: Make active_pipes check skl specific
c93186da4f39 drm/i915: Extract skl SAGV checking
1a28a5c25a7d drm/i915: Introduce skl_plane_wm_level accessor.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev37)
  2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
                   ` (7 preceding siblings ...)
  2020-05-13 10:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-13 11:44 ` Patchwork
  8 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2020-05-13 11:44 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: SAGV support for Gen12+ (rev37)
URL   : https://patchwork.freedesktop.org/series/75129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8471_full -> Patchwork_17641_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_17641_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_busy@basic-modeset-pipe-b:
    - shard-snb:          [PASS][1] -> [SKIP][2] ([fdo#109271]) +4 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-snb1/igt@kms_busy@basic-modeset-pipe-b.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-snb2/igt@kms_busy@basic-modeset-pipe-b.html

  * igt@kms_color@pipe-b-legacy-gamma-reset:
    - shard-kbl:          [PASS][3] -> [DMESG-WARN][4] ([i915#78])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-kbl6/igt@kms_color@pipe-b-legacy-gamma-reset.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-kbl2/igt@kms_color@pipe-b-legacy-gamma-reset.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([i915#54])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-skl:          [PASS][7] -> [INCOMPLETE][8] ([i915#300])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html

  
#### Possible fixes ####

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-kbl6/igt@gem_softpin@noreloc-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-kbl2/igt@gem_softpin@noreloc-s3.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [DMESG-WARN][17] ([i915#1436] / [i915#716]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-apl4/igt@gen9_exec_parse@allowed-all.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-apl7/igt@gen9_exec_parse@allowed-all.html

  * igt@kms_cursor_legacy@pipe-c-torture-move:
    - shard-tglb:         [DMESG-WARN][19] ([i915#128]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-tglb3/igt@kms_cursor_legacy@pipe-c-torture-move.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-tglb5/igt@kms_cursor_legacy@pipe-c-torture-move.html

  * {igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2}:
    - shard-glk:          [FAIL][21] ([i915#79]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * {igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1}:
    - shard-skl:          [FAIL][23] ([i915#79]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][25] ([i915#1188]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][27] ([fdo#108145] / [i915#265]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [SKIP][29] ([fdo#109441]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html

  * {igt@sysfs_heartbeat_interval@mixed@rcs0}:
    - shard-skl:          [FAIL][31] ([i915#1731]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-skl1/igt@sysfs_heartbeat_interval@mixed@rcs0.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-skl6/igt@sysfs_heartbeat_interval@mixed@rcs0.html

  * {igt@sysfs_heartbeat_interval@mixed@vecs0}:
    - shard-tglb:         [FAIL][33] ([i915#1879]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-tglb6/igt@sysfs_heartbeat_interval@mixed@vecs0.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-tglb6/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic-dpms:
    - shard-kbl:          [TIMEOUT][35] ([i915#1319]) -> [FAIL][36] ([fdo#110321] / [fdo#110336] / [i915#93] / [i915#95])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-kbl6/igt@kms_content_protection@atomic-dpms.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-kbl2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][37] ([fdo#109642] / [fdo#111068]) -> [FAIL][38] ([i915#608])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8471/shard-iclb3/igt@kms_psr2_su@page_flip.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/shard-iclb2/igt@kms_psr2_su@page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1879]: https://gitlab.freedesktop.org/drm/intel/issues/1879
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8471 -> Patchwork_17641

  CI-20190529: 20190529
  CI_DRM_8471: 3c84a88ed50e99b200fac400a9b817a23d399c01 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5651: e54e2642f1967ca3c488db32264607df670d1dfb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17641: dcde82c42f62fc0bec3264ae2caf4cf67e345f5e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17641/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v29 3/6] drm/i915: Make active_pipes check skl specific
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 3/6] drm/i915: Make active_pipes check skl specific Stanislav Lisovskiy
@ 2020-05-13 13:34   ` Ville Syrjälä
  0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2020-05-13 13:34 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Wed, May 13, 2020 at 12:38:13PM +0300, Stanislav Lisovskiy wrote:
> Seems that only skl needs to have SAGV turned off
> for multipipe scenarios, so lets do it this way.

Commit msg still a bit misleading, but meh, pushed 1-3 anyway. Thanks.

> 
> If anything blows up - we can always revert this patch.
> 
> v2: Changed if condition to look better (Ville).
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++-----
>  drivers/gpu/drm/i915/intel_pm.h |  3 ++-
>  2 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6a212d47aec8..de0f8cede59c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
<snip>
> @@ -3901,7 +3904,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  			return ret;
>  	}
>  
> -	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> +	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {

I did wrap this line while applying since it was trivial and made
checkpatch happy.

I see one other valid checkpatch complaint in the report (some alignment
fail in one of the later patches). The wm debug >80col warnings we can't
really fix without some refactoring or making the code look evem uglier
so imo ignore those.

>  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
>  		if (ret)
>  			return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index fd1dc422e6c5..614ac7f8d4cc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -42,7 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  			      struct skl_pipe_wm *out);
>  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
>  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> -bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> +bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> +			   const struct intel_bw_state *bw_state);
>  int intel_enable_sagv(struct drm_i915_private *dev_priv);
>  int intel_disable_sagv(struct drm_i915_private *dev_priv);
>  void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v29 4/6] drm/i915: Add TGL+ SAGV support
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 4/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-05-13 13:41   ` Ville Syrjälä
  0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2020-05-13 13:41 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Wed, May 13, 2020 at 12:38:14PM +0300, Stanislav Lisovskiy wrote:
> Starting from TGL we need to have a separate wm0
> values for SAGV and non-SAGV which affects
> how calculations are done.
> 
> v2: Remove long lines
> v3: Removed COLOR_PLANE enum references
> v4, v5, v6: Fixed rebase conflict
> v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
>     - Removed sagv_uv_wm0(Ville)
>     - can_sagv->use_sagv_wm(Ville)
> 
> v8: - Moved tgl_crtc_can_enable_sagv function up(Ville)
>     - Changed comment regarding pipe_wm usage(Ville)
>     - Call intel_can_enable_sagv and tgl_compute_sagv_wm only
>       for Gen12(Ville)
>     - Some sagv debugs removed(Ville)
>     - skl_print_wm_changes improvements(Ville)
>     - Do assignment instead of memcpy in
>       skl_pipe_wm_get_hw_state(Ville)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   8 +-
>  .../drm/i915/display/intel_display_types.h    |   2 +
>  drivers/gpu/drm/i915/intel_pm.c               | 112 +++++++++++++++---
>  3 files changed, 103 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index fd6d63b03489..be5741cb7595 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> +							       &sw_plane_wm->sagv_wm0)))
>  				continue;
>  
>  			drm_err(&dev_priv->drm,
> @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			    (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
> +							       &sw_plane_wm->sagv_wm0)))
>  				continue;
>  
>  			drm_err(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9488449e4b94..8cede29c9562 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -688,11 +688,13 @@ struct skl_plane_wm {
>  	struct skl_wm_level wm[8];
>  	struct skl_wm_level uv_wm[8];
>  	struct skl_wm_level trans_wm;
> +	struct skl_wm_level sagv_wm0;
>  	bool is_planar;
>  };
>  
>  struct skl_pipe_wm {
>  	struct skl_plane_wm planes[I915_MAX_PLANES];
> +	bool use_sagv_wm;
>  };
>  
>  enum vlv_wm_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index de0f8cede59c..1f253db3b7c0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3853,9 +3853,39 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  	return true;
>  }
>  
> +static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum plane_id plane_id;
> +
> +	if (!crtc_state->hw.active)
> +		return true;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		const struct skl_ddb_entry *plane_alloc =
> +			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +		const struct skl_plane_wm *wm =
> +			&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +		if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
> +			return false;
> +	}
> +
> +	return true;
> +}
> +
>  static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  {
> -	return skl_crtc_can_enable_sagv(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	bool can_sagv;
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		can_sagv = tgl_crtc_can_enable_sagv(crtc_state);
> +	else
> +		can_sagv = skl_crtc_can_enable_sagv(crtc_state);
> +
> +	return can_sagv;

nit: pointless variable. Just

if (gen>=12)
	return tgl...();
else
	return skl...()

would do.

>  }
>  
>  bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> @@ -3873,7 +3903,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	int ret;
>  	struct intel_crtc *crtc;
> -	const struct intel_crtc_state *new_crtc_state;
> +	struct intel_crtc_state *new_crtc_state;
>  	struct intel_bw_state *new_bw_state = NULL;
>  	const struct intel_bw_state *old_bw_state = NULL;
>  	int i;
> @@ -3904,6 +3934,20 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  			return ret;
>  	}
>  
> +	for_each_new_intel_crtc_in_state(state, crtc,
> +					 new_crtc_state, i) {
> +		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
> +
> +		/*
> +		 * We store use_sagv_wm in the crtc state rather than relying on
> +		 * that bw state since we have no convenient way to get at the
> +		 * latter from the plane commit hooks (especially in the legacy
> +		 * cursor case)
> +		 */
> +		pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
> +				       intel_can_enable_sagv(dev_priv, new_bw_state);
> +	}
> +
>  	if (intel_can_enable_sagv(dev_priv, new_bw_state) != intel_can_enable_sagv(dev_priv, old_bw_state)) {
>  		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
>  		if (ret)
> @@ -4646,8 +4690,11 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
>  		   enum plane_id plane_id,
>  		   int level)
>  {
> -	const struct skl_plane_wm *wm =
> -		&crtc_state->wm.skl.optimal.planes[plane_id];
> +	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> +	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +
> +	if (level == 0 && pipe_wm->use_sagv_wm)
> +		return &wm->sagv_wm0;
>  
>  	return &wm->wm[level];
>  }
> @@ -4688,7 +4735,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  							 plane_data_rate,
>  							 uv_plane_data_rate);
>  
> -
>  	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
>  					   alloc, &num_active);
>  	alloc_size = skl_ddb_entry_size(alloc);
> @@ -5223,6 +5269,22 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>  	}
>  }
>  
> +static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
> +				const struct skl_wm_params *wm_params,
> +				struct skl_plane_wm *plane_wm)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
> +	struct skl_wm_level *levels = plane_wm->wm;
> +

Spurious empty line.

> +	u32 latency = dev_priv->wm.skl_latency[0];

A few more nits here:

I think we went with 'unsigned int 'in most places?

> +
> +	latency += dev_priv->sagv_block_time_us;

Single statement

unsigned int latency = a + b;

would be less confusing imo.


> +	skl_compute_plane_wm(crtc_state, 0, latency,
> +			     wm_params, &levels[0],

Hmm. Wonder if we should pass this or sagv_wm itself
as result_prev. I guess in theory we should never hit
the relevant checks since sagv_wm should get a higher
watermark than wm0 anyway. So probably fine this way.

> +			     sagv_wm);
> +}
> +
>  static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
>  				      const struct skl_wm_params *wp,
>  				      struct skl_plane_wm *wm)
> @@ -5290,6 +5352,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  				     const struct intel_plane_state *plane_state,
>  				     enum plane_id plane_id, int color_plane)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
>  	struct skl_wm_params wm_params;
>  	int ret;
> @@ -5300,6 +5364,10 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  		return ret;
>  
>  	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
> +
>  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
>  
>  	return 0;
> @@ -5666,23 +5734,25 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  				continue;
>  
>  			drm_dbg_kms(&dev_priv->drm,
> -				    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
> -				    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
> +				    "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm"
> +				    " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm\n",
>  				    plane->base.base.id, plane->base.name,
>  				    enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
>  				    enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
>  				    enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
>  				    enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
>  				    enast(old_wm->trans_wm.plane_en),
> +				    enast(old_wm->sagv_wm0.plane_en),
>  				    enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
>  				    enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
>  				    enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
>  				    enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
> -				    enast(new_wm->trans_wm.plane_en));
> +				    enast(new_wm->trans_wm.plane_en),
> +				    enast(new_wm->sagv_wm0.plane_en));
>  
>  			drm_dbg_kms(&dev_priv->drm,
> -				    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
> -				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
> +				    "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
> +				      " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
>  				    plane->base.base.id, plane->base.name,
>  				    enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
>  				    enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
> @@ -5693,6 +5763,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  				    enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
>  				    enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
>  				    enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
> +				    enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,
>  
>  				    enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
>  				    enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
> @@ -5702,37 +5773,42 @@ skl_print_wm_changes(struct intel_atomic_state *state)
>  				    enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
>  				    enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
>  				    enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
> -				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
> +				    enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
> +				    enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);
>  
>  			drm_dbg_kms(&dev_priv->drm,
> -				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> -				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> +				    "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> +				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
>  				    plane->base.base.id, plane->base.name,
>  				    old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
>  				    old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
>  				    old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
>  				    old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
>  				    old_wm->trans_wm.plane_res_b,
> +				    old_wm->sagv_wm0.plane_res_b,
>  				    new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
>  				    new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
>  				    new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
>  				    new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
> -				    new_wm->trans_wm.plane_res_b);
> +				    new_wm->trans_wm.plane_res_b,
> +				    new_wm->sagv_wm0.plane_res_b);
>  
>  			drm_dbg_kms(&dev_priv->drm,
> -				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> -				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
> +				    "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
> +				    " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
>  				    plane->base.base.id, plane->base.name,
>  				    old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
>  				    old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
>  				    old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
>  				    old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
>  				    old_wm->trans_wm.min_ddb_alloc,
> +				    old_wm->sagv_wm0.min_ddb_alloc,
>  				    new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
>  				    new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
>  				    new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
>  				    new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
> -				    new_wm->trans_wm.min_ddb_alloc);
> +				    new_wm->trans_wm.min_ddb_alloc,
> +				    new_wm->sagv_wm0.min_ddb_alloc);
>  		}
>  	}
>  }
> @@ -6025,6 +6101,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
>  		}
>  
> +		wm->sagv_wm0 = wm->wm[0];

This should probably have a gen>=12 check too since we only compute
it for tgl+ now.

If nothing else it should work as a good reminder that we need to
adjust this code again in the near future for the next gen.

Apart from that, and the small nits above, the rest looks nice.

> +
>  		if (plane_id != PLANE_CURSOR)
>  			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
>  		else
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH v29 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth.
  2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-05-13 13:44   ` Ville Syrjälä
  0 siblings, 0 replies; 13+ messages in thread
From: Ville Syrjälä @ 2020-05-13 13:44 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Wed, May 13, 2020 at 12:38:15PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
>     values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
>     restricting qgv points. Put the actual restriction
>     to commit function, added serialization(thanks to Ville)
>     to prevent commit being applied out of order in case of
>     nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
>     - Change the naming of qgv point
>       masking/unmasking functions(James Ausmus).
>     - Simplify the masking/unmasking operation itself,
>       as we don't need to mask only single point per request(James Ausmus)
>     - Reject and stick to highest bandwidth point if SAGV
>       can't be enabled(BSpec)
> 
> v5:
>     - Add new mailbox reply codes, which seems to happen during boot
>       time for TGL and indicate that QGV setting is not yet available.
> 
> v6:
>     - Increase number of supported QGV points to be in sync with BSpec.
> 
> v7: - Rebased and resolved conflict to fix build failure.
>     - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
> 
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
>       can be disabled by BIOS, which is completely legal. So don't
>       make CI panic. Instead if we detect that there is only 1 QGV
>       point accessible just analyze if we can fit the required bandwidth
>       requirements, but no need in restricting.
> 
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
>       simultaneously.
> 
> v10: - Fix CDCLK corruption, because of global state getting serialized
>        without modeset, which caused copying of non-calculated cdclk
>        to be copied to dev_priv(thanks to Ville for the hint).
> 
> v11: - Remove unneeded headers and spaces(Matthew Roper)
>      - Remove unneeded intel_qgv_info qi struct from bw check and zero
>        out the needed one(Matthew Roper)
>      - Changed QGV error message to have more clear meaning(Matthew Roper)
>      - Use state->modeset_set instead of any_ms(Matthew Roper)
>      - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
>      - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
>      - Moved unrelated changes to other patch(using latency as parameter
>        for plane wm calculation, moved to SAGV refactoring patch)
> 
> v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
>      - Remove unnecessary mask being zero check when unmasking
>        qgv points as this is completely legal(Matt Roper)
>      - Check if we are setting the same mask as already being set
>        in hardware to prevent error from PCode.
>      - Fix error message when restricting/unrestricting qgv points
>        to "mask/unmask" which sounds more accurate(Matt Roper)
>      - Move sagv status setting to icl_get_bw_info from atomic check
>        as this should be calculated only once.(Matt Roper)
>      - Edited comments for the case when we can't enable SAGV and
>        use only 1 QGV point with highest bandwidth to be more
>        understandable.(Matt Roper)
> 
> v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
>      - Changed comment for zero new_mask in qgv points masking function
>        to better reflect reality(Ville Syrjälä)
>      - Simplified bit mask operation in qgv points masking function
>        (Ville Syrjälä)
>      - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
>        however this still can't be under modeset condition(Ville Syrjälä)
>      - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
>        (Ville Syrjälä)
>      - Extracted PCode changes to separate patch.(Ville Syrjälä)
>      - Now treat num_planes 0 same as 1 to avoid confusion and
>        returning max_bw as 0, which would prevent choosing QGV
>        point having max bandwidth in case if SAGV is not allowed,
>        as per BSpec(Ville Syrjälä)
>      - Do the actual qgv_points_mask swap in the same place as
>        all other global state parts like cdclk are swapped.
>        In the next patch, this all will be moved to bw state as
>        global state, once new global state patch series from Ville
>        lands
> 
> v14: - Now using global state to serialize access to qgv points
>      - Added global state locking back, otherwise we seem to read
>        bw state in a wrong way.
> 
> v15: - Added TODO comment for near atomic global state locking in
>        bw code.
> 
> v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
>        with Jani Nikula.
>      - Take bw_state_changed flag into use.
> 
> v17: - Moved qgv point related manipulations next to SAGV code, as
>        those are semantically related(Ville Syrjälä)
>      - Renamed those into intel_sagv_(pre)|(post)_plane_update
>        (Ville Syrjälä)
> 
> v18: - Move sagv related calls from commit tail into
>        intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
> 
> v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
>        for commit tail stage.
> 
> v20: - Return max bandwidth for 0 planes(Ville)
>      - Constify old_bw_state in bw_atomic_check(Ville)
>      - Removed some debugs(Ville)
>      - Added data rate to debug print when no QGV points(Ville)
>      - Removed some comments(Ville)
> 
> v21, v22, v23: - Fixed rebase conflict
> 
> v24: - Changed PCode mask to use ICL_ prefix
> v25: - Resolved rebase conflict
> 
> v26: - Removed redundant NULL checks(Ville)
>      - Removed redundant error prints(Ville)
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c       | 137 +++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_bw.h       |   9 ++
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/intel_pm.c               |  54 ++++++-
>  drivers/gpu/drm/i915/intel_pm.h               |   2 +
>  5 files changed, 167 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 6e7cc3a4f1aa..d28ca4d0b1c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
> @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>  	return 0;
>  }
>  
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask)
> +{
> +	int ret;
> +
> +	/* bspec says to keep retrying for at least 1 ms */
> +	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> +				points_mask,
> +				ICL_PCODE_POINTS_RESTRICTED_MASK,
> +				ICL_PCODE_POINTS_RESTRICTED,
> +				1);
> +
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);

Pls use the per-device logging. drm_err() or whatever it's called.

Apart from that (and the checkpatch issue ci reported) this looks
ready to go in.

> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>  			      struct intel_qgv_info *qi)
>  {

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-05-13 13:44 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-13  9:38 [Intel-gfx] [PATCH v29 0/6] SAGV support for Gen12+ Stanislav Lisovskiy
2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 1/6] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 2/6] drm/i915: Extract skl SAGV checking Stanislav Lisovskiy
2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 3/6] drm/i915: Make active_pipes check skl specific Stanislav Lisovskiy
2020-05-13 13:34   ` Ville Syrjälä
2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 4/6] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
2020-05-13 13:41   ` Ville Syrjälä
2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 5/6] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-05-13 13:44   ` Ville Syrjälä
2020-05-13  9:38 ` [Intel-gfx] [PATCH v29 6/6] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-05-13 10:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev37) Patchwork
2020-05-13 10:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-13 11:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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