* [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Verify timeslicing between submit-fence @ 2020-05-20 16:29 ` Chris Wilson 0 siblings, 0 replies; 5+ messages in thread From: Chris Wilson @ 2020-05-20 16:29 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev, Chris Wilson Use a spinner to create a fence, and then use that as to synchronise another batch to cancel the spinner. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/gem_exec_schedule.c | 121 +++++++++++++++++++++++++++++++-- 1 file changed, 116 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 62e387cc1..0a7deb5a1 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -65,6 +65,11 @@ IGT_TEST_DESCRIPTION("Check that we can control the order of execution"); +static unsigned int offset_in_page(void *addr) +{ + return (uintptr_t)addr & 4095; +} + static inline uint32_t __sync_read_u32(int fd, uint32_t handle, uint64_t offset) { @@ -670,6 +675,110 @@ static void lateslice(int i915, unsigned int engine) igt_spin_free(i915, spin[1]); } +static void cancel_spinner(int i915, + uint32_t ctx, unsigned int engine, + igt_spin_t *spin) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = gem_create(i915, 4096), + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .flags = engine | I915_EXEC_FENCE_SUBMIT, + .rsvd1 = ctx, /* same vm */ + .rsvd2 = spin->out_fence, + }; + uint32_t *map, *cs; + + map = gem_mmap__device_coherent(i915, obj.handle, 0, 4096, PROT_WRITE); + cs = map; + + *cs++ = MI_STORE_DWORD_IMM; + *cs++ = spin->obj[IGT_SPIN_BATCH].offset + + offset_in_page(spin->condition); + *cs++ = spin->obj[IGT_SPIN_BATCH].offset >> 32; + *cs++ = MI_BATCH_BUFFER_END; + + *cs++ = MI_BATCH_BUFFER_END; + munmap(map, 4096); + + gem_execbuf(i915, &execbuf); + gem_close(i915, obj.handle); +} + +static void submit_slice(int i915, + const struct intel_execution_engine2 *e, + unsigned int flags) +#define EARLY_SUBMIT 0x1 +#define LATE_SUBMIT 0x2 +{ + I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , 1) = {}; + const struct intel_execution_engine2 *cancel; + struct drm_i915_gem_context_param param = { + .ctx_id = gem_context_create(i915), + .param = I915_CONTEXT_PARAM_ENGINES, + .value = to_user_pointer(&engines), + .size = sizeof(engines), + }; + + /* + * When using a submit fence, we do not want to block concurrent work, + * especially when that work is coperating with the spinner. + */ + + igt_require(gem_scheduler_has_semaphores(i915)); + igt_require(gem_scheduler_has_preemption(i915)); + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + __for_each_physical_engine(i915, cancel) { + igt_spin_t *bg, *spin; + int timeline = -1; + int fence = -1; + + if (!gem_class_can_store_dword(i915, cancel->class)) + continue; + + igt_debug("Testing cancellation from %s\n", e->name); + + bg = igt_spin_new(i915, .engine = e->flags); + + if (flags & LATE_SUBMIT) { + timeline = sw_sync_timeline_create(); + fence = sw_sync_timeline_create_fence(timeline, 1); + } + + engines.engines[0].engine_class = e->class; + engines.engines[0].engine_instance = e->instance; + gem_context_set_param(i915, ¶m); + spin = igt_spin_new(i915, .ctx = param.ctx_id, + .fence = fence, + .flags = + IGT_SPIN_POLL_RUN | + (flags & LATE_SUBMIT ? IGT_SPIN_FENCE_IN : 0) | + IGT_SPIN_FENCE_OUT); + if (fence != -1) + close(fence); + + if (flags & EARLY_SUBMIT) + igt_spin_busywait_until_started(spin); + + engines.engines[0].engine_class = cancel->class; + engines.engines[0].engine_instance = cancel->instance; + gem_context_set_param(i915, ¶m); + cancel_spinner(i915, param.ctx_id, 0, spin); + + if (timeline != -1) + close(timeline); + + gem_sync(i915, spin->handle); + igt_spin_free(i915, spin); + igt_spin_free(i915, bg); + } + + gem_context_destroy(i915, param.ctx_id); +} + static uint32_t __batch_create(int i915, uint32_t offset) { const uint32_t bbe = MI_BATCH_BUFFER_END; @@ -812,11 +921,6 @@ static void semaphore_codependency(int i915) } } -static unsigned int offset_in_page(void *addr) -{ - return (uintptr_t)addr & 4095; -} - static void semaphore_resolve(int i915) { const struct intel_execution_engine2 *e; @@ -2454,6 +2558,13 @@ igt_main test_each_engine("lateslice", fd, e) lateslice(fd, e->flags); + test_each_engine("submit-early-slice", fd, e) + submit_slice(fd, e, EARLY_SUBMIT); + test_each_engine("submit-golden-slice", fd, e) + submit_slice(fd, e, 0); + test_each_engine("submit-late-slice", fd, e) + submit_slice(fd, e, LATE_SUBMIT); + igt_subtest("semaphore-user") semaphore_userlock(fd); igt_subtest("semaphore-codependency") -- 2.27.0.rc0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Verify timeslicing between submit-fence @ 2020-05-20 16:29 ` Chris Wilson 0 siblings, 0 replies; 5+ messages in thread From: Chris Wilson @ 2020-05-20 16:29 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin, Chris Wilson Use a spinner to create a fence, and then use that as to synchronise another batch to cancel the spinner. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- tests/i915/gem_exec_schedule.c | 121 +++++++++++++++++++++++++++++++-- 1 file changed, 116 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 62e387cc1..0a7deb5a1 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -65,6 +65,11 @@ IGT_TEST_DESCRIPTION("Check that we can control the order of execution"); +static unsigned int offset_in_page(void *addr) +{ + return (uintptr_t)addr & 4095; +} + static inline uint32_t __sync_read_u32(int fd, uint32_t handle, uint64_t offset) { @@ -670,6 +675,110 @@ static void lateslice(int i915, unsigned int engine) igt_spin_free(i915, spin[1]); } +static void cancel_spinner(int i915, + uint32_t ctx, unsigned int engine, + igt_spin_t *spin) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = gem_create(i915, 4096), + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .flags = engine | I915_EXEC_FENCE_SUBMIT, + .rsvd1 = ctx, /* same vm */ + .rsvd2 = spin->out_fence, + }; + uint32_t *map, *cs; + + map = gem_mmap__device_coherent(i915, obj.handle, 0, 4096, PROT_WRITE); + cs = map; + + *cs++ = MI_STORE_DWORD_IMM; + *cs++ = spin->obj[IGT_SPIN_BATCH].offset + + offset_in_page(spin->condition); + *cs++ = spin->obj[IGT_SPIN_BATCH].offset >> 32; + *cs++ = MI_BATCH_BUFFER_END; + + *cs++ = MI_BATCH_BUFFER_END; + munmap(map, 4096); + + gem_execbuf(i915, &execbuf); + gem_close(i915, obj.handle); +} + +static void submit_slice(int i915, + const struct intel_execution_engine2 *e, + unsigned int flags) +#define EARLY_SUBMIT 0x1 +#define LATE_SUBMIT 0x2 +{ + I915_DEFINE_CONTEXT_PARAM_ENGINES(engines , 1) = {}; + const struct intel_execution_engine2 *cancel; + struct drm_i915_gem_context_param param = { + .ctx_id = gem_context_create(i915), + .param = I915_CONTEXT_PARAM_ENGINES, + .value = to_user_pointer(&engines), + .size = sizeof(engines), + }; + + /* + * When using a submit fence, we do not want to block concurrent work, + * especially when that work is coperating with the spinner. + */ + + igt_require(gem_scheduler_has_semaphores(i915)); + igt_require(gem_scheduler_has_preemption(i915)); + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + __for_each_physical_engine(i915, cancel) { + igt_spin_t *bg, *spin; + int timeline = -1; + int fence = -1; + + if (!gem_class_can_store_dword(i915, cancel->class)) + continue; + + igt_debug("Testing cancellation from %s\n", e->name); + + bg = igt_spin_new(i915, .engine = e->flags); + + if (flags & LATE_SUBMIT) { + timeline = sw_sync_timeline_create(); + fence = sw_sync_timeline_create_fence(timeline, 1); + } + + engines.engines[0].engine_class = e->class; + engines.engines[0].engine_instance = e->instance; + gem_context_set_param(i915, ¶m); + spin = igt_spin_new(i915, .ctx = param.ctx_id, + .fence = fence, + .flags = + IGT_SPIN_POLL_RUN | + (flags & LATE_SUBMIT ? IGT_SPIN_FENCE_IN : 0) | + IGT_SPIN_FENCE_OUT); + if (fence != -1) + close(fence); + + if (flags & EARLY_SUBMIT) + igt_spin_busywait_until_started(spin); + + engines.engines[0].engine_class = cancel->class; + engines.engines[0].engine_instance = cancel->instance; + gem_context_set_param(i915, ¶m); + cancel_spinner(i915, param.ctx_id, 0, spin); + + if (timeline != -1) + close(timeline); + + gem_sync(i915, spin->handle); + igt_spin_free(i915, spin); + igt_spin_free(i915, bg); + } + + gem_context_destroy(i915, param.ctx_id); +} + static uint32_t __batch_create(int i915, uint32_t offset) { const uint32_t bbe = MI_BATCH_BUFFER_END; @@ -812,11 +921,6 @@ static void semaphore_codependency(int i915) } } -static unsigned int offset_in_page(void *addr) -{ - return (uintptr_t)addr & 4095; -} - static void semaphore_resolve(int i915) { const struct intel_execution_engine2 *e; @@ -2454,6 +2558,13 @@ igt_main test_each_engine("lateslice", fd, e) lateslice(fd, e->flags); + test_each_engine("submit-early-slice", fd, e) + submit_slice(fd, e, EARLY_SUBMIT); + test_each_engine("submit-golden-slice", fd, e) + submit_slice(fd, e, 0); + test_each_engine("submit-late-slice", fd, e) + submit_slice(fd, e, LATE_SUBMIT); + igt_subtest("semaphore-user") semaphore_userlock(fd); igt_subtest("semaphore-codependency") -- 2.27.0.rc0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: failure for i915/gem_exec_schedule: Verify timeslicing between submit-fence 2020-05-20 16:29 ` [igt-dev] " Chris Wilson (?) @ 2020-05-20 18:11 ` Patchwork -1 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-05-20 18:11 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_exec_schedule: Verify timeslicing between submit-fence URL : https://patchwork.freedesktop.org/series/77485/ State : failure == Summary == ERROR! This series introduces new undocumented tests: gem_exec_schedule@submit-early-slice gem_exec_schedule@submit-golden-slice gem_exec_schedule@submit-late-slice Can you document them as per the requirement in the [CONTRIBUTING.md]? [Documentation] has more details on how to do this. Here are few examples: https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/0316695d03aa46108296b27f3982ec93200c7a6e https://gitlab.freedesktop.org/drm/igt-gpu-tools/commit/443cc658e1e6b492ee17bf4f4d891029eb7a205d Thanks in advance! [CONTRIBUTING.md]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/blob/master/CONTRIBUTING.md#L19 [Documentation]: https://drm.pages.freedesktop.org/igt-gpu-tools/igt-gpu-tools-Core.html#igt-describe Other than that, pipeline status: SUCCESS. see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/149310 for the overview. == Logs == For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/pipelines/149310 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_schedule: Verify timeslicing between submit-fence 2020-05-20 16:29 ` [igt-dev] " Chris Wilson (?) (?) @ 2020-05-20 18:17 ` Patchwork -1 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-05-20 18:17 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_exec_schedule: Verify timeslicing between submit-fence URL : https://patchwork.freedesktop.org/series/77485/ State : success == Summary == CI Bug Log - changes from CI_DRM_8514 -> IGTPW_4602 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/index.html Known issues ------------ Here are the changes found in IGTPW_4602 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-cfl-8109u: [INCOMPLETE][1] ([i915#1874]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/fi-cfl-8109u/igt@i915_selftest@live@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/fi-cfl-8109u/igt@i915_selftest@live@execlists.html [i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874 Participating hosts (47 -> 42) ------------------------------ Additional (1): fi-kbl-r Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-hsw-4770 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5664 -> IGTPW_4602 CI-20190529: 20190529 CI_DRM_8514: c98b2ef26a5a946fd22839fce7dc4cc868f565fb @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4602: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/index.html IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Testlist changes == +igt@gem_exec_schedule@submit-early-slice +igt@gem_exec_schedule@submit-golden-slice +igt@gem_exec_schedule@submit-late-slice == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915/gem_exec_schedule: Verify timeslicing between submit-fence 2020-05-20 16:29 ` [igt-dev] " Chris Wilson ` (2 preceding siblings ...) (?) @ 2020-05-21 11:50 ` Patchwork -1 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2020-05-21 11:50 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev == Series Details == Series: i915/gem_exec_schedule: Verify timeslicing between submit-fence URL : https://patchwork.freedesktop.org/series/77485/ State : success == Summary == CI Bug Log - changes from CI_DRM_8514_full -> IGTPW_4602_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/index.html New tests --------- New tests have been introduced between CI_DRM_8514_full and IGTPW_4602_full: ### New IGT tests (18) ### * igt@gem_exec_schedule@submit-early-slice: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@gem_exec_schedule@submit-early-slice@bcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.04] s * igt@gem_exec_schedule@submit-early-slice@rcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.04] s * igt@gem_exec_schedule@submit-early-slice@vcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.04] s * igt@gem_exec_schedule@submit-early-slice@vcs1: - Statuses : 2 pass(s) - Exec time: [0.03] s * igt@gem_exec_schedule@submit-early-slice@vecs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.03] s * igt@gem_exec_schedule@submit-golden-slice: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@gem_exec_schedule@submit-golden-slice@bcs0: - Statuses : 5 pass(s) - Exec time: [0.03] s * igt@gem_exec_schedule@submit-golden-slice@rcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.03] s * igt@gem_exec_schedule@submit-golden-slice@vcs0: - Statuses : 5 pass(s) - Exec time: [0.03] s * igt@gem_exec_schedule@submit-golden-slice@vcs1: - Statuses : 2 pass(s) - Exec time: [0.03] s * igt@gem_exec_schedule@submit-golden-slice@vecs0: - Statuses : 5 pass(s) - Exec time: [0.03] s * igt@gem_exec_schedule@submit-late-slice: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@gem_exec_schedule@submit-late-slice@bcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.03] s * igt@gem_exec_schedule@submit-late-slice@rcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.03] s * igt@gem_exec_schedule@submit-late-slice@vcs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.03] s * igt@gem_exec_schedule@submit-late-slice@vcs1: - Statuses : 2 pass(s) - Exec time: [0.03] s * igt@gem_exec_schedule@submit-late-slice@vecs0: - Statuses : 5 pass(s) - Exec time: [0.02, 0.03] s Known issues ------------ Here are the changes found in IGTPW_4602_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl7/igt@gem_workarounds@suspend-resume-context.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl6/igt@gem_workarounds@suspend-resume-context.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen: - shard-kbl: [PASS][3] -> [FAIL][4] ([i915#54] / [i915#93] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#52] / [i915#54] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl8/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid: - shard-kbl: [PASS][7] -> [FAIL][8] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html - shard-apl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-mid.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_setmode@basic: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#31]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl8/igt@kms_setmode@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl1/igt@kms_setmode@basic.html #### Possible fixes #### * igt@gem_ctx_persistence@engines-mixed-process@vecs0: - shard-apl: [FAIL][15] ([i915#1528]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl3/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl6/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][17] ([i915#1436] / [i915#716]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl4/igt@gen9_exec_parse@allowed-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl8/igt@gen9_exec_parse@allowed-all.html * igt@i915_pm_dc@dc5-psr: - shard-iclb: [FAIL][19] ([i915#1899]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-iclb7/igt@i915_pm_dc@dc5-psr.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-iclb1/igt@i915_pm_dc@dc5-psr.html - shard-tglb: [FAIL][21] ([i915#1899]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-tglb1/igt@i915_pm_dc@dc5-psr.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-tglb6/igt@i915_pm_dc@dc5-psr.html * igt@kms_big_fb@linear-32bpp-rotate-180: - shard-apl: [FAIL][23] ([i915#1119] / [i915#95]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl6/igt@kms_big_fb@linear-32bpp-rotate-180.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl4/igt@kms_big_fb@linear-32bpp-rotate-180.html - shard-kbl: [FAIL][25] ([i915#1119] / [i915#93] / [i915#95]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl7/igt@kms_big_fb@linear-32bpp-rotate-180.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl6/igt@kms_big_fb@linear-32bpp-rotate-180.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen: - shard-kbl: [FAIL][27] ([i915#54] / [i915#93] / [i915#95]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][29] ([fdo#109349]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-tglb: [FAIL][31] ([i915#1121]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][33] ([i915#180] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl1/igt@kms_frontbuffer_tracking@fbc-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_psr2_su@frontbuffer: - shard-tglb: [SKIP][35] -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-tglb5/igt@kms_psr2_su@frontbuffer.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-tglb7/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +3 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * {igt@perf@polling-parameterized}: - shard-tglb: [FAIL][41] ([i915#1542]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-tglb8/igt@perf@polling-parameterized.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-tglb5/igt@perf@polling-parameterized.html #### Warnings #### * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [INCOMPLETE][43] ([i915#155]) -> [DMESG-WARN][44] ([i915#180]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html * igt@kms_content_protection@atomic: - shard-apl: [TIMEOUT][45] ([i915#1319]) -> [FAIL][46] ([fdo#110321] / [fdo#110336]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl8/igt@kms_content_protection@atomic.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl4/igt@kms_content_protection@atomic.html * igt@kms_content_protection@atomic-dpms: - shard-apl: [FAIL][47] ([fdo#110321] / [fdo#110336] / [i915#95]) -> [FAIL][48] ([fdo#110321] / [fdo#110336]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl1/igt@kms_content_protection@atomic-dpms.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl6/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@legacy: - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl3/igt@kms_content_protection@legacy.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl8/igt@kms_content_protection@legacy.html * igt@kms_content_protection@lic: - shard-apl: [FAIL][51] ([fdo#110321]) -> [TIMEOUT][52] ([i915#1319]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl4/igt@kms_content_protection@lic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl7/igt@kms_content_protection@lic.html * igt@kms_fbcon_fbt@fbc: - shard-kbl: [FAIL][53] ([i915#1121] / [i915#93] / [i915#95]) -> [FAIL][54] ([i915#64]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl6/igt@kms_fbcon_fbt@fbc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl4/igt@kms_fbcon_fbt@fbc.html - shard-apl: [FAIL][55] ([i915#1121] / [i915#95]) -> [FAIL][56] ([i915#1525]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl4/igt@kms_fbcon_fbt@fbc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl6/igt@kms_fbcon_fbt@fbc.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][57] ([i915#1525]) -> [FAIL][58] ([i915#1121] / [i915#95]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html - shard-kbl: [FAIL][59] ([i915#64]) -> [FAIL][60] ([i915#1121] / [i915#93] / [i915#95]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-kbl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [FAIL][62] ([fdo#108145] / [i915#265] / [i915#93] / [i915#95]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8514/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#1121]: https://gitlab.freedesktop.org/drm/intel/issues/1121 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5664 -> IGTPW_4602 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_8514: c98b2ef26a5a946fd22839fce7dc4cc868f565fb @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4602: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/index.html IGT_5664: 404e2fa06b9c5986dec3fa210234fe8b034b157e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4602/index.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-05-21 11:50 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-20 16:29 [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Verify timeslicing between submit-fence Chris Wilson 2020-05-20 16:29 ` [igt-dev] " Chris Wilson 2020-05-20 18:11 ` [igt-dev] ✗ GitLab.Pipeline: failure for " Patchwork 2020-05-20 18:17 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork 2020-05-21 11:50 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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