* [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU
@ 2020-06-05 7:38 Bin Meng
2020-06-05 7:38 ` [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU Bin Meng
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Bin Meng @ 2020-06-05 7:38 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have exactly the same
codes for 32-bit and 64-bit base CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/cpu.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9007a25..d38d829 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -126,9 +126,7 @@ static void riscv_any_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void riscv_base32_cpu_init(Object *obj)
+static void riscv_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
@@ -136,6 +134,8 @@ static void riscv_base32_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
+#if defined(TARGET_RISCV32)
+
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
-static void riscv_base64_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- /* We set this in the realise function */
- set_misa(env, 0);
- set_resetvec(env, DEFAULT_RSTVEC);
-}
-
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -601,13 +593,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU
2020-06-05 7:38 [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU Bin Meng
@ 2020-06-05 7:38 ` Bin Meng
2020-06-10 22:52 ` Alistair Francis
2020-06-05 7:38 ` [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU Bin Meng
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Bin Meng @ 2020-06-05 7:38 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit gcsu CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/cpu.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d38d829..e66488f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -134,16 +134,16 @@ static void riscv_base_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
+static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
}
+#if defined(TARGET_RISCV32)
+
static void rv32imcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
-static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
-}
-
static void rv64imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -597,11 +589,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init),
#endif
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU
2020-06-05 7:38 [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU Bin Meng
2020-06-05 7:38 ` [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU Bin Meng
@ 2020-06-05 7:38 ` Bin Meng
2020-06-10 22:55 ` Alistair Francis
2020-06-05 7:38 ` [PATCH 4/4] riscv: Keep the CPU init routine names consistent Bin Meng
2020-06-10 22:50 ` Alistair Francis
3 siblings, 1 reply; 12+ messages in thread
From: Bin Meng @ 2020-06-05 7:38 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit imacu CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/cpu.c | 31 ++++++++++---------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e66488f..c5c2abc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -142,23 +142,23 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
}
-#if defined(TARGET_RISCV32)
-
-static void rv32imcu_nommu_cpu_init(Object *obj)
+static void rvnn_imacu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+ set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, 0x8090);
+ set_resetvec(env, DEFAULT_RSTVEC);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-static void rv32imacu_nommu_cpu_init(Object *obj)
+#if defined(TARGET_RISCV32)
+
+static void rv32imcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+ set_misa(env, RV32 | RVI | RVM | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
+ set_resetvec(env, 0x8090);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
@@ -171,17 +171,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-#elif defined(TARGET_RISCV64)
-
-static void rv64imacu_nommu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
- qdev_prop_set_bit(DEVICE(obj), "mmu", false);
-}
-
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -587,12 +576,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvnn_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init),
#endif
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/4] riscv: Keep the CPU init routine names consistent
2020-06-05 7:38 [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU Bin Meng
2020-06-05 7:38 ` [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU Bin Meng
2020-06-05 7:38 ` [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU Bin Meng
@ 2020-06-05 7:38 ` Bin Meng
2020-06-10 22:57 ` Alistair Francis
2020-06-10 22:50 ` Alistair Francis
3 siblings, 1 reply; 12+ messages in thread
From: Bin Meng @ 2020-06-05 7:38 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Adding a _ to keep some consistency among the CPU init routines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c5c2abc..5060534 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,7 +153,7 @@ static void rvnn_imacu_nommu_cpu_init(Object *obj)
#if defined(TARGET_RISCV32)
-static void rv32imcu_nommu_cpu_init(Object *obj)
+static void rv32_imcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
@@ -162,7 +162,7 @@ static void rv32imcu_nommu_cpu_init(Object *obj)
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-static void rv32imafcu_nommu_cpu_init(Object *obj)
+static void rv32_imafcu_nommu_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
@@ -575,9 +575,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU
2020-06-05 7:38 [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU Bin Meng
@ 2020-06-10 22:50 ` Alistair Francis
2020-06-05 7:38 ` [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU Bin Meng
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:50 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have exactly the same
> codes for 32-bit and 64-bit base CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/cpu.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9007a25..d38d829 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -126,9 +126,7 @@ static void riscv_any_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void riscv_base32_cpu_init(Object *obj)
> +static void riscv_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> @@ -136,6 +134,8 @@ static void riscv_base32_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> +#if defined(TARGET_RISCV32)
> +
> static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
>
> #elif defined(TARGET_RISCV64)
>
> -static void riscv_base64_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - /* We set this in the realise function */
> - set_misa(env, 0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> -}
> -
> static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -601,13 +593,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> },
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(TARGET_RISCV32)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> #endif
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU
@ 2020-06-10 22:50 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:50 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have exactly the same
> codes for 32-bit and 64-bit base CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/cpu.c | 18 +++++-------------
> 1 file changed, 5 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9007a25..d38d829 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -126,9 +126,7 @@ static void riscv_any_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void riscv_base32_cpu_init(Object *obj)
> +static void riscv_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> /* We set this in the realise function */
> @@ -136,6 +134,8 @@ static void riscv_base32_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> +#if defined(TARGET_RISCV32)
> +
> static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
>
> #elif defined(TARGET_RISCV64)
>
> -static void riscv_base64_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - /* We set this in the realise function */
> - set_misa(env, 0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> -}
> -
> static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -601,13 +593,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> },
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(TARGET_RISCV32)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> #endif
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU
2020-06-05 7:38 ` [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU Bin Meng
@ 2020-06-10 22:52 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:52 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Jun 5, 2020 at 12:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have almost the same
> codes for 32-bit and 64-bit gcsu CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> target/riscv/cpu.c | 20 ++++++--------------
> 1 file changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d38d829..e66488f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -134,16 +134,16 @@ static void riscv_base_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> +static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
Could we change the function names to rvxx_*?
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> +#if defined(TARGET_RISCV32)
> +
> static void rv32imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
>
> #elif defined(TARGET_RISCV64)
>
> -static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> -}
> -
> static void rv64imacu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -597,11 +589,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init),
> #endif
> };
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU
@ 2020-06-10 22:52 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:52 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Fri, Jun 5, 2020 at 12:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have almost the same
> codes for 32-bit and 64-bit gcsu CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> target/riscv/cpu.c | 20 ++++++--------------
> 1 file changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d38d829..e66488f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -134,16 +134,16 @@ static void riscv_base_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> +static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
Could we change the function names to rvxx_*?
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> +#if defined(TARGET_RISCV32)
> +
> static void rv32imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
>
> #elif defined(TARGET_RISCV64)
>
> -static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> -}
> -
> static void rv64imacu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -597,11 +589,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init),
> #endif
> };
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU
2020-06-05 7:38 ` [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU Bin Meng
@ 2020-06-10 22:55 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:55 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have almost the same
> codes for 32-bit and 64-bit imacu CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> target/riscv/cpu.c | 31 ++++++++++---------------------
> 1 file changed, 10 insertions(+), 21 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e66488f..c5c2abc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -142,23 +142,23 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void rv32imcu_nommu_cpu_init(Object *obj)
> +static void rvnn_imacu_nommu_cpu_init(Object *obj)
Same request with rvxx_*
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, 0x8090);
> + set_resetvec(env, DEFAULT_RSTVEC);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> -static void rv32imacu_nommu_cpu_init(Object *obj)
> +#if defined(TARGET_RISCV32)
> +
> +static void rv32imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
> + set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + set_resetvec(env, 0x8090);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> @@ -171,17 +171,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> -#elif defined(TARGET_RISCV64)
> -
> -static void rv64imacu_nommu_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> - qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> -}
> -
> #endif
>
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> @@ -587,12 +576,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvnn_imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init),
> #endif
> };
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU
@ 2020-06-10 22:55 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:55 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Fri, Jun 5, 2020 at 12:40 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to have two functions that have almost the same
> codes for 32-bit and 64-bit imacu CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> target/riscv/cpu.c | 31 ++++++++++---------------------
> 1 file changed, 10 insertions(+), 21 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e66488f..c5c2abc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -142,23 +142,23 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
> set_resetvec(env, DEFAULT_RSTVEC);
> }
>
> -#if defined(TARGET_RISCV32)
> -
> -static void rv32imcu_nommu_cpu_init(Object *obj)
> +static void rvnn_imacu_nommu_cpu_init(Object *obj)
Same request with rvxx_*
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, 0x8090);
> + set_resetvec(env, DEFAULT_RSTVEC);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> -static void rv32imacu_nommu_cpu_init(Object *obj)
> +#if defined(TARGET_RISCV32)
> +
> +static void rv32imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
> + set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + set_resetvec(env, 0x8090);
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> @@ -171,17 +171,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj)
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> -#elif defined(TARGET_RISCV64)
> -
> -static void rv64imacu_nommu_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> - qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> -}
> -
> #endif
>
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> @@ -587,12 +576,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvnn_imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvnn_gcsu_priv1_10_0_cpu_init),
> #endif
> };
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] riscv: Keep the CPU init routine names consistent
2020-06-05 7:38 ` [PATCH 4/4] riscv: Keep the CPU init routine names consistent Bin Meng
@ 2020-06-10 22:57 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:57 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Jun 5, 2020 at 12:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Adding a _ to keep some consistency among the CPU init routines.
We now differ from the actual ISA strings, but as these are internal
functions I don't think it matters. This seems clearer.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/cpu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c5c2abc..5060534 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -153,7 +153,7 @@ static void rvnn_imacu_nommu_cpu_init(Object *obj)
>
> #if defined(TARGET_RISCV32)
>
> -static void rv32imcu_nommu_cpu_init(Object *obj)
> +static void rv32_imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> @@ -162,7 +162,7 @@ static void rv32imcu_nommu_cpu_init(Object *obj)
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> -static void rv32imafcu_nommu_cpu_init(Object *obj)
> +static void rv32_imafcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
> @@ -575,9 +575,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] riscv: Keep the CPU init routine names consistent
@ 2020-06-10 22:57 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2020-06-10 22:57 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Fri, Jun 5, 2020 at 12:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Adding a _ to keep some consistency among the CPU init routines.
We now differ from the actual ISA strings, but as these are internal
functions I don't think it matters. This seems clearer.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/cpu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c5c2abc..5060534 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -153,7 +153,7 @@ static void rvnn_imacu_nommu_cpu_init(Object *obj)
>
> #if defined(TARGET_RISCV32)
>
> -static void rv32imcu_nommu_cpu_init(Object *obj)
> +static void rv32_imcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> @@ -162,7 +162,7 @@ static void rv32imcu_nommu_cpu_init(Object *obj)
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> -static void rv32imafcu_nommu_cpu_init(Object *obj)
> +static void rv32_imafcu_nommu_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
> @@ -575,9 +575,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
> #if defined(TARGET_RISCV32)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvnn_imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvnn_gcsu_priv1_10_0_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-06-10 23:07 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
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2020-06-05 7:38 [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU Bin Meng
2020-06-05 7:38 ` [PATCH 2/4] riscv: Generalize CPU init routine for the gcsu CPU Bin Meng
2020-06-10 22:52 ` Alistair Francis
2020-06-10 22:52 ` Alistair Francis
2020-06-05 7:38 ` [PATCH 3/4] riscv: Generalize CPU init routine for the imacu CPU Bin Meng
2020-06-10 22:55 ` Alistair Francis
2020-06-10 22:55 ` Alistair Francis
2020-06-05 7:38 ` [PATCH 4/4] riscv: Keep the CPU init routine names consistent Bin Meng
2020-06-10 22:57 ` Alistair Francis
2020-06-10 22:57 ` Alistair Francis
2020-06-10 22:50 ` [PATCH 1/4] riscv: Generalize CPU init routine for the base CPU Alistair Francis
2020-06-10 22:50 ` Alistair Francis
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