* [PATCH] drivers/perf: hisi: Fix wrong value for all counters enable
@ 2020-06-05 9:43 Shaokun Zhang
2020-06-08 15:17 ` Will Deacon
0 siblings, 1 reply; 3+ messages in thread
From: Shaokun Zhang @ 2020-06-05 9:43 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Shaokun Zhang, Mark Rutland, Will Deacon
In L3C uncore PMU drivers, bit16 is used to control all counters enable &
disable. Wrong value is given in the driver and its default value is 1'b1,
it can work because each PMU counter has its own control bits too.
Let's fix the wrong value.
Fixes: 2940bc433370 ("perf: hisi: Add support for HiSilicon SoC L3C PMU driver")
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
index 8dd1278bec04..7719ae4e2c56 100644
--- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
@@ -35,7 +35,7 @@
/* L3C has 8-counters */
#define L3C_NR_COUNTERS 0x8
-#define L3C_PERF_CTRL_EN 0x20000
+#define L3C_PERF_CTRL_EN 0x10000
#define L3C_EVTYPE_NONE 0xff
/*
--
2.7.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drivers/perf: hisi: Fix wrong value for all counters enable
2020-06-05 9:43 [PATCH] drivers/perf: hisi: Fix wrong value for all counters enable Shaokun Zhang
@ 2020-06-08 15:17 ` Will Deacon
2020-06-09 3:16 ` Shaokun Zhang
0 siblings, 1 reply; 3+ messages in thread
From: Will Deacon @ 2020-06-08 15:17 UTC (permalink / raw)
To: Shaokun Zhang, linux-arm-kernel
Cc: Mark Rutland, catalin.marinas, Will Deacon
On Fri, 5 Jun 2020 17:43:41 +0800, Shaokun Zhang wrote:
> In L3C uncore PMU drivers, bit16 is used to control all counters enable &
> disable. Wrong value is given in the driver and its default value is 1'b1,
> it can work because each PMU counter has its own control bits too.
> Let's fix the wrong value.
Applied to arm64 (for-next/core), thanks!
[1/1] drivers/perf: hisi: Fix wrong value for all counters enable
https://git.kernel.org/arm64/c/961abd78adcb
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drivers/perf: hisi: Fix wrong value for all counters enable
2020-06-08 15:17 ` Will Deacon
@ 2020-06-09 3:16 ` Shaokun Zhang
0 siblings, 0 replies; 3+ messages in thread
From: Shaokun Zhang @ 2020-06-09 3:16 UTC (permalink / raw)
To: Will Deacon, linux-arm-kernel; +Cc: Mark Rutland, catalin.marinas
Thanks Will.
在 2020/6/8 23:17, Will Deacon 写道:
> On Fri, 5 Jun 2020 17:43:41 +0800, Shaokun Zhang wrote:
>> In L3C uncore PMU drivers, bit16 is used to control all counters enable &
>> disable. Wrong value is given in the driver and its default value is 1'b1,
>> it can work because each PMU counter has its own control bits too.
>> Let's fix the wrong value.
>
> Applied to arm64 (for-next/core), thanks!
>
> [1/1] drivers/perf: hisi: Fix wrong value for all counters enable
> https://git.kernel.org/arm64/c/961abd78adcb
>
> Cheers,
>
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^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-06-09 3:16 UTC | newest]
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2020-06-05 9:43 [PATCH] drivers/perf: hisi: Fix wrong value for all counters enable Shaokun Zhang
2020-06-08 15:17 ` Will Deacon
2020-06-09 3:16 ` Shaokun Zhang
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