* [Intel-gfx] [PATCH v3] drm/i915/psr: Program default IO buffer Wake and Fast Wake
@ 2020-06-07 14:01 Gwan-gyeong Mun
2020-06-07 14:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3) Patchwork
2020-06-07 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
0 siblings, 2 replies; 3+ messages in thread
From: Gwan-gyeong Mun @ 2020-06-07 14:01 UTC (permalink / raw)
To: intel-gfx
The IO buffer Wake and Fast Wake bit size and value have been changed from
Gen12+. It programs the default value of IO buffer Wake and Fast Wake on
Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12
and Gen12+. And it aligns PSR2 definition macros.
v2: Fix macro definitions. (José)
v3: Addressed review comments from José
- Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+
- Change a style of macro naming in order to use lines as input.
- Update Todo comments.
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++---------
2 files changed, 49 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a0011e42e00..ab380e6dc674 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
val |= intel_psr2_get_tp_time(intel_dp);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /*
+ * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
+ * values from BSpec. In order to setting an optimal power
+ * consumption, lower than 4k resoluition mode needs to decrese
+ * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
+ * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
+ */
+ val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
+ val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
+ val |= TGL_EDP_PSR2_FAST_WAKE(7);
+ } else if (INTEL_GEN(dev_priv) >= 9) {
+ val |= EDP_PSR2_IO_BUFFER_WAKE(7);
+ val |= EDP_PSR2_FAST_WAKE(7);
+ }
+
/*
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
* recommending keep this bit unset while PSR2 is enabled.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 814a70945468..080ff728d047 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4511,25 +4511,39 @@ enum {
#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
-#define _PSR2_CTL_A 0x60900
-#define _PSR2_CTL_EDP 0x6f900
-#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
-#define EDP_PSR2_ENABLE (1 << 31)
-#define EDP_SU_TRACK_ENABLE (1 << 30)
-#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
-#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
-#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
-#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
-#define EDP_PSR2_TP2_TIME_500us (0 << 8)
-#define EDP_PSR2_TP2_TIME_100us (1 << 8)
-#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
-#define EDP_PSR2_TP2_TIME_50us (3 << 8)
-#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
-#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
-#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
-#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
-#define EDP_PSR2_IDLE_FRAME_MASK 0xf
-#define EDP_PSR2_IDLE_FRAME_SHIFT 0
+#define _PSR2_CTL_A 0x60900
+#define _PSR2_CTL_EDP 0x6f900
+#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
+#define EDP_PSR2_ENABLE (1 << 31)
+#define EDP_SU_TRACK_ENABLE (1 << 30)
+#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28)
+#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28)
+#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
+#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */
+#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20)
+#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20)
+#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8
+#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - lines) << 13)
+#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13)
+#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
+#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
+#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13)
+#define EDP_PSR2_FAST_WAKE_MAX_LINES 8
+#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - lines) << 11)
+#define EDP_PSR2_FAST_WAKE_MASK (3 << 11)
+#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5
+#define TGL_EDP_PSR2_FAST_WAKE(lines) ((lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
+#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)
+#define EDP_PSR2_TP2_TIME_500us (0 << 8)
+#define EDP_PSR2_TP2_TIME_100us (1 << 8)
+#define EDP_PSR2_TP2_TIME_2500us (2 << 8)
+#define EDP_PSR2_TP2_TIME_50us (3 << 8)
+#define EDP_PSR2_TP2_TIME_MASK (3 << 8)
+#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
+#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4)
+#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4)
+#define EDP_PSR2_IDLE_FRAME_MASK 0xf
+#define EDP_PSR2_IDLE_FRAME_SHIFT 0
#define _PSR_EVENT_TRANS_A 0x60848
#define _PSR_EVENT_TRANS_B 0x61848
--
2.25.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3)
2020-06-07 14:01 [Intel-gfx] [PATCH v3] drm/i915/psr: Program default IO buffer Wake and Fast Wake Gwan-gyeong Mun
@ 2020-06-07 14:20 ` Patchwork
2020-06-07 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2020-06-07 14:20 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3)
URL : https://patchwork.freedesktop.org/series/78019/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ffef3ca6c982 drm/i915/psr: Program default IO buffer Wake and Fast Wake
-:89: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues
#89: FILE: drivers/gpu/drm/i915/i915_reg.h:4526:
+#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - lines) << 13)
-:92: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#92: FILE: drivers/gpu/drm/i915/i915_reg.h:4529:
+#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
-:92: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues
#92: FILE: drivers/gpu/drm/i915/i915_reg.h:4529:
+#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
-:95: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues
#95: FILE: drivers/gpu/drm/i915/i915_reg.h:4532:
+#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - lines) << 11)
-:98: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues
#98: FILE: drivers/gpu/drm/i915/i915_reg.h:4535:
+#define TGL_EDP_PSR2_FAST_WAKE(lines) ((lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
total: 0 errors, 1 warnings, 4 checks, 80 lines checked
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3)
2020-06-07 14:01 [Intel-gfx] [PATCH v3] drm/i915/psr: Program default IO buffer Wake and Fast Wake Gwan-gyeong Mun
2020-06-07 14:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3) Patchwork
@ 2020-06-07 14:41 ` Patchwork
1 sibling, 0 replies; 3+ messages in thread
From: Patchwork @ 2020-06-07 14:41 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3)
URL : https://patchwork.freedesktop.org/series/78019/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8596 -> Patchwork_17898
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/index.html
Known issues
------------
Here are the changes found in Patchwork_17898 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-tgl-dsi/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-tgl-dsi/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-guc: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-guc/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-icl-guc/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
- fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92]) -> [DMESG-WARN][8] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (49 -> 41)
------------------------------
Missing (8): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8596 -> Patchwork_17898
CI-20190529: 20190529
CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17898: ffef3ca6c9829bcbb8086649350ba11085e3aa55 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ffef3ca6c982 drm/i915/psr: Program default IO buffer Wake and Fast Wake
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/index.html
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-- links below jump to the message on this page --
2020-06-07 14:01 [Intel-gfx] [PATCH v3] drm/i915/psr: Program default IO buffer Wake and Fast Wake Gwan-gyeong Mun
2020-06-07 14:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3) Patchwork
2020-06-07 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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