* [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
@ 2020-06-25 10:31 ` Sai Prakash Ranjan
0 siblings, 0 replies; 6+ messages in thread
From: Sai Prakash Ranjan @ 2020-06-25 10:31 UTC (permalink / raw)
To: Will Deacon, Catalin Marinas, Mark Rutland, Douglas Anderson,
Stephen Boyd
Cc: Jeffrey Hugo, linux-kernel, linux-arm-kernel, linux-arm-msm,
Sai Prakash Ranjan
QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
Cortex-A55 and are SSB safe, hence add them to SSB
safelist -> arm64_ssb_cpus[].
Reported-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
arch/arm64/kernel/cpu_errata.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index ad06d6802d2e..cf50c53e9357 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -460,6 +460,8 @@ static const struct midr_range arm64_ssb_cpus[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
+ MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
+ MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
{},
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
@ 2020-06-25 10:31 ` Sai Prakash Ranjan
0 siblings, 0 replies; 6+ messages in thread
From: Sai Prakash Ranjan @ 2020-06-25 10:31 UTC (permalink / raw)
To: Will Deacon, Catalin Marinas, Mark Rutland, Douglas Anderson,
Stephen Boyd
Cc: Jeffrey Hugo, linux-arm-msm, Sai Prakash Ranjan, linux-kernel,
linux-arm-kernel
QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
Cortex-A55 and are SSB safe, hence add them to SSB
safelist -> arm64_ssb_cpus[].
Reported-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
arch/arm64/kernel/cpu_errata.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index ad06d6802d2e..cf50c53e9357 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -460,6 +460,8 @@ static const struct midr_range arm64_ssb_cpus[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
+ MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
+ MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
{},
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
2020-06-25 10:31 ` Sai Prakash Ranjan
@ 2020-06-25 13:48 ` Doug Anderson
-1 siblings, 0 replies; 6+ messages in thread
From: Doug Anderson @ 2020-06-25 13:48 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Will Deacon, Catalin Marinas, Mark Rutland, Stephen Boyd,
Jeffrey Hugo, LKML, Linux ARM, linux-arm-msm
Hi,
On Thu, Jun 25, 2020 at 3:31 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
> Cortex-A55 and are SSB safe, hence add them to SSB
> safelist -> arm64_ssb_cpus[].
>
> Reported-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> arch/arm64/kernel/cpu_errata.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index ad06d6802d2e..cf50c53e9357 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -460,6 +460,8 @@ static const struct midr_range arm64_ssb_cpus[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
> MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
@ 2020-06-25 13:48 ` Doug Anderson
0 siblings, 0 replies; 6+ messages in thread
From: Doug Anderson @ 2020-06-25 13:48 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mark Rutland, Jeffrey Hugo, Catalin Marinas, LKML, Stephen Boyd,
linux-arm-msm, Will Deacon, Linux ARM
Hi,
On Thu, Jun 25, 2020 at 3:31 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
> Cortex-A55 and are SSB safe, hence add them to SSB
> safelist -> arm64_ssb_cpus[].
>
> Reported-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> arch/arm64/kernel/cpu_errata.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index ad06d6802d2e..cf50c53e9357 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -460,6 +460,8 @@ static const struct midr_range arm64_ssb_cpus[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
> MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
> + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
Reviewed-by: Douglas Anderson <dianders@chromium.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
2020-06-25 10:31 ` Sai Prakash Ranjan
@ 2020-06-25 19:22 ` Will Deacon
-1 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2020-06-25 19:22 UTC (permalink / raw)
To: Douglas Anderson, Stephen Boyd, Sai Prakash Ranjan, Mark Rutland,
Catalin Marinas
Cc: kernel-team, Will Deacon, linux-kernel, Jeffrey Hugo,
linux-arm-kernel, linux-arm-msm
On Thu, 25 Jun 2020 16:01:23 +0530, Sai Prakash Ranjan wrote:
> QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
> Cortex-A55 and are SSB safe, hence add them to SSB
> safelist -> arm64_ssb_cpus[].
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
https://git.kernel.org/arm64/c/108447fd0d1a
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
@ 2020-06-25 19:22 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2020-06-25 19:22 UTC (permalink / raw)
To: Douglas Anderson, Stephen Boyd, Sai Prakash Ranjan, Mark Rutland,
Catalin Marinas
Cc: Jeffrey Hugo, kernel-team, linux-kernel, linux-arm-msm,
Will Deacon, linux-arm-kernel
On Thu, 25 Jun 2020 16:01:23 +0530, Sai Prakash Ranjan wrote:
> QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
> Cortex-A55 and are SSB safe, hence add them to SSB
> safelist -> arm64_ssb_cpus[].
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist
https://git.kernel.org/arm64/c/108447fd0d1a
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-26 13:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-25 10:31 [PATCH] arm64: Add KRYO{3,4}XX silver CPU cores to SSB safelist Sai Prakash Ranjan
2020-06-25 10:31 ` Sai Prakash Ranjan
2020-06-25 13:48 ` Doug Anderson
2020-06-25 13:48 ` Doug Anderson
2020-06-25 19:22 ` Will Deacon
2020-06-25 19:22 ` Will Deacon
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.