[igt-dev] [PATCH i-g-t 0/4] Remove libdrm dependency from gem_[caching/hang]

[igt-dev] [PATCH i-g-t 0/4] Remove libdrm dependency from gem_[caching/hang]

[Dominik Grzegorzek]

This series contains a smaller portion of Zbigniew's changes in intel_bb
and intel_buf needed for this libdrm removal. Removal libdrm dependency from
gem_hang made by git rm :).

Dominik Grzegorzek (2):
  i915/gem_caching: Remove libdrm dependency
  i915/gem_hang: Removal

Zbigniew Kempczyński (2):
  lib/intel_bufops: Add intel_buf create/destroy functions
  lib/intel_batchbuffer: Extend intel_bb

 lib/intel_batchbuffer.c  | 189 +++++++++++++++++++++++++++++++++++----
 lib/intel_batchbuffer.h  |  12 +++
 lib/intel_bufops.c       |  32 ++++++-
 lib/intel_bufops.h       |   8 +-
 tests/i915/gem_caching.c | 174 +++++++++++++++++++++--------------
 tests/i915/gem_hang.c    |  98 --------------------
 tests/meson.build        |   1 -
 7 files changed, 325 insertions(+), 189 deletions(-)
 delete mode 100644 tests/i915/gem_hang.c

-- 
2.20.1

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[igt-dev] [PATCH i-g-t 1/4] lib/intel_bufops: Add intel_buf create/destroy functions

[Dominik Grzegorzek]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Add create/destroy of intel_buf objects to fill the API gap.

Change function name to be more consistent with other functions names:
buf_ops_getfd() -> buf_ops_get_fd()

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_bufops.c | 32 ++++++++++++++++++++++++++++----
 lib/intel_bufops.h |  8 +++++++-
 2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 0337b638..8bbb8b12 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -697,7 +697,6 @@ static void __intel_buf_init(struct buf_ops *bops,
 		igt_require(bops->intel_gen >= 9);
 		igt_assert(req_tiling == I915_TILING_Y ||
 			   req_tiling == I915_TILING_Yf);
-
 		/*
 		 * On GEN12+ we align the main surface to 4 * 4 main surface
 		 * tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
@@ -724,7 +723,6 @@ static void __intel_buf_init(struct buf_ops *bops,
 		buf->aux.stride = aux_width;
 
 		size = buf->aux.offset + aux_width * aux_height;
-
 	} else {
 		if (buf->tiling) {
 			devid =  intel_get_drm_devid(bops->fd);
@@ -826,6 +824,32 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
 			 req_tiling, compression);
 }
 
+struct intel_buf *intel_buf_create(struct buf_ops *bops,
+				   int width, int height,
+				   int bpp, int alignment,
+				   uint32_t req_tiling, uint32_t compression)
+{
+	struct intel_buf *buf;
+
+	igt_assert(bops);
+
+	buf = calloc(1, sizeof(*buf));
+	igt_assert(buf);
+
+	intel_buf_init(bops, buf, width, height, bpp, alignment,
+		       req_tiling, compression);
+
+	return buf;
+}
+
+void intel_buf_destroy(struct intel_buf *buf)
+{
+	igt_assert(buf);
+
+	intel_buf_close(buf->bops, buf);
+	free(buf);
+}
+
 #define DEFAULT_BUFOPS(__gen_start, __gen_end) \
 	.gen_start          = __gen_start, \
 	.gen_end            = __gen_end, \
@@ -1061,12 +1085,12 @@ void buf_ops_destroy(struct buf_ops *bops)
 }
 
 /**
- * buf_ops_getfd
+ * buf_ops_get_fd
  * @bops: pointer to buf_ops
  *
  * Returns: drm fd
  */
-int buf_ops_getfd(struct buf_ops *bops)
+int buf_ops_get_fd(struct buf_ops *bops)
 {
 	igt_assert(bops);
 
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 95217cfe..327ac92e 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -64,7 +64,7 @@ intel_buf_aux_height(int gen, const struct intel_buf *buf)
 
 struct buf_ops *buf_ops_create(int fd);
 void buf_ops_destroy(struct buf_ops *bops);
-int buf_ops_getfd(struct buf_ops *bops);
+int buf_ops_get_fd(struct buf_ops *bops);
 
 bool buf_ops_set_software_tiling(struct buf_ops *bops,
 				 uint32_t tiling,
@@ -90,4 +90,10 @@ void intel_buf_init_using_handle(struct buf_ops *bops,
 				 int width, int height, int bpp, int alignment,
 				 uint32_t req_tiling, uint32_t compression);
 
+struct intel_buf *intel_buf_create(struct buf_ops *bops,
+				   int width, int height,
+				   int bpp, int alignment,
+				   uint32_t req_tiling, uint32_t compression);
+void intel_buf_destroy(struct intel_buf *buf);
+
 #endif
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 2/4] lib/intel_batchbuffer: Extend intel_bb

[Dominik Grzegorzek]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

As we're going toward removing libdrm from rendercopy tests some
additional code in intel_bb is required. So add new functions
and fix memory issues in the reset path.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 189 ++++++++++++++++++++++++++++++++++++----
 lib/intel_batchbuffer.h |  12 +++
 2 files changed, 185 insertions(+), 16 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 2a882627..c041465d 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1250,24 +1250,32 @@ static void __do_nothing(void *node)
 	(void) node;
 }
 
-static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+static void __intel_bb_destroy_relocations(struct intel_bb *ibb)
 {
 	uint32_t i;
 
 	/* Free relocations */
-	for (i = 0; i < ibb->num_objects; i++)
+	for (i = 0; i < ibb->num_objects; i++) {
 		free(from_user_pointer(ibb->objects[i].relocs_ptr));
+		ibb->objects[i].relocs_ptr = to_user_pointer(NULL);
+		ibb->objects[i].relocation_count = 0;
+	}
 
-	free(ibb->objects);
-	tdestroy(ibb->root, __do_nothing);
+	ibb->relocs = NULL;
+	ibb->num_relocs = 0;
+	ibb->allocated_relocs = 0;
+}
 
+static void __intel_bb_destroy_objects(struct intel_bb *ibb)
+{
+	free(ibb->objects);
 	ibb->objects = NULL;
+
+	tdestroy(ibb->root, __do_nothing);
 	ibb->root = NULL;
+
 	ibb->num_objects = 0;
-	ibb->num_relocs = 0;
 	ibb->allocated_objects = 0;
-	ibb->allocated_relocs = 0;
-	ibb->ptr = ibb->batch;
 }
 
 /**
@@ -1280,6 +1288,7 @@ void intel_bb_destroy(struct intel_bb *ibb)
 {
 	igt_assert(ibb);
 
+	__intel_bb_destroy_relocations(ibb);
 	__intel_bb_destroy_objects(ibb);
 	gem_close(ibb->i915, ibb->handle);
 
@@ -1295,6 +1304,8 @@ void intel_bb_destroy(struct intel_bb *ibb)
 */
 void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 {
+	__intel_bb_destroy_relocations(ibb);
+
 	if (purge_objects_cache) {
 		__intel_bb_destroy_objects(ibb);
 		__reallocate_objects(ibb);
@@ -1305,6 +1316,61 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 
 	intel_bb_add_object(ibb, ibb->handle, 0, false);
 	ibb->ptr = ibb->batch;
+	memset(ibb->batch, 0, ibb->size);
+}
+
+/*
+ * intel_bb_sync:
+ * @ibb: pointer to intel_bb
+ *
+ * Waits for bb completion.
+ */
+void intel_bb_sync(struct intel_bb *ibb)
+{
+	gem_sync(ibb->i915, ibb->handle);
+}
+
+/*
+ * intel_bb_print:
+ * @ibb: pointer to intel_bb
+ *
+ * Prints batch to stdout.
+ */
+void intel_bb_print(struct intel_bb *ibb)
+{
+	igt_info("drm fd: %d, gen: %d, devid: %u, debug: %d\n",
+		 ibb->i915, ibb->gen, ibb->devid, ibb->debug);
+	igt_info("handle: %u, size: %u, batch: %p, ptr: %p\n",
+		 ibb->handle, ibb->size, ibb->batch, ibb->ptr);
+	igt_info("prng: %u, gtt_size: %" PRIu64 ", supports 48bit: %d\n",
+		 ibb->prng, ibb->gtt_size, ibb->supports_48b_address);
+	igt_info("ctx: %u\n", ibb->ctx);
+	igt_info("root: %p\n", ibb->root);
+	igt_info("objects: %p, num_objects: %u, allocated obj: %u\n",
+		 ibb->objects, ibb->num_objects, ibb->allocated_objects);
+	igt_info("relocs: %p, num_relocs: %u, allocated_relocs: %u\n----\n",
+		 ibb->relocs, ibb->num_relocs, ibb->allocated_relocs);
+}
+
+/*
+ * intel_bb_dump:
+ * @ibb: pointer to intel_bb
+ * @filename: name to which write bb
+ *
+ * Dump batch bo to file.
+ */
+void intel_bb_dump(struct intel_bb *ibb, const char *filename)
+{
+	FILE *out;
+	void *ptr;
+
+	ptr = gem_mmap__device_coherent(ibb->i915, ibb->handle, 0, ibb->size,
+					PROT_READ);
+	out = fopen(filename, "wb");
+	igt_assert(out);
+	fwrite(ptr, ibb->size, 1, out);
+	fclose(out);
+	munmap(ptr, ibb->size);
 }
 
 /**
@@ -1382,6 +1448,23 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle,
 	return object;
 }
 
+static bool intel_bb_object_set_fence(struct intel_bb *ibb, uint32_t handle)
+{
+	struct drm_i915_gem_exec_object2 object = { .handle = handle };
+	struct drm_i915_gem_exec_object2 **found;
+
+	found = tfind((void *) &object, &ibb->root, __compare_objects);
+	if (!found) {
+		igt_warn("Trying to set fence on not found handle: %u\n",
+			 handle);
+		return false;
+	}
+
+	(*found)->flags |= EXEC_OBJECT_NEEDS_FENCE;
+
+	return true;
+}
+
 /*
  * intel_bb_add_reloc:
  * @ibb: pointer to intel_bb
@@ -1431,9 +1514,10 @@ static uint64_t intel_bb_add_reloc(struct intel_bb *ibb,
 	igt_debug("add reloc: handle: %u, r/w: 0x%x/0x%x, "
 		  "delta: 0x%" PRIx64 ", "
 		  "offset: 0x%" PRIx64 ", "
-		  "poffset: 0x%" PRIx64 "\n",
+		  "poffset: %p\n",
 		  handle, read_domains, write_domain,
-		  delta, offset, presumed_offset);
+		  delta, offset,
+		  from_user_pointer(relocs[i].presumed_offset));
 
 	return object->offset;
 }
@@ -1479,6 +1563,38 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
 	return address;
 }
 
+/**
+ * intel_bb_emit_reloc_fenced:
+ * @ibb: pointer to intel_bb
+ * @handle: object handle which address will be taken to patch the bb
+ * @read_domains: gem domain bits for the relocation
+ * @write_domain: gem domain bit for the relocation
+ * @delta: delta value to add to @buffer's gpu address
+ * @presumed_offset: address of the object in address space, important for
+ * I915_EXEC_NO_RELOC flag
+ * @write: does a handle is a render target
+ *
+ * Function works similar to intel_bb_emit_reloc but additionally marks an
+ * object with EXEC_OBJECT_NEEDS_FENCE to ensure appropriate fence will
+ * be configured when it is required on older gens.
+ */
+uint64_t intel_bb_emit_reloc_fenced(struct intel_bb *ibb,
+				    uint32_t handle,
+				    uint32_t read_domains,
+				    uint32_t write_domain,
+				    uint64_t delta,
+				    uint64_t presumed_offset)
+{
+	uint64_t address;
+
+	address = intel_bb_emit_reloc(ibb, handle, read_domains, write_domain,
+				      delta, presumed_offset);
+
+	intel_bb_object_set_fence(ibb, handle);
+
+	return address;
+}
+
 /**
  * intel_bb_offset_reloc:
  * @ibb: pointer to intel_bb
@@ -1509,7 +1625,8 @@ uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
 				  0, offset, presumed_offset);
 }
 
-static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
+static void intel_bb_dump_execbuf(struct intel_bb *ibb,
+				  struct drm_i915_gem_execbuffer2 *execbuf)
 {
 	struct drm_i915_gem_exec_object2 *objects;
 	struct drm_i915_gem_relocation_entry *relocs, *reloc;
@@ -1535,7 +1652,8 @@ static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
 			 i, objects->handle, objects->relocation_count,
 			 relocs,
 			 objects->alignment,
-			 objects->offset, objects->flags,
+			 objects->offset & (ibb->gtt_size - 1),
+			 objects->flags,
 			 objects->rsvd1, objects->rsvd2);
 		if (objects->relocation_count) {
 			igt_info("\texecbuf relocs:\n");
@@ -1548,7 +1666,7 @@ static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
 					 "write_domain: 0x%x\n",
 					 j, reloc->target_handle,
 					 reloc->offset, reloc->delta,
-					 reloc->presumed_offset,
+					 reloc->presumed_offset & (ibb->gtt_size - 1),
 					 reloc->read_domains,
 					 reloc->write_domain);
 			}
@@ -1609,14 +1727,16 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	execbuf.flags = flags | I915_EXEC_BATCH_FIRST;
 
 	ret = __gem_execbuf(ibb->i915, &execbuf);
-	if (ret)
+	if (ret) {
+		intel_bb_dump_execbuf(ibb, &execbuf);
 		return ret;
+	}
 
 	if (sync || ibb->debug)
 		gem_sync(ibb->i915, ibb->handle);
 
 	if (ibb->debug) {
-		intel_bb_dump_execbuf(&execbuf);
+		intel_bb_dump_execbuf(ibb, &execbuf);
 		if (intel_bb_debug_tree) {
 			igt_info("\nTree:\n");
 			twalk(ibb->root, print_node);
@@ -1679,7 +1799,7 @@ uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle)
 	if (!found)
 		return 0;
 
-	return (*found)->offset;
+	return (*found)->offset & (ibb->gtt_size - 1);
 }
 
 /**
@@ -1706,8 +1826,45 @@ bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf)
 		return false;
 	}
 
-	buf->addr.offset = (*found)->offset;
+	buf->addr.offset = (*found)->offset & (ibb->gtt_size - 1);
 	buf->addr.ctx = ibb->ctx;
 
 	return true;
 }
+
+/*
+ * intel_bb_out_flush:
+ * @ibb: batchbuffer
+ *
+ * Outputs flushing code to the batch.
+ */
+#define CMD_POLY_STIPPLE_OFFSET       0x7906
+uint32_t intel_bb_out_flush(struct intel_bb *ibb)
+{
+	if (intel_bb_offset(ibb) == 0)
+		return 0;
+
+	if (ibb->gen == 5) {
+		intel_bb_out(ibb, CMD_POLY_STIPPLE_OFFSET << 16);
+		intel_bb_out(ibb, 0);
+	}
+
+	/* Round batchbuffer usage to 2 DWORDs. */
+	intel_bb_ptr_align(ibb, 8);
+
+	if (ibb->gen <= 4) {
+		intel_bb_out(ibb, MI_FLUSH);
+	} else {
+		intel_bb_out(ibb, MI_FLUSH_DW | 2);
+		intel_bb_out(ibb, 0);
+		intel_bb_out(ibb, 0);
+		intel_bb_out(ibb, 0);
+	}
+
+	/* Mark the end of the buffer. */
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END); /* noop */
+	intel_bb_out(ibb, 0);
+
+	return intel_bb_offset(ibb);
+}
+
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 0649fc22..2ced3ea6 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -460,6 +460,9 @@ struct intel_bb *intel_bb_create(int i915, uint32_t size);
 
 void intel_bb_destroy(struct intel_bb *ibb);
 void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache);
+void intel_bb_sync(struct intel_bb *ibb);
+void intel_bb_print(struct intel_bb *ibb);
+void intel_bb_dump(struct intel_bb *ibb, const char *filename);
 void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
 
 static inline uint32_t intel_bb_offset(struct intel_bb *ibb)
@@ -510,6 +513,13 @@ uint64_t intel_bb_emit_reloc(struct intel_bb *ibb,
 			 uint64_t delta,
 			 uint64_t presumed_offset);
 
+uint64_t intel_bb_emit_reloc_fenced(struct intel_bb *ibb,
+				    uint32_t handle,
+				    uint32_t read_domains,
+				    uint32_t write_domain,
+				    uint64_t delta,
+				    uint64_t presumed_offset);
+
 uint64_t intel_bb_offset_reloc(struct intel_bb *ibb,
 			       uint32_t handle,
 			       uint32_t read_domains,
@@ -529,4 +539,6 @@ void intel_bb_exec_with_context(struct intel_bb *ibb, uint32_t end_offset,
 uint64_t intel_bb_get_object_offset(struct intel_bb *ibb, uint32_t handle);
 bool intel_bb_object_offset_to_buf(struct intel_bb *ibb, struct intel_buf *buf);
 
+uint32_t intel_bb_out_flush(struct intel_bb *ibb);
+
 #endif
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 3/4] i915/gem_caching: Remove libdrm dependency

[Dominik Grzegorzek]

Thanks to intel_bb we are able to remove libdrm from gem_caching.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_caching.c | 174 +++++++++++++++++++++++----------------
 1 file changed, 105 insertions(+), 69 deletions(-)

diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index 0ffffa05..4a615bb8 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -39,7 +39,6 @@
 
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test snoop consistency when touching partial"
 		     " cachelines.");
@@ -49,50 +48,81 @@ IGT_TEST_DESCRIPTION("Test snoop consistency when touching partial"
  *
  */
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-
-drm_intel_bo *scratch_bo;
-drm_intel_bo *staging_bo;
 #define BO_SIZE (4*4096)
-uint32_t devid;
-int fd;
+#define PAGE_SIZE 4096
+
+typedef struct {
+	int fd;
+	uint32_t devid;
+	struct buf_ops *bops;
+} data_t;
+
+
+static void *__try_gtt_map_first(data_t *data, struct intel_buf *buf,
+				 int write_enable)
+{
+	uint8_t *ptr;
+	unsigned int prot = PROT_READ | (write_enable ? PROT_WRITE : 0);
+
+	ptr = __gem_mmap__gtt(data->fd, buf->handle, buf->size, prot);
+	if (!ptr) {
+		ptr = gem_mmap__device_coherent(data->fd, buf->handle,
+					  0, buf->size,  prot);
+	}
+	return ptr;
+}
 
 static void
-copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
+copy_bo(struct intel_bb *ibb, struct intel_buf *src, struct intel_buf *dst)
 {
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
-		  (0xcc << 16) | /* copy ROP */
-		  4096);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
-	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(4096);
-	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
+	bool has_64b_reloc;
+
+	has_64b_reloc = ibb->gen >= 8;
+
+	intel_bb_out(ibb,
+		     XY_SRC_COPY_BLT_CMD |
+		     XY_SRC_COPY_BLT_WRITE_ALPHA |
+		     XY_SRC_COPY_BLT_WRITE_RGB |
+		     (6 + 2 * has_64b_reloc));
+
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
+		     (0xcc << 16) | /* copy ROP */
+		     4096);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, (BO_SIZE/4096) << 16 | 1024);
+	intel_bb_emit_reloc_fenced(ibb, dst->handle,
+				   I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER,
+				   0, 0x0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, 4096);
+	intel_bb_emit_reloc_fenced(ibb, src->handle,
+				   I915_GEM_DOMAIN_RENDER,
+				   0, 0, 0x0);
+
+	intel_bb_out_flush(ibb);
+	intel_bb_exec(ibb, intel_bb_offset(ibb),
+		      ibb->gen >= 6 ? I915_EXEC_BLT : 0, true);
+	intel_bb_reset(ibb, false);
 }
 
 static void
-blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
+blt_bo_fill(data_t *data, struct intel_bb *ibb, struct intel_buf *tmp_bo,
+	    struct intel_buf *bo, uint8_t val)
 {
 	uint8_t *gtt_ptr;
 	int i;
 
-	do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
-	gtt_ptr = tmp_bo->virtual;
+	gtt_ptr = __try_gtt_map_first(data, tmp_bo, 1);
 
 	for (i = 0; i < BO_SIZE; i++)
 		gtt_ptr[i] = val;
 
-	drm_intel_gem_bo_unmap_gtt(tmp_bo);
+	munmap(gtt_ptr, tmp_bo->size);
 
-	igt_drop_caches_set(fd, DROP_BOUND);
+	igt_drop_caches_set(data->fd, DROP_BOUND);
 
-	copy_bo(tmp_bo, bo);
+	copy_bo(ibb, tmp_bo, bo);
 }
 
 #define MAX_BLT_SIZE 128
@@ -102,6 +132,9 @@ blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
 #define TEST_BOTH (TEST_READ | TEST_WRITE)
 igt_main
 {
+	struct intel_buf *scratch_buf, *staging_buf;
+	struct intel_bb *ibb;
+	data_t data = {0, };
 	unsigned flags = TEST_BOTH;
 	int i, j;
 	uint8_t *cpu_ptr;
@@ -110,29 +143,30 @@ igt_main
 	igt_fixture {
 		srandom(0xdeadbeef);
 
-		fd = drm_open_driver(DRIVER_INTEL);
+		data.fd = drm_open_driver(DRIVER_INTEL);
 
-		igt_require_gem(fd);
-		gem_require_blitter(fd);
-		gem_require_caching(fd);
+		igt_require_gem(data.fd);
+		gem_require_blitter(data.fd);
+		gem_require_caching(data.fd);
 
-		devid = intel_get_drm_devid(fd);
-		if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
+		data.devid = intel_get_drm_devid(data.fd);
+		if (IS_GEN2(data.devid)) /* chipset only handles cached -> uncached */
 			flags &= ~TEST_READ;
-		if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
+		if (IS_BROADWATER(data.devid) || IS_CRESTLINE(data.devid)) {
 			/* chipset is completely fubar */
 			igt_info("coherency broken on i965g/gm\n");
 			flags = 0;
 		}
+		data.bops = buf_ops_create(data.fd);
+		ibb = intel_bb_create(data.fd, PAGE_SIZE);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
+		scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
+					       32, 0, I915_TILING_NONE, 0);
 
-		/* overallocate the buffers we're actually using because */
-		scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
-		gem_set_caching(fd, scratch_bo->handle, 1);
+		gem_set_caching(data.fd, scratch_buf->handle, 1);
 
-		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
+		staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
+					       32, 0, I915_TILING_NONE, 0);
 	}
 
 	igt_subtest("reads") {
@@ -144,19 +178,19 @@ igt_main
 			uint8_t val0 = i;
 			int start, len;
 
-			blt_bo_fill(staging_bo, scratch_bo, i);
+			blt_bo_fill(&data, ibb, staging_buf, scratch_buf, i);
 
 			start = random() % BO_SIZE;
 			len = random() % (BO_SIZE-start) + 1;
 
-			drm_intel_bo_map(scratch_bo, false);
-			cpu_ptr = scratch_bo->virtual;
+			cpu_ptr = gem_mmap__cpu(data.fd, scratch_buf->handle,
+						0, scratch_buf->size, PROT_READ);
 			for (j = 0; j < len; j++) {
 				igt_assert_f(cpu_ptr[j] == val0,
 					     "mismatch at %i, got: %i, expected: %i\n",
 					     j, cpu_ptr[j], val0);
 			}
-			drm_intel_bo_unmap(scratch_bo);
+			munmap(cpu_ptr, scratch_buf->size);
 
 			igt_progress("partial reads test: ", i, ROUNDS);
 		}
@@ -171,20 +205,19 @@ igt_main
 			uint8_t val0 = i, val1;
 			int start, len;
 
-			blt_bo_fill(staging_bo, scratch_bo, val0);
+			blt_bo_fill(&data, ibb, staging_buf, scratch_buf, val0);
 
 			start = random() % BO_SIZE;
 			len = random() % (BO_SIZE-start) + 1;
 
 			val1 = val0 + 63;
-			drm_intel_bo_map(scratch_bo, true);
-			cpu_ptr = scratch_bo->virtual;
-			memset(cpu_ptr + start, val1, len);
-			drm_intel_bo_unmap(scratch_bo);
+			cpu_ptr = gem_mmap__cpu(data.fd, scratch_buf->handle,
+						0, scratch_buf->size, PROT_READ | PROT_WRITE);
 
-			copy_bo(scratch_bo, staging_bo);
-			do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
-			gtt_ptr = staging_bo->virtual;
+			memset(cpu_ptr + start, val1, len);
+			munmap(cpu_ptr, scratch_buf->size);
+			copy_bo(ibb, scratch_buf, staging_buf);
+			gtt_ptr = __try_gtt_map_first(&data, staging_buf, 0);
 
 			for (j = 0; j < start; j++) {
 				igt_assert_f(gtt_ptr[j] == val0,
@@ -201,7 +234,7 @@ igt_main
 					     "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 					     j, start, len, gtt_ptr[j], val0);
 			}
-			drm_intel_gem_bo_unmap_gtt(staging_bo);
+			munmap(gtt_ptr, staging_buf->size);
 
 			igt_progress("partial writes test: ", i, ROUNDS);
 		}
@@ -216,38 +249,39 @@ igt_main
 			uint8_t val0 = i, val1, val2;
 			int start, len;
 
-			blt_bo_fill(staging_bo, scratch_bo, val0);
+			blt_bo_fill(&data, ibb, staging_buf, scratch_buf, val0);
 
 			/* partial read */
 			start = random() % BO_SIZE;
 			len = random() % (BO_SIZE-start) + 1;
 
-			do_or_die(drm_intel_bo_map(scratch_bo, false));
-			cpu_ptr = scratch_bo->virtual;
+			cpu_ptr = gem_mmap__cpu(data.fd, scratch_buf->handle,
+						0, scratch_buf->size, PROT_READ);
+
 			for (j = 0; j < len; j++) {
 				igt_assert_f(cpu_ptr[j] == val0,
 					     "mismatch in read at %i, got: %i, expected: %i\n",
 					     j, cpu_ptr[j], val0);
 			}
-			drm_intel_bo_unmap(scratch_bo);
+			munmap(cpu_ptr, scratch_buf->size);
 
 			/* Change contents through gtt to make the pread cachelines
 			 * stale. */
 			val1 = i + 17;
-			blt_bo_fill(staging_bo, scratch_bo, val1);
+			blt_bo_fill(&data, ibb, staging_buf, scratch_buf, val1);
 
 			/* partial write */
 			start = random() % BO_SIZE;
 			len = random() % (BO_SIZE-start) + 1;
 
 			val2 = i + 63;
-			do_or_die(drm_intel_bo_map(scratch_bo, false));
-			cpu_ptr = scratch_bo->virtual;
+			cpu_ptr = gem_mmap__cpu(data.fd, scratch_buf->handle,
+						0, scratch_buf->size, PROT_READ);
+
 			memset(cpu_ptr + start, val2, len);
 
-			copy_bo(scratch_bo, staging_bo);
-			do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
-			gtt_ptr = staging_bo->virtual;
+			copy_bo(ibb, scratch_buf, staging_buf);
+			gtt_ptr = __try_gtt_map_first(&data, staging_buf, 0);
 
 			for (j = 0; j < start; j++) {
 				igt_assert_f(gtt_ptr[j] == val1,
@@ -264,16 +298,18 @@ igt_main
 					     "mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
 					     j, start, len, gtt_ptr[j], val1);
 			}
-			drm_intel_gem_bo_unmap_gtt(staging_bo);
-			drm_intel_bo_unmap(scratch_bo);
+			munmap(cpu_ptr, scratch_buf->handle);
+			munmap(gtt_ptr, staging_buf->handle);
 
 			igt_progress("partial read/writes test: ", i, ROUNDS);
 		}
 	}
 
 	igt_fixture {
-		drm_intel_bufmgr_destroy(bufmgr);
-
-		close(fd);
+		intel_bb_destroy(ibb);
+		intel_buf_destroy(scratch_buf);
+		intel_buf_destroy(staging_buf);
+		buf_ops_destroy(data.bops);
+		close(data.fd);
 	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 4/4] i915/gem_hang: Removal

[Dominik Grzegorzek]

Remove gem_hang because it's not correct for more recent
gen and redundant with the hangcheck checks.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
---
 tests/i915/gem_hang.c | 98 -------------------------------------------
 tests/meson.build     |  1 -
 2 files changed, 99 deletions(-)
 delete mode 100644 tests/i915/gem_hang.c

diff --git a/tests/i915/gem_hang.c b/tests/i915/gem_hang.c
deleted file mode 100644
index 2c61cac0..00000000
--- a/tests/i915/gem_hang.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *    Jesse Barnes <jbarnes@virtuousgeek.org> (based on gem_bad_blit.c)
- *
- */
-
-#include "igt.h"
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-static int bad_pipe;
-
-static void
-gpu_hang(void)
-{
-	int cmd;
-
-	cmd = bad_pipe ? MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW :
-		MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW;
-
-	BEGIN_BATCH(6, 0);
-	/* The documentation says that the LOAD_SCAN_LINES command
-	 * always comes in pairs. Don't ask me why. */
-	OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | (bad_pipe << 20));
-	OUT_BATCH((0 << 16) | 2048);
-	OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | (bad_pipe << 20));
-	OUT_BATCH((0 << 16) | 2048);
-	OUT_BATCH(MI_WAIT_FOR_EVENT | cmd);
-	OUT_BATCH(MI_NOOP);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
-}
-
-static int opt_handler(int opt, int opt_index, void *data)
-{
-	switch (opt) {
-	case 'p':
-		bad_pipe = atoi(optarg);
-		break;
-	default:
-		return IGT_OPT_HANDLER_ERROR;
-	}
-
-	return IGT_OPT_HANDLER_SUCCESS;
-}
-
-const char *help_str = "  -p\tDisabled pipe number\n";
-
-igt_simple_main_args("p:", NULL, help_str, opt_handler, NULL)
-{
-	int fd;
-
-	fd = drm_open_driver(DRIVER_INTEL);
-
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-
-	gpu_hang();
-
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
-
-	close(fd);
-}
diff --git a/tests/meson.build b/tests/meson.build
index 28091794..58b0822e 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -408,7 +408,6 @@ executable('gem_stress', 'i915/gem_stress.c',
 # unrecoverable gpu hangs. Don't put real testcases here.
 hang_progs = [
 	'gem_bad_batch',
-	'gem_hang',
 	'gem_bad_blit',
 	'gem_bad_address',
 	'gem_non_secure_batch',
-- 
2.20.1

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[igt-dev] ✗ Fi.CI.BAT: failure for Remove libdrm dependency from gem_[caching/hang] (rev2)

[Patchwork]

== Series Details ==

Series: Remove libdrm dependency from gem_[caching/hang] (rev2)
URL   : https://patchwork.freedesktop.org/series/78886/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8673 -> IGTPW_4711
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_4711 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_4711, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4711:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_timelines:
    - fi-tgl-u2:          [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt@i915_selftest@live@gt_timelines.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-tgl-u2/igt@i915_selftest@live@gt_timelines.html

  
Known issues
------------

  Here are the changes found in IGTPW_4711 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@gem_flink_basic@double-flink:
    - fi-tgl-y:           [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt@gem_flink_basic@double-flink.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-tgl-y/igt@gem_flink_basic@double-flink.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-whl-u:           [DMESG-WARN][9] ([i915#95]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-n2820:       [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-n2820/igt@i915_pm_rpm@basic-pci-d3-state.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-byt-n2820/igt@i915_pm_rpm@basic-pci-d3-state.html
    - {fi-tgl-dsi}:       [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-tgl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@coherency:
    - fi-gdg-551:         [DMESG-FAIL][15] ([i915#1748]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-gdg-551/igt@i915_selftest@live@coherency.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-gdg-551/igt@i915_selftest@live@coherency.html

  * igt@i915_selftest@live@gt_pm:
    - fi-icl-y:           [DMESG-FAIL][17] -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-y/igt@i915_selftest@live@gt_pm.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-icl-y/igt@i915_selftest@live@gt_pm.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html

  * igt@kms_psr@primary_page_flip:
    - fi-tgl-y:           [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt@kms_psr@primary_page_flip.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-tgl-y/igt@kms_psr@primary_page_flip.html

  
#### Warnings ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-x1275:       [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-kbl-x1275:       [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +4 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (45 -> 39)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5718 -> IGTPW_4711

  CI-20190529: 20190529
  CI_DRM_8673: ae0a2b45fe022c02a2779c2ae8c83473763c1feb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4711: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/index.html
  IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4711/index.html
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