From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: iommu@lists.linux-foundation.org, LKML <linux-kernel@vger.kernel.org>, "Lu Baolu" <baolu.lu@linux.intel.com>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org> Cc: Yi Liu <yi.l.liu@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Eric Auger <eric.auger@redhat.com>, Jacob Pan <jacob.jun.pan@linux.intel.com> Subject: [PATCH v3 4/7] iommu/vt-d: Handle non-page aligned address Date: Wed, 1 Jul 2020 08:33:53 -0700 [thread overview] Message-ID: <1593617636-79385-5-git-send-email-jacob.jun.pan@linux.intel.com> (raw) In-Reply-To: <1593617636-79385-1-git-send-email-jacob.jun.pan@linux.intel.com> From: Liu Yi L <yi.l.liu@intel.com> Address information for device TLB invalidation comes from userspace when device is directly assigned to a guest with vIOMMU support. VT-d requires page aligned address. This patch checks and enforce address to be page aligned, otherwise reserved bits can be set in the invalidation descriptor. Unrecoverable fault will be reported due to non-zero value in the reserved bits. Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation cache types") Acked-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> --- drivers/iommu/intel/dmar.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index d9f973fa1190..3899f3161071 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, * Max Invs Pending (MIP) is set to 0 for now until we have DIT in * ECAP. */ - desc.qw1 |= addr & ~mask; - if (size_order) + if (addr & ~VTD_PAGE_MASK) + pr_warn_ratelimited("Invalidate non-page aligned address %llx\n", addr); + + /* Take page address */ + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr); + + if (size_order) { + /* + * Existing 0s in address below size_order may be the least + * significant bit, we must set them to 1s to avoid having + * smaller size than desired. + */ + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT, + VTD_PAGE_SHIFT); + /* Clear size_order bit to indicate size */ + desc.qw1 &= ~mask; + /* Set the S bit to indicate flushing more than 1 page */ desc.qw1 |= QI_DEV_EIOTLB_SIZE; + } qi_submit_sync(iommu, &desc, 1, 0); } -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: iommu@lists.linux-foundation.org, LKML <linux-kernel@vger.kernel.org>, "Lu Baolu" <baolu.lu@linux.intel.com>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org> Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com> Subject: [PATCH v3 4/7] iommu/vt-d: Handle non-page aligned address Date: Wed, 1 Jul 2020 08:33:53 -0700 [thread overview] Message-ID: <1593617636-79385-5-git-send-email-jacob.jun.pan@linux.intel.com> (raw) In-Reply-To: <1593617636-79385-1-git-send-email-jacob.jun.pan@linux.intel.com> From: Liu Yi L <yi.l.liu@intel.com> Address information for device TLB invalidation comes from userspace when device is directly assigned to a guest with vIOMMU support. VT-d requires page aligned address. This patch checks and enforce address to be page aligned, otherwise reserved bits can be set in the invalidation descriptor. Unrecoverable fault will be reported due to non-zero value in the reserved bits. Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation cache types") Acked-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> --- drivers/iommu/intel/dmar.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index d9f973fa1190..3899f3161071 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, * Max Invs Pending (MIP) is set to 0 for now until we have DIT in * ECAP. */ - desc.qw1 |= addr & ~mask; - if (size_order) + if (addr & ~VTD_PAGE_MASK) + pr_warn_ratelimited("Invalidate non-page aligned address %llx\n", addr); + + /* Take page address */ + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr); + + if (size_order) { + /* + * Existing 0s in address below size_order may be the least + * significant bit, we must set them to 1s to avoid having + * smaller size than desired. + */ + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT, + VTD_PAGE_SHIFT); + /* Clear size_order bit to indicate size */ + desc.qw1 &= ~mask; + /* Set the S bit to indicate flushing more than 1 page */ desc.qw1 |= QI_DEV_EIOTLB_SIZE; + } qi_submit_sync(iommu, &desc, 1, 0); } -- 2.7.4 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-07-01 15:27 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-01 15:33 [PATCH v3 0/7] iommu/vt-d: Misc tweaks and fixes for vSVA Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-01 15:33 ` [PATCH v3 1/7] iommu/vt-d: Enforce PASID devTLB field mask Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-02 7:16 ` Auger Eric 2020-07-02 7:16 ` Auger Eric 2020-07-01 15:33 ` [PATCH v3 2/7] iommu/vt-d: Remove global page support in devTLB flush Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-02 7:16 ` Auger Eric 2020-07-02 7:16 ` Auger Eric 2020-07-06 23:58 ` Jacob Pan 2020-07-06 23:58 ` Jacob Pan 2020-07-01 15:33 ` [PATCH v3 3/7] iommu/vt-d: Fix PASID devTLB invalidation Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-02 0:50 ` Lu Baolu 2020-07-02 0:50 ` Lu Baolu 2020-07-02 7:16 ` Auger Eric 2020-07-02 7:16 ` Auger Eric 2020-07-01 15:33 ` Jacob Pan [this message] 2020-07-01 15:33 ` [PATCH v3 4/7] iommu/vt-d: Handle non-page aligned address Jacob Pan 2020-07-02 7:50 ` Auger Eric 2020-07-02 7:50 ` Auger Eric 2020-07-06 23:28 ` Jacob Pan 2020-07-06 23:28 ` Jacob Pan 2020-07-01 15:33 ` [PATCH v3 5/7] iommu/vt-d: Fix devTLB flush for vSVA Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-02 8:39 ` Auger Eric 2020-07-02 8:39 ` Auger Eric 2020-07-06 21:05 ` Jacob Pan 2020-07-06 21:05 ` Jacob Pan 2020-07-01 15:33 ` [PATCH v3 6/7] iommu/vt-d: Warn on out-of-range invalidation address Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-02 0:55 ` Lu Baolu 2020-07-02 0:55 ` Lu Baolu 2020-07-02 8:47 ` Auger Eric 2020-07-02 8:47 ` Auger Eric 2020-07-02 13:43 ` Jacob Pan 2020-07-02 13:43 ` Jacob Pan 2020-07-01 15:33 ` [PATCH v3 7/7] iommu/vt-d: Disable multiple GPASID-dev bind Jacob Pan 2020-07-01 15:33 ` Jacob Pan 2020-07-02 8:50 ` Auger Eric 2020-07-02 8:50 ` Auger Eric
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