* [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
@ 2020-07-09 19:58 Umesh Nerlige Ramappa
2020-07-09 20:37 ` Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Umesh Nerlige Ramappa @ 2020-07-09 19:58 UTC (permalink / raw)
To: intel-gfx, Lionel G Landwerlin
MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
translation to use when saving restoring the engine general purpose
registers to and from the GT scratch. Since GT scratch is mapped to
ggtt, we need to set an additional bit in the command to use GTT.
Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index de69d430b1ed..c6f6370283cf 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
u32 d;
cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
+ cmd |= MI_SRM_LRM_GLOBAL_GTT;
if (INTEL_GEN(stream->perf->i915) >= 8)
cmd++;
--
2.20.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 19:58 [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR Umesh Nerlige Ramappa
@ 2020-07-09 20:37 ` Chris Wilson
2020-07-09 20:42 ` Lionel Landwerlin
2020-07-09 20:40 ` Lionel Landwerlin
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-07-09 20:37 UTC (permalink / raw)
To: Lionel G Landwerlin, Umesh Nerlige Ramappa, intel-gfx
Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> translation to use when saving restoring the engine general purpose
> registers to and from the GT scratch. Since GT scratch is mapped to
> ggtt, we need to set an additional bit in the command to use GTT.
>
> Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
> Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index de69d430b1ed..c6f6370283cf 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
> u32 d;
>
> cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
> + cmd |= MI_SRM_LRM_GLOBAL_GTT;
Indeed.
For bonus points, please write a selftest to verify that the user's GPR
are restored. Something as simple as live_noa_delay, but instead of
measuring the time; submit a request to write telltales into the GPR,
submit a request to run noa_wait; then readback the telltales from a
final request.
Now since the noa_wait is being run from the GGTT, the address space
selector should be reading from the GGTT. So I am actually curious as to
whether we have a bug or not.
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 19:58 [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR Umesh Nerlige Ramappa
2020-07-09 20:37 ` Chris Wilson
@ 2020-07-09 20:40 ` Lionel Landwerlin
2020-07-10 9:43 ` Chris Wilson
2020-07-09 20:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-07-10 0:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 10+ messages in thread
From: Lionel Landwerlin @ 2020-07-09 20:40 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, intel-gfx
On 09/07/2020 22:58, Umesh Nerlige Ramappa wrote:
> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> translation to use when saving restoring the engine general purpose
> registers to and from the GT scratch. Since GT scratch is mapped to
> ggtt, we need to set an additional bit in the command to use GTT.
>
> Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
> Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Thanks a lot!
> ---
> drivers/gpu/drm/i915/i915_perf.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index de69d430b1ed..c6f6370283cf 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
> u32 d;
>
> cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
> + cmd |= MI_SRM_LRM_GLOBAL_GTT;
> if (INTEL_GEN(stream->perf->i915) >= 8)
> cmd++;
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 20:37 ` Chris Wilson
@ 2020-07-09 20:42 ` Lionel Landwerlin
2020-07-09 20:46 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Lionel Landwerlin @ 2020-07-09 20:42 UTC (permalink / raw)
To: Chris Wilson, Umesh Nerlige Ramappa, intel-gfx
On 09/07/2020 23:37, Chris Wilson wrote:
> Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
>> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
>> translation to use when saving restoring the engine general purpose
>> registers to and from the GT scratch. Since GT scratch is mapped to
>> ggtt, we need to set an additional bit in the command to use GTT.
>>
>> Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
>> Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_perf.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index de69d430b1ed..c6f6370283cf 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
>> u32 d;
>>
>> cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
>> + cmd |= MI_SRM_LRM_GLOBAL_GTT;
> Indeed.
>
> For bonus points, please write a selftest to verify that the user's GPR
> are restored. Something as simple as live_noa_delay, but instead of
> measuring the time; submit a request to write telltales into the GPR,
> submit a request to run noa_wait; then readback the telltales from a
> final request.
>
> Now since the noa_wait is being run from the GGTT, the address space
> selector should be reading from the GGTT. So I am actually curious as to
> whether we have a bug or not.
> -Chris
I'm not super competent on the PPGTT setup, but I assumed this worked
because we wrote into the ppgtt scratch page.
Potentially trashing an app VM space if it executes a reconfiguration.
-Lionel
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 20:42 ` Lionel Landwerlin
@ 2020-07-09 20:46 ` Chris Wilson
2020-07-09 20:50 ` Lionel Landwerlin
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-07-09 20:46 UTC (permalink / raw)
To: Lionel Landwerlin, Umesh Nerlige Ramappa, intel-gfx
Quoting Lionel Landwerlin (2020-07-09 21:42:39)
> On 09/07/2020 23:37, Chris Wilson wrote:
> > Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
> >> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> >> translation to use when saving restoring the engine general purpose
> >> registers to and from the GT scratch. Since GT scratch is mapped to
> >> ggtt, we need to set an additional bit in the command to use GTT.
> >>
> >> Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
> >> Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> >> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_perf.c | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> >> index de69d430b1ed..c6f6370283cf 100644
> >> --- a/drivers/gpu/drm/i915/i915_perf.c
> >> +++ b/drivers/gpu/drm/i915/i915_perf.c
> >> @@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
> >> u32 d;
> >>
> >> cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
> >> + cmd |= MI_SRM_LRM_GLOBAL_GTT;
> > Indeed.
> >
> > For bonus points, please write a selftest to verify that the user's GPR
> > are restored. Something as simple as live_noa_delay, but instead of
> > measuring the time; submit a request to write telltales into the GPR,
> > submit a request to run noa_wait; then readback the telltales from a
> > final request.
> >
> > Now since the noa_wait is being run from the GGTT, the address space
> > selector should be reading from the GGTT. So I am actually curious as to
> > whether we have a bug or not.
> > -Chris
>
> I'm not super competent on the PPGTT setup, but I assumed this worked
> because we wrote into the ppgtt scratch page.
It's not a STORE_INDEX, it's writing to an absolute address based on the
address space selector which is a combination of the batch address space
and the command bits. Certainly the batch itself is read from the GGTT,
but I can't off hand remember the rules for the various MI (whether they
could even access ppGTT when launched from GGTT).
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 19:58 [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR Umesh Nerlige Ramappa
2020-07-09 20:37 ` Chris Wilson
2020-07-09 20:40 ` Lionel Landwerlin
@ 2020-07-09 20:48 ` Patchwork
2020-07-10 0:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-07-09 20:48 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/perf: Use GTT when saving/restoring engine GPR
URL : https://patchwork.freedesktop.org/series/79311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8723 -> Patchwork_18127
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/index.html
Known issues
------------
Here are the changes found in Patchwork_18127 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#402])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-tgl-u2/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@vgem_basic@mmap:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-tgl-y/igt@vgem_basic@mmap.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-tgl-y/igt@vgem_basic@mmap.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][7] ([i915#1888]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-byt-j1900/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@vgem_basic@setversion:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-tgl-y/igt@vgem_basic@setversion.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-tgl-y/igt@vgem_basic@setversion.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (42 -> 37)
------------------------------
Additional (1): fi-ehl-1
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_8723 -> Patchwork_18127
CI-20190529: 20190529
CI_DRM_8723: 75a99370a8038a14e093b260cacbbdc4f7655e21 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18127: 8d6f9a7b8cec4411fbb068775123b068e776b759 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8d6f9a7b8cec drm/i915/perf: Use GTT when saving/restoring engine GPR
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/index.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 20:46 ` Chris Wilson
@ 2020-07-09 20:50 ` Lionel Landwerlin
2020-07-09 21:00 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Lionel Landwerlin @ 2020-07-09 20:50 UTC (permalink / raw)
To: Chris Wilson, Umesh Nerlige Ramappa, intel-gfx
On 09/07/2020 23:46, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2020-07-09 21:42:39)
>> On 09/07/2020 23:37, Chris Wilson wrote:
>>> Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
>>>> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
>>>> translation to use when saving restoring the engine general purpose
>>>> registers to and from the GT scratch. Since GT scratch is mapped to
>>>> ggtt, we need to set an additional bit in the command to use GTT.
>>>>
>>>> Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
>>>> Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>>>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_perf.c | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>>>> index de69d430b1ed..c6f6370283cf 100644
>>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>>> @@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
>>>> u32 d;
>>>>
>>>> cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
>>>> + cmd |= MI_SRM_LRM_GLOBAL_GTT;
>>> Indeed.
>>>
>>> For bonus points, please write a selftest to verify that the user's GPR
>>> are restored. Something as simple as live_noa_delay, but instead of
>>> measuring the time; submit a request to write telltales into the GPR,
>>> submit a request to run noa_wait; then readback the telltales from a
>>> final request.
>>>
>>> Now since the noa_wait is being run from the GGTT, the address space
>>> selector should be reading from the GGTT. So I am actually curious as to
>>> whether we have a bug or not.
>>> -Chris
>> I'm not super competent on the PPGTT setup, but I assumed this worked
>> because we wrote into the ppgtt scratch page.
> It's not a STORE_INDEX, it's writing to an absolute address based on the
> address space selector which is a combination of the batch address space
> and the command bits. Certainly the batch itself is read from the GGTT,
> but I can't off hand remember the rules for the various MI (whether they
> could even access ppGTT when launched from GGTT).
> -Chris
My understanding was that from a GGTT batch you could read/write into PPGTT.
But not the other way around (obvisously).
I thought the kernel mapped a page throughout the entire PPGTT space to
prevent pagefaults. Is that not the case?
-Lionel
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 20:50 ` Lionel Landwerlin
@ 2020-07-09 21:00 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-07-09 21:00 UTC (permalink / raw)
To: Lionel Landwerlin, Umesh Nerlige Ramappa, intel-gfx
Quoting Lionel Landwerlin (2020-07-09 21:50:30)
> On 09/07/2020 23:46, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2020-07-09 21:42:39)
> >> On 09/07/2020 23:37, Chris Wilson wrote:
> >>> Quoting Umesh Nerlige Ramappa (2020-07-09 20:58:37)
> >>>> MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> >>>> translation to use when saving restoring the engine general purpose
> >>>> registers to and from the GT scratch. Since GT scratch is mapped to
> >>>> ggtt, we need to set an additional bit in the command to use GTT.
> >>>>
> >>>> Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
> >>>> Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> >>>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >>>> ---
> >>>> drivers/gpu/drm/i915/i915_perf.c | 1 +
> >>>> 1 file changed, 1 insertion(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> >>>> index de69d430b1ed..c6f6370283cf 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_perf.c
> >>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
> >>>> @@ -1592,6 +1592,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
> >>>> u32 d;
> >>>>
> >>>> cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
> >>>> + cmd |= MI_SRM_LRM_GLOBAL_GTT;
> >>> Indeed.
> >>>
> >>> For bonus points, please write a selftest to verify that the user's GPR
> >>> are restored. Something as simple as live_noa_delay, but instead of
> >>> measuring the time; submit a request to write telltales into the GPR,
> >>> submit a request to run noa_wait; then readback the telltales from a
> >>> final request.
> >>>
> >>> Now since the noa_wait is being run from the GGTT, the address space
> >>> selector should be reading from the GGTT. So I am actually curious as to
> >>> whether we have a bug or not.
> >>> -Chris
> >> I'm not super competent on the PPGTT setup, but I assumed this worked
> >> because we wrote into the ppgtt scratch page.
> > It's not a STORE_INDEX, it's writing to an absolute address based on the
> > address space selector which is a combination of the batch address space
> > and the command bits. Certainly the batch itself is read from the GGTT,
> > but I can't off hand remember the rules for the various MI (whether they
> > could even access ppGTT when launched from GGTT).
> > -Chris
>
> My understanding was that from a GGTT batch you could read/write into PPGTT.
>
> But not the other way around (obvisously).
>
> I thought the kernel mapped a page throughout the entire PPGTT space to
> prevent pagefaults. Is that not the case?
Yes, a readonly page, where supported.
Ah, now I understand you meant *that* scratch page as opposed to a
page we allocated for the purpose of saving per-context state like the
gt->scratch page.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 19:58 [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR Umesh Nerlige Ramappa
` (2 preceding siblings ...)
2020-07-09 20:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2020-07-10 0:33 ` Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-07-10 0:33 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/perf: Use GTT when saving/restoring engine GPR
URL : https://patchwork.freedesktop.org/series/79311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8723_full -> Patchwork_18127_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_18127_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_params@invalid-fence-in:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#93] / [i915#95]) +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-kbl4/igt@gem_exec_params@invalid-fence-in.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-kbl6/igt@gem_exec_params@invalid-fence-in.html
* igt@gem_exec_whisper@basic-forked-all:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-glk7/igt@gem_exec_whisper@basic-forked-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-glk4/igt@gem_exec_whisper@basic-forked-all.html
* igt@i915_module_load@reload:
- shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb7/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-tglb8/igt@i915_module_load@reload.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#454])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@kms_color@pipe-c-ctm-negative:
- shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +5 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl8/igt@kms_color@pipe-c-ctm-negative.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl10/igt@kms_color@pipe-c-ctm-negative.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#95]) +11 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][13] -> [FAIL][14] ([IGT#5])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@basic:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-glk1/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-glk7/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl5/igt@kms_hdr@bpc-switch.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf_pmu@semaphore-busy@rcs0:
- shard-kbl: [PASS][27] -> [FAIL][28] ([i915#1820])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-kbl3/igt@perf_pmu@semaphore-busy@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-kbl1/igt@perf_pmu@semaphore-busy@rcs0.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-concurrent0:
- shard-glk: [FAIL][29] ([i915#1930]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-glk7/igt@gem_exec_reloc@basic-concurrent0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-glk4/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gen9_exec_parse@bb-start-far:
- shard-apl: [DMESG-WARN][31] ([i915#1635] / [i915#95]) -> [PASS][32] +10 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl4/igt@gen9_exec_parse@bb-start-far.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl3/igt@gen9_exec_parse@bb-start-far.html
* igt@i915_selftest@mock@requests:
- shard-snb: [INCOMPLETE][33] ([i915#2110] / [i915#82]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-snb5/igt@i915_selftest@mock@requests.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-snb6/igt@i915_selftest@mock@requests.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge:
- shard-glk: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-glk8/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-glk6/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-tglb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- shard-tglb: [DMESG-WARN][43] ([i915#402]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][45] ([i915#1188]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_lease@simple_lease:
- shard-glk: [INCOMPLETE][47] ([i915#58] / [k.org#198133]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-glk5/igt@kms_lease@simple_lease.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-glk5/igt@kms_lease@simple_lease.html
#### Warnings ####
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: [SKIP][49] ([fdo#109271]) -> [SKIP][50] ([fdo#109271] / [i915#1635]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl4/igt@gem_render_copy@linear-to-vebox-y-tiled.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl7/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: [SKIP][51] ([fdo#109271] / [i915#1937]) -> [SKIP][52] ([fdo#109271] / [i915#1635] / [i915#1937])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_suspend@forcewake:
- shard-kbl: [INCOMPLETE][53] ([i915#155] / [i915#636]) -> [DMESG-WARN][54] ([i915#180])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-kbl4/igt@i915_suspend@forcewake.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-kbl7/igt@i915_suspend@forcewake.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-apl: [SKIP][55] ([fdo#109271] / [fdo#111827]) -> [SKIP][56] ([fdo#109271] / [fdo#111827] / [i915#1635]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl8/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl4/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-apl: [SKIP][57] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl4/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl3/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [DMESG-WARN][60] ([i915#180] / [i915#93] / [i915#95])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
- shard-apl: [SKIP][61] ([fdo#109271] / [i915#1635]) -> [SKIP][62] ([fdo#109271]) +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
* igt@runner@aborted:
- shard-apl: ([FAIL][63], [FAIL][64], [FAIL][65], [FAIL][66]) ([i915#1610] / [i915#1635] / [i915#2110] / [i915#637]) -> [FAIL][67] ([i915#1635] / [i915#2110])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl8/igt@runner@aborted.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl8/igt@runner@aborted.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl4/igt@runner@aborted.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-apl8/igt@runner@aborted.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-apl3/igt@runner@aborted.html
- shard-tglb: ([FAIL][68], [FAIL][69], [FAIL][70], [FAIL][71], [FAIL][72]) ([i915#1764] / [i915#2110] / [i915#2150]) -> ([FAIL][73], [FAIL][74]) ([i915#2110] / [i915#2150])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb7/igt@runner@aborted.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb2/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb6/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb2/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-tglb3/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-tglb8/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-tglb2/igt@runner@aborted.html
- shard-skl: ([FAIL][75], [FAIL][76]) ([i915#2110] / [i915#69]) -> [FAIL][77] ([i915#69])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl6/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8723/shard-skl5/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/shard-skl3/igt@runner@aborted.html
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2150]: https://gitlab.freedesktop.org/drm/intel/issues/2150
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
[i915#637]: https://gitlab.freedesktop.org/drm/intel/issues/637
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8723 -> Patchwork_18127
CI-20190529: 20190529
CI_DRM_8723: 75a99370a8038a14e093b260cacbbdc4f7655e21 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18127: 8d6f9a7b8cec4411fbb068775123b068e776b759 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18127/index.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR
2020-07-09 20:40 ` Lionel Landwerlin
@ 2020-07-10 9:43 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-07-10 9:43 UTC (permalink / raw)
To: Lionel Landwerlin, Umesh Nerlige Ramappa, intel-gfx
Quoting Lionel Landwerlin (2020-07-09 21:40:50)
> On 09/07/2020 22:58, Umesh Nerlige Ramappa wrote:
> > MI_STORE_REGISTER_MEM and MI_LOAD_REGISTER_MEM need to know which
> > translation to use when saving restoring the engine general purpose
> > registers to and from the GT scratch. Since GT scratch is mapped to
> > ggtt, we need to set an additional bit in the command to use GTT.
> >
> > Fixes: daed3e44396d17 ("drm/i915/perf: implement active wait for noa configurations")
> > Suggested-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
>
> Thanks a lot!
Pushed, thanks for the fix.
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-07-10 9:43 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-09 19:58 [Intel-gfx] [PATCH] drm/i915/perf: Use GTT when saving/restoring engine GPR Umesh Nerlige Ramappa
2020-07-09 20:37 ` Chris Wilson
2020-07-09 20:42 ` Lionel Landwerlin
2020-07-09 20:46 ` Chris Wilson
2020-07-09 20:50 ` Lionel Landwerlin
2020-07-09 21:00 ` Chris Wilson
2020-07-09 20:40 ` Lionel Landwerlin
2020-07-10 9:43 ` Chris Wilson
2020-07-09 20:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-07-10 0:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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