* [Intel-gfx] [RFC 01/60] drm/i915: Add has_master_unit_irq flag
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
@ 2020-07-10 11:56 ` Matthew Auld
2020-07-10 11:56 ` [Intel-gfx] [RFC 02/60] drm/i915/dg1: add initial DG-1 definitions Matthew Auld
` (63 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Stuart Summers <stuart.summers@intel.com>
Add flag to differentiate platforms with and without the master
IRQ control bit.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 87973dedf8e7..d357043db44e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1599,6 +1599,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
+#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)
+
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 242d00862b1a..71edb396b31a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -122,6 +122,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_contexts); \
func(has_logical_ring_elsq); \
func(has_logical_ring_preemption); \
+ func(has_master_unit_irq); \
func(has_pooled_eu); \
func(has_rc6); \
func(has_rc6p); \
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 02/60] drm/i915/dg1: add initial DG-1 definitions
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
2020-07-10 11:56 ` [Intel-gfx] [RFC 01/60] drm/i915: Add has_master_unit_irq flag Matthew Auld
@ 2020-07-10 11:56 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 03/60] drm/i915/dg1: Add DG1 PCI IDs Matthew Auld
` (62 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue, Vanshidhar Konda, Lucas De Marchi
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Bspec: 33617, 33617
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Vanshidhar Konda <vanshidhar.r.konda@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++++++
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d357043db44e..7f668a49b03d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1431,6 +1431,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
+#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
@@ -1559,6 +1560,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_RKL_REVID(p, since, until) \
(IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define DG1_REVID_A0 0x0
+#define DG1_REVID_B0 0x1
+
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
+
#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index db916fff3f0d..f5af72521de6 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -897,8 +897,20 @@ static const struct intel_device_info rkl_info = {
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
+ .memory_regions = REGION_SMEM | REGION_LMEM, \
+ .has_master_unit_irq = 1, \
.is_dgfx = 1
+static const struct intel_device_info intel_dg1_info = {
+ GEN12_DGFX_FEATURES,
+ PLATFORM(INTEL_DG1),
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ .require_force_probe = 1,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
+ BIT(VCS0) | BIT(VCS2),
+};
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3f5dc37d2b7c..40c590db3c76 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -64,6 +64,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ELKHARTLAKE),
PLATFORM_NAME(TIGERLAKE),
PLATFORM_NAME(ROCKETLAKE),
+ PLATFORM_NAME(DG1),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 71edb396b31a..fd2385457ab6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -82,6 +82,7 @@ enum intel_platform {
/* gen12 */
INTEL_TIGERLAKE,
INTEL_ROCKETLAKE,
+ INTEL_DG1,
INTEL_MAX_PLATFORMS
};
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 03/60] drm/i915/dg1: Add DG1 PCI IDs
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
2020-07-10 11:56 ` [Intel-gfx] [RFC 01/60] drm/i915: Add has_master_unit_irq flag Matthew Auld
2020-07-10 11:56 ` [Intel-gfx] [RFC 02/60] drm/i915/dg1: add initial DG-1 definitions Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 04/60] drm/i915/dg1: add support for the master unit interrupt Matthew Auld
` (61 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue, Lucas De Marchi
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Add the PCI ID for DG1, but keep it out of the table we use to register
the driver. At this point we can't consider the driver ready to bind to
the device since we basically miss support for everything. When more
support is merged we can enable it to work partially for example as a
display-only driver.
v2: remove DG1 from the pci table and reword commit message (Lucas)
Bspec: 44463
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com> # v1
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: kernel test robot <lkp@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
include/drm/i915_pciids.h | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f5af72521de6..85e2557563cf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -901,7 +901,7 @@ static const struct intel_device_info rkl_info = {
.has_master_unit_irq = 1, \
.is_dgfx = 1
-static const struct intel_device_info intel_dg1_info = {
+static const struct intel_device_info dg1_info = {
GEN12_DGFX_FEATURES,
PLATFORM(INTEL_DG1),
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index d6cb28992ba0..96e408b4bdc9 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -618,4 +618,8 @@
INTEL_VGA_DEVICE(0x4C90, info), \
INTEL_VGA_DEVICE(0x4C9A, info)
+/* DG1 */
+#define INTEL_DG1_IDS(info) \
+ INTEL_VGA_DEVICE(0x4905, info)
+
#endif /* _I915_PCIIDS_H */
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 04/60] drm/i915/dg1: add support for the master unit interrupt
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (2 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 03/60] drm/i915/dg1: Add DG1 PCI IDs Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 05/60] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Matthew Auld
` (60 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
DG1 has master unit interrupt register which is used to indicate the
correct source of interrupt.
v2: fix coding style on register definition
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++
drivers/gpu/drm/i915/i915_irq.c | 56 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 4 +++
3 files changed, 61 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 78ebede51fb3..784219962193 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -495,6 +495,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "PCU interrupt enable:\t%08x\n",
I915_READ(GEN8_PCU_IER));
} else if (INTEL_GEN(dev_priv) >= 11) {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ seq_printf(m, "Master Unit Interrupt Control: %08x\n",
+ I915_READ(DG1_MSTR_UNIT_INTR));
+
seq_printf(m, "Master Interrupt Control: %08x\n",
I915_READ(GEN11_GFX_MSTR_IRQ));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 562b43ed077f..4c9d0a4a2476 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2584,6 +2584,46 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gen11_master_intr_enable);
}
+static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
+{
+ u32 val;
+
+ /* First disable interrupts */
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
+
+ /* Get the indication levels and ack the master unit */
+ val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
+
+ /*
+ * Now with master disabled, get a sample of level indications
+ * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
+ * out as this bit doesn't exist anymore for DG1
+ */
+ val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
+ if (unlikely(!val))
+ return 0;
+
+ raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
+
+ return val;
+}
+
+static inline void dg1_master_intr_enable(void __iomem * const regs)
+{
+ raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
+}
+
+static irqreturn_t dg1_irq_handler(int irq, void *arg)
+{
+ return __gen11_irq_handler(arg,
+ dg1_master_intr_disable_and_ack,
+ dg1_master_intr_enable);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2920,7 +2960,10 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
- gen11_master_intr_disable(dev_priv->uncore.regs);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
+ else
+ gen11_master_intr_disable(dev_priv->uncore.regs);
gen11_gt_irq_reset(&dev_priv->gt);
gen11_display_irq_reset(dev_priv);
@@ -3517,8 +3560,13 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
- gen11_master_intr_enable(uncore->regs);
- POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
+ dg1_master_intr_enable(uncore->regs);
+ POSTING_READ(DG1_MSTR_UNIT_INTR);
+ } else {
+ gen11_master_intr_enable(uncore->regs);
+ POSTING_READ(GEN11_GFX_MSTR_IRQ);
+ }
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4043,6 +4091,8 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
else
return i8xx_irq_handler;
} else {
+ if (HAS_MASTER_UNIT_IRQ(dev_priv))
+ return dg1_irq_handler;
if (INTEL_GEN(dev_priv) >= 11)
return gen11_irq_handler;
else if (INTEL_GEN(dev_priv) >= 8)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86a23ced051b..4e796ff4d7d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7733,6 +7733,10 @@ enum {
#define GEN11_GT_DW1_IRQ (1 << 1)
#define GEN11_GT_DW0_IRQ (1 << 0)
+#define DG1_MSTR_UNIT_INTR _MMIO(0x190008)
+#define DG1_MSTR_IRQ REG_BIT(31)
+#define DG1_MSTR_UNIT(u) REG_BIT(u)
+
#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 05/60] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (3 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 04/60] drm/i915/dg1: add support for the master unit interrupt Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 06/60] drm/i915/dg1: Add fake PCH Matthew Auld
` (59 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Bspec asks us to remove the special programming of the
SHPD_FILTER_CNT register which we have been doing since CNP+.
Bspec: 49305
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4c9d0a4a2476..1fa67700d8f4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3114,7 +3114,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
hotplug_irqs = sde_ddi_mask | sde_tc_mask;
enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+ if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
+ I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 06/60] drm/i915/dg1: Add fake PCH
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (4 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 05/60] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 07/60] drm/i915/dg1: Initialize RAWCLK properly Matthew Auld
` (58 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
DG1 has the south engine display on the same PCI device. Ideally we
could use HAS_PCH_SPLIT(), but that macro is misused all across the
code base to rather signify a range of gens. So add a fake one for DG1
to be used where needed.
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_pch.c | 6 ++++++
drivers/gpu/drm/i915/intel_pch.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index c668e99eb2e4..6c97192e9ca8 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
{
struct pci_dev *pch = NULL;
+ /* DG1 has south engine display on the same PCI device */
+ if (IS_DG1(dev_priv)) {
+ dev_priv->pch_type = PCH_DG1;
+ return;
+ }
+
/*
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
* make graphics device passthrough work easy for VMM, that only
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 3053d1ce398b..06d2cd50af0b 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,9 @@ enum intel_pch {
PCH_JSP, /* Jasper Lake PCH */
PCH_MCC, /* Mule Creek Canyon PCH */
PCH_TGP, /* Tiger Lake PCH */
+
+ /* Fake PCHs, functionality handled on the same PCI dev */
+ PCH_DG1 = 1024,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -56,6 +59,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 07/60] drm/i915/dg1: Initialize RAWCLK properly
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (5 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 06/60] drm/i915/dg1: Add fake PCH Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 08/60] drm/i915/dg1: Define MOCS table for DG1 Matthew Auld
` (57 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+. Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.
For simplicity, let's just assume that this 38.4 MHz frequency will hold
true for other future platforms with "fake" PCH south displays and that
the CNP-style behavior will remain for other platforms with a real PCH.
Bspec: 49950
Bspec: 49309
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bb91dace304a..a779da701ad5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2680,6 +2680,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
}
+static int dg1_rawclk(struct drm_i915_private *dev_priv)
+{
+ /*
+ * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
+ * "Program Numerator=2, Denominator=4, Divider=37 decimal."
+ */
+ I915_WRITE(PCH_RAWCLK_FREQ,
+ CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+
+ return 38400;
+}
+
static int cnp_rawclk(struct drm_i915_private *dev_priv)
{
u32 rawclk;
@@ -2788,7 +2800,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
{
u32 freq;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ freq = dg1_rawclk(dev_priv);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
freq = cnp_rawclk(dev_priv);
else if (HAS_PCH_SPLIT(dev_priv))
freq = pch_rawclk(dev_priv);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 08/60] drm/i915/dg1: Define MOCS table for DG1
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (6 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 07/60] drm/i915/dg1: Initialize RAWCLK properly Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 09/60] drm/i915/dg1: Add DG1 power wells Matthew Auld
` (56 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b..7217c6e2087c 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
GEN11_MOCS_ENTRIES
};
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* Reserved */
+ MOCS_ENTRY(2, 0, L3_0_DIRECT),
+ MOCS_ENTRY(3, 0, L3_0_DIRECT),
+ MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+ /* WB - L3 */
+ MOCS_ENTRY(5, 0, L3_3_WB),
+ /* WB - L3 50% */
+ MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+ /* WB - L3 25% */
+ MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+ /* WB - L3 12.5% */
+ MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+ /* HDC:L1 + L3 */
+ MOCS_ENTRY(48, 0, L3_3_WB),
+ /* HDC:L1 */
+ MOCS_ENTRY(49, 0, L3_1_UC),
+
+ /* HW Reserved */
+ MOCS_ENTRY(60, 0, L3_1_UC),
+ MOCS_ENTRY(61, 0, L3_1_UC),
+ MOCS_ENTRY(62, 0, L3_1_UC),
+ MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
{
unsigned int flags;
- if (INTEL_GEN(i915) >= 12) {
+ if (IS_DG1(i915)) {
+ table->size = ARRAY_SIZE(dg1_mocs_table);
+ table->table = dg1_mocs_table;
+ table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+ } else if (INTEL_GEN(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 09/60] drm/i915/dg1: Add DG1 power wells
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (7 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 08/60] drm/i915/dg1: Define MOCS table for DG1 Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 10/60] drm/i915/dg1: Increase mmio size to 4MB Matthew Auld
` (55 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Uma Shankar <uma.shankar@intel.com>
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
Need to keep Transcoder C and D to Pipe Power wells, this is against
the spec but else hitting unclaimed register warnings (kept the logic
same as TGL)
Bspec: 49182
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 201 +++++++++++++++++-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0c713e83274d..b51b82cb2398 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_4_POWER_DOMAINS ( \
+ DG1_PW_5_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_3_POWER_DOMAINS ( \
+ DG1_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ },
+ {
+ .name = "DDI D TC1 IO",
+ .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ },
+ {
+ .name = "DDI E TC2 IO",
+ .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_ddi_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ },
+ {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ },
+ {
+ .name = "AUX D TC1",
+ .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "AUX E TC2",
+ .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &icl_aux_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ },
+ {
+ .name = "power well 4",
+ .domains = DG1_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ },
+ {
+ .name = "power well 5",
+ .domains = DG1_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = &hsw_power_well_regs,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ err = set_power_wells(power_domains, dg1_power_wells);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
} else if (IS_GEN(dev_priv, 12)) {
err = set_power_wells(power_domains, tgl_power_wells);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 10/60] drm/i915/dg1: Increase mmio size to 4MB
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (8 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 09/60] drm/i915/dg1: Add DG1 power wells Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 11/60] drm/i915/dg1: Wait for pcode/uncore handshake at startup Matthew Auld
` (54 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f5edee17902a..8f9c82aa7338 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
* clobbering the GTT which we want ioremap_wc instead. Fortunately,
* the register BAR remains the same size for all the earlier
* generations up to Ironlake.
+ * For dgfx chips register range is expanded to 4MB.
*/
if (INTEL_GEN(i915) < 5)
mmio_size = 512 * 1024;
+ else if (IS_DGFX(i915))
+ mmio_size = 4 * 1024 * 1024;
else
mmio_size = 2 * 1024 * 1024;
+
uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
if (uncore->regs == NULL) {
drm_err(&i915->drm, "failed to map registers\n");
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 11/60] drm/i915/dg1: Wait for pcode/uncore handshake at startup
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (9 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 10/60] drm/i915/dg1: Increase mmio size to 4MB Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 12/60] drm/i915/dg1: Add DPLL macros for DG1 Matthew Auld
` (53 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshaking is complete.
The bspec doesn't give guidance on how long we may need to wait for this
handshaking to complete. For now, let's just set a really long timeout;
if we still don't get a completion status by the end of that timeout,
we'll just continue on and hope for the best.
Bspec: 52065
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sideband.h | 2 ++
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5fd5af4bc855..5473bfe9126c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -85,6 +85,7 @@
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pm.h"
+#include "intel_sideband.h"
#include "vlv_suspend.h"
static struct drm_driver driver;
@@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
*/
intel_dram_detect(dev_priv);
+ intel_pcode_init(dev_priv);
+
intel_bw_init_hw(dev_priv);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e796ff4d7d0..20f48f24f2dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9226,6 +9226,9 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_CHECK_UNCORE_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_COMPLETE 0x1
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 916ccd1c0e96..8b093525240d 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
return ret ? ret : status;
#undef COND
}
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ if (!IS_DGFX(i915))
+ return;
+
+ ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+ DG1_CHECK_UNCORE_INIT_STATUS,
+ DG1_UNCORE_INIT_COMPLETE,
+ DG1_UNCORE_INIT_COMPLETE, 50);
+ if (ret)
+ drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..094c7b19c5d4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
+void intel_pcode_init(struct drm_i915_private *i915);
+
#endif /* _INTEL_SIDEBAND_H */
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 12/60] drm/i915/dg1: Add DPLL macros for DG1
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (10 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 11/60] drm/i915/dg1: Wait for pcode/uncore handshake at startup Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 13/60] drm/i915/dg1: Add and setup DPLLs " Matthew Auld
` (52 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Aditya Swarup <aditya.swarup@intel.com>
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++++++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..205542fb8dc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
*/
DPLL_ID_TGL_MGPLL6 = 8,
+
+ /**
+ * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+ */
+ DPLL_ID_DG1_DPLL0 = 0,
+ /**
+ * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+ */
+ DPLL_ID_DG1_DPLL1 = 1,
+ /**
+ * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+ */
+ DPLL_ID_DG1_DPLL2 = 2,
+ /**
+ * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+ */
+ DPLL_ID_DG1_DPLL3 = 3,
};
#define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 20f48f24f2dd..f362c65b1de7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
+#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
+
/*
* Device info offset array based helpers for groups of registers with unevenly
@@ -10520,6 +10521,20 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DG1_DPLL2_CFGCR0 0x16C284
+#define _DG1_DPLL3_CFGCR0 0x16C28C
+#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+ _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, \
+ _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1 0x16C288
+#define _DG1_DPLL3_CFGCR1 0x16C290
+#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+ _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, \
+ _DG1_DPLL3_CFGCR1)
+
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
#define _DKL_PHY3_BASE 0x16A000
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 13/60] drm/i915/dg1: Add and setup DPLLs for DG1
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (11 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 12/60] drm/i915/dg1: Add DPLL macros for DG1 Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 14/60] drm/i915/dg1: Enable DPLL " Matthew Auld
` (51 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Aditya Swarup <aditya.swarup@intel.com>
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++--
1 file changed, 37 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index aeb6ee395cce..25c6dca096ac 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3504,7 +3504,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
+ if (IS_DG1(dev_priv)) {
+ if (port == PORT_D || port == PORT_E) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_DG1_DPLL3);
+ } else {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL0) |
+ BIT(DPLL_ID_DG1_DPLL1);
+ }
+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
dpll_mask =
BIT(DPLL_ID_EHL_DPLL4) |
BIT(DPLL_ID_ICL_DPLL1) |
@@ -3791,7 +3801,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+ } else if (INTEL_GEN(dev_priv) >= 12) {
hw_state->cfgcr0 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3844,7 +3857,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (IS_DG1(dev_priv)) {
+ cfgcr0_reg = DG1_DPLL_CFGCR0(id);
+ cfgcr1_reg = DG1_DPLL_CFGCR1(id);
+ } else if (INTEL_GEN(dev_priv) >= 12) {
cfgcr0_reg = TGL_DPLL_CFGCR0(id);
cfgcr1_reg = TGL_DPLL_CFGCR1(id);
} else {
@@ -4276,6 +4292,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info dg1_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr dg1_pll_mgr = {
+ .dpll_info = dg1_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4289,7 +4320,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_DG1(dev_priv))
+ dpll_mgr = &dg1_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 12)
dpll_mgr = &tgl_pll_mgr;
else if (IS_ELKHARTLAKE(dev_priv))
dpll_mgr = &ehl_pll_mgr;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 14/60] drm/i915/dg1: Enable DPLL for DG1
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (12 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 13/60] drm/i915/dg1: Add and setup DPLLs " Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 15/60] drm/i915/dg1: add hpd interrupt handling Matthew Auld
` (50 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Aditya Swarup <aditya.swarup@intel.com>
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 +++
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 25c6dca096ac..0c58d8012d32 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3833,12 +3833,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv))
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4)
enable_reg = MG_PLL_ENABLE(0);
- }
+ else
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
@@ -4036,10 +4038,12 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
/*
@@ -4049,6 +4053,8 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
*/
pll->wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_DPLL_DC_OFF);
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4148,16 +4154,20 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
return;
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_disable(dev_priv, pll, enable_reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f362c65b1de7..a423946e0f78 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10307,6 +10307,10 @@ enum skl_power_gate {
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 15/60] drm/i915/dg1: add hpd interrupt handling
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (13 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 14/60] drm/i915/dg1: Enable DPLL " Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 16/60] drm/i915/dg1: invert HPD pins Matthew Auld
` (49 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
v2: Also change intel_hpd_pin_default() to include DG1 mapping
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 8 +++
3 files changed, 61 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 3f1d7b804a66..1838e3c87e73 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -95,7 +95,8 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
* shold be HPD_PORT_{D,E} rather than {C,D}. Note that this differs
* from the behavior of both TGL+TGP and RKL+CMP.
*/
- if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv))
+ if (IS_DG1(dev_priv) ||
+ (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)))
return HPD_PORT_A + port - PORT_A;
switch (phy) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1fa67700d8f4..e8bdc52c94bb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
};
+static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
+ [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
+ [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
+};
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct i915_hotplug *hpd = &dev_priv->hotplug;
@@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
else
hpd->hpd = hpd_ilk;
- if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+ if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+ (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ hpd->pch_hpd = hpd_dg1_sde;
+ else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
hpd->pch_hpd = hpd_tgp;
else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
hpd->pch_hpd = hpd_icp;
@@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
+static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+ case HPD_PORT_B:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+ case HPD_PORT_D:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+ case HPD_PORT_E:
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
u32 ddi_hotplug_trigger, tc_hotplug_trigger;
u32 pin_mask = 0, long_mask = 0;
bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
+ bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
- if (HAS_PCH_TGP(dev_priv)) {
+ if (HAS_PCH_DG1(dev_priv)) {
+ ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+ ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
+ tc_hotplug_trigger = 0;
+ } else if (HAS_PCH_TGP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
} else if (HAS_PCH_JSP(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
@@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
INTEL_PCH_TYPE(dev_priv));
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+ ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
}
@@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
ddi_hotplug_trigger, dig_hotplug_reg,
dev_priv->hotplug.pch_hpd,
- icp_ddi_port_hotplug_long_detect);
+ ddi_port_hotplug_long_detect);
}
if (tc_hotplug_trigger) {
@@ -3145,6 +3179,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
TGP_DDI_HPD_ENABLE_MASK, 0);
}
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ icp_hpd_irq_setup(dev_priv,
+ SDE_DDI_MASK_DG1, 0,
+ DG1_DDI_HPD_ENABLE_MASK, 0);
+}
+
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3533,7 +3574,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
- if (HAS_PCH_TGP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
+ else if (HAS_PCH_TGP(dev_priv))
icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
TGP_TC_HPD_ENABLE_MASK);
else if (HAS_PCH_JSP(dev_priv))
@@ -4049,7 +4092,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
} else {
- if (HAS_PCH_JSP(dev_priv))
+ if (HAS_PCH_DG1(dev_priv))
+ dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ else if (HAS_PCH_JSP(dev_priv))
dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
else if (HAS_PCH_MCC(dev_priv))
dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a423946e0f78..614b2da4e6b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8230,6 +8230,10 @@ enum {
SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_C) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+ SDE_DDI_HOTPLUG_ICP(PORT_A))
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -8429,6 +8433,10 @@ enum {
#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
ICP_TC_HPD_ENABLE(PORT_TC5) | \
ICP_TC_HPD_ENABLE_MASK)
+#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 16/60] drm/i915/dg1: invert HPD pins
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (14 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 15/60] drm/i915/dg1: add hpd interrupt handling Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 17/60] drm/i915/dg1: gmbus pin mapping Matthew Auld
` (48 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Clinton A Taylor <clinton.a.taylor@intel.com>
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e8bdc52c94bb..6225390edbb4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3181,6 +3181,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
+ intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0,
+ INVERT_DDIA_HPD | INVERT_DDIB_HPD |
+ INVERT_DDIC_HPD | INVERT_DDID_HPD);
+
icp_hpd_irq_setup(dev_priv,
SDE_DDI_MASK_DG1, 0,
DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 614b2da4e6b6..1ae8d8542b66 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8697,6 +8697,10 @@ enum {
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define FDI_BC_BIFURCATION_SELECT (1 << 12)
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 17/60] drm/i915/dg1: gmbus pin mapping
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (15 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 16/60] drm/i915/dg1: invert HPD pins Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 18/60] drm/i915/dg1: Enable first 2 ports for DG1 Matthew Auld
` (47 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
BSpec: 49311, 49945, 20124
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 9 ++++++++-
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index c53c85d38fa5..b6a0f5e5a9a6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1602,7 +1602,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ return vbt_pin;
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map);
} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a8d119b6b45c..528e48658340 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
};
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ return &gmbus_pins_dg1[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return &gmbus_pins_icp[pin];
else if (HAS_PCH_CNP(dev_priv))
return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ size = ARRAY_SIZE(gmbus_pins_dg1);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
else if (HAS_PCH_CNP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7dc11ea4c6e4..b0e112bda429 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3116,6 +3116,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
return GMBUS_PIN_1_BXT + phy;
}
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+ return intel_port_to_phy(dev_priv, port) + 1;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3153,7 +3158,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
return ddc_pin;
}
- if (IS_ROCKETLAKE(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+ else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
else if (HAS_PCH_MCC(dev_priv))
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 18/60] drm/i915/dg1: Enable first 2 ports for DG1
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (16 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 17/60] drm/i915/dg1: gmbus pin mapping Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 19/60] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Matthew Auld
` (46 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Aditya Swarup <aditya.swarup@intel.com>
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 729ec6e0d43a..8b30daf7e304 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7230,6 +7230,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_DG1(dev_priv))
+ /* FIXME: Enable only two ports for now */
+ return phy <= PHY_B;
else if (IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
@@ -7242,7 +7245,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv))
return false;
else if (INTEL_GEN(dev_priv) >= 12)
return phy >= PHY_D && phy <= PHY_I;
@@ -16842,11 +16845,15 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
return;
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ /* FIXME: Enable only two ports for now */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
- intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
} else if (INTEL_GEN(dev_priv) >= 12) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 19/60] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (17 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 18/60] drm/i915/dg1: Enable first 2 ports for DG1 Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 20/60] drm/i915/dg1: Update comp master/slave relationships for PHYs Matthew Auld
` (45 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
logic that conditionally skips PHY_MISC usage to DG1 as well.
Bspec: 50107
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index eccaa79cb4a9..f6d7f807b884 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
* other combo PHY's.
*/
if (IS_ELKHARTLAKE(i915) ||
- IS_ROCKETLAKE(i915))
+ IS_ROCKETLAKE(i915) ||
+ IS_DG1(i915))
return phy < PHY_C;
return true;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 20/60] drm/i915/dg1: Update comp master/slave relationships for PHYs
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (18 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 19/60] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 21/60] drm/i915/dg1: Update voltage swing tables for DP Matthew Auld
` (44 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index f6d7f807b884..f10c96d1ec39 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
*
* ICL,TGL:
* A(master) -> B(slave), C(slave)
- * RKL:
+ * RKL,DG1:
* A(master) -> B(slave)
* C(master) -> D(slave)
*
* We must set the IREFGEN bit for any PHY acting as a master
* to another PHY.
*/
- if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+ if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
return true;
return phy == PHY_A;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 21/60] drm/i915/dg1: Update voltage swing tables for DP
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (19 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 20/60] drm/i915/dg1: Update comp master/slave relationships for PHYs Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 22/60] drm/i915/dg1: provide port/phy mapping for vbt Matthew Auld
` (43 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2c484b55bcdf..4a1a896098f9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
+ { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
+ { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
+ { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1012,6 +1040,12 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
return icl_combo_phy_ddi_translations_edp_hbr2;
+ } else if (IS_DG1(dev_priv) && rate > 270000) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
+ return dg1_combo_phy_ddi_translations_dp_hbr2;
+ } else if (IS_DG1(dev_priv)) {
+ *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+ return dg1_combo_phy_ddi_translations_dp_hbr;
}
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 22/60] drm/i915/dg1: provide port/phy mapping for vbt
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (20 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 21/60] drm/i915/dg1: Update voltage swing tables for DP Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 23/60] drm/i915/dg1: map/unmap pll clocks Matthew Auld
` (42 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Roper <matthew.d.roper@intel.com>
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index b6a0f5e5a9a6..2516f561fb8d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1673,7 +1673,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
- if (IS_ROCKETLAKE(dev_priv))
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2638,10 +2638,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_D : AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+ aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+ AUX_CH_E : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 23/60] drm/i915/dg1: map/unmap pll clocks
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (21 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 22/60] drm/i915/dg1: provide port/phy mapping for vbt Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 24/60] drm/i915/dg1: enable PORT C/D aka D/E Matthew Auld
` (41 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.
The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.c | 25 +++++-
drivers/gpu/drm/i915/i915_reg.h | 15 ++++
3 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4a1a896098f9..b5ba02deb24b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2848,6 +2848,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
return 0;
}
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
+
+ /*
+ * If we fail this, something went very wrong: first 2 PLLs should be
+ * used by first 2 phys and last 2 PLLs by last phys
+ */
+ if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+ (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+ return;
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+ val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -2885,6 +2917,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(&dev_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(&dev_priv->dpll.lock);
+}
+
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2900,6 +2945,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpll.lock);
}
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+ u32 port_mask, bool ddi_clk_needed)
+{
+ enum port port;
+ u32 val;
+
+ for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool ddi_clk_off;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+ ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+ if (ddi_clk_needed == !ddi_clk_off)
+ continue;
+
+ /*
+ * Punt on the case now where clock is gated, but it would
+ * be needed by the port. Something else is really broken then.
+ */
+ if (ddi_clk_needed) {
+ WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
+ ddi_clk_needed, ddi_clk_off, phy);
+ continue;
+ }
+
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+ phy_name(phy));
+
+ val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ }
+}
+
static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
@@ -2982,7 +3061,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
ddi_clk_needed = false;
}
- icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ if (IS_DG1(dev_priv))
+ dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+ else
+ icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
}
static void intel_ddi_clk_select(struct intel_encoder *encoder,
@@ -3507,7 +3589,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_map_plls_to_ports(encoder, crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(encoder, crtc_state);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -3693,7 +3777,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
old_conn_state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_unmap_plls_to_ports(encoder);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(encoder);
if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8b30daf7e304..8dc83b480466 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10781,6 +10781,27 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
return 0;
}
+static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ enum intel_dpll_id id;
+ u32 val;
+
+ val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy))
+ & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy);
+
+ if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
+ return;
+
+ pipe_config->icl_port_dplls[port_dpll_id].pll =
+ intel_get_shared_dpll_by_id(dev_priv, id);
+
+ icl_set_active_port_dpll(pipe_config, port_dpll_id);
+}
+
static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
struct intel_crtc_state *pipe_config)
{
@@ -11080,7 +11101,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_DG1(dev_priv))
+ dg1_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (INTEL_GEN(dev_priv) >= 11)
icl_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_CANNONLAKE(dev_priv))
cnl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1ae8d8542b66..7b963f362190 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
@@ -10291,6 +10293,7 @@ enum skl_power_gate {
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+/* ICL Clocks */
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
@@ -10300,6 +10303,18 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+/* DG1 Clocks */
+#define _DG1_DPCLKA_CFGCR0 0x164280
+#define _DG1_DPCLKA1_CFGCR0 0x16C280
+#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
+ _DG1_DPCLKA_CFGCR0, \
+ _DG1_DPCLKA1_CFGCR0)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << (10 + ((phy) % 2)))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << (((phy) % 2) * 2))
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (((pll) % 2) << (((phy) % 2)) * 2)
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 24/60] drm/i915/dg1: enable PORT C/D aka D/E
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (22 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 23/60] drm/i915/dg1: map/unmap pll clocks Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC Matthew Auld
` (40 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the index of A, B, D and E. However in some places this is
not true:
- VBT: uses C and D and have to be mapped to D/E
- IO/Combo: uses C and D, but we already differentiate those when
we created the phy vs port distinction.
Ths additional mapping for VBT and phy are already covered in previous
patches, so now we can initialize the DDI as D/E.
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8dc83b480466..223042bcbfd7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7230,10 +7230,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
- else if (IS_DG1(dev_priv))
- /* FIXME: Enable only two ports for now */
- return phy <= PHY_B;
- else if (IS_ROCKETLAKE(dev_priv))
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
@@ -7257,7 +7254,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+ if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D)
return (enum phy)port - 1;
else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
return PHY_A;
@@ -16869,9 +16866,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (IS_DG1(dev_priv)) {
- /* FIXME: Enable only two ports for now */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+
+ /*
+ * Bspec lists the ports as A, B, C (USBC1) and D (USBC2).
+ * However from the Display Engine perspective all registers are
+ * actually wired to handle C and D as offsets of D/E. Instead
+ * of fighting all our macros for handling them specially for
+ * DG1, just call them D/E
+ */
+ intel_ddi_init(dev_priv, PORT_D);
+ intel_ddi_init(dev_priv, PORT_E);
} else if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (23 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 24/60] drm/i915/dg1: enable PORT C/D aka D/E Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 26/60] drm/i915/rkl: Add initial workarounds Matthew Auld
` (39 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Matt Atwood <matthew.s.atwood@intel.com>
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index f22a7645c249..ccf13ea627d7 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -38,15 +38,19 @@
* low-power state and comes back to normal.
*/
-#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
+#define DG1_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+MODULE_FIRMWARE(DG1_CSR_PATH);
#define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin"
#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+#define RKL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(RKL_CSR_PATH);
#define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin"
#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6)
-#define TGL_CSR_MAX_FW_SIZE 0x6000
+#define TGL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
MODULE_FIRMWARE(TGL_CSR_PATH);
#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin"
@@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ csr->fw_path = DG1_CSR_PATH;
+ csr->required_version = DG1_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
+ } else if (IS_ROCKETLAKE(dev_priv)) {
csr->fw_path = RKL_CSR_PATH;
csr->required_version = RKL_CSR_VERSION_REQUIRED;
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
} else if (INTEL_GEN(dev_priv) >= 12) {
csr->fw_path = TGL_CSR_PATH;
csr->required_version = TGL_CSR_VERSION_REQUIRED;
- /* Allow to load fw via parameter using the last known size */
- csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
} else if (IS_GEN(dev_priv, 11)) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 26/60] drm/i915/rkl: Add initial workarounds
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (24 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 27/60] drm/i915/dg1: Add initial DG1 workarounds Matthew Auld
` (38 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
RKL and TGL share some general gen12 workarounds, but each platform also
has its own platform-specific workarounds.
v2:
- Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to
TGL's, so we'll have both functions call the tgl_ function for now;
this workaround isn't listed for DG1 so we don't want to add it to
the general gen12_ function.
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++--------
2 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index d03860fef2d7..c26ca029fc0a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2843,8 +2843,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0] */
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ /* Wa_14010477008:tgl[a0..c0],rkl[all] */
+ if (IS_ROCKETLAKE(dev_priv) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5726cd0a37e0..1521dbc13b9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
-static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
/*
* Wa_1409142259:tgl
@@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
* Wa_1409207793:tgl
* Wa_1409178076:tgl
* Wa_1408979724:tgl
+ * Wa_14010443199:rkl
+ * Wa_14010698770:rkl
*/
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ /* WaDisableGPGPUMidThreadPreemption:gen12 */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
+ GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
+}
+
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
/*
- * Wa_1604555607:gen12 and Wa_1608008084:gen12
+ * Wa_1604555607:tgl,rkl
+ *
+ * Note that the implementation of this workaround is further modified
+ * according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
* FF_MODE2 register will return the wrong value when read. The default
* value for this register is zero for all fields and there are no bit
* masks. So instead of doing a RMW we should just write the GS Timer
@@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
0);
-
- /* WaDisableGPGPUMidThreadPreemption:tgl */
- WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
}
static void
@@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
@@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
static void
-tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+gen12_gt_workarounds_init(struct drm_i915_private *i915,
+ struct i915_wa_list *wal)
{
wa_init_mcr(i915, wal);
+}
+
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
@@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 12))
+ if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 12))
+ gen12_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
@@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
- /*
- * Wa_1607030317:tgl
- * Wa_1607186500:tgl
- * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2
- * of then says it is fixed on B0 the other one says it is
- * permanent
- */
- wa_masked_en(wal,
- GEN6_RC_SLEEP_PSMI_CONTROL,
- GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
- GEN8_RC_SEMA_IDLE_MSG_DISABLE);
-
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1654,22 +1664,17 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl */
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
- /* Wa_1409804808:tgl */
+ /* Wa_1409804808:tgl,rkl */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
- /* Wa_1606700617:tgl */
- wa_masked_en(wal,
- GEN9_CS_DEBUG_MODE1,
- FF_DOP_CLOCK_GATE_DISABLE);
-
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl
+ * Wa_14010229206:tgl,rkl
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
@@ -1680,6 +1685,25 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
*/
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
+
+ /*
+ * Wa_1607030317:tgl
+ * Wa_1607186500:tgl
+ * Wa_1607297627:tgl,rkl there are multiple entries for this
+ * WA in the BSpec; some indicate this is an A0-only WA,
+ * others indicate it applies to all steppings.
+ */
+ wa_masked_en(wal,
+ GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE);
+ }
+
+ if (IS_TIGERLAKE(i915)) {
+ /* Wa_1606700617:tgl */
+ wa_masked_en(wal,
+ GEN9_CS_DEBUG_MODE1,
+ FF_DOP_CLOCK_GATE_DISABLE);
}
if (IS_GEN(i915, 11)) {
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 27/60] drm/i915/dg1: Add initial DG1 workarounds
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (25 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 26/60] drm/i915/rkl: Add initial workarounds Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 28/60] drm/i915/dg1: DG1 does not support DC6 Matthew Auld
` (37 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Stuart Summers <stuart.summers@intel.com>
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
BSpec: 53508
v2: Also add Wa_16011227922
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../drm/i915/display/intel_display_power.c | 5 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++++---
drivers/gpu/drm/i915/i915_pci.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 17 +++-
6 files changed, 108 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b51b82cb2398..21f39c94056e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5462,8 +5462,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
- if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
- /* Wa_1409767108: tgl */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ /* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index c26ca029fc0a..d03a239e6977 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2843,8 +2843,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- /* Wa_14010477008:tgl[a0..c0],rkl[all] */
- if (IS_ROCKETLAKE(dev_priv) ||
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1521dbc13b9d..6294022e23a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -641,6 +641,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
0);
}
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+
+ /* Wa_1409044764 */
+ WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+ /* Wa_22010493298 */
+ WA_SET_BIT_MASKED(HIZ_CHICKEN,
+ DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -653,7 +667,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_ctx_workarounds_init(engine, wal);
+ else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -1213,10 +1229,30 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
}
+static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+
+ /* Wa_1607087056:dg1 */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ wa_write_or(wal,
+ SLICE_UNIT_LEVEL_CLKGATE,
+ L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+ /* Wa_1409420604:dg1 */
+ if (IS_DG1(i915))
+ wa_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_TIGERLAKE(i915))
+ if (IS_DG1(i915))
+ dg1_gt_workarounds_init(i915, wal);
+ else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
else if (IS_GEN(i915, 12))
gen12_gt_workarounds_init(i915, wal);
@@ -1581,6 +1617,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
}
}
+static void dg1_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ tgl_whitelist_build(engine);
+
+ /* GEN:BUG:1409280441:dg1 */
+ if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+ (engine->class == RENDER_CLASS ||
+ engine->class == COPY_ENGINE_CLASS))
+ whitelist_reg_ext(w, RING_ID(engine->mmio_base),
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1588,7 +1638,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 12))
+ if (IS_DG1(i915))
+ dg1_whitelist_build(engine);
+ else if (IS_GEN(i915, 12))
tgl_whitelist_build(engine);
else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
@@ -1642,15 +1694,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
- * Wa_1607138336:tgl
- * Wa_1607063988:tgl
+ * Wa_1607138336:tgl[a0],dg1[a0]
+ * Wa_1607063988:tgl[a0],dg1[a0]
*/
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+ }
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/*
* Wa_1606679103:tgl
* (see also Wa_1606682166:icl)
@@ -1660,21 +1715,28 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
/* Wa_1408615072:tgl */
+ }
+
+ if (IS_DG1(i915) || IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+ /* Wa_1408615072:tgl[a0],dg1 */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
}
- if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1606931601:tgl,rkl */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1606931601:tgl,rkl,dg1 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ }
- /* Wa_1409804808:tgl,rkl */
+ if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+ /* Wa_1409804808:tgl,rkl,dg1[a0] */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
- * Wa_14010229206:tgl,rkl
+ * Wa_14010229206:tgl,rkl,dg1[a0]
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
@@ -1689,9 +1751,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
/*
* Wa_1607030317:tgl
* Wa_1607186500:tgl
- * Wa_1607297627:tgl,rkl there are multiple entries for this
- * WA in the BSpec; some indicate this is an A0-only WA,
- * others indicate it applies to all steppings.
+ * Wa_1607297627:tgl,rkl,dg1[a0]
+ *
+ * On TGL and RKL there are multiple entries for this WA in the
+ * BSpec; some indicate this is an A0-only WA, others indicate
+ * it applies to all steppings so we trust the "all steppings."
+ * For DG1 this only applies to A0.
*/
wa_masked_en(wal,
GEN6_RC_SLEEP_PSMI_CONTROL,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 85e2557563cf..8f2e44cabd56 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -909,6 +909,8 @@ static const struct intel_device_info dg1_info = {
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
BIT(VCS0) | BIT(VCS2),
+ /* Wa_16011227922 */
+ .ppgtt_size = 47,
};
#undef GEN
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7b963f362190..7191ebd7c13f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2529,6 +2529,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
#define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
#define RING_HWS_PGA(base) _MMIO((base) + 0x80)
+#define RING_ID(base) _MMIO((base) + 0x8c)
#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080)
#define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
#define RESET_CTL_CAT_ERROR REG_BIT(2)
@@ -4142,6 +4143,7 @@ enum {
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
+#define DPT_GATING_DIS REG_BIT(22)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
@@ -8021,12 +8023,14 @@ enum {
#define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9)
-#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
- #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
- #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9)
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
+#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
+#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1 << 15)
+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE (1 << 14)
# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3)
#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfabbe0481ab..0c4e95fbda4d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7151,6 +7151,19 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
0, DFR_DISABLE);
}
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ /*
+ * As opposed to TGL, we should not touch the registers for media power
+ * gating
+ */
+
+ /* Wa_14010096844:dg1[a0] */
+ if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+ I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+ DPT_GATING_DIS);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -7592,7 +7605,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 12))
+ if (IS_DG1(dev_priv))
+ dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ else if (IS_GEN(dev_priv, 12))
dev_priv->display.init_clock_gating = tgl_init_clock_gating;
else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 28/60] drm/i915/dg1: DG1 does not support DC6
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (26 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 27/60] drm/i915/dg1: Add initial DG1 workarounds Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 29/60] drm/i915/lmem: Limit block size to 4G Matthew Auld
` (36 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: Anshuman Gupta <anshuman.gupta@intel.com>
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21f39c94056e..389a0f2d3a14 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int max_dc;
if (INTEL_GEN(dev_priv) >= 12) {
- max_dc = 4;
+ if (IS_DG1(dev_priv))
+ max_dc = 3;
+ else
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 29/60] drm/i915/lmem: Limit block size to 4G
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (27 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 28/60] drm/i915/dg1: DG1 does not support DC6 Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 30/60] drm/i915/lmem: Do not check r->sgt.pfn for NULL Matthew Auld
` (35 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
when allocating pages to lmem object of size 4G or greater
we allocate memory blocks from buddy system. In this scenario
buddy sytem can allocate blocks that can have size >= 4G and
these blocks require >32b to represent block size with these
blocks we run into an issue with sg list construction because
sg->length field is only 32b wide.
Hence limit the max allowed block size to less than 4G.
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: CQ Tang <cq.tang@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
---
drivers/gpu/drm/i915/intel_memory_region.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 6b5e9d88646d..2943c7778d5e 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -72,6 +72,7 @@ __intel_memory_region_get_pages_buddy(struct intel_memory_region *mem,
struct list_head *blocks)
{
unsigned int min_order = 0;
+ unsigned int max_order;
unsigned long n_pages;
GEM_BUG_ON(!IS_ALIGNED(size, mem->mm.chunk_size));
@@ -92,13 +93,24 @@ __intel_memory_region_get_pages_buddy(struct intel_memory_region *mem,
n_pages = size >> ilog2(mem->mm.chunk_size);
+ /*
+ * When allocating pages for an lmem object of size > 4G
+ * the memory blocks allocated from buddy system could be
+ * from sizes greater than 4G requiring > 32b to represent
+ * block size. But those blocks cannot be used in sg list
+ * construction(in caller) as sg->length is only 32b wide.
+ * Hence limiting the block size to 4G.
+ */
+ max_order = (ilog2(SZ_4G) - 1) - ilog2(mem->mm.chunk_size);
+
mutex_lock(&mem->mm_lock);
do {
struct i915_buddy_block *block;
unsigned int order;
- order = fls(n_pages) - 1;
+ order = min_t(u32, (fls(n_pages) - 1), max_order);
+
GEM_BUG_ON(order > mem->mm.max_order);
GEM_BUG_ON(order < min_order);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 30/60] drm/i915/lmem: Do not check r->sgt.pfn for NULL
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (28 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 29/60] drm/i915/lmem: Limit block size to 4G Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 31/60] drm/i915/dgfx: define llc and snooping behaviour Matthew Auld
` (34 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Wen, Kui
From: "Wen, Kui" <kui.wen@intel.com>
When user space does mmap, kernel would map the physical page of local memory
to virtual memory address. The r->sgt.pfn is page address allocated from
local memory and the local memory region is from 0 to LMEM size. Hence the
r->sgt.pfn is possible to be 0, but this is normal case.
Signed-off-by: Kui Wen <kui.wen@intel.com>
---
drivers/gpu/drm/i915/i915_mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 43039dc8c607..dcf6b3e5bfdf 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -62,7 +62,7 @@ static int remap_sg(pte_t *pte, unsigned long addr, void *data)
{
struct remap_pfn *r = data;
- if (GEM_WARN_ON(!r->sgt.pfn))
+ if (GEM_WARN_ON(!use_dma(r->iobase) && !r->sgt.pfn))
return -EINVAL;
/* Special PTE are not associated with any struct page */
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 31/60] drm/i915/dgfx: define llc and snooping behaviour
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (29 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 30/60] drm/i915/lmem: Do not check r->sgt.pfn for NULL Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread Matthew Auld
` (33 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
While we do lack the faster shared LLC, we should still have support
for snooping over PCIe.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8f2e44cabd56..d5e27202d150 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -899,6 +899,8 @@ static const struct intel_device_info rkl_info = {
GEN12_FEATURES, \
.memory_regions = REGION_SMEM | REGION_LMEM, \
.has_master_unit_irq = 1, \
+ .has_llc = 0, \
+ .has_snoop = 1, \
.is_dgfx = 1
static const struct intel_device_info dg1_info = {
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (30 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 31/60] drm/i915/dgfx: define llc and snooping behaviour Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 12:39 ` Tvrtko Ursulin
2020-07-10 11:57 ` [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite Matthew Auld
` (32 subsequent siblings)
64 siblings, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
We need to add support for pread'ing an LMEM object.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 112 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 6 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 6 +
4 files changed, 126 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 932ee21e6609..9142ba299aa1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -8,6 +8,92 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
+static int lmem_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *arg)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_runtime_pm *rpm = &i915->runtime_pm;
+ intel_wakeref_t wakeref;
+ struct dma_fence *fence;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_wc_domain(obj, false);
+ if (ret) {
+ i915_gem_object_unlock(obj);
+ goto out_unpin;
+ }
+
+ fence = i915_gem_object_lock_fence(obj);
+ i915_gem_object_unlock(obj);
+ if (!fence) {
+ ret = -ENOMEM;
+ goto out_unpin;
+ }
+
+ wakeref = intel_runtime_pm_get(rpm);
+
+ remain = arg->size;
+ user_data = u64_to_user_ptr(arg->data_ptr);
+ offset = offset_in_page(arg->offset);
+ for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+ unwritten = __copy_to_user_inatomic(user_data,
+ (void __force *)vaddr + offset,
+ length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ unwritten = copy_to_user(user_data,
+ (void __force *)vaddr + offset,
+ length);
+ io_mapping_unmap(vaddr);
+ }
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(rpm, wakeref);
+ i915_gem_object_unlock_fence(obj, fence);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.name = "i915_gem_object_lmem",
.flags = I915_GEM_OBJECT_HAS_IOMEM,
@@ -15,8 +101,34 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
+
+ .pread = lmem_pread,
};
+void __iomem *
+i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
+
+ return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
return obj->ops == &i915_gem_lmem_obj_ops;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index fc3f15580fe3..a24d94bc380f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -14,6 +14,12 @@ struct intel_memory_region;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 5335f799b548..b37ae7b32f53 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -56,6 +56,8 @@ struct drm_i915_gem_object_ops {
void (*truncate)(struct drm_i915_gem_object *obj);
void (*writeback)(struct drm_i915_gem_object *obj);
+ int (*pread)(struct drm_i915_gem_object *,
+ const struct drm_i915_gem_pread *arg);
int (*pwrite)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pwrite *arg);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9aa3066cb75d..1805b5e6bc30 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -519,6 +519,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
trace_i915_gem_object_pread(obj, args->offset, args->size);
+ ret = -ENODEV;
+ if (obj->ops->pread)
+ ret = obj->ops->pread(obj, args);
+ if (ret != -ENODEV)
+ goto out;
+
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread
2020-07-10 11:57 ` [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread Matthew Auld
@ 2020-07-10 12:39 ` Tvrtko Ursulin
2020-07-10 13:04 ` Chris Wilson
0 siblings, 1 reply; 88+ messages in thread
From: Tvrtko Ursulin @ 2020-07-10 12:39 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
On 10/07/2020 12:57, Matthew Auld wrote:
> We need to add support for pread'ing an LMEM object.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 112 ++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 6 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
> drivers/gpu/drm/i915/i915_gem.c | 6 +
> 4 files changed, 126 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> index 932ee21e6609..9142ba299aa1 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> @@ -8,6 +8,92 @@
> #include "gem/i915_gem_lmem.h"
> #include "i915_drv.h"
>
> +static int lmem_pread(struct drm_i915_gem_object *obj,
> + const struct drm_i915_gem_pread *arg)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> + struct intel_runtime_pm *rpm = &i915->runtime_pm;
> + intel_wakeref_t wakeref;
> + struct dma_fence *fence;
> + char __user *user_data;
> + unsigned int offset;
> + unsigned long idx;
> + u64 remain;
> + int ret;
> +
> + ret = i915_gem_object_wait(obj,
> + I915_WAIT_INTERRUPTIBLE,
> + MAX_SCHEDULE_TIMEOUT);
> + if (ret)
> + return ret;
> +
> + ret = i915_gem_object_pin_pages(obj);
> + if (ret)
> + return ret;
> +
> + i915_gem_object_lock(obj);
> + ret = i915_gem_object_set_to_wc_domain(obj, false);
> + if (ret) {
> + i915_gem_object_unlock(obj);
> + goto out_unpin;
> + }
> +
> + fence = i915_gem_object_lock_fence(obj);
> + i915_gem_object_unlock(obj);
> + if (!fence) {
> + ret = -ENOMEM;
> + goto out_unpin;
> + }
> +
> + wakeref = intel_runtime_pm_get(rpm);
> +
> + remain = arg->size;
> + user_data = u64_to_user_ptr(arg->data_ptr);
> + offset = offset_in_page(arg->offset);
> + for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
> + unsigned long unwritten;
> + void __iomem *vaddr;
> + int length;
> +
> + length = remain;
> + if (offset + length > PAGE_SIZE)
> + length = PAGE_SIZE - offset;
> +
> + vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
> + if (!vaddr) {
> + ret = -ENOMEM;
> + goto out_put;
> + }
> + unwritten = __copy_to_user_inatomic(user_data,
> + (void __force *)vaddr + offset,
> + length);
> + io_mapping_unmap_atomic(vaddr);
> + if (unwritten) {
> + vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
> + unwritten = copy_to_user(user_data,
> + (void __force *)vaddr + offset,
> + length);
> + io_mapping_unmap(vaddr);
> + }
> + if (unwritten) {
> + ret = -EFAULT;
> + goto out_put;
> + }
> +
> + remain -= length;
> + user_data += length;
> + offset = 0;
> + }
> +
> +out_put:
> + intel_runtime_pm_put(rpm, wakeref);
> + i915_gem_object_unlock_fence(obj, fence);
> +out_unpin:
> + i915_gem_object_unpin_pages(obj);
> +
> + return ret;
> +}
> +
> const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
> .name = "i915_gem_object_lmem",
> .flags = I915_GEM_OBJECT_HAS_IOMEM,
> @@ -15,8 +101,34 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
> .get_pages = i915_gem_object_get_pages_buddy,
> .put_pages = i915_gem_object_put_pages_buddy,
> .release = i915_gem_object_release_memory_region,
> +
> + .pread = lmem_pread,
> };
>
> +void __iomem *
> +i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
> + unsigned long n)
> +{
> + resource_size_t offset;
> +
> + offset = i915_gem_object_get_dma_address(obj, n);
> + offset -= obj->mm.region->region.start;
> +
> + return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
> +}
> +
> +void __iomem *
> +i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
> + unsigned long n)
> +{
> + resource_size_t offset;
> +
> + offset = i915_gem_object_get_dma_address(obj, n);
> + offset -= obj->mm.region->region.start;
> +
> + return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
> +}
> +
> bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
> {
> return obj->ops == &i915_gem_lmem_obj_ops;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
> index fc3f15580fe3..a24d94bc380f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
> @@ -14,6 +14,12 @@ struct intel_memory_region;
>
> extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
>
> +void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
> + unsigned long n);
> +void __iomem *
> +i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
> + unsigned long n);
> +
> bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
>
> struct drm_i915_gem_object *
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 5335f799b548..b37ae7b32f53 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -56,6 +56,8 @@ struct drm_i915_gem_object_ops {
> void (*truncate)(struct drm_i915_gem_object *obj);
> void (*writeback)(struct drm_i915_gem_object *obj);
>
> + int (*pread)(struct drm_i915_gem_object *,
> + const struct drm_i915_gem_pread *arg);
> int (*pwrite)(struct drm_i915_gem_object *obj,
> const struct drm_i915_gem_pwrite *arg);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 9aa3066cb75d..1805b5e6bc30 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -519,6 +519,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
>
> trace_i915_gem_object_pread(obj, args->offset, args->size);
>
> + ret = -ENODEV;
> + if (obj->ops->pread)
> + ret = obj->ops->pread(obj, args);
> + if (ret != -ENODEV)
> + goto out;
> +
> ret = i915_gem_object_wait(obj,
> I915_WAIT_INTERRUPTIBLE,
> MAX_SCHEDULE_TIMEOUT);
>
It would be really nice to consolidate the redundant
wait/lock/pin/domain management between smem and lmem paths (new vfunc
vs the existing code). Maybe pull out all the common operations and to
the rest wholly via vfuncs?
Or maybe bits of Maarten's "drm/i915: Remove locking from
i915_gem_object_prepare_read/write" could be used here, not sure without
a deeper look. Just wanting to pencil this area for rework hopefully
before the merge.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread
2020-07-10 12:39 ` Tvrtko Ursulin
@ 2020-07-10 13:04 ` Chris Wilson
0 siblings, 0 replies; 88+ messages in thread
From: Chris Wilson @ 2020-07-10 13:04 UTC (permalink / raw)
To: Matthew Auld, Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-07-10 13:39:32)
>
> On 10/07/2020 12:57, Matthew Auld wrote:
> > We need to add support for pread'ing an LMEM object.
> >
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 112 ++++++++++++++++++
> > drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 6 +
> > .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
> > drivers/gpu/drm/i915/i915_gem.c | 6 +
> > 4 files changed, 126 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> > index 932ee21e6609..9142ba299aa1 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> > @@ -8,6 +8,92 @@
> > #include "gem/i915_gem_lmem.h"
> > #include "i915_drv.h"
> >
> > +static int lmem_pread(struct drm_i915_gem_object *obj,
> > + const struct drm_i915_gem_pread *arg)
> > +{
> > + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> > + struct intel_runtime_pm *rpm = &i915->runtime_pm;
> > + intel_wakeref_t wakeref;
> > + struct dma_fence *fence;
> > + char __user *user_data;
> > + unsigned int offset;
> > + unsigned long idx;
> > + u64 remain;
> > + int ret;
> > +
> > + ret = i915_gem_object_wait(obj,
> > + I915_WAIT_INTERRUPTIBLE,
> > + MAX_SCHEDULE_TIMEOUT);
> > + if (ret)
> > + return ret;
> > +
> > + ret = i915_gem_object_pin_pages(obj);
> > + if (ret)
> > + return ret;
> > +
> > + i915_gem_object_lock(obj);
> > + ret = i915_gem_object_set_to_wc_domain(obj, false);
> > + if (ret) {
> > + i915_gem_object_unlock(obj);
> > + goto out_unpin;
> > + }
> > +
> > + fence = i915_gem_object_lock_fence(obj);
> > + i915_gem_object_unlock(obj);
> > + if (!fence) {
> > + ret = -ENOMEM;
> > + goto out_unpin;
> > + }
> > +
> > + wakeref = intel_runtime_pm_get(rpm);
> > +
> > + remain = arg->size;
> > + user_data = u64_to_user_ptr(arg->data_ptr);
> > + offset = offset_in_page(arg->offset);
> > + for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
> > + unsigned long unwritten;
> > + void __iomem *vaddr;
> > + int length;
> > +
> > + length = remain;
> > + if (offset + length > PAGE_SIZE)
> > + length = PAGE_SIZE - offset;
> > +
> > + vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
> > + if (!vaddr) {
> > + ret = -ENOMEM;
> > + goto out_put;
> > + }
> > + unwritten = __copy_to_user_inatomic(user_data,
> > + (void __force *)vaddr + offset,
> > + length);
> > + io_mapping_unmap_atomic(vaddr);
> > + if (unwritten) {
> > + vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
> > + unwritten = copy_to_user(user_data,
> > + (void __force *)vaddr + offset,
> > + length);
> > + io_mapping_unmap(vaddr);
> > + }
> > + if (unwritten) {
> > + ret = -EFAULT;
> > + goto out_put;
> > + }
> > +
> > + remain -= length;
> > + user_data += length;
> > + offset = 0;
> > + }
> > +
> > +out_put:
> > + intel_runtime_pm_put(rpm, wakeref);
> > + i915_gem_object_unlock_fence(obj, fence);
> > +out_unpin:
> > + i915_gem_object_unpin_pages(obj);
> > +
> > + return ret;
> > +}
> > +
> > const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
> > .name = "i915_gem_object_lmem",
> > .flags = I915_GEM_OBJECT_HAS_IOMEM,
> > @@ -15,8 +101,34 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
> > .get_pages = i915_gem_object_get_pages_buddy,
> > .put_pages = i915_gem_object_put_pages_buddy,
> > .release = i915_gem_object_release_memory_region,
> > +
> > + .pread = lmem_pread,
> > };
> >
> > +void __iomem *
> > +i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
> > + unsigned long n)
> > +{
> > + resource_size_t offset;
> > +
> > + offset = i915_gem_object_get_dma_address(obj, n);
> > + offset -= obj->mm.region->region.start;
> > +
> > + return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
> > +}
> > +
> > +void __iomem *
> > +i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
> > + unsigned long n)
> > +{
> > + resource_size_t offset;
> > +
> > + offset = i915_gem_object_get_dma_address(obj, n);
> > + offset -= obj->mm.region->region.start;
> > +
> > + return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
> > +}
> > +
> > bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
> > {
> > return obj->ops == &i915_gem_lmem_obj_ops;
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
> > index fc3f15580fe3..a24d94bc380f 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
> > @@ -14,6 +14,12 @@ struct intel_memory_region;
> >
> > extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
> >
> > +void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
> > + unsigned long n);
> > +void __iomem *
> > +i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
> > + unsigned long n);
> > +
> > bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
> >
> > struct drm_i915_gem_object *
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > index 5335f799b548..b37ae7b32f53 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > @@ -56,6 +56,8 @@ struct drm_i915_gem_object_ops {
> > void (*truncate)(struct drm_i915_gem_object *obj);
> > void (*writeback)(struct drm_i915_gem_object *obj);
> >
> > + int (*pread)(struct drm_i915_gem_object *,
> > + const struct drm_i915_gem_pread *arg);
> > int (*pwrite)(struct drm_i915_gem_object *obj,
> > const struct drm_i915_gem_pwrite *arg);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 9aa3066cb75d..1805b5e6bc30 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -519,6 +519,12 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
> >
> > trace_i915_gem_object_pread(obj, args->offset, args->size);
> >
> > + ret = -ENODEV;
> > + if (obj->ops->pread)
> > + ret = obj->ops->pread(obj, args);
> > + if (ret != -ENODEV)
> > + goto out;
> > +
> > ret = i915_gem_object_wait(obj,
> > I915_WAIT_INTERRUPTIBLE,
> > MAX_SCHEDULE_TIMEOUT);
> >
>
> It would be really nice to consolidate the redundant
> wait/lock/pin/domain management between smem and lmem paths (new vfunc
> vs the existing code). Maybe pull out all the common operations and to
> the rest wholly via vfuncs?
>
> Or maybe bits of Maarten's "drm/i915: Remove locking from
> i915_gem_object_prepare_read/write" could be used here, not sure without
> a deeper look. Just wanting to pencil this area for rework hopefully
> before the merge.
The sketch was to go fully vfunc, but with the vfuncs on the backing
store not the GEM object itself. I have a plan for a simple but universal
handler that complies with ww_mutex semantics (not being allowed to hold
anything across the copy_(to|from)_user is painful, if only we already
knew how to handle that, sigh), but it will be slow and heavy. That
should allow for the default handler in all cases, with special casing
for shmemfs backing store and the like if we know we can do lighter
fastpaths. Same applies for all the other direct access, since we need
to isolate those from migration (and I think we should do them all in
situ without initiating migration implicitly.).
-Chris
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^ permalink raw reply [flat|nested] 88+ messages in thread
* [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (31 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 32/60] drm/i915/lmem: support pread Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-13 5:09 ` Dave Airlie
2020-07-10 11:57 ` [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context Matthew Auld
` (31 subsequent siblings)
64 siblings, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
We need to add support for pwrite'ing an LMEM object.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 86 ++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 9142ba299aa1..e324328639d2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -94,6 +94,91 @@ static int lmem_pread(struct drm_i915_gem_object *obj,
return ret;
}
+static int lmem_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *arg)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_runtime_pm *rpm = &i915->runtime_pm;
+ intel_wakeref_t wakeref;
+ struct dma_fence *fence;
+ char __user *user_data;
+ unsigned int offset;
+ unsigned long idx;
+ u64 remain;
+ int ret;
+
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
+ return ret;
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_wc_domain(obj, true);
+ if (ret) {
+ i915_gem_object_unlock(obj);
+ goto out_unpin;
+ }
+
+ fence = i915_gem_object_lock_fence(obj);
+ i915_gem_object_unlock(obj);
+ if (!fence) {
+ ret = -ENOMEM;
+ goto out_unpin;
+ }
+
+ wakeref = intel_runtime_pm_get(rpm);
+
+ remain = arg->size;
+ user_data = u64_to_user_ptr(arg->data_ptr);
+ offset = offset_in_page(arg->offset);
+ for (idx = arg->offset >> PAGE_SHIFT; remain; idx++) {
+ unsigned long unwritten;
+ void __iomem *vaddr;
+ int length;
+
+ length = remain;
+ if (offset + length > PAGE_SIZE)
+ length = PAGE_SIZE - offset;
+
+ vaddr = i915_gem_object_lmem_io_map_page_atomic(obj, idx);
+ if (!vaddr) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
+
+ unwritten = __copy_from_user_inatomic_nocache((void __force*)vaddr + offset,
+ user_data, length);
+ io_mapping_unmap_atomic(vaddr);
+ if (unwritten) {
+ vaddr = i915_gem_object_lmem_io_map_page(obj, idx);
+ unwritten = copy_from_user((void __force*)vaddr + offset,
+ user_data, length);
+ io_mapping_unmap(vaddr);
+ }
+ if (unwritten) {
+ ret = -EFAULT;
+ goto out_put;
+ }
+
+ remain -= length;
+ user_data += length;
+ offset = 0;
+ }
+
+out_put:
+ intel_runtime_pm_put(rpm, wakeref);
+ i915_gem_object_unlock_fence(obj, fence);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+
+ return ret;
+}
+
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.name = "i915_gem_object_lmem",
.flags = I915_GEM_OBJECT_HAS_IOMEM,
@@ -103,6 +188,7 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.release = i915_gem_object_release_memory_region,
.pread = lmem_pread,
+ .pwrite = lmem_pwrite,
};
void __iomem *
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-10 11:57 ` [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite Matthew Auld
@ 2020-07-13 5:09 ` Dave Airlie
2020-07-14 14:35 ` Matthew Auld
2020-08-07 9:46 ` Joonas Lahtinen
0 siblings, 2 replies; 88+ messages in thread
From: Dave Airlie @ 2020-07-13 5:09 UTC (permalink / raw)
To: Matthew Auld; +Cc: Abdiel Janulgue, Intel Graphics Development
On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
>
> We need to add support for pwrite'ing an LMEM object.
why? DG1 is a discrete GPU, these interfaces we already gross and
overly hacky for integrated, I'd prefer not to drag them across into
discrete land.
same goes for pread.
You have no legacy userspace here, userspace needs change to support
LMEM, it can be fixed to avoid legacy ioctls paths.
Dave.
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-13 5:09 ` Dave Airlie
@ 2020-07-14 14:35 ` Matthew Auld
2020-07-16 0:43 ` Dave Airlie
2020-08-07 9:46 ` Joonas Lahtinen
1 sibling, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-14 14:35 UTC (permalink / raw)
To: Dave Airlie; +Cc: Abdiel Janulgue, Intel Graphics Development
On 13/07/2020 06:09, Dave Airlie wrote:
> On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
>>
>> We need to add support for pwrite'ing an LMEM object.
>
> why? DG1 is a discrete GPU, these interfaces we already gross and
> overly hacky for integrated, I'd prefer not to drag them across into
> discrete land.
>
> same goes for pread.
>
> You have no legacy userspace here, userspace needs change to support
> LMEM, it can be fixed to avoid legacy ioctls paths.
Ok, there have also been similar discussions internally in the past. I
think one of the reasons was around IGT, and how keeping the
pread/pwrite interface meant slightly less pain, also it's not much
effort to implement for LMEM. If this is a NACK, then I guess the other
idea was to somehow fallback to mmap and update IGT accordingly.
>
> Dave.
>
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-14 14:35 ` Matthew Auld
@ 2020-07-16 0:43 ` Dave Airlie
2020-07-16 10:11 ` Matthew Auld
0 siblings, 1 reply; 88+ messages in thread
From: Dave Airlie @ 2020-07-16 0:43 UTC (permalink / raw)
To: Matthew Auld; +Cc: Abdiel Janulgue, Intel Graphics Development
On Wed, 15 Jul 2020 at 00:35, Matthew Auld <matthew.auld@intel.com> wrote:
>
> On 13/07/2020 06:09, Dave Airlie wrote:
> > On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
> >>
> >> We need to add support for pwrite'ing an LMEM object.
> >
> > why? DG1 is a discrete GPU, these interfaces we already gross and
> > overly hacky for integrated, I'd prefer not to drag them across into
> > discrete land.
> >
> > same goes for pread.
> >
> > You have no legacy userspace here, userspace needs change to support
> > LMEM, it can be fixed to avoid legacy ioctls paths.
>
> Ok, there have also been similar discussions internally in the past. I
> think one of the reasons was around IGT, and how keeping the
> pread/pwrite interface meant slightly less pain, also it's not much
> effort to implement for LMEM. If this is a NACK, then I guess the other
> idea was to somehow fallback to mmap and update IGT accordingly.
I just don't think we should have internal kernel interfaces for
mapping ram in the kernel address space, seems pointless, makes less
sense with a discrete GPU in the mix, so yes I think NAK for
pread/pwrite at least at this time.
I'd also like to see a hard no relocs policy for DG1 enforced in the kernel.
Dave.
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-16 0:43 ` Dave Airlie
@ 2020-07-16 10:11 ` Matthew Auld
2020-07-19 21:52 ` Dave Airlie
0 siblings, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-16 10:11 UTC (permalink / raw)
To: Dave Airlie; +Cc: Intel Graphics Development
On 16/07/2020 01:43, Dave Airlie wrote:
> On Wed, 15 Jul 2020 at 00:35, Matthew Auld <matthew.auld@intel.com> wrote:
>>
>> On 13/07/2020 06:09, Dave Airlie wrote:
>>> On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
>>>>
>>>> We need to add support for pwrite'ing an LMEM object.
>>>
>>> why? DG1 is a discrete GPU, these interfaces we already gross and
>>> overly hacky for integrated, I'd prefer not to drag them across into
>>> discrete land.
>>>
>>> same goes for pread.
>>>
>>> You have no legacy userspace here, userspace needs change to support
>>> LMEM, it can be fixed to avoid legacy ioctls paths.
>>
>> Ok, there have also been similar discussions internally in the past. I
>> think one of the reasons was around IGT, and how keeping the
>> pread/pwrite interface meant slightly less pain, also it's not much
>> effort to implement for LMEM. If this is a NACK, then I guess the other
>> idea was to somehow fallback to mmap and update IGT accordingly.
>
> I just don't think we should have internal kernel interfaces for
> mapping ram in the kernel address space, seems pointless, makes less
> sense with a discrete GPU in the mix, so yes I think NAK for
> pread/pwrite at least at this time.
Ok.
>
> I'd also like to see a hard no relocs policy for DG1 enforced in the kernel.
Ok, just checking, is that the case even if we don't require extra code
to support it? We recently dropped the CPU reloc path completely, in
favour of single GPU reloc path, and so no special code is required to
support LMEM, it should just work. IGT of course makes heavy use of
relocs, so that would need an overhaul.
>
> Dave.
>
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-16 10:11 ` Matthew Auld
@ 2020-07-19 21:52 ` Dave Airlie
2020-08-07 9:32 ` Joonas Lahtinen
0 siblings, 1 reply; 88+ messages in thread
From: Dave Airlie @ 2020-07-19 21:52 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
On Thu, 16 Jul 2020 at 20:11, Matthew Auld <matthew.auld@intel.com> wrote:
>
> On 16/07/2020 01:43, Dave Airlie wrote:
> > On Wed, 15 Jul 2020 at 00:35, Matthew Auld <matthew.auld@intel.com> wrote:
> >>
> >> On 13/07/2020 06:09, Dave Airlie wrote:
> >>> On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
> >>>>
> >>>> We need to add support for pwrite'ing an LMEM object.
> >>>
> >>> why? DG1 is a discrete GPU, these interfaces we already gross and
> >>> overly hacky for integrated, I'd prefer not to drag them across into
> >>> discrete land.
> >>>
> >>> same goes for pread.
> >>>
> >>> You have no legacy userspace here, userspace needs change to support
> >>> LMEM, it can be fixed to avoid legacy ioctls paths.
> >>
> >> Ok, there have also been similar discussions internally in the past. I
> >> think one of the reasons was around IGT, and how keeping the
> >> pread/pwrite interface meant slightly less pain, also it's not much
> >> effort to implement for LMEM. If this is a NACK, then I guess the other
> >> idea was to somehow fallback to mmap and update IGT accordingly.
> >
> > I just don't think we should have internal kernel interfaces for
> > mapping ram in the kernel address space, seems pointless, makes less
> > sense with a discrete GPU in the mix, so yes I think NAK for
> > pread/pwrite at least at this time.
>
> Ok.
>
> >
> > I'd also like to see a hard no relocs policy for DG1 enforced in the kernel.
>
> Ok, just checking, is that the case even if we don't require extra code
> to support it? We recently dropped the CPU reloc path completely, in
> favour of single GPU reloc path, and so no special code is required to
> support LMEM, it should just work. IGT of course makes heavy use of
> relocs, so that would need an overhaul.
The GPU reloc path is optimising a path that we simply shouldn't need
or be using.
IGT tests relocs, ripping out relocs should reduce the amount of
testing IGT has to do and reduce CI run times. Why carry the techincal
debt deliberately.
I expect the kernel team to be a bit more authorative inside Intel on
why uAPI gets exposed and why, it seems like everytime there is an
attempt to limit the tech debt of carrying forward unnecessary uAPIs
there is some push back for media driver or IGT. Fix stuff and be
harder in pushing back on carrying unneeded interfaces forward so we
future products are less mired in pointless debt. DG1 uAPI should
really be a chance to full review the legacy of integrated graphics +
pre-48-bit VM interfaces and they should all be turned off for DG1 so
that future discrete GPUs can move forward cleaner. I really shouldn't
be the one enforcing this, the i915 team needs to be a bit
authoritative on what is necessary to support.
Dave.
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-19 21:52 ` Dave Airlie
@ 2020-08-07 9:32 ` Joonas Lahtinen
0 siblings, 0 replies; 88+ messages in thread
From: Joonas Lahtinen @ 2020-08-07 9:32 UTC (permalink / raw)
To: Dave Airlie, Matthew Auld; +Cc: Intel Graphics Development
Quoting Dave Airlie (2020-07-20 00:52:19)
> On Thu, 16 Jul 2020 at 20:11, Matthew Auld <matthew.auld@intel.com> wrote:
> >
> > On 16/07/2020 01:43, Dave Airlie wrote:
> > > On Wed, 15 Jul 2020 at 00:35, Matthew Auld <matthew.auld@intel.com> wrote:
> > >>
> > >> On 13/07/2020 06:09, Dave Airlie wrote:
> > >>> On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
> > >>>>
> > >>>> We need to add support for pwrite'ing an LMEM object.
> > >>>
> > >>> why? DG1 is a discrete GPU, these interfaces we already gross and
> > >>> overly hacky for integrated, I'd prefer not to drag them across into
> > >>> discrete land.
> > >>>
> > >>> same goes for pread.
> > >>>
> > >>> You have no legacy userspace here, userspace needs change to support
> > >>> LMEM, it can be fixed to avoid legacy ioctls paths.
> > >>
> > >> Ok, there have also been similar discussions internally in the past. I
> > >> think one of the reasons was around IGT, and how keeping the
> > >> pread/pwrite interface meant slightly less pain, also it's not much
> > >> effort to implement for LMEM. If this is a NACK, then I guess the other
> > >> idea was to somehow fallback to mmap and update IGT accordingly.
> > >
> > > I just don't think we should have internal kernel interfaces for
> > > mapping ram in the kernel address space, seems pointless, makes less
> > > sense with a discrete GPU in the mix, so yes I think NAK for
> > > pread/pwrite at least at this time.
> >
> > Ok.
> >
> > >
> > > I'd also like to see a hard no relocs policy for DG1 enforced in the kernel.
> >
> > Ok, just checking, is that the case even if we don't require extra code
> > to support it? We recently dropped the CPU reloc path completely, in
> > favour of single GPU reloc path, and so no special code is required to
> > support LMEM, it should just work. IGT of course makes heavy use of
> > relocs, so that would need an overhaul.
>
> The GPU reloc path is optimising a path that we simply shouldn't need
> or be using.
>
> IGT tests relocs, ripping out relocs should reduce the amount of
> testing IGT has to do and reduce CI run times. Why carry the techincal
> debt deliberately.
We still have to optimize and keep the the relocations for the older
generations, where they are used. So can't really be eliminated from
codebase as much of the code is shared.
Agreed on the benefit in the more distant future coming from dropping
the relocations, once pre-Gen12 hardware is no more.
Note that IGT also uses relocations indirectly in non-relocation-specific
testtests, so there is quite some work according to our validation team.
Wrt this RFC, as no extra code is needed, it is faster to get stack
up and running with relocations. It also keeps the changes between
iGFX and dGFX minimal, which should help debugging. So that path was
taken to get the functional RFC out as fast as possible.
Moving away from relocations in both IGT and media driver is being
discussed and worked on. See below.
> I expect the kernel team to be a bit more authorative inside Intel on
> why uAPI gets exposed and why, it seems like everytime there is an
> attempt to limit the tech debt of carrying forward unnecessary uAPIs
> there is some push back for media driver or IGT. Fix stuff and be
> harder in pushing back on carrying unneeded interfaces forward so we
> future products are less mired in pointless debt. DG1 uAPI should
> really be a chance to full review the legacy of integrated graphics +
> pre-48-bit VM interfaces and they should all be turned off for DG1 so
> that future discrete GPUs can move forward cleaner. I really shouldn't
> be the one enforcing this, the i915 team needs to be a bit
> authoritative on what is necessary to support.
The patches were sent out as RFC to collect comments. Based on the
comments, we're expediting the work to eliminate the use of relocations.
Regards, Joonas
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-07-13 5:09 ` Dave Airlie
2020-07-14 14:35 ` Matthew Auld
@ 2020-08-07 9:46 ` Joonas Lahtinen
2020-08-09 21:06 ` Dave Airlie
1 sibling, 1 reply; 88+ messages in thread
From: Joonas Lahtinen @ 2020-08-07 9:46 UTC (permalink / raw)
To: Dave Airlie, Matthew Auld; +Cc: Abdiel Janulgue, Intel Graphics Development
Quoting Dave Airlie (2020-07-13 08:09:30)
> On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
> >
> > We need to add support for pwrite'ing an LMEM object.
>
> why? DG1 is a discrete GPU, these interfaces we already gross and
> overly hacky for integrated, I'd prefer not to drag them across into
> discrete land.
>
> same goes for pread.
>
> You have no legacy userspace here, userspace needs change to support
> LMEM, it can be fixed to avoid legacy ioctls paths.
(This answer is really along the same lines as related to the
relocations, which I sent earlier in the end of this thread)
PREAD/PWRITE are used by IGT tests indirectly in the testing, as
a means to validate test end results as an example. So IGT
reworking is needed not to lose testing coverage when the
functionality is disabled.
Same reasoning as with relocations, as to why this is included
in the RFC; it will get a functional stack with least changes and
is virtually no extra effort to carry. It's recognized that once
pre-Gen12 hardware ceases to exist, there are optimization
opportunities.
Based on the feedback to this Request for Comments series, we are
expediting the work on those IGT reworks.
Regards, Joonas
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite
2020-08-07 9:46 ` Joonas Lahtinen
@ 2020-08-09 21:06 ` Dave Airlie
0 siblings, 0 replies; 88+ messages in thread
From: Dave Airlie @ 2020-08-09 21:06 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: Abdiel Janulgue, Intel Graphics Development, Matthew Auld
On Fri, 7 Aug 2020 at 19:46, Joonas Lahtinen
<joonas.lahtinen@linux.intel.com> wrote:
>
> Quoting Dave Airlie (2020-07-13 08:09:30)
> > On Fri, 10 Jul 2020 at 22:00, Matthew Auld <matthew.auld@intel.com> wrote:
> > >
> > > We need to add support for pwrite'ing an LMEM object.
> >
> > why? DG1 is a discrete GPU, these interfaces we already gross and
> > overly hacky for integrated, I'd prefer not to drag them across into
> > discrete land.
> >
> > same goes for pread.
> >
> > You have no legacy userspace here, userspace needs change to support
> > LMEM, it can be fixed to avoid legacy ioctls paths.
>
> (This answer is really along the same lines as related to the
> relocations, which I sent earlier in the end of this thread)
>
> PREAD/PWRITE are used by IGT tests indirectly in the testing, as
> a means to validate test end results as an example. So IGT
> reworking is needed not to lose testing coverage when the
> functionality is disabled.
>
> Same reasoning as with relocations, as to why this is included
> in the RFC; it will get a functional stack with least changes and
> is virtually no extra effort to carry. It's recognized that once
> pre-Gen12 hardware ceases to exist, there are optimization
> opportunities.
Why do you have to wait until pre-GEN12 hw ceases to exist?
There are clear optimization opportunities since Broadwell, there have
been clear pointless optimisations done to the kernel because
userspace was stuck to the legacy paths way past when it made sense.
I'm pretty sure the media driver is broadwell+ in terms of hw support,
but it's all relocation heavy, like why isn't that the priority of the
kernel team to just go fix it rather than make the kernel long term
harder to maintain. Siloed development is an artifact of *your*
orgchart, and shouldn't leak into the upstream kernel development if
not required.
Would IGT ever have been fixed up? it's test code, it should have been
roadmap and resourced to fix up instead of writing kernel code for
platforms that don't require it. You can valdiate IGT on the older
hardware anyways.
If you need test interfaces in the kernel, please put them under
BROKEN or somewhere that only CI finds them, until you can rework CI
tests, but we need to be a bit more stringent on carrying forward
interfaces that aren't needed by modern HW, or else you will never get
to pre-GEN12 disappearing, like in reality it should in a lot of cases
be pre-GEN8.
Dave.
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^ permalink raw reply [flat|nested] 88+ messages in thread
* [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (32 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 33/60] drm/i915/lmem: support pwrite Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-08-03 19:59 ` Lucas De Marchi
2020-07-10 11:57 ` [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI Matthew Auld
` (30 subsequent siblings)
64 siblings, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
We may be without a context to perform various internal blitter
operations, for example when performing object migration. Piggybacking
off the kernel_context is probably a bad idea, since it has other uses.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 +++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dd1a42c4d344..1df94e82550f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -792,6 +792,7 @@ create_kernel_context(struct intel_engine_cs *engine)
int err;
ce = intel_context_create(engine);
+
if (IS_ERR(ce))
return ce;
@@ -845,16 +846,32 @@ static int engine_init_common(struct intel_engine_cs *engine)
return PTR_ERR(ce);
ret = measure_breadcrumb_dw(ce);
- if (ret < 0)
- goto err_context;
+ if (ret < 0) {
+ intel_context_put(ce);
+ return ret;
+ }
engine->emit_fini_breadcrumb_dw = ret;
engine->kernel_context = ce;
+ /*
+ * The blitter context is used to quickly memset or migrate objects
+ * in local memory, so it has to always be available.
+ */
+ if (engine->class == COPY_ENGINE_CLASS) {
+ ce = create_kernel_context(engine);
+ if (IS_ERR(ce)) {
+ ret = PTR_ERR(ce);
+ goto err_kernel_context;
+ }
+
+ engine->blitter_context = ce;
+ }
+
return 0;
-err_context:
- intel_context_put(ce);
+err_kernel_context:
+ intel_context_put(engine->kernel_context);
return ret;
}
@@ -910,6 +927,11 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
if (engine->default_state)
fput(engine->default_state);
+ if (engine->blitter_context) {
+ intel_context_unpin(engine->blitter_context);
+ intel_context_put(engine->blitter_context);
+ }
+
if (engine->kernel_context) {
intel_context_unpin(engine->kernel_context);
intel_context_put(engine->kernel_context);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 490af81bd6f3..3b2d9ed7670f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -342,6 +342,7 @@ struct intel_engine_cs {
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
+ struct intel_context *blitter_context; /* pinned; exists for BCS only */
intel_engine_mask_t saturated; /* submitting semaphores too late? */
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context
2020-07-10 11:57 ` [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context Matthew Auld
@ 2020-08-03 19:59 ` Lucas De Marchi
2020-08-03 20:17 ` Lucas De Marchi
0 siblings, 1 reply; 88+ messages in thread
From: Lucas De Marchi @ 2020-08-03 19:59 UTC (permalink / raw)
To: Matthew Auld; +Cc: Abdiel Janulgue, Intel Graphics
On Fri, Jul 10, 2020 at 5:00 AM Matthew Auld <matthew.auld@intel.com> wrote:
>
> We may be without a context to perform various internal blitter
> operations, for example when performing object migration. Piggybacking
> off the kernel_context is probably a bad idea, since it has other uses.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 +++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> 2 files changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index dd1a42c4d344..1df94e82550f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -792,6 +792,7 @@ create_kernel_context(struct intel_engine_cs *engine)
> int err;
>
> ce = intel_context_create(engine);
> +
> if (IS_ERR(ce))
> return ce;
>
> @@ -845,16 +846,32 @@ static int engine_init_common(struct intel_engine_cs *engine)
> return PTR_ERR(ce);
>
> ret = measure_breadcrumb_dw(ce);
> - if (ret < 0)
> - goto err_context;
> + if (ret < 0) {
> + intel_context_put(ce);
I think it's easier to follow the code if the error handling is in one
place. Since you have to put the context.
And since create_kernel_context() pins it, don't we have to
intel_context_unpin() like we are doing
in intel_engine_cleanup_common()? Which would also mean to probably
factor out a `destroy_kernel_context()`
to always do it, and call from here and from intel_engine_cleanup_common().
Lucas De Marchi
> + return ret;
> + }
>
> engine->emit_fini_breadcrumb_dw = ret;
> engine->kernel_context = ce;
>
> + /*
> + * The blitter context is used to quickly memset or migrate objects
> + * in local memory, so it has to always be available.
> + */
> + if (engine->class == COPY_ENGINE_CLASS) {
> + ce = create_kernel_context(engine);
> + if (IS_ERR(ce)) {
> + ret = PTR_ERR(ce);
> + goto err_kernel_context;
> + }
> +
> + engine->blitter_context = ce;
> + }
> +
> return 0;
>
> -err_context:
> - intel_context_put(ce);
> +err_kernel_context:
> + intel_context_put(engine->kernel_context);
> return ret;
> }
>
> @@ -910,6 +927,11 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> if (engine->default_state)
> fput(engine->default_state);
>
> + if (engine->blitter_context) {
> + intel_context_unpin(engine->blitter_context);
> + intel_context_put(engine->blitter_context);
> + }
> +
> if (engine->kernel_context) {
> intel_context_unpin(engine->kernel_context);
> intel_context_put(engine->kernel_context);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 490af81bd6f3..3b2d9ed7670f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -342,6 +342,7 @@ struct intel_engine_cs {
> struct llist_head barrier_tasks;
>
> struct intel_context *kernel_context; /* pinned */
> + struct intel_context *blitter_context; /* pinned; exists for BCS only */
>
> intel_engine_mask_t saturated; /* submitting semaphores too late? */
>
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context
2020-08-03 19:59 ` Lucas De Marchi
@ 2020-08-03 20:17 ` Lucas De Marchi
0 siblings, 0 replies; 88+ messages in thread
From: Lucas De Marchi @ 2020-08-03 20:17 UTC (permalink / raw)
To: Matthew Auld, Chris Wilson; +Cc: Intel Graphics
+Chris Wilson
On Mon, Aug 3, 2020 at 12:59 PM Lucas De Marchi
<lucas.de.marchi@gmail.com> wrote:
>
> On Fri, Jul 10, 2020 at 5:00 AM Matthew Auld <matthew.auld@intel.com> wrote:
> >
> > We may be without a context to perform various internal blitter
> > operations, for example when performing object migration. Piggybacking
> > off the kernel_context is probably a bad idea, since it has other uses.
> >
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 +++++++++++++++++---
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> > 2 files changed, 27 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index dd1a42c4d344..1df94e82550f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -792,6 +792,7 @@ create_kernel_context(struct intel_engine_cs *engine)
> > int err;
> >
> > ce = intel_context_create(engine);
> > +
> > if (IS_ERR(ce))
> > return ce;
> >
> > @@ -845,16 +846,32 @@ static int engine_init_common(struct intel_engine_cs *engine)
> > return PTR_ERR(ce);
> >
> > ret = measure_breadcrumb_dw(ce);
> > - if (ret < 0)
> > - goto err_context;
> > + if (ret < 0) {
> > + intel_context_put(ce);
>
> I think it's easier to follow the code if the error handling is in one
> place. Since you have to put the context.
> And since create_kernel_context() pins it, don't we have to
> intel_context_unpin() like we are doing
> in intel_engine_cleanup_common()? Which would also mean to probably
> factor out a `destroy_kernel_context()`
> to always do it, and call from here and from intel_engine_cleanup_common().
We actually had a destroy_kernel_context() and the unpin, but that got dropped
by e6ba76480299 ("drm/i915: Remove i915->kernel_context") .
Wouldn't we hit a GEM_BUG_ON() in the destroy function if we don't unpin it ?
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (33 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 34/60] drm/i915: introduce kernel blitter_context Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 16:20 ` Tvrtko Ursulin
2020-07-10 11:57 ` [Intel-gfx] [RFC 36/60] drm/i915/uapi: introduce drm_i915_gem_create_ext Matthew Auld
` (29 subsequent siblings)
64 siblings, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Returns the available memory region areas supported by the HW.
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 12 ++++-
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 ++
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/i915_query.c | 62 ++++++++++++++++++++++
drivers/gpu/drm/i915/intel_memory_region.c | 32 ++++++-----
drivers/gpu/drm/i915/intel_memory_region.h | 38 +++++++------
include/uapi/drm/i915_drm.h | 58 ++++++++++++++++++++
8 files changed, 172 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index e0f21f12d3ce..6704877fbda8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -646,11 +646,19 @@ _i915_gem_object_create_stolen(struct intel_memory_region *mem,
return obj;
}
+struct intel_memory_region *i915_stolen_region(struct drm_i915_private *i915)
+{
+ if (HAS_LMEM(i915))
+ return i915->mm.regions[INTEL_REGION_STOLEN_LMEM];
+
+ return i915->mm.regions[INTEL_REGION_STOLEN_SMEM];
+}
+
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_i915_private *i915,
resource_size_t size)
{
- return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_STOLEN],
+ return i915_gem_object_create_region(i915_stolen_region(i915),
size, I915_BO_ALLOC_CONTIGUOUS);
}
@@ -690,7 +698,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *i915,
resource_size_t stolen_offset,
resource_size_t size)
{
- struct intel_memory_region *mem = i915->mm.regions[INTEL_REGION_STOLEN];
+ struct intel_memory_region *mem = i915_stolen_region(i915);
struct drm_i915_gem_object *obj;
struct drm_mm_node *stolen;
int ret;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
index e15c0adad8af..a19110a1b75a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
@@ -22,6 +22,9 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
struct drm_mm_node *node);
struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private *i915);
+
+struct intel_memory_region *i915_stolen_region(struct drm_i915_private *i915);
+
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
resource_size_t size);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5473bfe9126c..39826b98fac2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -963,7 +963,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
i915->params.fake_lmem_start) {
mkwrite_device_info(i915)->memory_regions =
- REGION_SMEM | REGION_LMEM | REGION_STOLEN;
+ REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
mkwrite_device_info(i915)->is_dgfx = true;
GEM_BUG_ON(!HAS_LMEM(i915));
GEM_BUG_ON(!IS_DGFX(i915));
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d5e27202d150..e132fdffa432 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -154,7 +154,7 @@
.page_sizes = I915_GTT_PAGE_SIZE_4K
#define GEN_DEFAULT_REGIONS \
- .memory_regions = REGION_SMEM | REGION_STOLEN
+ .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
#define I830_FEATURES \
GEN(2), \
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index fed337ad7b68..d4ca040c528b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -419,11 +419,73 @@ static int query_perf_config(struct drm_i915_private *i915,
}
}
+static int query_memregion_info(struct drm_i915_private *dev_priv,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_memory_regions __user *query_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_memory_region_info __user *info_ptr =
+ &query_ptr->regions[0];
+ struct drm_i915_memory_region_info info = { };
+ struct drm_i915_query_memory_regions query;
+ u32 total_length;
+ int ret, i;
+
+ if (query_item->flags != 0)
+ return -EINVAL;
+
+ total_length = sizeof(query);
+ for (i = 0; i < ARRAY_SIZE(dev_priv->mm.regions); ++i) {
+ struct intel_memory_region *region = dev_priv->mm.regions[i];
+
+ if (!region)
+ continue;
+
+ total_length += sizeof(info);
+ }
+
+ ret = copy_query_item(&query, sizeof(query), total_length, query_item);
+ if (ret != 0)
+ return ret;
+
+ if (query.num_regions)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(query.rsvd); ++i) {
+ if (query.rsvd[i])
+ return -EINVAL;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(dev_priv->mm.regions); ++i) {
+ struct intel_memory_region *region = dev_priv->mm.regions[i];
+
+ if (!region)
+ continue;
+
+ info.region.memory_class = region->type;
+ info.region.memory_instance = region->instance;
+ info.probed_size = region->total;
+ info.unallocated_size = region->avail;
+
+ if (__copy_to_user(info_ptr, &info, sizeof(info)))
+ return -EFAULT;
+
+ query.num_regions++;
+ info_ptr++;
+ }
+
+ if (__copy_to_user(query_ptr, &query, sizeof(query)))
+ return -EFAULT;
+
+ return total_length;
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item) = {
query_topology_info,
query_engine_info,
query_perf_config,
+ query_memregion_info,
};
int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 2943c7778d5e..b9eb1a42dd3a 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -6,14 +6,19 @@
#include "intel_memory_region.h"
#include "i915_drv.h"
-/* XXX: Hysterical raisins. BIT(inst) needs to just be (inst) at some point. */
-#define REGION_MAP(type, inst) \
- BIT((type) + INTEL_MEMORY_TYPE_SHIFT) | BIT(inst)
-
-const u32 intel_region_map[] = {
- [INTEL_REGION_SMEM] = REGION_MAP(INTEL_MEMORY_SYSTEM, 0),
- [INTEL_REGION_LMEM] = REGION_MAP(INTEL_MEMORY_LOCAL, 0),
- [INTEL_REGION_STOLEN] = REGION_MAP(INTEL_MEMORY_STOLEN, 0),
+const struct intel_memory_region_info intel_region_map[] = {
+ [INTEL_REGION_SMEM] = {
+ .class = INTEL_MEMORY_SYSTEM,
+ .instance = 0,
+ },
+ [INTEL_REGION_LMEM] = {
+ .class = INTEL_MEMORY_LOCAL,
+ .instance = 0,
+ },
+ [INTEL_REGION_STOLEN_SMEM] = {
+ .class = INTEL_MEMORY_STOLEN_SYSTEM,
+ .instance = 0,
+ },
};
struct intel_memory_region *
@@ -257,17 +262,18 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
struct intel_memory_region *mem = ERR_PTR(-ENODEV);
- u32 type;
+ u16 type, instance;
if (!HAS_REGION(i915, BIT(i)))
continue;
- type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
+ type = intel_region_map[i].class;
+ instance = intel_region_map[i].instance;
switch (type) {
case INTEL_MEMORY_SYSTEM:
mem = i915_gem_shmem_setup(i915);
break;
- case INTEL_MEMORY_STOLEN:
+ case INTEL_MEMORY_STOLEN_SYSTEM:
mem = i915_gem_stolen_setup(i915);
break;
case INTEL_MEMORY_LOCAL:
@@ -283,9 +289,9 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
goto out_cleanup;
}
- mem->id = intel_region_map[i];
+ mem->id = i;
mem->type = type;
- mem->instance = MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
+ mem->instance = instance;
i915->mm.regions[i] = mem;
}
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 232490d89a83..c047cf7c5e7c 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -11,6 +11,7 @@
#include <linux/mutex.h>
#include <linux/io-mapping.h>
#include <drm/drm_mm.h>
+#include <drm/i915_drm.h>
#include "i915_buddy.h"
@@ -19,30 +20,25 @@ struct drm_i915_gem_object;
struct intel_memory_region;
struct sg_table;
-/**
- * Base memory type
- */
enum intel_memory_type {
- INTEL_MEMORY_SYSTEM = 0,
- INTEL_MEMORY_LOCAL,
- INTEL_MEMORY_STOLEN,
+ INTEL_MEMORY_SYSTEM = I915_MEMORY_CLASS_SYSTEM,
+ INTEL_MEMORY_LOCAL = I915_MEMORY_CLASS_DEVICE,
+ INTEL_MEMORY_STOLEN_SYSTEM = I915_MEMORY_CLASS_STOLEN_SYSTEM,
+ INTEL_MEMORY_STOLEN_LOCAL = I915_MEMORY_CLASS_STOLEN_DEVICE,
};
enum intel_region_id {
INTEL_REGION_SMEM = 0,
INTEL_REGION_LMEM,
- INTEL_REGION_STOLEN,
+ INTEL_REGION_STOLEN_SMEM,
+ INTEL_REGION_STOLEN_LMEM,
INTEL_REGION_UNKNOWN, /* Should be last */
};
#define REGION_SMEM BIT(INTEL_REGION_SMEM)
#define REGION_LMEM BIT(INTEL_REGION_LMEM)
-#define REGION_STOLEN BIT(INTEL_REGION_STOLEN)
-
-#define INTEL_MEMORY_TYPE_SHIFT 16
-
-#define MEMORY_TYPE_FROM_REGION(r) (ilog2((r) >> INTEL_MEMORY_TYPE_SHIFT))
-#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2((r) & 0xffff))
+#define REGION_STOLEN_SMEM BIT(INTEL_REGION_STOLEN_SMEM)
+#define REGION_STOLEN_LMEM BIT(INTEL_REGION_STOLEN_LMEM)
#define I915_ALLOC_MIN_PAGE_SIZE BIT(0)
#define I915_ALLOC_CONTIGUOUS BIT(1)
@@ -51,10 +47,12 @@ enum intel_region_id {
for (id = 0; id < ARRAY_SIZE((i915)->mm.regions); id++) \
for_each_if((mr) = (i915)->mm.regions[id])
-/**
- * Memory regions encoded as type | instance
- */
-extern const u32 intel_region_map[];
+struct intel_memory_region_info {
+ u16 class;
+ u16 instance;
+};
+
+extern const struct intel_memory_region_info intel_region_map[];
struct intel_memory_region_ops {
unsigned int flags;
@@ -89,9 +87,9 @@ struct intel_memory_region {
resource_size_t total;
resource_size_t avail;
- unsigned int type;
- unsigned int instance;
- unsigned int id;
+ u16 type;
+ u16 instance;
+ enum intel_region_id id;
char name[8];
dma_addr_t remap_addr;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 14b67cd6b54b..46baedf71cb1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2122,6 +2122,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
+#define DRM_I915_QUERY_MEMORY_REGIONS 4
/* Must be kept compact -- no holes and well documented */
/*
@@ -2322,6 +2323,63 @@ struct drm_i915_query_perf_config {
__u8 data[];
};
+enum drm_i915_gem_memory_class {
+ I915_MEMORY_CLASS_SYSTEM = 0,
+ I915_MEMORY_CLASS_DEVICE,
+ I915_MEMORY_CLASS_STOLEN_SYSTEM,
+ I915_MEMORY_CLASS_STOLEN_DEVICE,
+};
+
+struct drm_i915_gem_memory_class_instance {
+ __u16 memory_class; /* see enum drm_i915_gem_memory_class */
+ __u16 memory_instance;
+};
+
+/**
+ * struct drm_i915_memory_region_info
+ *
+ * Describes one region as known to the driver.
+ */
+struct drm_i915_memory_region_info {
+ /** class:instance pair encoding */
+ struct drm_i915_gem_memory_class_instance region;
+
+ /** MBZ */
+ __u32 rsvd0;
+
+ /** MBZ */
+ __u64 caps;
+
+ /** MBZ */
+ __u64 flags;
+
+ /** Memory probed by the driver (-1 = unknown) */
+ __u64 probed_size;
+
+ /** Estimate of memory remaining (-1 = unknown) */
+ __u64 unallocated_size;
+
+ /** MBZ */
+ __u64 rsvd1[8];
+};
+
+/**
+ * struct drm_i915_query_memory_regions
+ *
+ * Region info query enumerates all regions known to the driver by filling in
+ * an array of struct drm_i915_memory_region_info structures.
+ */
+struct drm_i915_query_memory_regions {
+ /** Number of supported regions */
+ __u32 num_regions;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ /* Info about each supported region */
+ struct drm_i915_memory_region_info regions[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI
2020-07-10 11:57 ` [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI Matthew Auld
@ 2020-07-10 16:20 ` Tvrtko Ursulin
0 siblings, 0 replies; 88+ messages in thread
From: Tvrtko Ursulin @ 2020-07-10 16:20 UTC (permalink / raw)
To: Matthew Auld, intel-gfx
On 10/07/2020 12:57, Matthew Auld wrote:
> From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>
> Returns the available memory region areas supported by the HW.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 12 ++++-
> drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 3 ++
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/i915_query.c | 62 ++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_memory_region.c | 32 ++++++-----
> drivers/gpu/drm/i915/intel_memory_region.h | 38 +++++++------
> include/uapi/drm/i915_drm.h | 58 ++++++++++++++++++++
> 8 files changed, 172 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index e0f21f12d3ce..6704877fbda8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -646,11 +646,19 @@ _i915_gem_object_create_stolen(struct intel_memory_region *mem,
> return obj;
> }
>
> +struct intel_memory_region *i915_stolen_region(struct drm_i915_private *i915)
> +{
> + if (HAS_LMEM(i915))
> + return i915->mm.regions[INTEL_REGION_STOLEN_LMEM];
> +
> + return i915->mm.regions[INTEL_REGION_STOLEN_SMEM];
> +}
The split of the stolen region to lmem and smem should be a separate
patch I think.
> +
> struct drm_i915_gem_object *
> i915_gem_object_create_stolen(struct drm_i915_private *i915,
> resource_size_t size)
> {
> - return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_STOLEN],
> + return i915_gem_object_create_region(i915_stolen_region(i915),
> size, I915_BO_ALLOC_CONTIGUOUS);
> }
>
> @@ -690,7 +698,7 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *i915,
> resource_size_t stolen_offset,
> resource_size_t size)
> {
> - struct intel_memory_region *mem = i915->mm.regions[INTEL_REGION_STOLEN];
> + struct intel_memory_region *mem = i915_stolen_region(i915);
> struct drm_i915_gem_object *obj;
> struct drm_mm_node *stolen;
> int ret;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
> index e15c0adad8af..a19110a1b75a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
> @@ -22,6 +22,9 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
> void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
> struct drm_mm_node *node);
> struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private *i915);
> +
> +struct intel_memory_region *i915_stolen_region(struct drm_i915_private *i915);
> +
> struct drm_i915_gem_object *
> i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
> resource_size_t size);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5473bfe9126c..39826b98fac2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -963,7 +963,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
> i915->params.fake_lmem_start) {
> mkwrite_device_info(i915)->memory_regions =
> - REGION_SMEM | REGION_LMEM | REGION_STOLEN;
> + REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
> mkwrite_device_info(i915)->is_dgfx = true;
> GEM_BUG_ON(!HAS_LMEM(i915));
> GEM_BUG_ON(!IS_DGFX(i915));
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d5e27202d150..e132fdffa432 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -154,7 +154,7 @@
> .page_sizes = I915_GTT_PAGE_SIZE_4K
>
> #define GEN_DEFAULT_REGIONS \
> - .memory_regions = REGION_SMEM | REGION_STOLEN
> + .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
>
> #define I830_FEATURES \
> GEN(2), \
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index fed337ad7b68..d4ca040c528b 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -419,11 +419,73 @@ static int query_perf_config(struct drm_i915_private *i915,
> }
> }
>
> +static int query_memregion_info(struct drm_i915_private *dev_priv,
> + struct drm_i915_query_item *query_item)
> +{
> + struct drm_i915_query_memory_regions __user *query_ptr =
> + u64_to_user_ptr(query_item->data_ptr);
> + struct drm_i915_memory_region_info __user *info_ptr =
> + &query_ptr->regions[0];
> + struct drm_i915_memory_region_info info = { };
> + struct drm_i915_query_memory_regions query;
> + u32 total_length;
> + int ret, i;
> +
> + if (query_item->flags != 0)
> + return -EINVAL;
> +
> + total_length = sizeof(query);
> + for (i = 0; i < ARRAY_SIZE(dev_priv->mm.regions); ++i) {
> + struct intel_memory_region *region = dev_priv->mm.regions[i];
> +
> + if (!region)
> + continue;
> +
> + total_length += sizeof(info);
> + }
> +
> + ret = copy_query_item(&query, sizeof(query), total_length, query_item);
> + if (ret != 0)
> + return ret;
> +
> + if (query.num_regions)
> + return -EINVAL;
> +
> + for (i = 0; i < ARRAY_SIZE(query.rsvd); ++i) {
> + if (query.rsvd[i])
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(dev_priv->mm.regions); ++i) {
> + struct intel_memory_region *region = dev_priv->mm.regions[i];
> +
> + if (!region)
> + continue;
> +
> + info.region.memory_class = region->type;
> + info.region.memory_instance = region->instance;
> + info.probed_size = region->total;
> + info.unallocated_size = region->avail;
> +
> + if (__copy_to_user(info_ptr, &info, sizeof(info)))
> + return -EFAULT;
> +
> + query.num_regions++;
> + info_ptr++;
> + }
> +
> + if (__copy_to_user(query_ptr, &query, sizeof(query)))
> + return -EFAULT;
> +
> + return total_length;
> +}
> +
> static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> struct drm_i915_query_item *query_item) = {
> query_topology_info,
> query_engine_info,
> query_perf_config,
> + query_memregion_info,
> };
>
> int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
> index 2943c7778d5e..b9eb1a42dd3a 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -6,14 +6,19 @@
> #include "intel_memory_region.h"
> #include "i915_drv.h"
>
> -/* XXX: Hysterical raisins. BIT(inst) needs to just be (inst) at some point. */
> -#define REGION_MAP(type, inst) \
> - BIT((type) + INTEL_MEMORY_TYPE_SHIFT) | BIT(inst)
> -
> -const u32 intel_region_map[] = {
> - [INTEL_REGION_SMEM] = REGION_MAP(INTEL_MEMORY_SYSTEM, 0),
> - [INTEL_REGION_LMEM] = REGION_MAP(INTEL_MEMORY_LOCAL, 0),
> - [INTEL_REGION_STOLEN] = REGION_MAP(INTEL_MEMORY_STOLEN, 0),
> +const struct intel_memory_region_info intel_region_map[] = {
> + [INTEL_REGION_SMEM] = {
> + .class = INTEL_MEMORY_SYSTEM,
> + .instance = 0,
> + },
> + [INTEL_REGION_LMEM] = {
> + .class = INTEL_MEMORY_LOCAL,
> + .instance = 0,
> + },
> + [INTEL_REGION_STOLEN_SMEM] = {
> + .class = INTEL_MEMORY_STOLEN_SYSTEM,
> + .instance = 0,
> + },
> };
>
> struct intel_memory_region *
> @@ -257,17 +262,18 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
>
> for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
> struct intel_memory_region *mem = ERR_PTR(-ENODEV);
> - u32 type;
> + u16 type, instance;
>
> if (!HAS_REGION(i915, BIT(i)))
> continue;
>
> - type = MEMORY_TYPE_FROM_REGION(intel_region_map[i]);
> + type = intel_region_map[i].class;
> + instance = intel_region_map[i].instance;
> switch (type) {
> case INTEL_MEMORY_SYSTEM:
> mem = i915_gem_shmem_setup(i915);
> break;
> - case INTEL_MEMORY_STOLEN:
> + case INTEL_MEMORY_STOLEN_SYSTEM:
> mem = i915_gem_stolen_setup(i915);
> break;
> case INTEL_MEMORY_LOCAL:
> @@ -283,9 +289,9 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
> goto out_cleanup;
> }
>
> - mem->id = intel_region_map[i];
> + mem->id = i;
> mem->type = type;
> - mem->instance = MEMORY_INSTANCE_FROM_REGION(intel_region_map[i]);
> + mem->instance = instance;
>
> i915->mm.regions[i] = mem;
> }
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index 232490d89a83..c047cf7c5e7c 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -11,6 +11,7 @@
> #include <linux/mutex.h>
> #include <linux/io-mapping.h>
> #include <drm/drm_mm.h>
> +#include <drm/i915_drm.h>
>
> #include "i915_buddy.h"
>
> @@ -19,30 +20,25 @@ struct drm_i915_gem_object;
> struct intel_memory_region;
> struct sg_table;
>
> -/**
> - * Base memory type
> - */
> enum intel_memory_type {
> - INTEL_MEMORY_SYSTEM = 0,
> - INTEL_MEMORY_LOCAL,
> - INTEL_MEMORY_STOLEN,
> + INTEL_MEMORY_SYSTEM = I915_MEMORY_CLASS_SYSTEM,
> + INTEL_MEMORY_LOCAL = I915_MEMORY_CLASS_DEVICE,
> + INTEL_MEMORY_STOLEN_SYSTEM = I915_MEMORY_CLASS_STOLEN_SYSTEM,
> + INTEL_MEMORY_STOLEN_LOCAL = I915_MEMORY_CLASS_STOLEN_DEVICE,
> };
>
> enum intel_region_id {
> INTEL_REGION_SMEM = 0,
> INTEL_REGION_LMEM,
> - INTEL_REGION_STOLEN,
> + INTEL_REGION_STOLEN_SMEM,
> + INTEL_REGION_STOLEN_LMEM,
> INTEL_REGION_UNKNOWN, /* Should be last */
> };
>
> #define REGION_SMEM BIT(INTEL_REGION_SMEM)
> #define REGION_LMEM BIT(INTEL_REGION_LMEM)
> -#define REGION_STOLEN BIT(INTEL_REGION_STOLEN)
> -
> -#define INTEL_MEMORY_TYPE_SHIFT 16
> -
> -#define MEMORY_TYPE_FROM_REGION(r) (ilog2((r) >> INTEL_MEMORY_TYPE_SHIFT))
> -#define MEMORY_INSTANCE_FROM_REGION(r) (ilog2((r) & 0xffff))
> +#define REGION_STOLEN_SMEM BIT(INTEL_REGION_STOLEN_SMEM)
> +#define REGION_STOLEN_LMEM BIT(INTEL_REGION_STOLEN_LMEM)
>
> #define I915_ALLOC_MIN_PAGE_SIZE BIT(0)
> #define I915_ALLOC_CONTIGUOUS BIT(1)
> @@ -51,10 +47,12 @@ enum intel_region_id {
> for (id = 0; id < ARRAY_SIZE((i915)->mm.regions); id++) \
> for_each_if((mr) = (i915)->mm.regions[id])
>
> -/**
> - * Memory regions encoded as type | instance
> - */
> -extern const u32 intel_region_map[];
> +struct intel_memory_region_info {
> + u16 class;
> + u16 instance;
> +};
> +
> +extern const struct intel_memory_region_info intel_region_map[];
>
> struct intel_memory_region_ops {
> unsigned int flags;
> @@ -89,9 +87,9 @@ struct intel_memory_region {
> resource_size_t total;
> resource_size_t avail;
>
> - unsigned int type;
> - unsigned int instance;
> - unsigned int id;
> + u16 type;
> + u16 instance;
Class and type could be tidied to just one.
struct intel_memory_region_info could then be used here. Or even struct
drm_i915_gem_memory_class_instance but granted perhaps it is better to
keep uapi and implementation separate.
> + enum intel_region_id id;
> char name[8];
>
> dma_addr_t remap_addr;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 14b67cd6b54b..46baedf71cb1 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2122,6 +2122,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_TOPOLOGY_INFO 1
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> +#define DRM_I915_QUERY_MEMORY_REGIONS 4
> /* Must be kept compact -- no holes and well documented */
>
> /*
> @@ -2322,6 +2323,63 @@ struct drm_i915_query_perf_config {
> __u8 data[];
> };
>
> +enum drm_i915_gem_memory_class {
> + I915_MEMORY_CLASS_SYSTEM = 0,
> + I915_MEMORY_CLASS_DEVICE,
> + I915_MEMORY_CLASS_STOLEN_SYSTEM,
> + I915_MEMORY_CLASS_STOLEN_DEVICE,
> +};
> +
> +struct drm_i915_gem_memory_class_instance {
> + __u16 memory_class; /* see enum drm_i915_gem_memory_class */
> + __u16 memory_instance;
> +};
> +
> +/**
> + * struct drm_i915_memory_region_info
> + *
> + * Describes one region as known to the driver.
> + */
> +struct drm_i915_memory_region_info {
> + /** class:instance pair encoding */
> + struct drm_i915_gem_memory_class_instance region;
> +
> + /** MBZ */
> + __u32 rsvd0;
> +
> + /** MBZ */
> + __u64 caps;
> +
> + /** MBZ */
> + __u64 flags;
> +
> + /** Memory probed by the driver (-1 = unknown) */
> + __u64 probed_size;
> +
> + /** Estimate of memory remaining (-1 = unknown) */
> + __u64 unallocated_size;
> +
> + /** MBZ */
> + __u64 rsvd1[8];
> +};
> +
> +/**
> + * struct drm_i915_query_memory_regions
> + *
> + * Region info query enumerates all regions known to the driver by filling in
> + * an array of struct drm_i915_memory_region_info structures.
> + */
> +struct drm_i915_query_memory_regions {
> + /** Number of supported regions */
> + __u32 num_regions;
> +
> + /** MBZ */
> + __u32 rsvd[3];
> +
> + /* Info about each supported region */
> + struct drm_i915_memory_region_info regions[];
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
>
The rest looks good to me.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 88+ messages in thread
* [Intel-gfx] [RFC 36/60] drm/i915/uapi: introduce drm_i915_gem_create_ext
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (34 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 35/60] drm/i915/query: Expose memory regions through the query uAPI Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 37/60] drm/i915/lmem: allocate cmd ring in lmem Matthew Auld
` (28 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support setting an immutable-priority-list of potential
placements, at creation time.
If we wish to set the placements/regions we can simply do:
struct drm_i915_gem_object_param region_param = { … }; /* Unchanged */
struct drm_i915_gem_create_ext_setparam setparam_region = {
.base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
.param = region_param,
}
struct drm_i915_gem_create_ext create_ext = {
.size = 16 * PAGE_SIZE,
.extensions = (uintptr_t)&setparam_region,
};
int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
if (err) ...
If we use the normal gem_create or gem_create_ext without the
extensions/placements then we still get the old behaviour with only
placing the object in system memory.
One important change here is the returned size will now be rounded up to
the correct size, depending on the list of placements, where we might
have minimum page-size restrictions on some platforms when dealing with
device local-memory.
Testcase: igt/gem_create/create-ext-placement-sanity-check
Testcase: igt/gem_create/create-ext-placement-each
Testcase: igt/gem_create/create-ext-placement-all
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_create.c | 379 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +
drivers/gpu/drm/i915/gem/i915_gem_region.c | 4 +
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 103 +----
drivers/gpu/drm/i915/intel_memory_region.c | 20 +
drivers/gpu/drm/i915/intel_memory_region.h | 4 +
include/uapi/drm/i915_drm.h | 60 +++
10 files changed, 481 insertions(+), 103 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index bda4c0e408f8..b090174904b2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -131,6 +131,7 @@ gem-y += \
gem/i915_gem_clflush.o \
gem/i915_gem_client_blt.o \
gem/i915_gem_context.o \
+ gem/i915_gem_create.o \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
new file mode 100644
index 000000000000..981c3e6c6b9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "gt/intel_engine_user.h"
+
+#include "gem/i915_gem_ioctls.h"
+#include "gem/i915_gem_lmem.h"
+#include "gem/i915_gem_object_blt.h"
+#include "gem/i915_gem_region.h"
+
+#include "i915_drv.h"
+#include "i915_user_extensions.h"
+
+static u32 max_page_size(struct intel_memory_region **placements,
+ int n_placements)
+{
+ u32 max_page_size = 0;
+ int i;
+
+ for (i = 0; i < n_placements; ++i) {
+ max_page_size = max_t(u32, max_page_size,
+ placements[i]->min_page_size);
+ }
+
+ GEM_BUG_ON(!max_page_size);
+ return max_page_size;
+}
+
+static int
+i915_gem_create(struct drm_file *file,
+ struct intel_memory_region **placements,
+ int n_placements,
+ u64 *size_p,
+ u32 *handle_p)
+{
+ struct drm_i915_gem_object *obj;
+ u32 handle;
+ u64 size;
+ int ret;
+
+ size = round_up(*size_p, max_page_size(placements, n_placements));
+ if (size == 0)
+ return -EINVAL;
+
+ /* For most of the ABI (e.g. mmap) we think in system pages */
+ GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+ /* Allocate the new object */
+ obj = i915_gem_object_create_region(placements[0], size, 0);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ if (!i915_gem_object_has_struct_page(obj)) {
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_engine_cs *engine;
+
+ engine = intel_engine_lookup_user(i915,
+ I915_ENGINE_CLASS_COPY,
+ 0);
+ if (!engine) {
+ ret = -ENODEV;
+ goto out_put;
+ }
+
+ /*
+ * XXX: We really want to move this to get_pages(). In the
+ * pipeline is support for async get_pages() which should fit
+ * nicely for this. Also note that the actual clear should be
+ * done async(we currently do an object_wait which is pure
+ * garbage), we just need to take care if userspace opts of
+ * implicit sync for the execbuf, to avoid any potential info
+ * leak.
+ */
+
+ ret = i915_gem_object_fill_blt(obj, engine->blitter_context, 0);
+ if (ret) {
+ /*
+ * XXX: Post the error to where we would normally gather
+ * and clear the pages. This better reflects the final
+ * uapi behaviour, once we are at the point where we can
+ * move the clear worker to get_pages().
+ */
+ i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ __i915_gem_object_put_pages(obj);
+ obj->mm.gem_create_posted_err = ret;
+ goto handle_create;
+ }
+
+ i915_gem_object_lock(obj);
+ ret = i915_gem_object_set_to_cpu_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (ret) {
+ i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ __i915_gem_object_put_pages(obj);
+ obj->mm.gem_create_posted_err = ret;
+ goto handle_create;
+ }
+ }
+
+handle_create:
+ ret = drm_gem_handle_create(file, &obj->base, &handle);
+out_put:
+ /* drop reference from allocate - handle holds it now */
+ i915_gem_object_put(obj);
+ if (ret)
+ return ret;
+
+ obj->mm.placements = placements;
+ obj->mm.n_placements = n_placements;
+
+ *handle_p = handle;
+ *size_p = size;
+ return 0;
+}
+
+int
+i915_gem_dumb_create(struct drm_file *file,
+ struct drm_device *dev,
+ struct drm_mode_create_dumb *args)
+{
+ struct intel_memory_region **placements;
+ enum intel_memory_type mem_type;
+ int cpp = DIV_ROUND_UP(args->bpp, 8);
+ u32 format;
+ int ret;
+
+ switch (cpp) {
+ case 1:
+ format = DRM_FORMAT_C8;
+ break;
+ case 2:
+ format = DRM_FORMAT_RGB565;
+ break;
+ case 4:
+ format = DRM_FORMAT_XRGB8888;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* have to work out size/pitch and return them */
+ args->pitch = ALIGN(args->width * cpp, 64);
+
+ /* align stride to page size so that we can remap */
+ if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
+ DRM_FORMAT_MOD_LINEAR))
+ args->pitch = ALIGN(args->pitch, 4096);
+
+ args->size = mul_u32_u32(args->pitch, args->height);
+
+ mem_type = INTEL_MEMORY_SYSTEM;
+ if (HAS_LMEM(to_i915(dev)))
+ mem_type = INTEL_MEMORY_LOCAL;
+
+ placements = kmalloc(sizeof(struct intel_memory_region *), GFP_KERNEL);
+ if (!placements)
+ return -ENOMEM;
+
+ placements[0] = intel_memory_region_by_type(to_i915(dev), mem_type);
+
+ ret = i915_gem_create(file,
+ placements, 1,
+ &args->size, &args->handle);
+ if (ret)
+ kfree(placements);
+
+ return ret;
+}
+
+struct create_ext {
+ struct drm_i915_private *i915;
+ struct intel_memory_region **placements;
+ int n_placements;
+};
+
+static void repr_placements(char *buf, size_t size,
+ struct intel_memory_region **placements,
+ int n_placements)
+{
+ int i;
+
+ buf[0] = '\0';
+
+ for (i = 0; i < n_placements; i++) {
+ struct intel_memory_region *mr = placements[i];
+ int r;
+
+ r = snprintf(buf, size, "\n %s -> { class: %d, inst: %d }",
+ mr->name, mr->type, mr->instance);
+ if (r >= size)
+ return;
+
+ buf += r;
+ size -= r;
+ }
+}
+
+static int set_placements(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ struct drm_i915_private *i915 = ext_data->i915;
+ struct drm_i915_gem_memory_class_instance __user *uregions =
+ u64_to_user_ptr(args->data);
+ struct intel_memory_region **placements;
+ u32 mask;
+ int i, ret = 0;
+
+ if (args->handle) {
+ DRM_DEBUG("Handle should be zero\n");
+ ret = -EINVAL;
+ }
+
+ if (!args->size) {
+ DRM_DEBUG("Size is zero\n");
+ ret = -EINVAL;
+ }
+
+ if (args->size > ARRAY_SIZE(i915->mm.regions)) {
+ DRM_DEBUG("Too many placements\n");
+ ret = -EINVAL;
+ }
+
+ if (ret)
+ return ret;
+
+ placements = kmalloc_array(args->size,
+ sizeof(struct intel_memory_region *),
+ GFP_KERNEL);
+ if (!placements)
+ return -ENOMEM;
+
+ mask = 0;
+ for (i = 0; i < args->size; i++) {
+ struct drm_i915_gem_memory_class_instance region;
+ struct intel_memory_region *mr;
+
+ if (copy_from_user(®ion, uregions, sizeof(region))) {
+ ret = -EFAULT;
+ goto out_free;
+ }
+
+ mr = intel_memory_region_lookup(i915,
+ region.memory_class,
+ region.memory_instance);
+ if (!mr) {
+ DRM_DEBUG("Device is missing region { class: %d, inst: %d } at index = %d\n",
+ region.memory_class, region.memory_instance, i);
+ ret = -EINVAL;
+ goto out_dump;
+ }
+
+ if (mask & BIT(mr->id)) {
+ DRM_DEBUG("Found duplicate placement %s -> { class: %d, inst: %d } at index = %d\n",
+ mr->name, region.memory_class,
+ region.memory_instance, i);
+ ret = -EINVAL;
+ goto out_dump;
+ }
+
+ placements[i] = mr;
+ mask |= BIT(mr->id);
+
+ ++uregions;
+ }
+
+ if (ext_data->placements) {
+ ret = -EINVAL;
+ goto out_dump;
+ }
+
+ ext_data->placements = placements;
+ ext_data->n_placements = args->size;
+
+ return 0;
+
+out_dump:
+ if (1) {
+ char buf[256];
+
+ if (ext_data->placements) {
+ repr_placements(buf,
+ sizeof(buf),
+ ext_data->placements,
+ ext_data->n_placements);
+ DRM_DEBUG("Placements were already set in previous SETPARAM. Existing placements: %s\n",
+ buf);
+ }
+
+ repr_placements(buf, sizeof(buf), placements, i);
+ DRM_DEBUG("New placements(so far validated): %s\n", buf);
+ }
+
+out_free:
+ kfree(placements);
+ return ret;
+}
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_MEMORY_REGIONS:
+ return set_placements(args, ext_data);
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
+/**
+ * Creates a new mm object and returns a handle to it.
+ * @dev: drm device pointer
+ * @data: ioctl data blob
+ * @file: drm file pointer
+ */
+int
+i915_gem_create_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
+
+ i915_gem_flush_free_objects(i915);
+
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ goto err_free;
+
+ if (!ext_data.placements) {
+ struct intel_memory_region **placements;
+ enum intel_memory_type mem_type = INTEL_MEMORY_SYSTEM;
+
+ placements = kmalloc(sizeof(struct intel_memory_region *),
+ GFP_KERNEL);
+ if (!placements)
+ return -ENOMEM;
+
+ placements[0] = intel_memory_region_by_type(i915, mem_type);
+
+ ext_data.placements = placements;
+ ext_data.n_placements = 1;
+ }
+
+ ret = i915_gem_create(file,
+ ext_data.placements,
+ ext_data.n_placements,
+ &args->size, &args->handle);
+ if (!ret)
+ return 0;
+
+err_free:
+ kfree(ext_data.placements);
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index c8421fd9d2dc..11d98018c181 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -242,6 +242,8 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
if (obj->ops->release)
obj->ops->release(obj);
+ kfree(obj->mm.placements);
+
/* But keep the pointer alive for RCU-protected lookups */
call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
cond_resched();
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index b37ae7b32f53..848ac102b788 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -193,6 +193,15 @@ struct drm_i915_gem_object {
atomic_t pages_pin_count;
atomic_t shrink_pin;
+ /**
+ * Priority list of potential placements for this object.
+ */
+ struct intel_memory_region **placements;
+ int n_placements;
+
+ /* XXX: Nasty hack, see gem_create */
+ int gem_create_posted_err;
+
/**
* Memory region for this object.
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 1515384d7e0e..cc8116e63808 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -33,6 +33,10 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
unsigned int sg_page_sizes;
int ret;
+ /* XXX: Check if we have any post. This is nasty hack, see gem_create */
+ if (obj->mm.gem_create_posted_err)
+ return obj->mm.gem_create_posted_err;
+
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 39826b98fac2..7b758131e0dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1811,7 +1811,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1805b5e6bc30..69f6d88a42c2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -43,6 +43,7 @@
#include "gem/i915_gem_clflush.h"
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_ioctls.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_region.h"
#include "gt/intel_engine_user.h"
@@ -203,108 +204,6 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
return 0;
}
-static int
-i915_gem_create(struct drm_file *file,
- struct intel_memory_region *mr,
- u64 *size_p,
- u32 *handle_p)
-{
- struct drm_i915_gem_object *obj;
- u32 handle;
- u64 size;
- int ret;
-
- GEM_BUG_ON(!is_power_of_2(mr->min_page_size));
- size = round_up(*size_p, mr->min_page_size);
- if (size == 0)
- return -EINVAL;
-
- /* For most of the ABI (e.g. mmap) we think in system pages */
- GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
-
- /* Allocate the new object */
- obj = i915_gem_object_create_region(mr, size, 0);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- ret = drm_gem_handle_create(file, &obj->base, &handle);
- /* drop reference from allocate - handle holds it now */
- i915_gem_object_put(obj);
- if (ret)
- return ret;
-
- *handle_p = handle;
- *size_p = size;
- return 0;
-}
-
-int
-i915_gem_dumb_create(struct drm_file *file,
- struct drm_device *dev,
- struct drm_mode_create_dumb *args)
-{
- enum intel_memory_type mem_type;
- int cpp = DIV_ROUND_UP(args->bpp, 8);
- u32 format;
-
- switch (cpp) {
- case 1:
- format = DRM_FORMAT_C8;
- break;
- case 2:
- format = DRM_FORMAT_RGB565;
- break;
- case 4:
- format = DRM_FORMAT_XRGB8888;
- break;
- default:
- return -EINVAL;
- }
-
- /* have to work out size/pitch and return them */
- args->pitch = ALIGN(args->width * cpp, 64);
-
- /* align stride to page size so that we can remap */
- if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
- DRM_FORMAT_MOD_LINEAR))
- args->pitch = ALIGN(args->pitch, 4096);
-
- if (args->pitch < args->width)
- return -EINVAL;
-
- args->size = mul_u32_u32(args->pitch, args->height);
-
- mem_type = INTEL_MEMORY_SYSTEM;
- if (HAS_LMEM(to_i915(dev)))
- mem_type = INTEL_MEMORY_LOCAL;
-
- return i915_gem_create(file,
- intel_memory_region_by_type(to_i915(dev),
- mem_type),
- &args->size, &args->handle);
-}
-
-/**
- * Creates a new mm object and returns a handle to it.
- * @dev: drm device pointer
- * @data: ioctl data blob
- * @file: drm file pointer
- */
-int
-i915_gem_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file)
-{
- struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
-
- i915_gem_flush_free_objects(i915);
-
- return i915_gem_create(file,
- intel_memory_region_by_type(i915,
- INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
-}
-
static int
shmem_pread(struct page *page, int offset, int len, char __user *user_data,
bool needs_clflush)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index b9eb1a42dd3a..609a65935c98 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -21,6 +21,26 @@ const struct intel_memory_region_info intel_region_map[] = {
},
};
+struct intel_memory_region *
+intel_memory_region_lookup(struct drm_i915_private *i915,
+ u16 class, u16 instance)
+{
+ int i;
+
+ /* XXX: consider maybe converting to an rb tree at some point */
+ for (i = 0; i < ARRAY_SIZE(i915->mm.regions); ++i) {
+ struct intel_memory_region *region = i915->mm.regions[i];
+
+ if (!region)
+ continue;
+
+ if (region->type == class && region->instance == instance)
+ return region;
+ }
+
+ return NULL;
+}
+
struct intel_memory_region *
intel_memory_region_by_type(struct drm_i915_private *i915,
enum intel_memory_type mem_type)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index c047cf7c5e7c..83241b47e923 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -101,6 +101,10 @@ struct intel_memory_region {
} objects;
};
+struct intel_memory_region *
+intel_memory_region_lookup(struct drm_i915_private *i915,
+ u16 class, u16 instance);
+
int intel_memory_region_init_buddy(struct intel_memory_region *mem);
void intel_memory_region_release_buddy(struct intel_memory_region *mem);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 46baedf71cb1..a2471bd8e6ea 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -722,6 +723,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1645,6 +1667,44 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull<<32)
+
+/*
+ * I915_PARAM_MEMORY_REGIONS:
+ *
+ * Set the data pointer with the desired set of placements in priority
+ * order(each entry must be unique and supported by the device), as an array of
+ * drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance
+ * pair encodings. See DRM_I915_QUERY_MEMORY_REGIONS for how to query the
+ * supported regions.
+ *
+ * Note that this requires the I915_OBJECT_PARAM namespace:
+ * .param = I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS
+ */
+#define I915_PARAM_MEMORY_REGIONS 0x1
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 37/60] drm/i915/lmem: allocate cmd ring in lmem
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (35 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 36/60] drm/i915/uapi: introduce drm_i915_gem_create_ext Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 38/60] drm/i915/dg1: Introduce dmabuf mmap to LMEM Matthew Auld
` (27 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Abdiel Janulgue
From: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index bdb324167ef3..627d6034c244 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -4,6 +4,7 @@
* Copyright © 2019 Intel Corporation
*/
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_object.h"
#include "i915_drv.h"
#include "i915_vma.h"
@@ -102,10 +103,16 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
struct i915_vma *vma;
obj = ERR_PTR(-ENODEV);
- if (i915_ggtt_has_aperture(ggtt))
- obj = i915_gem_object_create_stolen(i915, size);
- if (IS_ERR(obj))
- obj = i915_gem_object_create_internal(i915, size);
+ if (HAS_LMEM(i915)) {
+ obj = i915_gem_object_create_lmem(i915, size,
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_VOLATILE);
+ } else {
+ if (i915_ggtt_has_aperture(ggtt))
+ obj = i915_gem_object_create_stolen(i915, size);
+ if (IS_ERR(obj))
+ obj = i915_gem_object_create_internal(i915, size);
+ }
if (IS_ERR(obj))
return ERR_CAST(obj);
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 38/60] drm/i915/dg1: Introduce dmabuf mmap to LMEM
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (36 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 37/60] drm/i915/lmem: allocate cmd ring in lmem Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 39/60] drm/i915: setup the LMEM region Matthew Auld
` (26 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: "Michael J. Ruhl" <michael.j.ruhl@intel.com>
The i915 GEM dmabuf mmap interface assumes all BOs are SHMEM. When
the BO is backed by LMEM, this assumption doesn't work so well.
Introduce the dmabuf mmap interface to LMEM by adding the appropriate
VMA faulting mechanism and update dmabuf to allow for LMEM backed BOs by
leveraging the gem_mman path.
Cc: Brian Welty <brian.welty@intel.com>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 58 ++++++++--
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 103 ++++++++++--------
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 8 ++
.../drm/i915/gem/selftests/i915_gem_mman.c | 12 +-
4 files changed, 119 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 2679380159fc..5824e56751ac 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -9,6 +9,8 @@
#include <linux/dma-resv.h>
#include "i915_drv.h"
+#include "i915_gem_lmem.h"
+#include "i915_gem_mman.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
@@ -97,7 +99,41 @@ static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr)
i915_gem_object_unpin_map(obj);
}
-static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
+/**
+ * i915_gem_dmabuf_update_vma - Setup VMA information for exported LMEM
+ * objects
+ * @obj: valid LMEM object
+ * @vma: va;od vma
+ *
+ * NOTE: on success, the final _object_put() will be done by the VMA
+ * vm_close() callback.
+ */
+static int i915_gem_dmabuf_update_vma(struct drm_i915_gem_object *obj,
+ struct vm_area_struct *vma)
+{
+ struct i915_mmap_offset *mmo;
+ int err;
+
+ i915_gem_object_get(obj);
+ mmo = i915_gem_mmap_offset_attach(obj, I915_MMAP_TYPE_WC, NULL);
+ if (IS_ERR(mmo)) {
+ err = PTR_ERR(mmo);
+ goto out;
+ }
+
+ err = i915_gem_update_vma_info(mmo, vma);
+ if (err)
+ goto out;
+
+ return 0;
+
+out:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf,
+ struct vm_area_struct *vma)
{
struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
int ret;
@@ -105,17 +141,21 @@ static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *
if (obj->base.size < vma->vm_end - vma->vm_start)
return -EINVAL;
- if (!obj->base.filp)
- return -ENODEV;
+ /* shmem */
+ if (obj->base.filp) {
+ ret = call_mmap(obj->base.filp, vma);
+ if (ret)
+ return ret;
+ fput(vma->vm_file);
+ vma->vm_file = get_file(obj->base.filp);
- ret = call_mmap(obj->base.filp, vma);
- if (ret)
- return ret;
+ return 0;
+ }
- fput(vma->vm_file);
- vma->vm_file = get_file(obj->base.filp);
+ if (i915_gem_object_is_lmem(obj))
+ return i915_gem_dmabuf_update_vma(obj, vma);
- return 0;
+ return -ENODEV;
}
static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index b23368529a40..38c8874e10d2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -568,10 +568,10 @@ insert_mmo(struct drm_i915_gem_object *obj, struct i915_mmap_offset *mmo)
return mmo;
}
-static struct i915_mmap_offset *
-mmap_offset_attach(struct drm_i915_gem_object *obj,
- enum i915_mmap_type mmap_type,
- struct drm_file *file)
+struct i915_mmap_offset *
+i915_gem_mmap_offset_attach(struct drm_i915_gem_object *obj,
+ enum i915_mmap_type mmap_type,
+ struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct i915_mmap_offset *mmo;
@@ -645,7 +645,7 @@ __assign_mmap_offset(struct drm_file *file,
goto out;
}
- mmo = mmap_offset_attach(obj, mmap_type, file);
+ mmo = i915_gem_mmap_offset_attach(obj, mmap_type, file);
if (IS_ERR(mmo)) {
err = PTR_ERR(mmo);
goto out;
@@ -816,56 +816,21 @@ static struct file *mmap_singleton(struct drm_i915_private *i915)
return file;
}
-/*
- * This overcomes the limitation in drm_gem_mmap's assignment of a
- * drm_gem_object as the vma->vm_private_data. Since we need to
- * be able to resolve multiple mmap offsets which could be tied
- * to a single gem object.
- */
-int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+int i915_gem_update_vma_info(struct i915_mmap_offset *mmo,
+ struct vm_area_struct *vma)
{
- struct drm_vma_offset_node *node;
- struct drm_file *priv = filp->private_data;
- struct drm_device *dev = priv->minor->dev;
- struct drm_i915_gem_object *obj = NULL;
- struct i915_mmap_offset *mmo = NULL;
struct file *anon;
- if (drm_dev_is_unplugged(dev))
- return -ENODEV;
-
- rcu_read_lock();
- drm_vma_offset_lock_lookup(dev->vma_offset_manager);
- node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
- vma->vm_pgoff,
- vma_pages(vma));
- if (node && drm_vma_node_is_allowed(node, priv)) {
- /*
- * Skip 0-refcnted objects as it is in the process of being
- * destroyed and will be invalid when the vma manager lock
- * is released.
- */
- mmo = container_of(node, struct i915_mmap_offset, vma_node);
- obj = i915_gem_object_get_rcu(mmo->obj);
- }
- drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
- rcu_read_unlock();
- if (!obj)
- return node ? -EACCES : -EINVAL;
-
- if (i915_gem_object_is_readonly(obj)) {
- if (vma->vm_flags & VM_WRITE) {
- i915_gem_object_put(obj);
+ if (i915_gem_object_is_readonly(mmo->obj)) {
+ if (vma->vm_flags & VM_WRITE)
return -EINVAL;
- }
+
vma->vm_flags &= ~VM_MAYWRITE;
}
- anon = mmap_singleton(to_i915(dev));
- if (IS_ERR(anon)) {
- i915_gem_object_put(obj);
+ anon = mmap_singleton(to_i915(mmo->obj->base.dev));
+ if (IS_ERR(anon))
return PTR_ERR(anon);
- }
vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
vma->vm_private_data = mmo;
@@ -910,6 +875,50 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
return 0;
}
+/*
+ * This overcomes the limitation in drm_gem_mmap's assignment of a
+ * drm_gem_object as the vma->vm_private_data. Since we need to
+ * be able to resolve multiple mmap offsets which could be tied
+ * to a single gem object.
+ */
+int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ struct drm_vma_offset_node *node;
+ struct drm_file *priv = filp->private_data;
+ struct drm_device *dev = priv->minor->dev;
+ struct drm_i915_gem_object *obj = NULL;
+ struct i915_mmap_offset *mmo = NULL;
+ int err;
+
+ if (drm_dev_is_unplugged(dev))
+ return -ENODEV;
+
+ rcu_read_lock();
+ drm_vma_offset_lock_lookup(dev->vma_offset_manager);
+ node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
+ vma->vm_pgoff,
+ vma_pages(vma));
+ if (node && drm_vma_node_is_allowed(node, priv)) {
+ /*
+ * Skip 0-refcnted objects as it is in the process of being
+ * destroyed and will be invalid when the vma manager lock
+ * is released.
+ */
+ mmo = container_of(node, struct i915_mmap_offset, vma_node);
+ obj = i915_gem_object_get_rcu(mmo->obj);
+ }
+ drm_vma_offset_unlock_lookup(dev->vma_offset_manager);
+ rcu_read_unlock();
+ if (!obj)
+ return node ? -EACCES : -EINVAL;
+
+ err = i915_gem_update_vma_info(mmo, vma);
+ if (err)
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/i915_gem_mman.c"
#endif
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
index efee9e0d2508..8da5f0d6f46f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h
@@ -10,6 +10,8 @@
#include <linux/mm_types.h>
#include <linux/types.h>
+#include "gem/i915_gem_object_types.h"
+
struct drm_device;
struct drm_file;
struct drm_i915_gem_object;
@@ -29,4 +31,10 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj);
void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj);
+struct i915_mmap_offset *
+i915_gem_mmap_offset_attach(struct drm_i915_gem_object *obj,
+ enum i915_mmap_type mmap_type,
+ struct drm_file *file);
+int i915_gem_update_vma_info(struct i915_mmap_offset *mmo,
+ struct vm_area_struct *vma);
#endif
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 9c7402ce5bf9..4343f4ccc9b6 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -572,7 +572,7 @@ static bool assert_mmap_offset(struct drm_i915_private *i915,
if (IS_ERR(obj))
return false;
- mmo = mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);
+ mmo = i915_gem_mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);
i915_gem_object_put(obj);
return PTR_ERR_OR_ZERO(mmo) == expected;
@@ -675,7 +675,7 @@ static int igt_mmap_offset_exhaustion(void *arg)
goto out;
}
- mmo = mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);
+ mmo = i915_gem_mmap_offset_attach(obj, I915_MMAP_OFFSET_GTT, NULL);
if (IS_ERR(mmo)) {
pr_err("Unable to insert object into reclaimed hole\n");
err = PTR_ERR(mmo);
@@ -850,7 +850,7 @@ static int __igt_mmap(struct drm_i915_private *i915,
if (err)
return err;
- mmo = mmap_offset_attach(obj, type, NULL);
+ mmo = i915_gem_mmap_offset_attach(obj, type, NULL);
if (IS_ERR(mmo))
return PTR_ERR(mmo);
@@ -988,7 +988,7 @@ static int __igt_mmap_access(struct drm_i915_private *i915,
if (!can_mmap(obj, type) || !can_access(obj))
return 0;
- mmo = mmap_offset_attach(obj, type, NULL);
+ mmo = i915_gem_mmap_offset_attach(obj, type, NULL);
if (IS_ERR(mmo))
return PTR_ERR(mmo);
@@ -1101,7 +1101,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
if (err)
return err;
- mmo = mmap_offset_attach(obj, type, NULL);
+ mmo = i915_gem_mmap_offset_attach(obj, type, NULL);
if (IS_ERR(mmo))
return PTR_ERR(mmo);
@@ -1267,7 +1267,7 @@ static int __igt_mmap_revoke(struct drm_i915_private *i915,
if (!can_mmap(obj, type))
return 0;
- mmo = mmap_offset_attach(obj, type, NULL);
+ mmo = i915_gem_mmap_offset_attach(obj, type, NULL);
if (IS_ERR(mmo))
return PTR_ERR(mmo);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 39/60] drm/i915: setup the LMEM region
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (37 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 38/60] drm/i915/dg1: Introduce dmabuf mmap to LMEM Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 40/60] drm/i915: drop fake LMEM Matthew Auld
` (25 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue, Lucas De Marchi
Hook up the LMEM region. Addresses will start from zero, and for CPU
access we get LMEM_BAR which is just a 1:1 mapping of said region.
Based on a patch from Michel Thierry.
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_memory_region.c | 11 ++++++-
drivers/gpu/drm/i915/intel_region_lmem.c | 38 ++++++++++++++++++++++
drivers/gpu/drm/i915/intel_region_lmem.h | 2 ++
4 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7191ebd7c13f..cebcd702d968 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12035,6 +12035,9 @@ enum skl_power_gate {
#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+#define GEN12_LMEM_CFG_ADDR _MMIO(0xcf58)
+#define LMEM_ENABLE (1 << 31)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 609a65935c98..1e9f52feec59 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -297,7 +297,16 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
mem = i915_gem_stolen_setup(i915);
break;
case INTEL_MEMORY_LOCAL:
- mem = intel_setup_fake_lmem(i915);
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+ if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
+ if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
+ i915->params.fake_lmem_start)
+ mem = intel_setup_fake_lmem(i915);
+ }
+#endif
+
+ if (IS_ERR(mem))
+ mem = i915_gem_setup_lmem(i915);
break;
}
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 40d8f1a95df6..e98582c76de1 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -136,3 +136,41 @@ intel_setup_fake_lmem(struct drm_i915_private *i915)
return mem;
}
+
+static struct intel_memory_region *
+setup_lmem(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct intel_memory_region *mem;
+ resource_size_t io_start;
+ resource_size_t size;
+
+ /* Enables Local Memory functionality in GAM */
+ I915_WRITE(GEN12_LMEM_CFG_ADDR, I915_READ(GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);
+
+ io_start = pci_resource_start(pdev, 2);
+ size = pci_resource_len(pdev, 2);
+
+ mem = intel_memory_region_create(dev_priv,
+ 0,
+ size,
+ I915_GTT_PAGE_SIZE_4K,
+ io_start,
+ &intel_region_lmem_ops);
+ if (!IS_ERR(mem)) {
+ DRM_INFO("Intel graphics LMEM: %pR\n", &mem->region);
+ DRM_INFO("Intel graphics LMEM IO start: %llx\n",
+ (u64)mem->io_start);
+ DRM_INFO("Intel graphics LMEM size: %llx\n",
+ (u64)size);
+ }
+
+ return mem;
+}
+
+struct intel_memory_region *
+i915_gem_setup_lmem(struct drm_i915_private *i915)
+{
+ return setup_lmem(i915);
+}
+
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.h b/drivers/gpu/drm/i915/intel_region_lmem.h
index 213def7c7b8a..054e729035c1 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.h
+++ b/drivers/gpu/drm/i915/intel_region_lmem.h
@@ -10,6 +10,8 @@ struct drm_i915_private;
extern const struct intel_memory_region_ops intel_region_lmem_ops;
+struct intel_memory_region *i915_gem_setup_lmem(struct drm_i915_private *i915);
+
struct intel_memory_region *
intel_setup_fake_lmem(struct drm_i915_private *i915);
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 40/60] drm/i915: drop fake LMEM
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (38 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 39/60] drm/i915: setup the LMEM region Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 41/60] drm/i915: Distinction of memory regions Matthew Auld
` (24 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 17 ----
drivers/gpu/drm/i915/i915_params.c | 5 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_memory_region.c | 11 +--
drivers/gpu/drm/i915/intel_region_lmem.c | 96 ----------------------
drivers/gpu/drm/i915/intel_region_lmem.h | 3 -
6 files changed, 1 insertion(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7b758131e0dc..dbec244f63bc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -954,23 +954,6 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (!i915->params.nuclear_pageflip && match_info->gen < 5)
i915->drm.driver_features &= ~DRIVER_ATOMIC;
- /*
- * Check if we support fake LMEM -- for now we only unleash this for
- * the live selftests(test-and-exit).
- */
-#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
- if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
- if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
- i915->params.fake_lmem_start) {
- mkwrite_device_info(i915)->memory_regions =
- REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
- mkwrite_device_info(i915)->is_dgfx = true;
- GEM_BUG_ON(!HAS_LMEM(i915));
- GEM_BUG_ON(!IS_DGFX(i915));
- }
- }
-#endif
-
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 8d8db9ff0a48..1e928e31fd22 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -187,11 +187,6 @@ i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
#endif
-#if IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)
-i915_param_named_unsafe(fake_lmem_start, ulong, 0400,
- "Fake LMEM start offset (default: 0)");
-#endif
-
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
const char *type,
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 53fb5ba8fbed..1416fabef227 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -69,7 +69,6 @@ struct drm_printer;
param(int, fastboot, -1, 0600) \
param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
- param(unsigned long, fake_lmem_start, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 1e9f52feec59..b4b7858f13e0 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -297,16 +297,7 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
mem = i915_gem_stolen_setup(i915);
break;
case INTEL_MEMORY_LOCAL:
-#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
- if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
- if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
- i915->params.fake_lmem_start)
- mem = intel_setup_fake_lmem(i915);
- }
-#endif
-
- if (IS_ERR(mem))
- mem = i915_gem_setup_lmem(i915);
+ mem = i915_gem_setup_lmem(i915);
break;
}
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index e98582c76de1..95c8d89d1fc9 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -9,64 +9,9 @@
#include "gem/i915_gem_region.h"
#include "intel_region_lmem.h"
-static int init_fake_lmem_bar(struct intel_memory_region *mem)
-{
- struct drm_i915_private *i915 = mem->i915;
- struct i915_ggtt *ggtt = &i915->ggtt;
- unsigned long n;
- int ret;
-
- /* We want to 1:1 map the mappable aperture to our reserved region */
-
- mem->fake_mappable.start = 0;
- mem->fake_mappable.size = resource_size(&mem->region);
- mem->fake_mappable.color = I915_COLOR_UNEVICTABLE;
-
- ret = drm_mm_reserve_node(&ggtt->vm.mm, &mem->fake_mappable);
- if (ret)
- return ret;
-
- mem->remap_addr = dma_map_resource(&i915->drm.pdev->dev,
- mem->region.start,
- mem->fake_mappable.size,
- PCI_DMA_BIDIRECTIONAL,
- DMA_ATTR_FORCE_CONTIGUOUS);
- if (dma_mapping_error(&i915->drm.pdev->dev, mem->remap_addr)) {
- drm_mm_remove_node(&mem->fake_mappable);
- return -EINVAL;
- }
-
- for (n = 0; n < mem->fake_mappable.size >> PAGE_SHIFT; ++n) {
- ggtt->vm.insert_page(&ggtt->vm,
- mem->remap_addr + (n << PAGE_SHIFT),
- n << PAGE_SHIFT,
- I915_CACHE_NONE, 0);
- }
-
- mem->region = (struct resource)DEFINE_RES_MEM(mem->remap_addr,
- mem->fake_mappable.size);
-
- return 0;
-}
-
-static void release_fake_lmem_bar(struct intel_memory_region *mem)
-{
- if (!drm_mm_node_allocated(&mem->fake_mappable))
- return;
-
- drm_mm_remove_node(&mem->fake_mappable);
-
- dma_unmap_resource(&mem->i915->drm.pdev->dev,
- mem->remap_addr,
- mem->fake_mappable.size,
- PCI_DMA_BIDIRECTIONAL,
- DMA_ATTR_FORCE_CONTIGUOUS);
-}
-
static void
region_lmem_release(struct intel_memory_region *mem)
{
- release_fake_lmem_bar(mem);
io_mapping_fini(&mem->iomap);
intel_memory_region_release_buddy(mem);
}
@@ -76,11 +21,6 @@ region_lmem_init(struct intel_memory_region *mem)
{
int ret;
- if (mem->i915->params.fake_lmem_start) {
- ret = init_fake_lmem_bar(mem);
- GEM_BUG_ON(ret);
- }
-
if (!io_mapping_init_wc(&mem->iomap,
mem->io_start,
resource_size(&mem->region)))
@@ -101,42 +41,6 @@ const struct intel_memory_region_ops intel_region_lmem_ops = {
.create_object = __i915_gem_lmem_object_create,
};
-struct intel_memory_region *
-intel_setup_fake_lmem(struct drm_i915_private *i915)
-{
- struct pci_dev *pdev = i915->drm.pdev;
- struct intel_memory_region *mem;
- resource_size_t mappable_end;
- resource_size_t io_start;
- resource_size_t start;
-
- GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt));
- GEM_BUG_ON(!i915->params.fake_lmem_start);
-
- /* Your mappable aperture belongs to me now! */
- mappable_end = pci_resource_len(pdev, 2);
- io_start = pci_resource_start(pdev, 2),
- start = i915->params.fake_lmem_start;
-
- mem = intel_memory_region_create(i915,
- start,
- mappable_end,
- PAGE_SIZE,
- io_start,
- &intel_region_lmem_ops);
- if (!IS_ERR(mem)) {
- drm_info(&i915->drm, "Intel graphics fake LMEM: %pR\n",
- &mem->region);
- drm_info(&i915->drm,
- "Intel graphics fake LMEM IO start: %llx\n",
- (u64)mem->io_start);
- drm_info(&i915->drm, "Intel graphics fake LMEM size: %llx\n",
- (u64)resource_size(&mem->region));
- }
-
- return mem;
-}
-
static struct intel_memory_region *
setup_lmem(struct drm_i915_private *dev_priv)
{
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.h b/drivers/gpu/drm/i915/intel_region_lmem.h
index 054e729035c1..6dbed8de3ce3 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.h
+++ b/drivers/gpu/drm/i915/intel_region_lmem.h
@@ -12,7 +12,4 @@ extern const struct intel_memory_region_ops intel_region_lmem_ops;
struct intel_memory_region *i915_gem_setup_lmem(struct drm_i915_private *i915);
-struct intel_memory_region *
-intel_setup_fake_lmem(struct drm_i915_private *i915);
-
#endif /* !__INTEL_REGION_LMEM_H */
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 41/60] drm/i915: Distinction of memory regions
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (39 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 40/60] drm/i915: drop fake LMEM Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 42/60] drm/i915: PPGTT support Matthew Auld
` (23 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
IGTs should be able to choose testing strategy depending on memory
regions and its sizes. Add region instance number to make this
easier and descriptive.
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Adam Miszczak <adam.miszczak@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
drivers/gpu/drm/i915/intel_memory_region.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index b4b7858f13e0..eeea520f97ba 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -313,6 +313,10 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
mem->type = type;
mem->instance = instance;
+ if (HAS_LMEM(mem->i915) && type != INTEL_MEMORY_SYSTEM)
+ intel_memory_region_set_name(mem, "%s%u",
+ mem->name, mem->instance);
+
i915->mm.regions[i] = mem;
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 42/60] drm/i915: PPGTT support
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (40 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 41/60] drm/i915: Distinction of memory regions Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 43/60] drm/i915: support GGTT LMEM entries Matthew Auld
` (22 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
All the top levels of the PPGTT now need to reside in LMEM, and for the
PTEs we get an LM bit, to signal whether the page resides in SMEM or
LMEM. For the scratch pages we opt for just keeping them SMEM.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 83 +++++++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_gtt.c | 74 +++++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 10 +++-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 10 +++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +
6 files changed, 155 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index cdc0b9c54305..9a605111c6c5 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -11,6 +11,8 @@
#include "i915_vgpu.h"
#include "intel_gt.h"
+#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
+
/* Write pde (index) from the page directory @pd to the page table @pt */
static inline void gen6_write_pde(const struct gen6_ppgtt *ppgtt,
const unsigned int pde,
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 699125928272..2b6ea31a8769 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -50,6 +50,21 @@ static u64 gen8_pte_encode(dma_addr_t addr,
return pte;
}
+static u64 gen12_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+
+ if (unlikely(flags & PTE_READ_ONLY))
+ pte &= ~_PAGE_RW;
+
+ if (flags & PTE_LM)
+ pte |= GEN12_PPGTT_PTE_LM;
+
+ return pte;
+}
+
static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
{
struct drm_i915_private *i915 = ppgtt->vm.i915;
@@ -187,11 +202,18 @@ static void __gen8_ppgtt_cleanup(struct i915_address_space *vm,
static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
{
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+ struct drm_i915_private *i915 = vm->i915;
if (intel_vgpu_active(vm->i915))
gen8_ppgtt_notify_vgt(ppgtt, false);
__gen8_ppgtt_cleanup(vm, ppgtt->pd, gen8_pd_top_count(vm), vm->top);
+ if (HAS_LMEM(i915)) {
+ struct intel_memory_region *mem =
+ i915->mm.regions[INTEL_REGION_LMEM];
+
+ intel_memory_region_put(mem);
+ }
free_scratch(vm);
}
@@ -237,11 +259,11 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
atomic_read(&pt->used));
GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
- vaddr = kmap_atomic_px(pt);
+ vaddr = kmap_atomic_base(&pt->base);
memset64(vaddr + gen8_pd_index(start, 0),
vm->scratch[0].encode,
count);
- kunmap_atomic(vaddr);
+ kunmap_atomic_base(&pt->base, vaddr);
atomic_sub(count, &pt->used);
start += count;
@@ -408,11 +430,13 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
u32 flags)
{
struct i915_page_directory *pd;
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ struct i915_page_table *pt;
+ const gen8_pte_t pte_encode = ppgtt->vm.pte_encode(0, cache_level, flags);
gen8_pte_t *vaddr;
pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
- vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
+ vaddr = kmap_atomic_base(&pt->base);
do {
GEM_BUG_ON(iter->sg->length < I915_GTT_PAGE_SIZE);
write_pte(&vaddr[gen8_pd_index(idx, 0)],
@@ -439,11 +463,12 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
- kunmap_atomic(vaddr);
- vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ kunmap_atomic_base(&pt->base, vaddr);
+ pt = i915_pt_entry(pd, gen8_pd_index(idx, 1));
+ vaddr = kmap_atomic_base(&pt->base);
}
} while (1);
- kunmap_atomic(vaddr);
+ kunmap_atomic_base(&pt->base, vaddr);
return idx;
}
@@ -453,7 +478,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags)
{
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
+ const gen8_pte_t pte_encode = vma->vm->pte_encode(0, cache_level, flags);
u64 start = vma->node.start;
dma_addr_t rem = iter->sg->length;
@@ -464,6 +489,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
gen8_pdp_for_page_address(vma->vm, start);
struct i915_page_directory * const pd =
i915_pd_entry(pdp, __gen8_pte_index(start, 2));
+ struct i915_page_dma *base;
gen8_pte_t encode = pte_encode;
unsigned int maybe_64K = -1;
unsigned int page_size;
@@ -478,7 +504,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
encode |= GEN8_PDE_PS_2M;
page_size = I915_GTT_PAGE_SIZE_2M;
- vaddr = kmap_atomic_px(pd);
+ base = &pd->pt.base;
} else {
struct i915_page_table *pt =
i915_pt_entry(pd, __gen8_pte_index(start, 1));
@@ -493,9 +519,11 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
maybe_64K = __gen8_pte_index(start, 1);
- vaddr = kmap_atomic_px(pt);
+ base = &pt->base;
}
+ vaddr = kmap_atomic_base(base);
+
do {
GEM_BUG_ON(iter->sg->length < page_size);
write_pte(&vaddr[index++], encode | iter->dma);
@@ -523,7 +551,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
}
} while (rem >= page_size && index < I915_PDES);
- kunmap_atomic(vaddr);
+ kunmap_atomic_base(base, vaddr);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -537,9 +565,9 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
!iter->sg && IS_ALIGNED(vma->node.start +
vma->node.size,
I915_GTT_PAGE_SIZE_2M)))) {
- vaddr = kmap_atomic_px(pd);
+ vaddr = kmap_atomic_base(&pd->pt.base);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- kunmap_atomic(vaddr);
+ kunmap_atomic_base(&pd->pt.base, vaddr);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -552,15 +580,17 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
* selftests.
*/
if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) {
+ struct i915_page_table *pt =
+ i915_pt_entry(pd, maybe_64K);
u16 i;
encode = vma->vm->scratch[0].encode;
- vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
+ vaddr = kmap_atomic_base(&pt->base);
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- kunmap_atomic(vaddr);
+ kunmap_atomic_base(&pt->base, vaddr);
}
}
@@ -595,6 +625,7 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
static int gen8_init_scratch(struct i915_address_space *vm)
{
+ u32 pte_flags = vm->has_read_only;
int ret;
int i;
@@ -617,9 +648,12 @@ static int gen8_init_scratch(struct i915_address_space *vm)
if (ret)
return ret;
+ if (vm->scratch[0].base.block_lm)
+ pte_flags |= PTE_LM;
+
vm->scratch[0].encode =
- gen8_pte_encode(px_dma(&vm->scratch[0]),
- I915_CACHE_LLC, vm->has_read_only);
+ vm->pte_encode(px_dma(&vm->scratch[0]),
+ I915_CACHE_LLC, pte_flags);
for (i = 1; i <= vm->top; i++) {
if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[i]))))
@@ -694,6 +728,7 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
*/
struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
{
+ struct drm_i915_private *i915 = gt->i915;
struct i915_ppgtt *ppgtt;
int err;
@@ -721,6 +756,11 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
if (IS_CHERRYVIEW(gt->i915) || IS_BROXTON(gt->i915))
ppgtt->vm.pt_kmap_wc = true;
+ if (INTEL_GEN(gt->i915) >= 12)
+ ppgtt->vm.pte_encode = gen12_pte_encode;
+ else
+ ppgtt->vm.pte_encode = gen8_pte_encode;
+
err = gen8_init_scratch(&ppgtt->vm);
if (err)
goto err_free;
@@ -737,13 +777,18 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
goto err_free_pd;
}
+ /* Paging structures are allocated in LMEM */
+ if (HAS_LMEM(i915)) {
+ struct intel_memory_region *mem =
+ i915->mm.regions[INTEL_REGION_LMEM];
+
+ intel_memory_region_get(mem);
+ }
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
- ppgtt->vm.pte_encode = gen8_pte_encode;
-
if (intel_vgpu_active(gt->i915))
gen8_ppgtt_notify_vgt(ppgtt, true);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 2a72cce63fd9..37816936f4a8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -264,10 +264,58 @@ void clear_pages(struct i915_vma *vma)
memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
}
+static struct i915_buddy_block *vm_alloc_lm(struct drm_i915_private *i915)
+{
+ struct intel_memory_region *mem = i915->mm.regions[INTEL_REGION_LMEM];
+
+ return __intel_memory_region_get_block_buddy(mem,
+ mem->mm.chunk_size,
+ I915_ALLOC_CONTIGUOUS);
+}
+
+static void vm_free_lm(struct i915_buddy_block *block)
+{
+ __intel_memory_region_put_block_buddy(block);
+}
+
+static inline dma_addr_t vm_daddr_lm(struct i915_buddy_block *block)
+{
+ struct intel_memory_region *mem = block->private;
+
+ return mem->region.start + i915_buddy_block_offset(block);
+}
+
+static inline void __iomem *vm_kmap_lm(struct i915_buddy_block *block)
+{
+ struct intel_memory_region *mem = block->private;
+
+ return io_mapping_map_atomic_wc(&mem->iomap,
+ i915_buddy_block_offset(block));
+}
+
+static inline void vm_kunmap_lm(void *vaddr)
+{
+ io_mapping_unmap_atomic(vaddr);
+}
+
static int __setup_page_dma(struct i915_address_space *vm,
struct i915_page_dma *p,
gfp_t gfp)
{
+ struct drm_i915_private *i915 = vm->i915;
+
+ if (HAS_LMEM(i915)) {
+ struct i915_buddy_block *block_lm;
+
+ block_lm = vm_alloc_lm(i915);
+ if (IS_ERR(block_lm))
+ return PTR_ERR(block_lm);
+
+ p->block_lm = block_lm;
+ p->daddr = vm_daddr_lm(block_lm);
+ return 0;
+ }
+
p->page = vm_alloc_page(vm, gfp | I915_GFP_ALLOW_FAIL);
if (unlikely(!p->page))
return -ENOMEM;
@@ -292,14 +340,34 @@ int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p)
void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p)
{
- dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
- vm_free_page(vm, p->page);
+ if (p->block_lm) {
+ vm_free_lm(p->block_lm);
+ } else {
+ dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ vm_free_page(vm, p->page);
+ }
+}
+
+void *kmap_page_dma(const struct i915_page_dma *p)
+{
+ if (p->block_lm)
+ return vm_kmap_lm(p->block_lm);
+ else
+ return kmap_atomic(p->page);
+}
+
+void kunmap_page_dma(const struct i915_page_dma *p, void *vaddr)
+{
+ if (p->block_lm)
+ vm_kunmap_lm(vaddr);
+ else
+ kunmap_atomic(vaddr);
}
void
fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
{
- kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
+ kunmap_atomic_base(p, memset64(kmap_atomic_base(p), val, count));
}
static void poison_scratch_page(struct page *page, unsigned long size)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index f2b75078e05f..2f4096ce06dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -85,6 +85,8 @@ typedef u64 gen8_pte_t;
#define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
#define BYT_PTE_WRITEABLE REG_BIT(1)
+#define GEN12_PPGTT_PTE_LM (1 << 11)
+
/*
* Cacheability Control is a 4-bit value. The low three bits are stored in bits
* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
@@ -140,6 +142,7 @@ struct i915_fence_reg;
__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
struct i915_page_dma {
+ struct i915_buddy_block *block_lm;
struct page *page;
union {
dma_addr_t daddr;
@@ -280,6 +283,7 @@ struct i915_address_space {
enum i915_cache_level level,
u32 flags); /* Create a valid PTE */
#define PTE_READ_ONLY BIT(0)
+#define PTE_LM BIT(1)
int (*allocate_va_range)(struct i915_address_space *vm,
u64 start, u64 length);
@@ -520,7 +524,11 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt);
int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p);
void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p);
-#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
+void *kmap_page_dma(const struct i915_page_dma *p);
+void kunmap_page_dma(const struct i915_page_dma *p, void *vaddr);
+
+#define kmap_atomic_base(base) kmap_page_dma(base)
+#define kunmap_atomic_base(base, vaddr) kunmap_page_dma(base, vaddr)
void
fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index f0862e924d11..e79c93b662c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -7,6 +7,8 @@
#include "i915_trace.h"
#include "intel_gtt.h"
+#include "gem/i915_gem_lmem.h"
+#include "gem/i915_gem_region.h"
#include "gen6_ppgtt.h"
#include "gen8_ppgtt.h"
@@ -14,7 +16,7 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm)
{
struct i915_page_table *pt;
- pt = kmalloc(sizeof(*pt), I915_GFP_ALLOW_FAIL);
+ pt = kzalloc(sizeof(*pt), I915_GFP_ALLOW_FAIL);
if (unlikely(!pt))
return ERR_PTR(-ENOMEM);
@@ -66,10 +68,10 @@ write_dma_entry(struct i915_page_dma * const pdma,
const unsigned short idx,
const u64 encoded_entry)
{
- u64 * const vaddr = kmap_atomic(pdma->page);
+ u64 * const vaddr = kmap_atomic_base(pdma);
vaddr[idx] = encoded_entry;
- kunmap_atomic(vaddr);
+ kunmap_atomic_base(pdma, vaddr);
}
void
@@ -175,6 +177,8 @@ int ppgtt_bind_vma(struct i915_address_space *vm,
pte_flags = 0;
if (i915_gem_object_is_readonly(vma->obj))
pte_flags |= PTE_READ_ONLY;
+ if (i915_gem_object_is_lmem(vma->obj))
+ pte_flags |= PTE_LM;
vm->insert_entries(vm, vma, cache_level, pte_flags);
wmb();
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5ee1567f3d1..038793178b3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -16,6 +16,8 @@
#include <asm/smp.h>
#include "display/intel_frontbuffer.h"
+#include "gem/i915_gem_lmem.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_requests.h"
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 43/60] drm/i915: support GGTT LMEM entries
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (41 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 42/60] drm/i915: PPGTT support Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 44/60] drm/i915: allocate context from LMEM Matthew Auld
` (21 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 24 ++++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 ++-
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 62979ea591f0..138546610f1f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -10,6 +10,7 @@
#include <drm/i915_drm.h>
+#include "gem/i915_gem_lmem.h"
#include "intel_gt.h"
#include "i915_drv.h"
#include "i915_scatterlist.h"
@@ -182,7 +183,12 @@ static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags)
{
- return addr | _PAGE_PRESENT;
+ gen8_pte_t pte = addr | _PAGE_PRESENT;
+
+ if (flags & PTE_LM)
+ pte |= GEN12_GGTT_PTE_LM;
+
+ return pte;
}
static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
@@ -194,13 +200,13 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
dma_addr_t addr,
u64 offset,
enum i915_cache_level level,
- u32 unused)
+ u32 flags)
{
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
gen8_pte_t __iomem *pte =
(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
- gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
+ gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
ggtt->invalidate(ggtt);
}
@@ -210,7 +216,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
enum i915_cache_level level,
u32 flags)
{
- const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);
+ const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
gen8_pte_t __iomem *gte;
gen8_pte_t __iomem *end;
@@ -449,8 +455,10 @@ static int ggtt_bind_vma(struct i915_address_space *vm,
/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
pte_flags = 0;
- if (i915_gem_object_is_readonly(obj))
+ if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
pte_flags |= PTE_READ_ONLY;
+ if (i915_gem_object_is_lmem(obj))
+ pte_flags |= PTE_LM;
vm->insert_entries(vm, vma, cache_level, pte_flags);
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
@@ -768,6 +776,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
struct drm_i915_private *i915 = ggtt->vm.i915;
struct pci_dev *pdev = i915->drm.pdev;
phys_addr_t phys_addr;
+ u32 pte_flags = 0;
int ret;
/* For Modern GENs the PTEs and register space are split in the BAR */
@@ -797,9 +806,12 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
return ret;
}
+ if (ggtt->vm.scratch[0].base.block_lm)
+ pte_flags |= PTE_LM;
+
ggtt->vm.scratch[0].encode =
ggtt->vm.pte_encode(px_dma(&ggtt->vm.scratch[0]),
- I915_CACHE_NONE, 0);
+ I915_CACHE_NONE, pte_flags);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 2f4096ce06dc..0aa9e0213d73 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -85,7 +85,8 @@ typedef u64 gen8_pte_t;
#define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
#define BYT_PTE_WRITEABLE REG_BIT(1)
-#define GEN12_PPGTT_PTE_LM (1 << 11)
+#define GEN12_GGTT_PTE_LM (1 << 1)
+#define GEN12_PPGTT_PTE_LM (1 << 11)
/*
* Cacheability Control is a 4-bit value. The low three bits are stored in bits
--
2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 44/60] drm/i915: allocate context from LMEM
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (42 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 43/60] drm/i915: support GGTT LMEM entries Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 45/60] drm/i915: move engine scratch to LMEM Matthew Auld
` (20 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 31 ++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fbcfeaed6441..c6528c8f9b2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -133,6 +133,8 @@
*/
#include <linux/interrupt.h>
+#include "gem/i915_gem_lmem.h"
+
#include "i915_drv.h"
#include "i915_perf.h"
#include "i915_trace.h"
@@ -5265,6 +5267,21 @@ populate_lr_context(struct intel_context *ce,
return 0;
}
+static int context_clear_lmem(struct drm_i915_gem_object *ctx_obj)
+{
+ void *vaddr;
+
+ vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WC);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ memset64(vaddr, 0, ctx_obj->base.size / sizeof(u64));
+
+ i915_gem_object_unpin_map(ctx_obj);
+
+ return 0;
+}
+
static int __execlists_context_alloc(struct intel_context *ce,
struct intel_engine_cs *engine)
{
@@ -5285,10 +5302,22 @@ static int __execlists_context_alloc(struct intel_context *ce,
context_size += PAGE_SIZE;
}
- ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
+ if (HAS_LMEM(engine->i915)) {
+ ctx_obj = i915_gem_object_create_lmem(engine->i915,
+ context_size,
+ I915_BO_ALLOC_CONTIGUOUS);
+ } else {
+ ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
+ }
if (IS_ERR(ctx_obj))
return PTR_ERR(ctx_obj);
+ if (HAS_LMEM(engine->i915)) {
+ ret = context_clear_lmem(ctx_obj);
+ if (ret)
+ goto error_deref_obj;
+ }
+
vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
--
2.26.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 45/60] drm/i915: move engine scratch to LMEM
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (43 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 44/60] drm/i915: allocate context from LMEM Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 46/60] drm/i915: Provide a way to disable PCIe relaxed write ordering Matthew Auld
` (19 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e0755f1a904b..a841bcf4953c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,6 +4,8 @@
*/
#include "debugfs_gt.h"
+
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -342,9 +344,15 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
struct i915_vma *vma;
int ret;
- obj = i915_gem_object_create_stolen(i915, size);
- if (IS_ERR(obj))
- obj = i915_gem_object_create_internal(i915, size);
+ if (HAS_LMEM(i915)) {
+ obj = i915_gem_object_create_lmem(i915, size,
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_VOLATILE);
+ } else {
+ obj = i915_gem_object_create_stolen(i915, size);
+ if (IS_ERR(obj))
+ obj = i915_gem_object_create_internal(i915, size);
+ }
if (IS_ERR(obj)) {
DRM_ERROR("Failed to allocate scratch page\n");
return PTR_ERR(obj);
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 46/60] drm/i915: Provide a way to disable PCIe relaxed write ordering
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (44 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 45/60] drm/i915: move engine scratch to LMEM Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 47/60] drm/i915: setup GPU device lmem region Matthew Auld
` (18 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
For performance writes over PCIe may not be strictly ordered by default.
This provides an option to expose a kernel configuration option to disable
relaxed ordering and turn on strict ordering instead for debug purposes.
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/Kconfig.debug | 11 +++++++++++
drivers/gpu/drm/i915/intel_memory_region.c | 12 ++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index 206882e154bc..114240e890aa 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -221,3 +221,14 @@ config DRM_I915_DEBUG_RUNTIME_PM
driver loading, suspend and resume operations.
If in doubt, say "N"
+
+config DRM_I915_PCIE_STRICT_WRITE_ORDERING
+ bool "Enable PCIe strict ordering "
+ depends on DRM_I915
+ default n
+ help
+ Relaxed ordering in writes is enabled by default to improve system
+ performance. Strict ordering can be selected instead to assist in
+ debugging.
+
+ If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index eeea520f97ba..d564b596efda 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -280,6 +280,18 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
{
int err, i;
+ /* All platforms currently have system memory */
+ GEM_BUG_ON(!HAS_REGION(i915, REGION_SMEM));
+
+ if (IS_DGFX(i915)) {
+ if (IS_ENABLED(CONFIG_DRM_I915_PCIE_STRICT_WRITE_ORDERING))
+ pcie_capability_clear_word(i915->drm.pdev, PCI_EXP_DEVCTL,
+ PCI_EXP_DEVCTL_RELAX_EN);
+ else
+ pcie_capability_set_word(i915->drm.pdev, PCI_EXP_DEVCTL,
+ PCI_EXP_DEVCTL_RELAX_EN);
+ }
+
for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
struct intel_memory_region *mem = ERR_PTR(-ENODEV);
u16 type, instance;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 47/60] drm/i915: setup GPU device lmem region
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (45 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 46/60] drm/i915: Provide a way to disable PCIe relaxed write ordering Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 48/60] drm/i915: Fix object page offset within a region Matthew Auld
` (17 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue, Chris P Wilson, Neel Desai, Balestrieri
From: CQ Tang <cq.tang@intel.com>
The lmem region needs to remove the stolen part.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Balestrieri, Francesco <francesco.balestrieri@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Venkata S Dhanalakota <venkata.s.dhanalakota@intel.com>
Cc: Neel Desai <neel.desai@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_region_lmem.c | 11 +++++++----
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cebcd702d968..6e67c4ee09c2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12038,6 +12038,8 @@ enum skl_power_gate {
#define GEN12_LMEM_CFG_ADDR _MMIO(0xcf58)
#define LMEM_ENABLE (1 << 31)
+#define GEN12_GSMBASE _MMIO(0x108100)
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 95c8d89d1fc9..3a8997fd832d 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -44,20 +44,23 @@ const struct intel_memory_region_ops intel_region_lmem_ops = {
static struct intel_memory_region *
setup_lmem(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
struct pci_dev *pdev = dev_priv->drm.pdev;
struct intel_memory_region *mem;
resource_size_t io_start;
- resource_size_t size;
+ resource_size_t lmem_size;
/* Enables Local Memory functionality in GAM */
I915_WRITE(GEN12_LMEM_CFG_ADDR, I915_READ(GEN12_LMEM_CFG_ADDR) | LMEM_ENABLE);
+ /* Stolen starts from GSMBASE on DG1 */
+ lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE);
+
io_start = pci_resource_start(pdev, 2);
- size = pci_resource_len(pdev, 2);
mem = intel_memory_region_create(dev_priv,
0,
- size,
+ lmem_size,
I915_GTT_PAGE_SIZE_4K,
io_start,
&intel_region_lmem_ops);
@@ -66,7 +69,7 @@ setup_lmem(struct drm_i915_private *dev_priv)
DRM_INFO("Intel graphics LMEM IO start: %llx\n",
(u64)mem->io_start);
DRM_INFO("Intel graphics LMEM size: %llx\n",
- (u64)size);
+ (u64)lmem_size);
}
return mem;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 48/60] drm/i915: Fix object page offset within a region
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (46 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 47/60] drm/i915: setup GPU device lmem region Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 49/60] drm/i915: add i915_gem_object_is_devmem() function Matthew Auld
` (16 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
From: CQ Tang <cq.tang@intel.com>
Adjust the page offset with region start dma address.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 678ddec3237f..07d53c4e1a2c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1033,7 +1033,9 @@ i915_vma_coredump_create(const struct intel_gt *gt,
for_each_sgt_daddr(dma, iter, vma->pages) {
void __iomem *s;
- s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
+ s = io_mapping_map_wc(&mem->iomap,
+ dma - mem->region.start,
+ PAGE_SIZE);
ret = compress_page(compress,
(void __force *)s, dst,
true);
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 49/60] drm/i915: add i915_gem_object_is_devmem() function
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (47 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 48/60] drm/i915: Fix object page offset within a region Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 50/60] drm/i915: finish memory region support for stolen objects Matthew Auld
` (15 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue, Chris P Wilson, Neel Desai
From: CQ Tang <cq.tang@intel.com>
We have three memory region types: INTEL_SMEM, INTEL_LMEM, and
INTEL_STOLEN. We also have two types of memory: system memory
and device memory (or called local memory).
Memory region with type INTEL_SMEM only has system memory; the
other two types of memory regions could have either system memory
or device memory.
This function is used to distinguish real local device memory or
system memory (including fake local memmory and bios stolen system
memory) for INTEL_LMEM and INTEL_STOLEN memory region type.
PPGTT will program PTE_LM bit based on this value.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Francesco Balestrieri <francesco.balestrieri@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Venkata S Dhanalakota <venkata.s.dhanalakota@intel.com>
Cc: Neel Desai <neel.desai@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 11 ++++++++++-
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 1 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.h | 1 +
drivers/gpu/drm/i915/intel_region_lmem.c | 3 +++
6 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index e324328639d2..c719f6b5e785 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -217,7 +217,16 @@ i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
- return obj->ops == &i915_gem_lmem_obj_ops;
+ struct intel_memory_region *region = obj->mm.region;
+
+ return region && (region->is_devmem || region->type == INTEL_MEMORY_LOCAL);
+}
+
+bool i915_gem_object_is_devmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *region = obj->mm.region;
+
+ return region && region->is_devmem;
}
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index a24d94bc380f..a1b6a10050bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -21,6 +21,7 @@ i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
unsigned long n);
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+bool i915_gem_object_is_devmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 138546610f1f..a693278a9578 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -457,7 +457,7 @@ static int ggtt_bind_vma(struct i915_address_space *vm,
pte_flags = 0;
if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
pte_flags |= PTE_READ_ONLY;
- if (i915_gem_object_is_lmem(obj))
+ if (i915_gem_object_is_devmem(obj))
pte_flags |= PTE_LM;
vm->insert_entries(vm, vma, cache_level, pte_flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index e79c93b662c5..30d0c7281f79 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -177,7 +177,7 @@ int ppgtt_bind_vma(struct i915_address_space *vm,
pte_flags = 0;
if (i915_gem_object_is_readonly(vma->obj))
pte_flags |= PTE_READ_ONLY;
- if (i915_gem_object_is_lmem(vma->obj))
+ if (i915_gem_object_is_devmem(vma->obj))
pte_flags |= PTE_LM;
vm->insert_entries(vm, vma, cache_level, pte_flags);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 83241b47e923..334ef0e3a792 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -91,6 +91,7 @@ struct intel_memory_region {
u16 instance;
enum intel_region_id id;
char name[8];
+ bool is_devmem; /* true for device memory */
dma_addr_t remap_addr;
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 3a8997fd832d..46a2aa468054 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -70,6 +70,9 @@ setup_lmem(struct drm_i915_private *dev_priv)
(u64)mem->io_start);
DRM_INFO("Intel graphics LMEM size: %llx\n",
(u64)lmem_size);
+
+ /* this is real device memory */
+ mem->is_devmem = true;
}
return mem;
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 50/60] drm/i915: finish memory region support for stolen objects.
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (48 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 49/60] drm/i915: add i915_gem_object_is_devmem() function Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 51/60] drm/i915/lmem: support optional CPU clearing for special internal use Matthew Auld
` (14 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
Cc: Abdiel Janulgue, Lucas De Marchi, Chris P Wilson, Neel Desai,
Balestrieri
From: CQ Tang <cq.tang@intel.com>
Current stolen code has partial memory region support. This patch
finish the rest of code, so object memory are allocated from stolen
memory region.
However, three "global" variables are still kept for the display code
to access, "i915->dsm", "i915->dsm_reserved",
and "i915->stolen_usable_size",
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Balestrieri, Francesco <francesco.balestrieri@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Venkata S Dhanalakota <venkata.s.dhanalakota@intel.com>
Cc: Neel Desai <neel.desai@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 20 ++-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 173 +++++++++++----------
drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 7 +-
drivers/gpu/drm/i915/i915_drv.h | 6 -
drivers/gpu/drm/i915/intel_memory_region.h | 3 +
5 files changed, 108 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ef2eb14f6157..9d982b486003 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -429,6 +429,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
unsigned int size,
unsigned int fb_cpp)
{
+ struct intel_memory_region *mem = i915_stolen_region(dev_priv);
int compression_threshold = 1;
int ret;
u64 end;
@@ -450,7 +451,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
*/
/* Try to over-allocate to reduce reallocations and fragmentation. */
- ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
+ ret = i915_gem_stolen_insert_node_in_range(mem, node, size <<= 1,
4096, 0, end);
if (ret == 0)
return compression_threshold;
@@ -461,7 +462,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
(fb_cpp == 2 && compression_threshold == 2))
return 0;
- ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
+ ret = i915_gem_stolen_insert_node_in_range(mem, node, size >>= 1,
4096, 0, end);
if (ret && INTEL_GEN(dev_priv) <= 4) {
return 0;
@@ -476,6 +477,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
unsigned int size, unsigned int fb_cpp)
{
+ struct intel_memory_region *mem = i915_stolen_region(dev_priv);
struct intel_fbc *fbc = &dev_priv->fbc;
struct drm_mm_node *uninitialized_var(compressed_llb);
int ret;
@@ -505,7 +507,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
if (!compressed_llb)
goto err_fb;
- ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
+ ret = i915_gem_stolen_insert_node(mem, compressed_llb,
4096, 4096);
if (ret)
goto err_fb;
@@ -532,15 +534,16 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
err_fb:
kfree(compressed_llb);
- i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
+ i915_gem_stolen_remove_node(mem, &fbc->compressed_fb);
err_llb:
- if (drm_mm_initialized(&dev_priv->mm.stolen))
+ if (drm_mm_initialized(&mem->stolen))
drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
return -ENOSPC;
}
static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
{
+ struct intel_memory_region *mem = i915_stolen_region(dev_priv);
struct intel_fbc *fbc = &dev_priv->fbc;
if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
@@ -550,11 +553,11 @@ static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
return;
if (fbc->compressed_llb) {
- i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
+ i915_gem_stolen_remove_node(mem, fbc->compressed_llb);
kfree(fbc->compressed_llb);
}
- i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
+ i915_gem_stolen_remove_node(mem, &fbc->compressed_fb);
}
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
@@ -1425,12 +1428,13 @@ static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
void intel_fbc_init(struct drm_i915_private *dev_priv)
{
struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_memory_region *mem = i915_stolen_region(dev_priv);
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
mutex_init(&fbc->lock);
fbc->active = false;
- if (!drm_mm_initialized(&dev_priv->mm.stolen))
+ if (!mem || !drm_mm_initialized(&mem->stolen))
mkwrite_device_info(dev_priv)->display.has_fbc = false;
if (need_fbc_vtd_wa(dev_priv))
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 6704877fbda8..fee5ff1a1863 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -27,42 +27,42 @@
* for is a boon.
*/
-int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *i915,
+int i915_gem_stolen_insert_node_in_range(struct intel_memory_region *mem,
struct drm_mm_node *node, u64 size,
unsigned alignment, u64 start, u64 end)
{
int ret;
- if (!drm_mm_initialized(&i915->mm.stolen))
+ if (!drm_mm_initialized(&mem->stolen))
return -ENODEV;
/* WaSkipStolenMemoryFirstPage:bdw+ */
- if (INTEL_GEN(i915) >= 8 && start < 4096)
+ if (INTEL_GEN(mem->i915) >= 8 && start < 4096)
start = 4096;
- mutex_lock(&i915->mm.stolen_lock);
- ret = drm_mm_insert_node_in_range(&i915->mm.stolen, node,
+ mutex_lock(&mem->mm_lock);
+ ret = drm_mm_insert_node_in_range(&mem->stolen, node,
size, alignment, 0,
start, end, DRM_MM_INSERT_BEST);
- mutex_unlock(&i915->mm.stolen_lock);
+ mutex_unlock(&mem->mm_lock);
return ret;
}
-int i915_gem_stolen_insert_node(struct drm_i915_private *i915,
+int i915_gem_stolen_insert_node(struct intel_memory_region *mem,
struct drm_mm_node *node, u64 size,
unsigned alignment)
{
- return i915_gem_stolen_insert_node_in_range(i915, node, size,
+ return i915_gem_stolen_insert_node_in_range(mem, node, size,
alignment, 0, U64_MAX);
}
-void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
+void i915_gem_stolen_remove_node(struct intel_memory_region *mem,
struct drm_mm_node *node)
{
- mutex_lock(&i915->mm.stolen_lock);
+ mutex_lock(&mem->mm_lock);
drm_mm_remove_node(node);
- mutex_unlock(&i915->mm.stolen_lock);
+ mutex_unlock(&mem->mm_lock);
}
static int i915_adjust_stolen(struct drm_i915_private *i915,
@@ -157,12 +157,12 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
return 0;
}
-static void i915_gem_cleanup_stolen(struct drm_i915_private *i915)
+static void i915_gem_cleanup_stolen(struct intel_memory_region *mem)
{
- if (!drm_mm_initialized(&i915->mm.stolen))
+ if (!drm_mm_initialized(&mem->stolen))
return;
- drm_mm_takedown(&i915->mm.stolen);
+ drm_mm_takedown(&mem->stolen);
}
static void g4x_get_stolen_reserved(struct drm_i915_private *i915,
@@ -372,14 +372,13 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
}
}
-static int i915_gem_init_stolen(struct drm_i915_private *i915)
+static int i915_gem_init_stolen(struct intel_memory_region *mem)
{
+ struct drm_i915_private *i915 = mem->i915;
struct intel_uncore *uncore = &i915->uncore;
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
- mutex_init(&i915->mm.stolen_lock);
-
if (intel_vgpu_active(i915)) {
drm_notice(&i915->drm,
"%s, disabling use of stolen memory\n",
@@ -394,10 +393,10 @@ static int i915_gem_init_stolen(struct drm_i915_private *i915)
return 0;
}
- if (resource_size(&intel_graphics_stolen_res) == 0)
+ if (resource_size(&mem->region) == 0)
return 0;
- i915->dsm = intel_graphics_stolen_res;
+ i915->dsm = mem->region;
if (i915_adjust_stolen(i915, &i915->dsm))
return 0;
@@ -490,20 +489,20 @@ static int i915_gem_init_stolen(struct drm_i915_private *i915)
resource_size(&i915->dsm) - reserved_total;
/* Basic memrange allocator for stolen space. */
- drm_mm_init(&i915->mm.stolen, 0, i915->stolen_usable_size);
+ drm_mm_init(&mem->stolen, 0, i915->stolen_usable_size);
return 0;
}
static struct sg_table *
-i915_pages_create_for_stolen(struct drm_device *dev,
+i915_pages_create_for_stolen(struct drm_i915_gem_object *obj,
resource_size_t offset, resource_size_t size)
{
- struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_memory_region *mem = obj->mm.region;
struct sg_table *st;
struct scatterlist *sg;
- GEM_BUG_ON(range_overflows(offset, size, resource_size(&i915->dsm)));
+ GEM_BUG_ON(range_overflows(offset, size, resource_size(&mem->region)));
/* We hide that we have no struct page backing our stolen object
* by wrapping the contiguous physical allocation with a fake
@@ -523,7 +522,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
sg->offset = 0;
sg->length = size;
- sg_dma_address(sg) = (dma_addr_t)i915->dsm.start + offset;
+ sg_dma_address(sg) = (dma_addr_t)mem->region.start + offset;
sg_dma_len(sg) = size;
return st;
@@ -532,7 +531,7 @@ i915_pages_create_for_stolen(struct drm_device *dev,
static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
{
struct sg_table *pages =
- i915_pages_create_for_stolen(obj->base.dev,
+ i915_pages_create_for_stolen(obj,
obj->stolen->start,
obj->stolen->size);
if (IS_ERR(pages))
@@ -546,104 +545,102 @@ static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
- /* Should only be called from i915_gem_object_release_stolen() */
- sg_free_table(pages);
- kfree(pages);
-}
-
-static void
-i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
-{
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_memory_region *mem = obj->mm.region;
struct drm_mm_node *stolen = fetch_and_zero(&obj->stolen);
+ GEM_BUG_ON(!mem);
GEM_BUG_ON(!stolen);
- i915_gem_object_release_memory_region(obj);
-
- i915_gem_stolen_remove_node(i915, stolen);
+ i915_gem_stolen_remove_node(mem, stolen);
kfree(stolen);
+
+ sg_free_table(pages);
+ kfree(pages);
}
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
.name = "i915_gem_object_stolen",
.get_pages = i915_gem_object_get_pages_stolen,
.put_pages = i915_gem_object_put_pages_stolen,
- .release = i915_gem_object_release_stolen,
+ .release = i915_gem_object_release_memory_region,
};
static struct drm_i915_gem_object *
__i915_gem_object_create_stolen(struct intel_memory_region *mem,
- struct drm_mm_node *stolen)
+ resource_size_t size,
+ unsigned int flags)
{
static struct lock_class_key lock_class;
+ struct drm_i915_private *i915 = mem->i915;
struct drm_i915_gem_object *obj;
- unsigned int cache_level;
- int err = -ENOMEM;
+
+ if (!drm_mm_initialized(&mem->stolen))
+ return ERR_PTR(-ENODEV);
+
+ if (size == 0)
+ return ERR_PTR(-EINVAL);
obj = i915_gem_object_alloc();
if (!obj)
- goto err;
+ return ERR_PTR(-ENOMEM);
- drm_gem_private_object_init(&mem->i915->drm, &obj->base, stolen->size);
+ drm_gem_private_object_init(&i915->drm, &obj->base, size);
i915_gem_object_init(obj, &i915_gem_object_stolen_ops, &lock_class);
- obj->stolen = stolen;
obj->read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
- cache_level = HAS_LLC(mem->i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
- i915_gem_object_set_cache_coherency(obj, cache_level);
-
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto cleanup;
+ obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
- i915_gem_object_init_memory_region(obj, mem, 0);
+ i915_gem_object_init_memory_region(obj, mem, flags);
return obj;
-
-cleanup:
- i915_gem_object_free(obj);
-err:
- return ERR_PTR(err);
}
static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct intel_memory_region *mem,
- resource_size_t size,
- unsigned int flags)
+i915_gem_object_create_stolen_region(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
{
- struct drm_i915_private *i915 = mem->i915;
- struct drm_i915_gem_object *obj;
+ struct drm_i915_gem_object *obj, *err;
struct drm_mm_node *stolen;
int ret;
- if (!drm_mm_initialized(&i915->mm.stolen))
- return ERR_PTR(-ENODEV);
-
- if (size == 0)
- return ERR_PTR(-EINVAL);
-
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
if (!stolen)
return ERR_PTR(-ENOMEM);
- ret = i915_gem_stolen_insert_node(i915, stolen, size, 4096);
+ ret = i915_gem_stolen_insert_node(mem, stolen, size,
+ mem->min_page_size);
if (ret) {
- obj = ERR_PTR(ret);
+ err = ERR_PTR(ret);
goto err_free;
}
- obj = __i915_gem_object_create_stolen(mem, stolen);
- if (IS_ERR(obj))
+ obj = __i915_gem_object_create_stolen(mem, size,
+ I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = obj;
goto err_remove;
+ }
+
+ /* must set before pin pages */
+ obj->stolen = stolen;
+
+ /* if pinning fails, caller needs to free stolen */
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret) {
+ err = ERR_PTR(ret);
+ goto free_obj;
+ }
return obj;
+free_obj:
+ i915_gem_object_put(obj);
err_remove:
- i915_gem_stolen_remove_node(i915, stolen);
+ i915_gem_stolen_remove_node(mem, stolen);
err_free:
kfree(stolen);
- return obj;
+ return err;
}
struct intel_memory_region *i915_stolen_region(struct drm_i915_private *i915)
@@ -670,18 +667,18 @@ static int init_stolen(struct intel_memory_region *mem)
* Initialise stolen early so that we may reserve preallocated
* objects for the BIOS to KMS transition.
*/
- return i915_gem_init_stolen(mem->i915);
+ return i915_gem_init_stolen(mem);
}
static void release_stolen(struct intel_memory_region *mem)
{
- i915_gem_cleanup_stolen(mem->i915);
+ i915_gem_cleanup_stolen(mem);
}
static const struct intel_memory_region_ops i915_region_stolen_ops = {
.init = init_stolen,
.release = release_stolen,
- .create_object = _i915_gem_object_create_stolen,
+ .create_object = i915_gem_object_create_stolen_region,
};
struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private *i915)
@@ -703,9 +700,6 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *i915,
struct drm_mm_node *stolen;
int ret;
- if (!drm_mm_initialized(&i915->mm.stolen))
- return ERR_PTR(-ENODEV);
-
drm_dbg(&i915->drm,
"creating preallocated stolen object: stolen_offset=%pa, size=%pa\n",
&stolen_offset, &size);
@@ -722,23 +716,34 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *i915,
stolen->start = stolen_offset;
stolen->size = size;
- mutex_lock(&i915->mm.stolen_lock);
- ret = drm_mm_reserve_node(&i915->mm.stolen, stolen);
- mutex_unlock(&i915->mm.stolen_lock);
+ mutex_lock(&mem->mm_lock);
+ ret = drm_mm_reserve_node(&mem->stolen, stolen);
+ mutex_unlock(&mem->mm_lock);
if (ret) {
obj = ERR_PTR(ret);
goto err_free;
}
- obj = __i915_gem_object_create_stolen(mem, stolen);
+ obj = __i915_gem_object_create_stolen(mem, size,
+ I915_BO_ALLOC_CONTIGUOUS);
if (IS_ERR(obj))
goto err_stolen;
+ /* must set before pin pages */
+ obj->stolen = stolen;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret) {
+ obj = ERR_PTR(ret);
+ i915_gem_object_put(obj);
+ goto err_stolen;
+ }
+
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
return obj;
err_stolen:
- i915_gem_stolen_remove_node(i915, stolen);
+ i915_gem_stolen_remove_node(mem, stolen);
err_free:
kfree(stolen);
return obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
index a19110a1b75a..5f266f6524b7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.h
@@ -11,15 +11,16 @@
struct drm_i915_private;
struct drm_mm_node;
struct drm_i915_gem_object;
+struct intel_memory_region;
-int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
+int i915_gem_stolen_insert_node(struct intel_memory_region *mem,
struct drm_mm_node *node, u64 size,
unsigned alignment);
-int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
+int i915_gem_stolen_insert_node_in_range(struct intel_memory_region *mem,
struct drm_mm_node *node, u64 size,
unsigned alignment, u64 start,
u64 end);
-void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
+void i915_gem_stolen_remove_node(struct intel_memory_region *mem,
struct drm_mm_node *node);
struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7f668a49b03d..6755658edf4e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -560,12 +560,6 @@ struct intel_l3_parity {
};
struct i915_gem_mm {
- /** Memory allocator for GTT stolen memory */
- struct drm_mm stolen;
- /** Protects the usage of the GTT stolen memory allocator. This is
- * always the inner lock when overlapping with struct_mutex. */
- struct mutex stolen_lock;
-
/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
spinlock_t obj_lock;
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 334ef0e3a792..a08cbae18979 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -6,6 +6,7 @@
#ifndef __INTEL_MEMORY_REGION_H__
#define __INTEL_MEMORY_REGION_H__
+#include <drm/drm_mm.h>
#include <linux/kref.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
@@ -77,6 +78,8 @@ struct intel_memory_region {
/* For fake LMEM */
struct drm_mm_node fake_mappable;
+ struct drm_mm stolen;
+
struct i915_buddy_mm mm;
struct mutex mm_lock;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 51/60] drm/i915/lmem: support optional CPU clearing for special internal use
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (49 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 50/60] drm/i915: finish memory region support for stolen objects Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 52/60] drm/i915/guc: put all guc objects in lmem when available Matthew Auld
` (13 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
For some internal device local-memory objects it would be useful to have
an option to CPU clear the pages upon gathering the backing store. Note
that this might be before the blitter is useable, which is the case for
some internal GuC objects.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c | 20 +++++
.../drm/i915/selftests/intel_memory_region.c | 83 +++++++++++++++++++
3 files changed, 108 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 848ac102b788..0ae33c7a9239 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -148,9 +148,11 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | I915_BO_ALLOC_VOLATILE)
-#define I915_BO_READONLY BIT(2)
-
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
+ I915_BO_ALLOC_VOLATILE | \
+ I915_BO_ALLOC_CPU_CLEAR)
+#define I915_BO_READONLY BIT(3)
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index cc8116e63808..88860169d340 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -95,6 +95,26 @@ i915_gem_object_get_pages_buddy(struct drm_i915_gem_object *obj)
sg_mark_end(sg);
i915_sg_trim(st);
+ /* Intended for kernel internal use only */
+ if (obj->flags & I915_BO_ALLOC_CPU_CLEAR) {
+ struct scatterlist *sg;
+ unsigned long i;
+
+ for_each_sg(st->sgl, sg, st->nents, i) {
+ unsigned int length;
+ void __iomem *vaddr;
+ dma_addr_t daddr;
+
+ daddr = sg_dma_address(sg);
+ daddr -= mem->region.start;
+ length = sg_dma_len(sg);
+
+ vaddr = io_mapping_map_wc(&mem->iomap, daddr, length);
+ memset64(vaddr, 0, length / sizeof(u64));
+ io_mapping_unmap(vaddr);
+ }
+ }
+
__i915_gem_object_set_pages(obj, st, sg_page_sizes);
return 0;
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 6e80d99048e4..d10f5b52b677 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -396,6 +396,88 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_create_cleared_cpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ u32 size, val, i;
+ int err;
+
+ i915_gem_drain_freed_objects(i915);
+
+ size = max_t(u32, PAGE_SIZE, i915_prandom_u32_max_state(SZ_32M, &prng));
+ size = round_up(size, PAGE_SIZE);
+ i = 0;
+
+ do {
+ struct drm_i915_gem_object *obj;
+ void __iomem *vaddr;
+ unsigned int flags;
+ unsigned long n;
+ u32 dword;
+
+ /*
+ * Alternate between cleared and uncleared allocations, while
+ * also dirtying the pages each time to check that they either
+ * remain dirty or are indeed cleared. Allocations should be
+ * deterministic.
+ */
+
+ flags = I915_BO_ALLOC_CPU_CLEAR;
+ if (i & 1)
+ flags = 0;
+ else
+ val = 0;
+
+ obj = i915_gem_object_create_lmem(i915, size, flags);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ dword = i915_prandom_u32_max_state(PAGE_SIZE / sizeof(u32),
+ &prng);
+
+ err = igt_cpu_check(obj, dword, val);
+ if (err) {
+ pr_err("%s failed with size=%u, flags=%u\n",
+ __func__, size, flags);
+ goto out_unpin;
+ }
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto out_unpin;
+ }
+
+ val = prandom_u32_state(&prng);
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ memset32(vaddr + n * PAGE_SIZE, val,
+ PAGE_SIZE / sizeof(u32));
+ }
+
+ i915_gem_object_unpin_map(obj);
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err)
+ break;
+ ++i;
+ } while (!__igt_timeout(end_time, NULL));
+
+ pr_info("%s completed (%u) iterations\n", __func__, i);
+
+ return err;
+}
+
static int igt_lmem_write_gpu(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -799,6 +881,7 @@ int intel_memory_region_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_lmem_create),
+ SUBTEST(igt_lmem_create_cleared_cpu),
SUBTEST(igt_lmem_write_cpu),
SUBTEST(igt_lmem_write_gpu),
};
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 52/60] drm/i915/guc: put all guc objects in lmem when available
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (50 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 51/60] drm/i915/lmem: support optional CPU clearing for special internal use Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory Matthew Auld
` (12 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
The firmware binary has to be loaded from lmem and the recommendation is
to put all other objects in there as well. Note that we don't fall back
to system memory if the allocation in lmem fails because all objects are
allocated during driver load and if we have issues with lmem at that point
something is seriously wrong with the system, so no point in trying to
handle it.
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> #v1
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 41 +++++++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 +++++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 ++++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 ++++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 ++++++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 35 ++++++++++++++++---
6 files changed, 107 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index c719f6b5e785..423662cec5da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -215,6 +215,21 @@ i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
}
+void __iomem *
+i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+ offset -= obj->mm.region->region.start;
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
struct intel_memory_region *region = obj->mm.region;
@@ -229,6 +244,32 @@ bool i915_gem_object_is_devmem(struct drm_i915_gem_object *obj)
return region && region->is_devmem;
}
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem_from_data(struct drm_i915_private *i915,
+ const void *data, size_t size)
+{
+ struct drm_i915_gem_object *obj;
+ void *map;
+
+ obj = i915_gem_object_create_lmem(i915,
+ round_up(size, PAGE_SIZE),
+ I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj))
+ return obj;
+
+ map = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(map)) {
+ i915_gem_object_put(obj);
+ return map;
+ }
+
+ memcpy(map, data, size);
+
+ i915_gem_object_unpin_map(obj);
+
+ return obj;
+}
+
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index a1b6a10050bf..e11e0545e39c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -14,6 +14,10 @@ struct intel_memory_region;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *
+i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size);
void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
unsigned long n);
void __iomem *
@@ -23,6 +27,10 @@ i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
bool i915_gem_object_is_devmem(struct drm_i915_gem_object *obj);
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem_from_data(struct drm_i915_private *i915,
+ const void *data, size_t size);
+
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 861657897c0f..9a43cfbfc26d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -3,6 +3,7 @@
* Copyright © 2014-2019 Intel Corporation
*/
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm_irq.h"
@@ -668,7 +669,13 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
u64 flags;
int ret;
- obj = i915_gem_object_create_shmem(gt->i915, size);
+ if (HAS_LMEM(gt->i915))
+ obj = i915_gem_object_create_lmem(gt->i915, size,
+ I915_BO_ALLOC_CPU_CLEAR |
+ I915_BO_ALLOC_CONTIGUOUS);
+ else
+ obj = i915_gem_object_create_shmem(gt->i915, size);
+
if (IS_ERR(obj))
return ERR_CAST(obj);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index d4a87f4c9421..93a1bdb3d81b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -41,7 +41,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
}
/* Copy RSA signature from the fw image to HW for verification */
-static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
+static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
struct intel_uncore *uncore)
{
u32 rsa[UOS_RSA_SCRATCH_COUNT];
@@ -49,10 +49,13 @@ static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
int i;
copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
- GEM_BUG_ON(copied < sizeof(rsa));
+ if (copied < sizeof(rsa))
+ return -ENOMEM;
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
+
+ return 0;
}
/*
@@ -129,7 +132,9 @@ int intel_guc_fw_upload(struct intel_guc *guc)
* by the DMA engine in one operation, whereas the RSA signature is
* loaded via MMIO.
*/
- guc_xfer_rsa(&guc->fw, uncore);
+ ret = guc_xfer_rsa(&guc->fw, uncore);
+ if (ret)
+ goto out;
/*
* Current uCode expects the code to be loaded at 8k; locations below
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 65eeb44b397d..359a0f947672 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -85,17 +85,25 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
i915_vma_unpin_and_release(&vma, 0);
- return PTR_ERR(vaddr);
+ err = PTR_ERR(vaddr);
+ goto unpin_out;
}
copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size);
- GEM_BUG_ON(copied < huc->fw.rsa_size);
-
i915_gem_object_unpin_map(vma->obj);
+ if (copied < huc->fw.rsa_size) {
+ err = -ENOMEM;
+ goto unpin_out;
+ }
+
huc->rsa_data = vma;
return 0;
+
+unpin_out:
+ i915_vma_unpin_and_release(&vma, 0);
+ return err;
}
static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 59b27aba15c6..2a49498fbdcb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -7,6 +7,7 @@
#include <linux/firmware.h>
#include <drm/drm_print.h>
+#include "gem/i915_gem_lmem.h"
#include "intel_uc_fw.h"
#include "intel_uc_fw_abi.h"
#include "i915_drv.h"
@@ -371,7 +372,11 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
}
}
- obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
+ if (HAS_LMEM(i915))
+ obj = i915_gem_object_create_lmem_from_data(i915, fw->data, fw->size);
+ else
+ obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
+
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
goto fail;
@@ -420,14 +425,19 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
.pages = obj->mm.pages,
.vm = &ggtt->vm,
};
+ u32 pte_flags = 0;
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size);
/* uc_fw->obj cache domains were not controlled across suspend */
- drm_clflush_sg(dummy.pages);
+ if (i915_gem_object_has_struct_page(obj))
+ drm_clflush_sg(dummy.pages);
+
+ if (i915_gem_object_is_lmem(obj))
+ pte_flags |= PTE_LM;
- ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0);
+ ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, pte_flags);
}
static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)
@@ -592,7 +602,24 @@ size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len)
GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw));
- return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset);
+ if (i915_gem_object_is_lmem(uc_fw->obj)) {
+ unsigned long page_idx = offset >> PAGE_SHIFT;
+ unsigned int page_off = offset_in_page(offset);
+ void __iomem *vaddr;
+
+ vaddr = i915_gem_object_lmem_io_map(uc_fw->obj,
+ page_idx,
+ page_off + size);
+ if (!vaddr)
+ return 0;
+
+ memcpy(dst, vaddr + page_off, size);
+ io_mapping_unmap(vaddr);
+ return size;
+ } else {
+ return sg_pcopy_to_buffer(pages->sgl, pages->nents,
+ dst, size, offset);
+ }
}
/**
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (51 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 52/60] drm/i915/guc: put all guc objects in lmem when available Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-13 4:48 ` Dave Airlie
2020-07-10 11:57 ` [Intel-gfx] [RFC 54/60] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
` (11 subsequent siblings)
64 siblings, 1 reply; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
Cc: Abdiel Janulgue, Lucas De Marchi, Chris P Wilson, Neel Desai,
Balestrieri
From: CQ Tang <cq.tang@intel.com>
Add "REGION_STOLEN" device info to dg1, create stolen memory
region from upper portion of local device memory, starting
from DSMBASE.
The memory region is marked with "is_devmem=true".
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Balestrieri, Francesco <francesco.balestrieri@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Venkata S Dhanalakota <venkata.s.dhanalakota@intel.com>
Cc: Neel Desai <neel.desai@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: CQ Tang <cq.tang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 12 ++---
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 7 +++
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 56 +++++++++++++++++++++-
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_memory_region.c | 5 ++
drivers/gpu/drm/i915/intel_memory_region.h | 2 +-
7 files changed, 75 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 423662cec5da..456b304b244e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -8,8 +8,8 @@
#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
-static int lmem_pread(struct drm_i915_gem_object *obj,
- const struct drm_i915_gem_pread *arg)
+int i915_gem_object_lmem_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *arg)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct intel_runtime_pm *rpm = &i915->runtime_pm;
@@ -94,8 +94,8 @@ static int lmem_pread(struct drm_i915_gem_object *obj,
return ret;
}
-static int lmem_pwrite(struct drm_i915_gem_object *obj,
- const struct drm_i915_gem_pwrite *arg)
+int i915_gem_object_lmem_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *arg)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct intel_runtime_pm *rpm = &i915->runtime_pm;
@@ -187,8 +187,8 @@ const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
- .pread = lmem_pread,
- .pwrite = lmem_pwrite,
+ .pread = i915_gem_object_lmem_pread,
+ .pwrite = i915_gem_object_lmem_pwrite,
};
void __iomem *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index e11e0545e39c..c59aa6c014c7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -11,9 +11,16 @@
struct drm_i915_private;
struct drm_i915_gem_object;
struct intel_memory_region;
+struct drm_i915_gem_pread;
+struct drm_i915_gem_pwrite;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+int i915_gem_object_lmem_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *args);
+int i915_gem_object_lmem_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *args);
+
void __iomem *
i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
unsigned long n,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index fee5ff1a1863..0bcfe4464fa1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -10,6 +10,7 @@
#include <drm/drm_mm.h>
#include <drm/i915_drm.h>
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
@@ -119,6 +120,14 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
}
}
+ /*
+ * With device local memory, we don't need to check the address range,
+ * this is device memory physical address, could overlap with system
+ * memory.
+ */
+ if (HAS_LMEM(i915))
+ return 0;
+
/*
* Verify that nothing else uses this physical address. Stolen
* memory should be reserved by the BIOS and hidden from the
@@ -558,7 +567,7 @@ static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj,
kfree(pages);
}
-static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
+static struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
.name = "i915_gem_object_stolen",
.get_pages = i915_gem_object_get_pages_stolen,
.put_pages = i915_gem_object_put_pages_stolen,
@@ -661,7 +670,19 @@ i915_gem_object_create_stolen(struct drm_i915_private *i915,
static int init_stolen(struct intel_memory_region *mem)
{
- intel_memory_region_set_name(mem, "stolen");
+ if (mem->type == INTEL_MEMORY_STOLEN_SYSTEM)
+ intel_memory_region_set_name(mem, "stolen-system");
+ else
+ intel_memory_region_set_name(mem, "stolen-local");
+
+ if (HAS_LMEM(mem->i915)) {
+ i915_gem_object_stolen_ops.pread = i915_gem_object_lmem_pread;
+ i915_gem_object_stolen_ops.pwrite = i915_gem_object_lmem_pwrite;
+ if (!io_mapping_init_wc(&mem->iomap,
+ mem->io_start,
+ resource_size(&mem->region)))
+ return -EIO;
+ }
/*
* Initialise stolen early so that we may reserve preallocated
@@ -681,8 +702,39 @@ static const struct intel_memory_region_ops i915_region_stolen_ops = {
.create_object = i915_gem_object_create_stolen_region,
};
+static
+struct intel_memory_region *setup_lmem_stolen(struct drm_i915_private *i915)
+{
+ struct intel_uncore *uncore = &i915->uncore;
+ struct pci_dev *pdev = i915->drm.pdev;
+ struct intel_memory_region *mem;
+ resource_size_t io_start;
+ resource_size_t lmem_size;
+ u64 lmem_base;
+
+ lmem_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
+ lmem_size = pci_resource_len(pdev, 2) - lmem_base;
+ io_start = pci_resource_start(pdev, 2) + lmem_base;
+
+ mem = intel_memory_region_create(i915, lmem_base, lmem_size,
+ I915_GTT_PAGE_SIZE_4K, io_start,
+ &i915_region_stolen_ops);
+ if (!IS_ERR(mem)) {
+ DRM_INFO("Intel graphics stolen LMEM: %pR\n", &mem->region);
+ DRM_INFO("Intel graphics stolen LMEM IO start: %llx\n",
+ (u64)mem->io_start);
+ /* this is real device memory */
+ mem->is_devmem = true;
+ }
+
+ return mem;
+}
+
struct intel_memory_region *i915_gem_stolen_setup(struct drm_i915_private *i915)
{
+ if (HAS_LMEM(i915))
+ return setup_lmem_stolen(i915);
+
return intel_memory_region_create(i915,
intel_graphics_stolen_res.start,
resource_size(&intel_graphics_stolen_res),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e132fdffa432..fbb7ac96d881 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -897,7 +897,7 @@ static const struct intel_device_info rkl_info = {
#define GEN12_DGFX_FEATURES \
GEN12_FEATURES, \
- .memory_regions = REGION_SMEM | REGION_LMEM, \
+ .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
.has_master_unit_irq = 1, \
.has_llc = 0, \
.has_snoop = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e67c4ee09c2..7ee322728a65 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12039,6 +12039,7 @@ enum skl_power_gate {
#define LMEM_ENABLE (1 << 31)
#define GEN12_GSMBASE _MMIO(0x108100)
+#define GEN12_DSMBASE _MMIO(0x1080C0)
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index d564b596efda..905cdfa6e3e2 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -19,6 +19,10 @@ const struct intel_memory_region_info intel_region_map[] = {
.class = INTEL_MEMORY_STOLEN_SYSTEM,
.instance = 0,
},
+ [INTEL_REGION_STOLEN_LMEM] = {
+ .class = INTEL_MEMORY_STOLEN_LOCAL,
+ .instance = 0,
+ },
};
struct intel_memory_region *
@@ -305,6 +309,7 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
case INTEL_MEMORY_SYSTEM:
mem = i915_gem_shmem_setup(i915);
break;
+ case INTEL_MEMORY_STOLEN_LOCAL: /* fallthrough */
case INTEL_MEMORY_STOLEN_SYSTEM:
mem = i915_gem_stolen_setup(i915);
break;
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index a08cbae18979..8f9c943a16af 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -93,7 +93,7 @@ struct intel_memory_region {
u16 type;
u16 instance;
enum intel_region_id id;
- char name[8];
+ char name[16];
bool is_devmem; /* true for device memory */
dma_addr_t remap_addr;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-10 11:57 ` [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory Matthew Auld
@ 2020-07-13 4:48 ` Dave Airlie
2020-07-14 15:01 ` Matthew Auld
0 siblings, 1 reply; 88+ messages in thread
From: Dave Airlie @ 2020-07-13 4:48 UTC (permalink / raw)
To: Matthew Auld
Cc: Abdiel Janulgue, Intel Graphics Development, Lucas De Marchi,
Chris P Wilson, Neel Desai
On Fri, 10 Jul 2020 at 22:01, Matthew Auld <matthew.auld@intel.com> wrote:
>
> From: CQ Tang <cq.tang@intel.com>
>
> Add "REGION_STOLEN" device info to dg1, create stolen memory
> region from upper portion of local device memory, starting
> from DSMBASE.
>
> The memory region is marked with "is_devmem=true".
So is stolen fake on LMEM devices? The concept of stolen doesn't seem
to make much sense with VRAM, so please enlighten me.
Dave.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-13 4:48 ` Dave Airlie
@ 2020-07-14 15:01 ` Matthew Auld
2020-07-14 16:57 ` Tang, CQ
2020-07-14 17:39 ` Ville Syrjälä
0 siblings, 2 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-14 15:01 UTC (permalink / raw)
To: Dave Airlie
Cc: Abdiel Janulgue, Intel Graphics Development, Lucas De Marchi,
Chris P Wilson, Neel Desai
On 13/07/2020 05:48, Dave Airlie wrote:
> On Fri, 10 Jul 2020 at 22:01, Matthew Auld <matthew.auld@intel.com> wrote:
>>
>> From: CQ Tang <cq.tang@intel.com>
>>
>> Add "REGION_STOLEN" device info to dg1, create stolen memory
>> region from upper portion of local device memory, starting
>> from DSMBASE.
>>
>> The memory region is marked with "is_devmem=true".
>
> So is stolen fake on LMEM devices? The concept of stolen doesn't seem
> to make much sense with VRAM, so please enlighten me.
CQ, do we actually need an explicit stolen LMEM region? The idea of
having a DSM like stolen region for LMEM does sound strange(outside of
the usual reserved portions which are for HW use etc), since the driver
has complete control over LMEM. Is it just a convenience thing to keep
things working as-is for fbc, initial fb, etc. or is there more to it?
There is buddy_alloc_range() for LMEM which we could potentially use to
wrap an object around for things like the initial fb or similar.
>
> Dave.
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-14 15:01 ` Matthew Auld
@ 2020-07-14 16:57 ` Tang, CQ
2020-07-14 19:26 ` Dave Airlie
2020-07-14 17:39 ` Ville Syrjälä
1 sibling, 1 reply; 88+ messages in thread
From: Tang, CQ @ 2020-07-14 16:57 UTC (permalink / raw)
To: Auld, Matthew, Dave Airlie
Cc: Abdiel Janulgue, Intel Graphics Development, De Marchi, Lucas,
Wilson, Chris P, Neel Desai
> -----Original Message-----
> From: Auld, Matthew <matthew.auld@intel.com>
> Sent: Tuesday, July 14, 2020 8:02 AM
> To: Dave Airlie <airlied@gmail.com>
> Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Tang, CQ
> <cq.tang@intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>;
> Abdiel Janulgue <abdiel.janulgue@linux.intel.com>; Wilson, Chris P
> <chris.p.wilson@intel.com>; Balestrieri, Francesco
> <francesco.balestrieri@intel.com>; Vishwanathapura, Niranjana
> <niranjana.vishwanathapura@intel.com>; Dhanalakota, Venkata S
> <venkata.s.dhanalakota@intel.com>; Neel Desai <neel.desai@intel.com>;
> Brost, Matthew <matthew.brost@intel.com>; Dutt, Sudeep
> <sudeep.dutt@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: Re: [RFC 53/60] drm/i915: Create stolen memory region from local
> memory
>
> On 13/07/2020 05:48, Dave Airlie wrote:
> > On Fri, 10 Jul 2020 at 22:01, Matthew Auld <matthew.auld@intel.com>
> wrote:
> >>
> >> From: CQ Tang <cq.tang@intel.com>
> >>
> >> Add "REGION_STOLEN" device info to dg1, create stolen memory region
> >> from upper portion of local device memory, starting from DSMBASE.
> >>
> >> The memory region is marked with "is_devmem=true".
> >
> > So is stolen fake on LMEM devices? The concept of stolen doesn't seem
> > to make much sense with VRAM, so please enlighten me.
>
> CQ, do we actually need an explicit stolen LMEM region? The idea of having a
> DSM like stolen region for LMEM does sound strange(outside of the usual
> reserved portions which are for HW use etc), since the driver has complete
> control over LMEM. Is it just a convenience thing to keep things working as-is
> for fbc, initial fb, etc. or is there more to it?
> There is buddy_alloc_range() for LMEM which we could potentially use to
> wrap an object around for things like the initial fb or similar.
This is a natural extension from IGT stolen memory region into DGT, we want to allocate objects from stolen area. In DGT, we have one stolen area per tile so we create one region in each of these area. Using memory region is easier to manage objects allocation and free. Other than fbc and rc6, we have gt/ring allocate stolen memory objects when without LMEM, so only apply to IGT case:
display/intel_display.c: obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
display/intel_fbdev.c: obj = i915_gem_object_create_stolen(dev_priv, size);
display/intel_overlay.c: obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
intel_rc6.c: pctx = i915_gem_object_create_stolen_for_preallocated(i915,
intel_rc6.c: pctx = i915_gem_object_create_stolen(i915, pctx_size);
intel_ring.c: obj = intel_gt_object_create_stolen(ggtt->vm.gt, size);
intel_gt.c: obj = intel_gt_object_create_stolen(gt, size);
For some reason, we don't use buddy allocator to manage the stolen memory, instead, we use drm_mm_node allocator directly, we have one-to-one mapping between drm_mm address space to dma address of the stolen memory. We also use contiguous allocation where an object always get a single contiguous block of pages.
So fundamentally, we want to use the same code to work on both IGT stolen memory and DGT stolen memory.
--CQ
>
> >
> > Dave.
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-14 16:57 ` Tang, CQ
@ 2020-07-14 19:26 ` Dave Airlie
2020-08-07 9:38 ` Joonas Lahtinen
0 siblings, 1 reply; 88+ messages in thread
From: Dave Airlie @ 2020-07-14 19:26 UTC (permalink / raw)
To: Tang, CQ
Cc: Abdiel Janulgue, Intel Graphics Development, De Marchi, Lucas,
Wilson, Chris P, Auld, Matthew, Neel Desai
On Wed, 15 Jul 2020 at 02:57, Tang, CQ <cq.tang@intel.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Auld, Matthew <matthew.auld@intel.com>
> > Sent: Tuesday, July 14, 2020 8:02 AM
> > To: Dave Airlie <airlied@gmail.com>
> > Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Tang, CQ
> > <cq.tang@intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>;
> > Abdiel Janulgue <abdiel.janulgue@linux.intel.com>; Wilson, Chris P
> > <chris.p.wilson@intel.com>; Balestrieri, Francesco
> > <francesco.balestrieri@intel.com>; Vishwanathapura, Niranjana
> > <niranjana.vishwanathapura@intel.com>; Dhanalakota, Venkata S
> > <venkata.s.dhanalakota@intel.com>; Neel Desai <neel.desai@intel.com>;
> > Brost, Matthew <matthew.brost@intel.com>; Dutt, Sudeep
> > <sudeep.dutt@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> > Subject: Re: [RFC 53/60] drm/i915: Create stolen memory region from local
> > memory
> >
> > On 13/07/2020 05:48, Dave Airlie wrote:
> > > On Fri, 10 Jul 2020 at 22:01, Matthew Auld <matthew.auld@intel.com>
> > wrote:
> > >>
> > >> From: CQ Tang <cq.tang@intel.com>
> > >>
> > >> Add "REGION_STOLEN" device info to dg1, create stolen memory region
> > >> from upper portion of local device memory, starting from DSMBASE.
> > >>
> > >> The memory region is marked with "is_devmem=true".
> > >
> > > So is stolen fake on LMEM devices? The concept of stolen doesn't seem
> > > to make much sense with VRAM, so please enlighten me.
> >
> > CQ, do we actually need an explicit stolen LMEM region? The idea of having a
> > DSM like stolen region for LMEM does sound strange(outside of the usual
> > reserved portions which are for HW use etc), since the driver has complete
> > control over LMEM. Is it just a convenience thing to keep things working as-is
> > for fbc, initial fb, etc. or is there more to it?
> > There is buddy_alloc_range() for LMEM which we could potentially use to
> > wrap an object around for things like the initial fb or similar.
>
> This is a natural extension from IGT stolen memory region into DGT, we want to allocate objects from stolen area. In DGT, we have one stolen area per tile so we create one region in each of these area. Using memory region is easier to manage objects allocation and free. Other than fbc and rc6, we have gt/ring allocate stolen memory objects when without LMEM, so only apply to IGT case:
>
> display/intel_display.c: obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
> display/intel_fbdev.c: obj = i915_gem_object_create_stolen(dev_priv, size);
> display/intel_overlay.c: obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
> intel_rc6.c: pctx = i915_gem_object_create_stolen_for_preallocated(i915,
> intel_rc6.c: pctx = i915_gem_object_create_stolen(i915, pctx_size);
>
> intel_ring.c: obj = intel_gt_object_create_stolen(ggtt->vm.gt, size);
> intel_gt.c: obj = intel_gt_object_create_stolen(gt, size);
>
> For some reason, we don't use buddy allocator to manage the stolen memory, instead, we use drm_mm_node allocator directly, we have one-to-one mapping between drm_mm address space to dma address of the stolen memory. We also use contiguous allocation where an object always get a single contiguous block of pages.
>
> So fundamentally, we want to use the same code to work on both IGT stolen memory and DGT stolen memory.
If this is fundamentally a software construct then it's horrible, if
the HW has a stolen base like Ville said, and it needs to be in a
chunk of VRAM, how do you go about sizing that, and carving it out
from the user?
I don't think wanting to share the same codepaths here is an
acceptable answer, just fix the code to handle LMEM vs stolen, but if
there are hw reasons on why this is required it would be good to
enumerate exactly what they are and document them.
Dave.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-14 19:26 ` Dave Airlie
@ 2020-08-07 9:38 ` Joonas Lahtinen
2020-08-07 16:24 ` Tang, CQ
0 siblings, 1 reply; 88+ messages in thread
From: Joonas Lahtinen @ 2020-08-07 9:38 UTC (permalink / raw)
To: Tang, CQ, Dave Airlie
Cc: Abdiel Janulgue, Intel Graphics Development, De Marchi, Lucas,
Wilson, Chris P, Auld, Matthew, Neel Desai
Quoting Dave Airlie (2020-07-14 22:26:16)
> On Wed, 15 Jul 2020 at 02:57, Tang, CQ <cq.tang@intel.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Auld, Matthew <matthew.auld@intel.com>
> > > Sent: Tuesday, July 14, 2020 8:02 AM
> > > To: Dave Airlie <airlied@gmail.com>
> > > Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Tang, CQ
> > > <cq.tang@intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>;
> > > Abdiel Janulgue <abdiel.janulgue@linux.intel.com>; Wilson, Chris P
> > > <chris.p.wilson@intel.com>; Balestrieri, Francesco
> > > <francesco.balestrieri@intel.com>; Vishwanathapura, Niranjana
> > > <niranjana.vishwanathapura@intel.com>; Dhanalakota, Venkata S
> > > <venkata.s.dhanalakota@intel.com>; Neel Desai <neel.desai@intel.com>;
> > > Brost, Matthew <matthew.brost@intel.com>; Dutt, Sudeep
> > > <sudeep.dutt@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> > > Subject: Re: [RFC 53/60] drm/i915: Create stolen memory region from local
> > > memory
> > >
> > > On 13/07/2020 05:48, Dave Airlie wrote:
> > > > On Fri, 10 Jul 2020 at 22:01, Matthew Auld <matthew.auld@intel.com>
> > > wrote:
> > > >>
> > > >> From: CQ Tang <cq.tang@intel.com>
> > > >>
> > > >> Add "REGION_STOLEN" device info to dg1, create stolen memory region
> > > >> from upper portion of local device memory, starting from DSMBASE.
> > > >>
> > > >> The memory region is marked with "is_devmem=true".
> > > >
> > > > So is stolen fake on LMEM devices? The concept of stolen doesn't seem
> > > > to make much sense with VRAM, so please enlighten me.
> > >
> > > CQ, do we actually need an explicit stolen LMEM region? The idea of having a
> > > DSM like stolen region for LMEM does sound strange(outside of the usual
> > > reserved portions which are for HW use etc), since the driver has complete
> > > control over LMEM. Is it just a convenience thing to keep things working as-is
> > > for fbc, initial fb, etc. or is there more to it?
> > > There is buddy_alloc_range() for LMEM which we could potentially use to
> > > wrap an object around for things like the initial fb or similar.
> >
> > This is a natural extension from IGT stolen memory region into DGT, we want to allocate objects from stolen area. In DGT, we have one stolen area per tile so we create one region in each of these area. Using memory region is easier to manage objects allocation and free. Other than fbc and rc6, we have gt/ring allocate stolen memory objects when without LMEM, so only apply to IGT case:
> >
> > display/intel_display.c: obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
> > display/intel_fbdev.c: obj = i915_gem_object_create_stolen(dev_priv, size);
> > display/intel_overlay.c: obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
> > intel_rc6.c: pctx = i915_gem_object_create_stolen_for_preallocated(i915,
> > intel_rc6.c: pctx = i915_gem_object_create_stolen(i915, pctx_size);
> >
> > intel_ring.c: obj = intel_gt_object_create_stolen(ggtt->vm.gt, size);
> > intel_gt.c: obj = intel_gt_object_create_stolen(gt, size);
> >
> > For some reason, we don't use buddy allocator to manage the stolen memory, instead, we use drm_mm_node allocator directly, we have one-to-one mapping between drm_mm address space to dma address of the stolen memory. We also use contiguous allocation where an object always get a single contiguous block of pages.
> >
> > So fundamentally, we want to use the same code to work on both IGT stolen memory and DGT stolen memory.
>
> If this is fundamentally a software construct then it's horrible, if
> the HW has a stolen base like Ville said, and it needs to be in a
> chunk of VRAM, how do you go about sizing that, and carving it out
> from the user?
>
> I don't think wanting to share the same codepaths here is an
> acceptable answer, just fix the code to handle LMEM vs stolen, but if
> there are hw reasons on why this is required it would be good to
> enumerate exactly what they are and document them.
The boot firmware does configure the stolen region, so it's not fake.
But there's no need to expose the stolen memory to userspace, so these
patches will be dropped.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-08-07 9:38 ` Joonas Lahtinen
@ 2020-08-07 16:24 ` Tang, CQ
0 siblings, 0 replies; 88+ messages in thread
From: Tang, CQ @ 2020-08-07 16:24 UTC (permalink / raw)
To: Joonas Lahtinen, Dave Airlie
Cc: Abdiel Janulgue, Intel Graphics Development, De Marchi, Lucas,
Wilson, Chris P, Auld, Matthew, Neel Desai
> -----Original Message-----
> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Sent: Friday, August 7, 2020 2:39 AM
> To: Tang, CQ <cq.tang@intel.com>; Dave Airlie <airlied@gmail.com>
> Cc: Auld, Matthew <matthew.auld@intel.com>; Intel Graphics Development
> <intel-gfx@lists.freedesktop.org>; Abdiel Janulgue
> <abdiel.janulgue@linux.intel.com>; Wilson, Chris P
> <chris.p.wilson@intel.com>; Balestrieri, Francesco
> <francesco.balestrieri@intel.com>; Vishwanathapura, Niranjana
> <niranjana.vishwanathapura@intel.com>; Dhanalakota, Venkata S
> <venkata.s.dhanalakota@intel.com>; Neel Desai <neel.desai@intel.com>;
> Brost, Matthew <matthew.brost@intel.com>; Dutt, Sudeep
> <sudeep.dutt@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: Re: [RFC 53/60] drm/i915: Create stolen memory region from local
> memory
>
> Quoting Dave Airlie (2020-07-14 22:26:16)
> > On Wed, 15 Jul 2020 at 02:57, Tang, CQ <cq.tang@intel.com> wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Auld, Matthew <matthew.auld@intel.com>
> > > > Sent: Tuesday, July 14, 2020 8:02 AM
> > > > To: Dave Airlie <airlied@gmail.com>
> > > > Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>;
> > > > Tang, CQ <cq.tang@intel.com>; Joonas Lahtinen
> > > > <joonas.lahtinen@linux.intel.com>;
> > > > Abdiel Janulgue <abdiel.janulgue@linux.intel.com>; Wilson, Chris P
> > > > <chris.p.wilson@intel.com>; Balestrieri, Francesco
> > > > <francesco.balestrieri@intel.com>; Vishwanathapura, Niranjana
> > > > <niranjana.vishwanathapura@intel.com>; Dhanalakota, Venkata S
> > > > <venkata.s.dhanalakota@intel.com>; Neel Desai
> > > > <neel.desai@intel.com>; Brost, Matthew <matthew.brost@intel.com>;
> > > > Dutt, Sudeep <sudeep.dutt@intel.com>; De Marchi, Lucas
> > > > <lucas.demarchi@intel.com>
> > > > Subject: Re: [RFC 53/60] drm/i915: Create stolen memory region
> > > > from local memory
> > > >
> > > > On 13/07/2020 05:48, Dave Airlie wrote:
> > > > > On Fri, 10 Jul 2020 at 22:01, Matthew Auld
> > > > > <matthew.auld@intel.com>
> > > > wrote:
> > > > >>
> > > > >> From: CQ Tang <cq.tang@intel.com>
> > > > >>
> > > > >> Add "REGION_STOLEN" device info to dg1, create stolen memory
> > > > >> region from upper portion of local device memory, starting from
> DSMBASE.
> > > > >>
> > > > >> The memory region is marked with "is_devmem=true".
> > > > >
> > > > > So is stolen fake on LMEM devices? The concept of stolen doesn't
> > > > > seem to make much sense with VRAM, so please enlighten me.
> > > >
> > > > CQ, do we actually need an explicit stolen LMEM region? The idea
> > > > of having a DSM like stolen region for LMEM does sound
> > > > strange(outside of the usual reserved portions which are for HW
> > > > use etc), since the driver has complete control over LMEM. Is it
> > > > just a convenience thing to keep things working as-is for fbc, initial fb,
> etc. or is there more to it?
> > > > There is buddy_alloc_range() for LMEM which we could potentially
> > > > use to wrap an object around for things like the initial fb or similar.
> > >
> > > This is a natural extension from IGT stolen memory region into DGT, we
> want to allocate objects from stolen area. In DGT, we have one stolen area
> per tile so we create one region in each of these area. Using memory region
> is easier to manage objects allocation and free. Other than fbc and rc6, we
> have gt/ring allocate stolen memory objects when without LMEM, so only
> apply to IGT case:
> > >
> > > display/intel_display.c: obj =
> i915_gem_object_create_stolen_for_preallocated(dev_priv,
> > > display/intel_fbdev.c: obj =
> i915_gem_object_create_stolen(dev_priv, size);
> > > display/intel_overlay.c: obj = i915_gem_object_create_stolen(i915,
> PAGE_SIZE);
> > > intel_rc6.c: pctx =
> i915_gem_object_create_stolen_for_preallocated(i915,
> > > intel_rc6.c: pctx = i915_gem_object_create_stolen(i915, pctx_size);
> > >
> > > intel_ring.c: obj = intel_gt_object_create_stolen(ggtt->vm.gt,
> size);
> > > intel_gt.c: obj = intel_gt_object_create_stolen(gt, size);
> > >
> > > For some reason, we don't use buddy allocator to manage the stolen
> memory, instead, we use drm_mm_node allocator directly, we have one-to-
> one mapping between drm_mm address space to dma address of the stolen
> memory. We also use contiguous allocation where an object always get a
> single contiguous block of pages.
> > >
> > > So fundamentally, we want to use the same code to work on both IGT
> stolen memory and DGT stolen memory.
> >
> > If this is fundamentally a software construct then it's horrible, if
> > the HW has a stolen base like Ville said, and it needs to be in a
> > chunk of VRAM, how do you go about sizing that, and carving it out
> > from the user?
> >
> > I don't think wanting to share the same codepaths here is an
> > acceptable answer, just fix the code to handle LMEM vs stolen, but if
> > there are hw reasons on why this is required it would be good to
> > enumerate exactly what they are and document them.
>
> The boot firmware does configure the stolen region, so it's not fake.
>
> But there's no need to expose the stolen memory to userspace, so these
> patches will be dropped.
Yes, I confirmed that on discrete GPU with display, firmware does reserve a portion of device local memory as stolen memory region, and used by device hardware, the usage of this local stolen memory is the same as system stolen memory on integrated GPU.
So we need to continue to create this local stolen memory region in driver. However, because this stolen memory region is only used by driver and hardware, there is no need to expose the stolen memory region to userspace.
--CQ
>
> Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory
2020-07-14 15:01 ` Matthew Auld
2020-07-14 16:57 ` Tang, CQ
@ 2020-07-14 17:39 ` Ville Syrjälä
1 sibling, 0 replies; 88+ messages in thread
From: Ville Syrjälä @ 2020-07-14 17:39 UTC (permalink / raw)
To: Matthew Auld
Cc: Abdiel Janulgue, Intel Graphics Development, Lucas De Marchi,
Chris P Wilson, Neel Desai
On Tue, Jul 14, 2020 at 04:01:31PM +0100, Matthew Auld wrote:
> On 13/07/2020 05:48, Dave Airlie wrote:
> > On Fri, 10 Jul 2020 at 22:01, Matthew Auld <matthew.auld@intel.com> wrote:
> >>
> >> From: CQ Tang <cq.tang@intel.com>
> >>
> >> Add "REGION_STOLEN" device info to dg1, create stolen memory
> >> region from upper portion of local device memory, starting
> >> from DSMBASE.
> >>
> >> The memory region is marked with "is_devmem=true".
> >
> > So is stolen fake on LMEM devices? The concept of stolen doesn't seem
> > to make much sense with VRAM, so please enlighten me.
>
> CQ, do we actually need an explicit stolen LMEM region? The idea of
> having a DSM like stolen region for LMEM does sound strange(outside of
> the usual reserved portions which are for HW use etc), since the driver
> has complete control over LMEM. Is it just a convenience thing to keep
> things working as-is for fbc, initial fb, etc. or is there more to it?
> There is buddy_alloc_range() for LMEM which we could potentially use to
> wrap an object around for things like the initial fb or similar.
For some reason the FBC hardware itself will treat the CFB base
as an offset into stolen memory. So assuming they didn't change
how the FBC hardware works we do still need the stolen
base set up in some fashion. Also the CFB base register is
32bits wide so without the stolen base it wouldn't be able
to address more than 4GiB or memory. Hmm, actually the
docs say the register only accepts 28bit offsets so only
256MiB in fact. I'll have to double check if that's true and
whether we are currently at risk of going past that limit...
I think there are some other magic things in the hardware that
also use the stolen base for something.
I do agree that having stolen inside lmem is a bit odd. That's
not how i810 worked IIRC. Back then you either had lmem or
you had stolen. But I guess all the i810 people retired by now
so there was no one to tell the new guys how to design this
stuff :P
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 88+ messages in thread
* [Intel-gfx] [RFC 54/60] drm/i915/lmem: Bypass aperture when lmem is available
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (52 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 53/60] drm/i915: Create stolen memory region from local memory Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 55/60] drm/i915/lmem: reset the lmem buffer created by fbdev Matthew Auld
` (10 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
Cc: Lucas De Marchi, Chris P Wilson, Dhinakaran Pandiyan, Daniel Vetter
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
In the scenario where local memory is available, we have
rely on CPU access via lmem directly instead of aperture.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: CQ Tang <cq.tang@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 23 +++++++++++++++-------
drivers/gpu/drm/i915/i915_vma.c | 19 ++++++++++++------
2 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index bd39eb6a21b8..f49280218413 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -41,6 +41,7 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_fourcc.h>
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_fbdev.h"
@@ -137,14 +138,22 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
size = mode_cmd.pitches[0] * mode_cmd.height;
size = PAGE_ALIGN(size);
- /* If the FB is too big, just don't use it since fbdev is not very
- * important and we should probably use that space with FBC or other
- * features. */
obj = ERR_PTR(-ENODEV);
- if (size * 2 < dev_priv->stolen_usable_size)
- obj = i915_gem_object_create_stolen(dev_priv, size);
- if (IS_ERR(obj))
- obj = i915_gem_object_create_shmem(dev_priv, size);
+ if (HAS_LMEM(dev_priv)) {
+ obj = i915_gem_object_create_lmem(dev_priv, size,
+ I915_BO_ALLOC_CONTIGUOUS);
+ } else {
+ /*
+ * If the FB is too big, just don't use it since fbdev is not very
+ * important and we should probably use that space with FBC or other
+ * features.
+ */
+ if (size * 2 < dev_priv->stolen_usable_size)
+ obj = i915_gem_object_create_stolen(dev_priv, size);
+ if (IS_ERR(obj))
+ obj = i915_gem_object_create_shmem(dev_priv, size);
+ }
+
if (IS_ERR(obj)) {
drm_err(&dev_priv->drm, "failed to allocate framebuffer\n");
return PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index bc64f773dcdb..ca51668a6663 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -27,6 +27,7 @@
#include "display/intel_frontbuffer.h"
+#include "gem/i915_gem_lmem.h"
#include "gt/intel_engine.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_gt.h"
@@ -447,9 +448,11 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
void __iomem *ptr;
int err;
- if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
- err = -ENODEV;
- goto err;
+ if (!i915_gem_object_is_devmem(vma->obj)) {
+ if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
+ err = -ENODEV;
+ goto err;
+ }
}
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
@@ -457,9 +460,13 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
ptr = READ_ONCE(vma->iomap);
if (ptr == NULL) {
- ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
- vma->node.start,
- vma->node.size);
+ if (i915_gem_object_is_devmem(vma->obj))
+ ptr = i915_gem_object_lmem_io_map(vma->obj, 0,
+ vma->obj->base.size);
+ else
+ ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->iomap,
+ vma->node.start,
+ vma->node.size);
if (ptr == NULL) {
err = -ENOMEM;
goto err;
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 55/60] drm/i915/lmem: reset the lmem buffer created by fbdev
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (53 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 54/60] drm/i915/lmem: Bypass aperture when lmem is available Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 56/60] drm/i915/dsb: Enable lmem for dsb Matthew Auld
` (9 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Animesh Manna <animesh.manna@intel.com>
Newly created lmem buffer by fbdev need reset otherwise it has old
garbage data. Same logic was present for stolen memory, extended
the same for lmem.
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index f49280218413..23a1e4638c1e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -265,7 +265,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (vma->obj->stolen && !prealloc)
+ if ((vma->obj->stolen || HAS_LMEM(dev_priv)) && !prealloc)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 56/60] drm/i915/dsb: Enable lmem for dsb
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (54 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 55/60] drm/i915/lmem: reset the lmem buffer created by fbdev Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 57/60] drm/i915: Reintroduce mem->reserved Matthew Auld
` (8 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Animesh Manna <animesh.manna@intel.com>
For dgfx, DSB should use local memory instead of system memory. Using
local memory surely brings performance improvement as local memory is
close to gpu. Also want to avoid multiple gpu using system memory.
Use LMEM API to create gem object needed for DSB command buffer.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 566fa72427b3..86f5f4b3c46b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_display_types.h"
+#include "gem/i915_gem_lmem.h"
#define DSB_BUF_SIZE (2 * PAGE_SIZE)
@@ -278,7 +279,11 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
- obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (HAS_LMEM(i915))
+ obj = i915_gem_object_create_lmem(i915, DSB_BUF_SIZE, 0);
+ else
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+
if (IS_ERR(obj)) {
drm_err(&i915->drm, "Gem object creation failed\n");
kfree(dsb);
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 57/60] drm/i915: Reintroduce mem->reserved
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (55 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 56/60] drm/i915/dsb: Enable lmem for dsb Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 58/60] drm/i915/dg1: Reserve first 1MB of local memory Matthew Auld
` (7 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Abdiel Janulgue
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
In the following patch we need to reserve regions unaccessible to the
driver during initialization, so add back mem->reserved for collecting
such regions.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/intel_memory_region.c | 2 +
drivers/gpu/drm/i915/intel_memory_region.h | 2 +
.../drm/i915/selftests/intel_memory_region.c | 89 +++++++++++++++++++
3 files changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 905cdfa6e3e2..6e9d0861cf8c 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -197,6 +197,7 @@ int intel_memory_region_init_buddy(struct intel_memory_region *mem)
void intel_memory_region_release_buddy(struct intel_memory_region *mem)
{
+ i915_buddy_free_list(&mem->mm, &mem->reserved);
i915_buddy_fini(&mem->mm);
}
@@ -226,6 +227,7 @@ intel_memory_region_create(struct drm_i915_private *i915,
mutex_init(&mem->objects.lock);
INIT_LIST_HEAD(&mem->objects.list);
INIT_LIST_HEAD(&mem->objects.purgeable);
+ INIT_LIST_HEAD(&mem->reserved);
mutex_init(&mem->mm_lock);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 8f9c943a16af..e082b895afdb 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -96,6 +96,8 @@ struct intel_memory_region {
char name[16];
bool is_devmem; /* true for device memory */
+ struct list_head reserved;
+
dma_addr_t remap_addr;
struct {
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index d10f5b52b677..f39be34c0980 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -129,6 +129,94 @@ static void igt_object_release(struct drm_i915_gem_object *obj)
i915_gem_object_put(obj);
}
+static int igt_reserve_range(struct intel_memory_region *mem,
+ struct list_head *reserved,
+ u64 offset,
+ u64 size)
+{
+ int ret;
+ LIST_HEAD(blocks);
+
+ ret = i915_buddy_alloc_range(&mem->mm, &blocks, offset, size);
+ if (!ret)
+ list_splice_tail(&blocks, reserved);
+
+ return ret;
+}
+
+static int igt_mock_reserve(void *arg)
+{
+ struct drm_i915_gem_object *obj;
+ struct intel_memory_region *mem = arg;
+ resource_size_t avail = resource_size(&mem->region);
+ I915_RND_STATE(prng);
+ LIST_HEAD(objects);
+ LIST_HEAD(reserved);
+ u32 i, offset, count, *order;
+ u64 allocated, cur_avail;
+ const u32 chunk_size = SZ_32M;
+ int err = 0;
+
+ count = avail / chunk_size;
+ order = i915_random_order(count, &prng);
+ if (!order)
+ return 0;
+
+ /* Reserve a bunch of ranges within the region */
+ for (i = 0; i < count; ++i) {
+ u64 start = order[i] * chunk_size;
+ u64 size = i915_prandom_u32_max_state(chunk_size, &prng);
+
+ /* Allow for some really big holes */
+ if (!size)
+ continue;
+
+ size = round_up(size, PAGE_SIZE);
+ offset = igt_random_offset(&prng, 0, chunk_size, size,
+ PAGE_SIZE);
+
+ err = igt_reserve_range(mem, &reserved, start + offset, size);
+ if (err) {
+ pr_err("%s failed to reserve range", __func__);
+ goto out_close;
+ }
+
+ /* XXX: maybe sanity check the block range here? */
+ avail -= size;
+ }
+
+ /* Try to see if we can allocate from the remaining space */
+ allocated = 0;
+ cur_avail = avail;
+ do {
+ u64 size = i915_prandom_u32_max_state(cur_avail, &prng);
+
+ size = max_t(u64, round_up(size, PAGE_SIZE), (u64)PAGE_SIZE);
+ obj = igt_object_create(mem, &objects, size, 0);
+
+ if (IS_ERR(obj)) {
+ if (PTR_ERR(obj) == -ENXIO)
+ break;
+
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+ cur_avail -= size;
+ allocated += size;
+ } while (1);
+
+ if (allocated != avail) {
+ pr_err("%s mismatch between allocation and free space", __func__);
+ err = -EINVAL;
+ }
+
+out_close:
+ kfree(order);
+ close_objects(mem, &objects);
+ i915_buddy_free_list(&mem->mm, &reserved);
+ return err;
+}
+
static int igt_mock_contiguous(void *arg)
{
struct intel_memory_region *mem = arg;
@@ -851,6 +939,7 @@ static int perf_memcpy(void *arg)
int intel_memory_region_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(igt_mock_reserve),
SUBTEST(igt_mock_fill),
SUBTEST(igt_mock_contiguous),
};
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 58/60] drm/i915/dg1: Reserve first 1MB of local memory
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (56 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 57/60] drm/i915: Reintroduce mem->reserved Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 59/60] drm/i915: defer pd lmem block put to worker Matthew Auld
` (6 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: Imre Deak <imre.deak@intel.com>
On DG1 A0 stepping the first 1MB of local memory must be reserved. One
reason for this is that the 0xA0000-0xB0000 range is not accessible by
the display, probably since this region is redirected to another memory
location for legacy VGA compatibility.
BSpec: 60029
Testcase: igt/kms_big_fb/linear-64bpp-rotate-0
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_region_lmem.c | 52 ++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c
index 46a2aa468054..b9e60d19d07c 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -41,6 +41,48 @@ const struct intel_memory_region_ops intel_region_lmem_ops = {
.create_object = __i915_gem_lmem_object_create,
};
+static void get_legacy_lowmem_region(struct intel_uncore *uncore,
+ u64 *start, u32 *size)
+{
+ *start = 0;
+ *size = 0;
+
+ if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_A0))
+ return;
+
+ *size = SZ_1M;
+
+ DRM_DEBUG_DRIVER("LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",
+ *start, *start + *size);
+}
+
+static int reserve_lowmem_region(struct intel_uncore *uncore,
+ struct intel_memory_region *mem)
+{
+ u64 reserve_start;
+ u64 reserve_end;
+ u64 region_start;
+ u32 region_size;
+ int ret;
+
+ get_legacy_lowmem_region(uncore, ®ion_start, ®ion_size);
+ reserve_start = region_start;
+ reserve_end = region_start + region_size;
+
+ if (!reserve_end)
+ return 0;
+
+ DRM_INFO("LMEM: reserving low-memory region [0x%llx-0x%llx]\n",
+ reserve_start, reserve_end);
+ ret = i915_buddy_alloc_range(&mem->mm, &mem->reserved,
+ reserve_start,
+ reserve_end - reserve_start);
+ if (ret)
+ DRM_ERROR("LMEM: reserving low memory region failed\n");
+
+ return ret;
+}
+
static struct intel_memory_region *
setup_lmem(struct drm_i915_private *dev_priv)
{
@@ -64,6 +106,16 @@ setup_lmem(struct drm_i915_private *dev_priv)
I915_GTT_PAGE_SIZE_4K,
io_start,
&intel_region_lmem_ops);
+ if (!IS_ERR(mem)) {
+ int err;
+
+ err = reserve_lowmem_region(uncore, mem);
+ if (err) {
+ intel_memory_region_put(mem);
+ return ERR_PTR(err);
+ }
+ }
+
if (!IS_ERR(mem)) {
DRM_INFO("Intel graphics LMEM: %pR\n", &mem->region);
DRM_INFO("Intel graphics LMEM IO start: %llx\n",
--
2.26.2
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^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 59/60] drm/i915: defer pd lmem block put to worker
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (57 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 58/60] drm/i915/dg1: Reserve first 1MB of local memory Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 11:57 ` [Intel-gfx] [RFC 60/60] drm/i915/lmem: allocate HWSP in lmem Matthew Auld
` (5 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
We take mem->mm_lock inside __i915_vma_unbind to release the memory
used for the page table itself, but __i915_vma_unbind is called while
holding vm->mutex; vm->mutex is tainted by the shrinker and therefore
locks related to allocations can't be taken while holding it
(kmem_cache_alloc is called under mem->mm_lock in i915_buddy_alloc,
so mem->mm_lock is a lock managing allocations).
As a temporary WA, move the memory release to a dedicated work called
outside the vm->mutex lock. A lockless list has been used to avoid any
locking dependency.
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
---
drivers/gpu/drm/i915/i915_buddy.h | 10 +++++++
drivers/gpu/drm/i915/intel_memory_region.c | 28 ++++++++++++++++---
drivers/gpu/drm/i915/intel_memory_region.h | 5 ++++
.../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
4 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_buddy.h b/drivers/gpu/drm/i915/i915_buddy.h
index ed41f3507cdc..fb08eb99d654 100644
--- a/drivers/gpu/drm/i915/i915_buddy.h
+++ b/drivers/gpu/drm/i915/i915_buddy.h
@@ -8,6 +8,7 @@
#include <linux/bitops.h>
#include <linux/list.h>
+#include <linux/llist.h>
struct i915_buddy_block {
#define I915_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
@@ -32,6 +33,15 @@ struct i915_buddy_block {
*/
struct list_head link;
struct list_head tmp_link;
+
+ /*
+ * XXX: consider moving this somewhere specific to the pd stuff. In an
+ * ideal world we would like to keep i915_buddy as non-i915 specific as
+ * possible and in this case the delayed freeing is only required for
+ * our pd handling, which is only one part of our overall i915_buddy
+ * use.
+ */
+ struct llist_node freed;
};
#define I915_BUDDY_MAX_ORDER I915_BUDDY_HEADER_ORDER
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 6e9d0861cf8c..80d827c4973d 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -84,14 +84,29 @@ __intel_memory_region_put_pages_buddy(struct intel_memory_region *mem,
mutex_unlock(&mem->mm_lock);
}
-void
-__intel_memory_region_put_block_buddy(struct i915_buddy_block *block)
+static void __intel_memory_region_put_block_work(struct work_struct *work)
{
+ struct intel_memory_region *mem =
+ container_of(work, struct intel_memory_region, pd_put.work);
+ struct llist_node *freed = llist_del_all(&mem->pd_put.blocks);
+ struct i915_buddy_block *block;
struct list_head blocks;
INIT_LIST_HEAD(&blocks);
- list_add(&block->link, &blocks);
- __intel_memory_region_put_pages_buddy(block->private, &blocks);
+
+ llist_for_each_entry(block, freed, freed)
+ list_add(&block->link, &blocks);
+
+ __intel_memory_region_put_pages_buddy(mem, &blocks);
+}
+
+void
+__intel_memory_region_put_block_buddy(struct i915_buddy_block *block)
+{
+ struct intel_memory_region *mem = block->private;
+
+ if (llist_add(&block->freed, &mem->pd_put.blocks))
+ queue_work(mem->i915->wq, &mem->pd_put.work);
}
int
@@ -224,6 +239,8 @@ intel_memory_region_create(struct drm_i915_private *i915,
mem->total = size;
mem->avail = mem->total;
+ INIT_WORK(&mem->pd_put.work, __intel_memory_region_put_block_work);
+
mutex_init(&mem->objects.lock);
INIT_LIST_HEAD(&mem->objects.list);
INIT_LIST_HEAD(&mem->objects.purgeable);
@@ -260,6 +277,9 @@ static void __intel_memory_region_destroy(struct kref *kref)
struct intel_memory_region *mem =
container_of(kref, typeof(*mem), kref);
+ /* Flush any pending work items to free blocks region */
+ flush_workqueue(mem->i915->wq);
+
if (mem->ops->release)
mem->ops->release(mem);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index e082b895afdb..e11ee974301f 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -83,6 +83,11 @@ struct intel_memory_region {
struct i915_buddy_mm mm;
struct mutex mm_lock;
+ struct {
+ struct work_struct work;
+ struct llist_head blocks;
+ } pd_put;
+
struct kref kref;
resource_size_t io_start;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 9a46be05425a..07838a587413 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -69,11 +69,12 @@ static void mock_device_release(struct drm_device *dev)
i915_gem_drain_freed_objects(i915);
mock_fini_ggtt(&i915->ggtt);
- destroy_workqueue(i915->wq);
intel_gt_driver_late_release(&i915->gt);
intel_memory_regions_driver_release(i915);
+ destroy_workqueue(i915->wq);
+
drm_mode_config_cleanup(&i915->drm);
out:
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] [RFC 60/60] drm/i915/lmem: allocate HWSP in lmem
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (58 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 59/60] drm/i915: defer pd lmem block put to worker Matthew Auld
@ 2020-07-10 11:57 ` Matthew Auld
2020-07-10 12:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 LMEM enabling Patchwork
` (4 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Matthew Auld @ 2020-07-10 11:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry, Abdiel Janulgue
From: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 14 ++++++++++++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +++++++++-
drivers/gpu/drm/i915/gt/intel_timeline.c | 8 +++++++-
3 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 7050519c87a4..bac33310594c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -251,8 +251,18 @@ static void *i915_gem_object_map(struct drm_i915_gem_object *obj,
struct vm_struct *area;
pgprot_t pgprot;
- if (!i915_gem_object_has_struct_page(obj) && type != I915_MAP_WC)
- return NULL;
+ /*
+ * XXX: we need to check all the places that try to kmap LMEM,
+ * and ensure that they only do so with WC(if we are certain
+ * that such an object should reside there). After that we can
+ * then re-add the following:
+ *
+ * if (!i915_gem_object_has_struct_page(obj) && type != I915_MAP_WC)
+ * return NULL;
+ */
+
+ if (!i915_gem_object_has_struct_page(obj) && type != I915_MAP_WC)
+ type = I915_MAP_WC;
/* A single page can always be kmapped */
if (n_pte == 1 && type == I915_MAP_WB)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1df94e82550f..1eb74571d142 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -25,6 +25,7 @@
#include <drm/drm_print.h>
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
@@ -651,7 +652,14 @@ static int init_status_page(struct intel_engine_cs *engine)
* in GFP_DMA32 for i965, and no earlier physical address users had
* access to more than 4G.
*/
- obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+ if (HAS_LMEM(engine->i915)) {
+ obj = i915_gem_object_create_lmem(engine->i915,
+ PAGE_SIZE,
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_VOLATILE);
+ } else {
+ obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+ }
if (IS_ERR(obj)) {
drm_err(&engine->i915->drm,
"Failed to allocate status page\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 4546284fede1..45e96ecba86a 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_active.h"
#include "i915_syncmap.h"
#include "intel_gt.h"
@@ -32,7 +33,12 @@ static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (HAS_LMEM(i915))
+ obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_VOLATILE);
+ else
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return ERR_CAST(obj);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 88+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 LMEM enabling
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (59 preceding siblings ...)
2020-07-10 11:57 ` [Intel-gfx] [RFC 60/60] drm/i915/lmem: allocate HWSP in lmem Matthew Auld
@ 2020-07-10 12:51 ` Patchwork
2020-07-10 12:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Patchwork @ 2020-07-10 12:51 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: DG1 LMEM enabling
URL : https://patchwork.freedesktop.org/series/79339/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
64e885563508 drm/i915: Add has_master_unit_irq flag
07333dfd467a drm/i915/dg1: add initial DG-1 definitions
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:1566:
+#define IS_DG1_REVID(p, since, until) \
+ (IS_DG1(p) && IS_REVID(p, since, until))
total: 0 errors, 0 warnings, 1 checks, 53 lines checked
aa3febafd54f drm/i915/dg1: Add DG1 PCI IDs
-:27: WARNING:BAD_SIGN_OFF: Duplicate signature
#27:
Reported-by: kernel test robot <lkp@intel.com>
total: 0 errors, 1 warnings, 0 checks, 16 lines checked
a8faa6244187 drm/i915/dg1: add support for the master unit interrupt
29620df1a5ff drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
e6fb62a95618 drm/i915/dg1: Add fake PCH
f89f5df391fa drm/i915/dg1: Initialize RAWCLK properly
c3be96ec4e2f drm/i915/dg1: Define MOCS table for DG1
f3e3af28e6da drm/i915/dg1: Add DG1 power wells
283845ab8957 drm/i915/dg1: Increase mmio size to 4MB
c73835ce2769 drm/i915/dg1: Wait for pcode/uncore handshake at startup
5467518226bd drm/i915/dg1: Add DPLL macros for DG1
d2b6d0fc64cf drm/i915/dg1: Add and setup DPLLs for DG1
fef23496c454 drm/i915/dg1: Enable DPLL for DG1
226726870402 drm/i915/dg1: add hpd interrupt handling
0b9012fb78d1 drm/i915/dg1: invert HPD pins
d520ab1c2265 drm/i915/dg1: gmbus pin mapping
f998462b8eb2 drm/i915/dg1: Enable first 2 ports for DG1
d4760bd1b4aa drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
649e6352cfc5 drm/i915/dg1: Update comp master/slave relationships for PHYs
f79c4ce6415d drm/i915/dg1: Update voltage swing tables for DP
9d91bbcfc48b drm/i915/dg1: provide port/phy mapping for vbt
ee5e03aaf90c drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10315:
+#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+ ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
total: 0 errors, 0 warnings, 1 checks, 204 lines checked
c9404617ff28 drm/i915/dg1: enable PORT C/D aka D/E
b6563ffa776b drm/i915/dg1: Load DMC
719467b3a5b9 drm/i915/rkl: Add initial workarounds
db688caa6c0b drm/i915/dg1: Add initial DG1 workarounds
720371af8fd0 drm/i915/dg1: DG1 does not support DC6
db311ea9f880 drm/i915/lmem: Limit block size to 4G
-:8: WARNING:TYPO_SPELLING: 'sytem' may be misspelled - perhaps 'system'?
#8:
buddy sytem can allocate blocks that can have size >= 4G and
total: 0 errors, 1 warnings, 0 checks, 32 lines checked
d1d490a37e6f drm/i915/lmem: Do not check r->sgt.pfn for NULL
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#6:
When user space does mmap, kernel would map the physical page of local memory
-:25: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Wen, Kui" <kui.wen@intel.com>'
total: 0 errors, 2 warnings, 0 checks, 8 lines checked
39d507e18b2c drm/i915/dgfx: define llc and snooping behaviour
7fcb3d5adb3d drm/i915/lmem: support pread
-:170: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct drm_i915_gem_object *' should also have an identifier name
#170: FILE: drivers/gpu/drm/i915/gem/i915_gem_object_types.h:59:
+ int (*pread)(struct drm_i915_gem_object *,
total: 0 errors, 1 warnings, 0 checks, 158 lines checked
6904f6ee9a66 drm/i915/lmem: support pwrite
-:78: ERROR:POINTER_LOCATION: "(foo*)" should be "(foo *)"
#78: FILE: drivers/gpu/drm/i915/gem/i915_gem_lmem.c:154:
+ unwritten = __copy_from_user_inatomic_nocache((void __force*)vaddr + offset,
-:83: ERROR:POINTER_LOCATION: "(foo*)" should be "(foo *)"
#83: FILE: drivers/gpu/drm/i915/gem/i915_gem_lmem.c:159:
+ unwritten = copy_from_user((void __force*)vaddr + offset,
total: 2 errors, 0 warnings, 0 checks, 98 lines checked
c654f1e3f508 drm/i915: introduce kernel blitter_context
83900007bf29 drm/i915/query: Expose memory regions through the query uAPI
-:180: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#180: FILE: drivers/gpu/drm/i915/intel_memory_region.c:10:
+ [INTEL_REGION_SMEM] = {$
-:181: ERROR:CODE_INDENT: code indent should use tabs where possible
#181: FILE: drivers/gpu/drm/i915/intel_memory_region.c:11:
+ .class = INTEL_MEMORY_SYSTEM,$
-:181: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#181: FILE: drivers/gpu/drm/i915/intel_memory_region.c:11:
+ .class = INTEL_MEMORY_SYSTEM,$
-:182: ERROR:CODE_INDENT: code indent should use tabs where possible
#182: FILE: drivers/gpu/drm/i915/intel_memory_region.c:12:
+ .instance = 0,$
-:182: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#182: FILE: drivers/gpu/drm/i915/intel_memory_region.c:12:
+ .instance = 0,$
-:183: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#183: FILE: drivers/gpu/drm/i915/intel_memory_region.c:13:
+ },$
-:184: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#184: FILE: drivers/gpu/drm/i915/intel_memory_region.c:14:
+ [INTEL_REGION_LMEM] = {$
-:185: ERROR:CODE_INDENT: code indent should use tabs where possible
#185: FILE: drivers/gpu/drm/i915/intel_memory_region.c:15:
+ .class = INTEL_MEMORY_LOCAL,$
-:185: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#185: FILE: drivers/gpu/drm/i915/intel_memory_region.c:15:
+ .class = INTEL_MEMORY_LOCAL,$
-:186: ERROR:CODE_INDENT: code indent should use tabs where possible
#186: FILE: drivers/gpu/drm/i915/intel_memory_region.c:16:
+ .instance = 0,$
-:186: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#186: FILE: drivers/gpu/drm/i915/intel_memory_region.c:16:
+ .instance = 0,$
-:187: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#187: FILE: drivers/gpu/drm/i915/intel_memory_region.c:17:
+ },$
-:188: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#188: FILE: drivers/gpu/drm/i915/intel_memory_region.c:18:
+ [INTEL_REGION_STOLEN_SMEM] = {$
-:189: ERROR:CODE_INDENT: code indent should use tabs where possible
#189: FILE: drivers/gpu/drm/i915/intel_memory_region.c:19:
+ .class = INTEL_MEMORY_STOLEN_SYSTEM,$
-:189: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#189: FILE: drivers/gpu/drm/i915/intel_memory_region.c:19:
+ .class = INTEL_MEMORY_STOLEN_SYSTEM,$
-:190: ERROR:CODE_INDENT: code indent should use tabs where possible
#190: FILE: drivers/gpu/drm/i915/intel_memory_region.c:20:
+ .instance = 0,$
-:190: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#190: FILE: drivers/gpu/drm/i915/intel_memory_region.c:20:
+ .instance = 0,$
-:191: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#191: FILE: drivers/gpu/drm/i915/intel_memory_region.c:21:
+ },$
-:289: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#289: FILE: drivers/gpu/drm/i915/intel_memory_region.h:51:
+ u16 class;$
-:290: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#290: FILE: drivers/gpu/drm/i915/intel_memory_region.h:52:
+ u16 instance;$
total: 6 errors, 14 warnings, 0 checks, 328 lines checked
cc6a052c411f drm/i915/uapi: introduce drm_i915_gem_create_ext
-:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#57:
new file mode 100644
-:677: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#677: FILE: include/uapi/drm/i915_drm.h:394:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
-:686: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#686: FILE: include/uapi/drm/i915_drm.h:727:
+struct drm_i915_gem_create_ext {
+
-:725: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#725: FILE: include/uapi/drm/i915_drm.h:1682:
+#define I915_OBJECT_PARAM (1ull<<32)
^
total: 0 errors, 2 warnings, 2 checks, 656 lines checked
25e66f7d0a5c drm/i915/lmem: allocate cmd ring in lmem
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 27 lines checked
f9f300099d61 drm/i915/dg1: Introduce dmabuf mmap to LMEM
4416c2f7894c drm/i915: setup the LMEM region
d8a3239ffeaa drm/i915: drop fake LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 182 lines checked
d41c52d4ed7a drm/i915: Distinction of memory regions
-:34: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author ''
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
643474aa3150 drm/i915: PPGTT support
c54410159094 drm/i915: support GGTT LMEM entries
f4982e6c0259 drm/i915: allocate context from LMEM
047b9d87f202 drm/i915: move engine scratch to LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
32e939403a2d drm/i915: Provide a way to disable PCIe relaxed write ordering
ca44b6c4d514 drm/i915: setup GPU device lmem region
1755a4e32c7f drm/i915: Fix object page offset within a region
9b32500e03cf drm/i915: add i915_gem_object_is_devmem() function
efea29d82bbd drm/i915: finish memory region support for stolen objects.
be0fce4a6e1c drm/i915/lmem: support optional CPU clearing for special internal use
-:75: WARNING:LINE_SPACING: Missing a blank line after declarations
#75: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:402:
+ struct drm_i915_private *i915 = arg;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 135 lines checked
6ee119d1496f drm/i915/guc: put all guc objects in lmem when available
-:19: WARNING:BAD_SIGN_OFF: Duplicate signature
#19:
Cc: Matthew Auld <matthew.auld@intel.com>
-:20: WARNING:BAD_SIGN_OFF: Duplicate signature
#20:
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
-:145: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#145: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c:45:
+static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
struct intel_uncore *uncore)
total: 0 errors, 2 warnings, 1 checks, 219 lines checked
a6d6e930f411 drm/i915: Create stolen memory region from local memory
-:213: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#213: FILE: drivers/gpu/drm/i915/intel_memory_region.c:22:
+ [INTEL_REGION_STOLEN_LMEM] = {$
-:214: ERROR:CODE_INDENT: code indent should use tabs where possible
#214: FILE: drivers/gpu/drm/i915/intel_memory_region.c:23:
+ .class = INTEL_MEMORY_STOLEN_LOCAL,$
-:214: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#214: FILE: drivers/gpu/drm/i915/intel_memory_region.c:23:
+ .class = INTEL_MEMORY_STOLEN_LOCAL,$
-:215: ERROR:CODE_INDENT: code indent should use tabs where possible
#215: FILE: drivers/gpu/drm/i915/intel_memory_region.c:24:
+ .instance = 0,$
-:215: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#215: FILE: drivers/gpu/drm/i915/intel_memory_region.c:24:
+ .instance = 0,$
-:216: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#216: FILE: drivers/gpu/drm/i915/intel_memory_region.c:25:
+ },$
-:224: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#224: FILE: drivers/gpu/drm/i915/intel_memory_region.c:312:
+ case INTEL_MEMORY_STOLEN_LOCAL: /* fallthrough */
total: 2 errors, 5 warnings, 0 checks, 174 lines checked
8d4bc254af2b drm/i915/lmem: Bypass aperture when lmem is available
be601b687707 drm/i915/lmem: reset the lmem buffer created by fbdev
dd7bf2daf3dc drm/i915/dsb: Enable lmem for dsb
78474d0ee907 drm/i915: Reintroduce mem->reserved
-:74: WARNING:LINE_SPACING: Missing a blank line after declarations
#74: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:152:
+ resource_size_t avail = resource_size(&mem->region);
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 123 lines checked
3e441301c8d3 drm/i915/dg1: Reserve first 1MB of local memory
9d929688551d drm/i915: defer pd lmem block put to worker
88b8c65b7fbf drm/i915/lmem: allocate HWSP in lmem
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:32: WARNING:TABSTOP: Statements should start on a tabstop
#32: FILE: drivers/gpu/drm/i915/gem/i915_gem_pages.c:264:
+ if (!i915_gem_object_has_struct_page(obj) && type != I915_MAP_WC)
-:32: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (9, 17)
#32: FILE: drivers/gpu/drm/i915/gem/i915_gem_pages.c:264:
+ if (!i915_gem_object_has_struct_page(obj) && type != I915_MAP_WC)
+ type = I915_MAP_WC;
total: 0 errors, 3 warnings, 0 checks, 62 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DG1 LMEM enabling
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (60 preceding siblings ...)
2020-07-10 12:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG1 LMEM enabling Patchwork
@ 2020-07-10 12:52 ` Patchwork
2020-07-10 13:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
64 siblings, 0 replies; 88+ messages in thread
From: Patchwork @ 2020-07-10 12:52 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: DG1 LMEM enabling
URL : https://patchwork.freedesktop.org/series/79339/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_region.c:113:34: expected unsigned long long [usertype] *s
+drivers/gpu/drm/i915/gem/i915_gem_region.c:113:34: got void [noderef] __iomem *[assigned] vaddr
+drivers/gpu/drm/i915/gem/i915_gem_region.c:113:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_gtt.c:298:33: expected void [noderef] __iomem *vaddr
+drivers/gpu/drm/i915/gt/intel_gtt.c:298:33: got void *vaddr
+drivers/gpu/drm/i915/gt/intel_gtt.c:298:33: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_gtt.c:354:34: expected void *
+drivers/gpu/drm/i915/gt/intel_gtt.c:354:34: got void [noderef] __iomem *
+drivers/gpu/drm/i915/gt/intel_gtt.c:354:34: warning: incorrect type in return expression (different address spaces)
+drivers/gpu/drm/i915/gt/intel_lrc.c:2787:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_lrc.c:2787:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:616:35: expected void const *from
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:616:35: got void [noderef] __iomem *
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:616:35: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:539:23: expected void [noderef] __iomem *vaddr
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:539:23: got void *
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:539:23: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:548:40: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:548:40: got void [noderef] __iomem *
+drivers/gpu/drm/i915/selftests/intel_memory_region.c:548:40: warning: incorrect type in argument 1 (different address spaces)
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for DG1 LMEM enabling
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (61 preceding siblings ...)
2020-07-10 12:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-07-10 13:12 ` Patchwork
2020-07-10 14:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-08-11 3:23 ` [Intel-gfx] [RFC 00/60] " Dave Airlie
64 siblings, 0 replies; 88+ messages in thread
From: Patchwork @ 2020-07-10 13:12 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: DG1 LMEM enabling
URL : https://patchwork.freedesktop.org/series/79339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8726 -> Patchwork_18131
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/index.html
Known issues
------------
Here are the changes found in Patchwork_18131 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_backlight@basic-brightness:
- fi-whl-u: [PASS][1] -> [DMESG-WARN][2] ([i915#95])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-whl-u/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-kbl-x1275/igt@kms_busy@basic@flip.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-u2: [INCOMPLETE][7] ([i915#1932] / [i915#2045]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_flip@basic-plain-flip@a-dp1:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/fi-kbl-x1275/igt@kms_flip@basic-plain-flip@a-dp1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/fi-kbl-x1275/igt@kms_flip@basic-plain-flip@a-dp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2045]: https://gitlab.freedesktop.org/drm/intel/issues/2045
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (40 -> 35)
------------------------------
Additional (2): fi-tgl-y fi-elk-e7500
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8726 -> Patchwork_18131
CI-20190529: 20190529
CI_DRM_8726: 723780498c9dd2f58b80e6b9daeaa5cd08ec8e7a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18131: 88b8c65b7fbfebc4e2adf798203f27e0ce8bd7a6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
88b8c65b7fbf drm/i915/lmem: allocate HWSP in lmem
9d929688551d drm/i915: defer pd lmem block put to worker
3e441301c8d3 drm/i915/dg1: Reserve first 1MB of local memory
78474d0ee907 drm/i915: Reintroduce mem->reserved
dd7bf2daf3dc drm/i915/dsb: Enable lmem for dsb
be601b687707 drm/i915/lmem: reset the lmem buffer created by fbdev
8d4bc254af2b drm/i915/lmem: Bypass aperture when lmem is available
a6d6e930f411 drm/i915: Create stolen memory region from local memory
6ee119d1496f drm/i915/guc: put all guc objects in lmem when available
be0fce4a6e1c drm/i915/lmem: support optional CPU clearing for special internal use
efea29d82bbd drm/i915: finish memory region support for stolen objects.
9b32500e03cf drm/i915: add i915_gem_object_is_devmem() function
1755a4e32c7f drm/i915: Fix object page offset within a region
ca44b6c4d514 drm/i915: setup GPU device lmem region
32e939403a2d drm/i915: Provide a way to disable PCIe relaxed write ordering
047b9d87f202 drm/i915: move engine scratch to LMEM
f4982e6c0259 drm/i915: allocate context from LMEM
c54410159094 drm/i915: support GGTT LMEM entries
643474aa3150 drm/i915: PPGTT support
d41c52d4ed7a drm/i915: Distinction of memory regions
d8a3239ffeaa drm/i915: drop fake LMEM
4416c2f7894c drm/i915: setup the LMEM region
f9f300099d61 drm/i915/dg1: Introduce dmabuf mmap to LMEM
25e66f7d0a5c drm/i915/lmem: allocate cmd ring in lmem
cc6a052c411f drm/i915/uapi: introduce drm_i915_gem_create_ext
83900007bf29 drm/i915/query: Expose memory regions through the query uAPI
c654f1e3f508 drm/i915: introduce kernel blitter_context
6904f6ee9a66 drm/i915/lmem: support pwrite
7fcb3d5adb3d drm/i915/lmem: support pread
39d507e18b2c drm/i915/dgfx: define llc and snooping behaviour
d1d490a37e6f drm/i915/lmem: Do not check r->sgt.pfn for NULL
db311ea9f880 drm/i915/lmem: Limit block size to 4G
720371af8fd0 drm/i915/dg1: DG1 does not support DC6
db688caa6c0b drm/i915/dg1: Add initial DG1 workarounds
719467b3a5b9 drm/i915/rkl: Add initial workarounds
b6563ffa776b drm/i915/dg1: Load DMC
c9404617ff28 drm/i915/dg1: enable PORT C/D aka D/E
ee5e03aaf90c drm/i915/dg1: map/unmap pll clocks
9d91bbcfc48b drm/i915/dg1: provide port/phy mapping for vbt
f79c4ce6415d drm/i915/dg1: Update voltage swing tables for DP
649e6352cfc5 drm/i915/dg1: Update comp master/slave relationships for PHYs
d4760bd1b4aa drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
f998462b8eb2 drm/i915/dg1: Enable first 2 ports for DG1
d520ab1c2265 drm/i915/dg1: gmbus pin mapping
0b9012fb78d1 drm/i915/dg1: invert HPD pins
226726870402 drm/i915/dg1: add hpd interrupt handling
fef23496c454 drm/i915/dg1: Enable DPLL for DG1
d2b6d0fc64cf drm/i915/dg1: Add and setup DPLLs for DG1
5467518226bd drm/i915/dg1: Add DPLL macros for DG1
c73835ce2769 drm/i915/dg1: Wait for pcode/uncore handshake at startup
283845ab8957 drm/i915/dg1: Increase mmio size to 4MB
f3e3af28e6da drm/i915/dg1: Add DG1 power wells
c3be96ec4e2f drm/i915/dg1: Define MOCS table for DG1
f89f5df391fa drm/i915/dg1: Initialize RAWCLK properly
e6fb62a95618 drm/i915/dg1: Add fake PCH
29620df1a5ff drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
a8faa6244187 drm/i915/dg1: add support for the master unit interrupt
aa3febafd54f drm/i915/dg1: Add DG1 PCI IDs
07333dfd467a drm/i915/dg1: add initial DG-1 definitions
64e885563508 drm/i915: Add has_master_unit_irq flag
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 88+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for DG1 LMEM enabling
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (62 preceding siblings ...)
2020-07-10 13:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-07-10 14:50 ` Patchwork
2020-08-11 3:23 ` [Intel-gfx] [RFC 00/60] " Dave Airlie
64 siblings, 0 replies; 88+ messages in thread
From: Patchwork @ 2020-07-10 14:50 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-gfx
== Series Details ==
Series: DG1 LMEM enabling
URL : https://patchwork.freedesktop.org/series/79339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8726_full -> Patchwork_18131_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18131_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18131_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18131_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@mock@hugepages:
- shard-skl: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl4/igt@i915_selftest@mock@hugepages.html
* igt@i915_selftest@mock@scatterlist:
- shard-hsw: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-hsw8/igt@i915_selftest@mock@scatterlist.html
Known issues
------------
Here are the changes found in Patchwork_18131_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_params@invalid-fence-in:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-kbl4/igt@gem_exec_params@invalid-fence-in.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-kbl4/igt@gem_exec_params@invalid-fence-in.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-glk2/igt@gem_exec_whisper@basic-queues-all.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-glk2/igt@gem_exec_whisper@basic-queues-all.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-iclb1/igt@kms_big_fb@linear-64bpp-rotate-180.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-iclb3/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#95]) +22 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-snb: [PASS][13] -> [TIMEOUT][14] ([i915#1958] / [i915#2119]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-256x256-random.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-hsw1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-hsw6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_frontbuffer_tracking@basic:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-glk3/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-glk9/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl3/igt@kms_hdr@bpc-switch.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl8/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-y:
- shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl3/igt@kms_plane_lowres@pipe-b-tiling-y.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl3/igt@kms_plane_lowres@pipe-b-tiling-y.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][27] -> [FAIL][28] ([i915#173])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-iclb8/igt@kms_psr@no_drrs.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
#### Possible fixes ####
* igt@gem_ctx_param@basic:
- shard-apl: [DMESG-WARN][31] ([i915#1635] / [i915#95]) -> [PASS][32] +15 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl7/igt@gem_ctx_param@basic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@gem_ctx_param@basic.html
* igt@gem_exec_balancer@bonded-early:
- shard-kbl: [FAIL][33] ([i915#2079]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-kbl3/igt@gem_exec_balancer@bonded-early.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-kbl3/igt@gem_exec_balancer@bonded-early.html
* igt@i915_module_load@reload:
- shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-tglb2/igt@i915_module_load@reload.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-tglb1/igt@i915_module_load@reload.html
* igt@i915_selftest@mock@requests:
- shard-skl: [INCOMPLETE][37] ([i915#198] / [i915#2110]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl5/igt@i915_selftest@mock@requests.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl4/igt@i915_selftest@mock@requests.html
- shard-snb: [INCOMPLETE][39] ([i915#2110] / [i915#82]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-snb4/igt@i915_selftest@mock@requests.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-snb4/igt@i915_selftest@mock@requests.html
* igt@i915_suspend@forcewake:
- shard-snb: [DMESG-WARN][41] ([i915#42]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-snb6/igt@i915_suspend@forcewake.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-snb2/igt@i915_suspend@forcewake.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +11 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl9/igt@kms_color@pipe-b-ctm-negative.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl1/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_flip@basic-flip-vs-dpms@a-dp1:
- shard-kbl: [DMESG-WARN][45] ([i915#165]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-kbl2/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-kbl2/igt@kms_flip@basic-flip-vs-dpms@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +9 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-skl: [FAIL][49] ([i915#49]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-iclb4/igt@kms_psr@psr2_sprite_plane_onoff.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@prime_busy@hang-wait@bcs0:
- shard-hsw: [INCOMPLETE][57] ([i915#409]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-hsw6/igt@prime_busy@hang-wait@bcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-hsw8/igt@prime_busy@hang-wait@bcs0.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent0:
- shard-apl: [FAIL][59] ([i915#1930]) -> [FAIL][60] ([i915#1635] / [i915#1930])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl4/igt@gem_exec_reloc@basic-concurrent0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl7/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [FAIL][61] ([i915#1930]) -> [TIMEOUT][62] ([i915#1958] / [i915#2119])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-snb6/igt@gem_exec_reloc@basic-concurrent16.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-snb6/igt@gem_exec_reloc@basic-concurrent16.html
* igt@gem_userptr_blits@process-exit-mmap@wb:
- shard-apl: [SKIP][63] ([fdo#109271] / [i915#1699]) -> [SKIP][64] ([fdo#109271] / [i915#1635] / [i915#1699]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl4/igt@gem_userptr_blits@process-exit-mmap@wb.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@gem_userptr_blits@process-exit-mmap@wb.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-apl: [SKIP][65] ([fdo#109271] / [i915#658]) -> [SKIP][66] ([fdo#109271] / [i915#1635] / [i915#658])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: [SKIP][67] ([fdo#109271] / [fdo#111827]) -> [SKIP][68] ([fdo#109271] / [fdo#111827] / [i915#1635]) +85 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl8/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl3/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [FAIL][70] ([fdo#110321] / [fdo#110336] / [i915#1635]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl8/igt@kms_content_protection@atomic-dpms.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-apl: [FAIL][71] ([fdo#110321]) -> [FAIL][72] ([fdo#110321] / [i915#1635]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl3/igt@kms_content_protection@lic.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: [FAIL][73] ([i915#2105]) -> [FAIL][74] ([i915#1635] / [i915#2105])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl1/igt@kms_content_protection@uevent.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@kms_content_protection@uevent.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][75] ([i915#1525]) -> [FAIL][76] ([i915#1525] / [i915#1635])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [DMESG-WARN][77] ([i915#1982]) -> [FAIL][78] ([i915#79])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-tglb: [INCOMPLETE][79] ([i915#1602] / [i915#1887] / [i915#456]) -> [DMESG-WARN][80] ([i915#1602] / [i915#1887])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-tglb6/igt@kms_flip@flip-vs-suspend@a-edp1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-tglb2/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: [FAIL][81] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][82] ([fdo#108145] / [i915#1635] / [i915#1982])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: [FAIL][83] ([fdo#108145] / [i915#265]) -> [FAIL][84] ([fdo#108145] / [i915#1635] / [i915#265]) +9 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: [FAIL][85] ([i915#265]) -> [FAIL][86] ([i915#1635] / [i915#265]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][87] ([i915#31]) -> [FAIL][88] ([i915#1635] / [i915#31])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl6/igt@kms_setmode@basic.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl6/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-apl: [FAIL][89] ([IGT#2]) -> [FAIL][90] ([IGT#2] / [i915#1635])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl7/igt@kms_sysfs_edid_timing.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl8/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: [SKIP][91] ([fdo#109271]) -> [SKIP][92] ([fdo#109271] / [i915#1635]) +852 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl4/igt@kms_vblank@pipe-d-ts-continuation-idle.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl3/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@perf@blocking-parameterized:
- shard-apl: [FAIL][93] ([i915#1542]) -> [FAIL][94] ([i915#1542] / [i915#1635])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl6/igt@perf@blocking-parameterized.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl3/igt@perf@blocking-parameterized.html
* igt@runner@aborted:
- shard-apl: ([FAIL][95], [FAIL][96]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][97] ([i915#1635] / [i915#2110])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl4/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8726/shard-apl3/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/shard-apl2/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1699]: https://gitlab.freedesktop.org/drm/intel/issues/1699
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110
[i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8726 -> Patchwork_18131
CI-20190529: 20190529
CI_DRM_8726: 723780498c9dd2f58b80e6b9daeaa5cd08ec8e7a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18131: 88b8c65b7fbfebc4e2adf798203f27e0ce8bd7a6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18131/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [Intel-gfx] [RFC 00/60] DG1 LMEM enabling
2020-07-10 11:56 [Intel-gfx] [RFC 00/60] DG1 LMEM enabling Matthew Auld
` (63 preceding siblings ...)
2020-07-10 14:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-08-11 3:23 ` Dave Airlie
2020-08-11 10:48 ` Matthew Auld
64 siblings, 1 reply; 88+ messages in thread
From: Dave Airlie @ 2020-08-11 3:23 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
Hi Matthew,
do you have a rebase of these or a git tree with them, once I hit the
PPGTT support applying started to get messy.
Dave.
On Fri, 10 Jul 2020 at 21:58, Matthew Auld <matthew.auld@intel.com> wrote:
>
> This is Lucas' DG1 enabling series[1], plus some of the DG1 specific enablers
> for supporting LMEM on top, including some bits of new uAPI.
>
> Posting this series as RFC to get feedback while we continue to work on adapting
> the code to use DMA reservation incrementally. This is currently WIP[2][3].
>
> In terms of new uAPI we have gem_create_ext, which offers extensions support for
> gem_create, this includes giving userspace the ability to optionally provide a
> priority list of potential placements for the object. The other bit of new uAPI
> is the query interface for memory regions, which describes the supported memory
> regions for the device. What this reports can then be fed into gem_create_ext to
> specify where an object might reside, like device local memory.
>
> [1] https://patchwork.freedesktop.org/series/77496/
> [2] https://patchwork.freedesktop.org/series/79091/
> [3] https://patchwork.freedesktop.org/series/79129/
>
> Abdiel Janulgue (5):
> drm/i915/dg1: add initial DG-1 definitions
> drm/i915/dg1: Add DG1 PCI IDs
> drm/i915/query: Expose memory regions through the query uAPI
> drm/i915: Provide a way to disable PCIe relaxed write ordering
> drm/i915: Reintroduce mem->reserved
>
> Aditya Swarup (4):
> drm/i915/dg1: Add DPLL macros for DG1
> drm/i915/dg1: Add and setup DPLLs for DG1
> drm/i915/dg1: Enable DPLL for DG1
> drm/i915/dg1: Enable first 2 ports for DG1
>
> Animesh Manna (2):
> drm/i915/lmem: reset the lmem buffer created by fbdev
> drm/i915/dsb: Enable lmem for dsb
>
> Anshuman Gupta (1):
> drm/i915/dg1: DG1 does not support DC6
>
> Anusha Srivatsa (2):
> drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
> drm/i915/lmem: Bypass aperture when lmem is available
>
> CQ Tang (5):
> drm/i915: setup GPU device lmem region
> drm/i915: Fix object page offset within a region
> drm/i915: add i915_gem_object_is_devmem() function
> drm/i915: finish memory region support for stolen objects.
> drm/i915: Create stolen memory region from local memory
>
> Clinton A Taylor (1):
> drm/i915/dg1: invert HPD pins
>
> Daniele Ceraolo Spurio (2):
> drm/i915/guc: put all guc objects in lmem when available
> drm/i915: defer pd lmem block put to worker
>
> Imre Deak (1):
> drm/i915/dg1: Reserve first 1MB of local memory
>
> Lucas De Marchi (7):
> drm/i915/dg1: add support for the master unit interrupt
> drm/i915/dg1: Add fake PCH
> drm/i915/dg1: Define MOCS table for DG1
> drm/i915/dg1: add hpd interrupt handling
> drm/i915/dg1: gmbus pin mapping
> drm/i915/dg1: map/unmap pll clocks
> drm/i915/dg1: enable PORT C/D aka D/E
>
> Matt Atwood (1):
> drm/i915/dg1: Load DMC
>
> Matt Roper (7):
> drm/i915/dg1: Initialize RAWCLK properly
> drm/i915/dg1: Wait for pcode/uncore handshake at startup
> drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
> drm/i915/dg1: Update comp master/slave relationships for PHYs
> drm/i915/dg1: Update voltage swing tables for DP
> drm/i915/dg1: provide port/phy mapping for vbt
> drm/i915/rkl: Add initial workarounds
>
> Matthew Auld (11):
> drm/i915/lmem: support pread
> drm/i915/lmem: support pwrite
> drm/i915: introduce kernel blitter_context
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915: setup the LMEM region
> drm/i915: drop fake LMEM
> drm/i915: PPGTT support
> drm/i915: support GGTT LMEM entries
> drm/i915: allocate context from LMEM
> drm/i915: move engine scratch to LMEM
> drm/i915/lmem: support optional CPU clearing for special internal use
>
> Michael J. Ruhl (1):
> drm/i915/dg1: Introduce dmabuf mmap to LMEM
>
> Michel Thierry (3):
> drm/i915/dgfx: define llc and snooping behaviour
> drm/i915/lmem: allocate cmd ring in lmem
> drm/i915/lmem: allocate HWSP in lmem
>
> Stuart Summers (2):
> drm/i915: Add has_master_unit_irq flag
> drm/i915/dg1: Add initial DG1 workarounds
>
> Uma Shankar (1):
> drm/i915/dg1: Add DG1 power wells
>
> Venkata Sandeep Dhanalakota (2):
> drm/i915/dg1: Increase mmio size to 4MB
> drm/i915/lmem: Limit block size to 4G
>
> Wen, Kui (1):
> drm/i915/lmem: Do not check r->sgt.pfn for NULL
>
> Zbigniew Kempczyński (1):
> drm/i915: Distinction of memory regions
>
> drivers/gpu/drm/i915/Kconfig.debug | 11 +
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_bios.c | 12 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +-
> .../gpu/drm/i915/display/intel_combo_phy.c | 7 +-
> drivers/gpu/drm/i915/display/intel_csr.c | 19 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 126 +++++-
> drivers/gpu/drm/i915/display/intel_display.c | 50 ++-
> .../drm/i915/display/intel_display_power.c | 211 +++++++++-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 71 +++-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 7 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 20 +-
> drivers/gpu/drm/i915/display/intel_fbdev.c | 25 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 5 +-
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 379 ++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 58 ++-
> drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 250 +++++++++++-
> drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 22 +
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 103 ++---
> drivers/gpu/drm/i915/gem/i915_gem_mman.h | 8 +
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 19 +-
> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 14 +-
> drivers/gpu/drm/i915/gem/i915_gem_region.c | 24 ++
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 241 +++++++----
> drivers/gpu/drm/i915/gem/i915_gem_stolen.h | 10 +-
> .../drm/i915/gem/selftests/i915_gem_mman.c | 12 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 83 +++-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 40 +-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 24 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 14 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 74 +++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 11 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 31 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 10 +-
> drivers/gpu/drm/i915/gt/intel_ring.c | 15 +-
> drivers/gpu/drm/i915/gt/intel_timeline.c | 8 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 159 ++++++--
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 9 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 11 +-
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 35 +-
> drivers/gpu/drm/i915/i915_buddy.h | 10 +
> drivers/gpu/drm/i915/i915_debugfs.c | 4 +
> drivers/gpu/drm/i915/i915_drv.c | 22 +-
> drivers/gpu/drm/i915/i915_drv.h | 15 +-
> drivers/gpu/drm/i915/i915_gem.c | 109 +----
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> drivers/gpu/drm/i915/i915_irq.c | 120 +++++-
> drivers/gpu/drm/i915/i915_mm.c | 2 +-
> drivers/gpu/drm/i915/i915_params.c | 5 -
> drivers/gpu/drm/i915/i915_params.h | 1 -
> drivers/gpu/drm/i915/i915_pci.c | 18 +-
> drivers/gpu/drm/i915/i915_query.c | 62 +++
> drivers/gpu/drm/i915/i915_reg.h | 71 +++-
> drivers/gpu/drm/i915/i915_vma.c | 19 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 +
> drivers/gpu/drm/i915/intel_memory_region.c | 119 +++++-
> drivers/gpu/drm/i915/intel_memory_region.h | 55 ++-
> drivers/gpu/drm/i915/intel_pch.c | 6 +
> drivers/gpu/drm/i915/intel_pch.h | 4 +
> drivers/gpu/drm/i915/intel_pm.c | 17 +-
> drivers/gpu/drm/i915/intel_region_lmem.c | 164 ++++----
> drivers/gpu/drm/i915/intel_region_lmem.h | 3 +-
> drivers/gpu/drm/i915/intel_sideband.c | 15 +
> drivers/gpu/drm/i915/intel_sideband.h | 2 +
> drivers/gpu/drm/i915/intel_uncore.c | 4 +
> .../drm/i915/selftests/intel_memory_region.c | 172 ++++++++
> .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
> include/drm/i915_pciids.h | 4 +
> include/uapi/drm/i915_drm.h | 118 ++++++
> 80 files changed, 2902 insertions(+), 598 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.c
>
> --
> 2.26.2
>
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^ permalink raw reply [flat|nested] 88+ messages in thread