[PATCH 00/12] Add label to pcie nodes

[PATCH 00/12] Add label to pcie nodes

[Wasim Khan]

This patch series
- Adds label to pcie nodes in dts file for NXP's layerscape SoCs 
- Print the pcie controller number starting from 1 to match RMs
- Add checks for config resource size and fix indendation.

Wasim Khan (12):
  pci: layerscape: Print pcie controller number starting from 1
  pci: ls_pcie_g4: Print pcie controller number starting from 1
  arm: dts: lx2160a: add label to pcie nodes in dts
  arm: dts: ls1046a: add label to pcie nodes in dts
  arm: dts: ls2080a: add label to pcie nodes in dts
  arm: dts: ls1088a: add label to pcie nodes in dts
  arm: dts: ls1012a: add label to pcie nodes in dts
  arm: dts: ls1043a: add label to pcie nodes in dts
  arm: dts: ls1028a: add label to pcie nodes in dts
  pci: layerscape: Add size check for config resource
  pci: ls_pcie_g4: Add size check for config resource
  pci: layerscape: indentation correction

 arch/arm/dts/fsl-ls1012a.dtsi      |  3 ++-
 arch/arm/dts/fsl-ls1028a.dtsi      |  6 +++---
 arch/arm/dts/fsl-ls1043a.dtsi      |  9 +++++----
 arch/arm/dts/fsl-ls1046a.dtsi      |  9 +++++----
 arch/arm/dts/fsl-ls1088a.dtsi      |  8 ++++----
 arch/arm/dts/fsl-ls2080a.dtsi      | 11 ++++++-----
 arch/arm/dts/fsl-lx2160a.dtsi      | 12 ++++++------
 drivers/pci/pcie_layerscape.c      | 23 ++++++++++++++++-------
 drivers/pci/pcie_layerscape_gen4.c | 20 ++++++++++++++++----
 9 files changed, 63 insertions(+), 38 deletions(-)

-- 
2.7.4

[PATCH 01/12] pci: layerscape: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 drivers/pci/pcie_layerscape.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 39b6d40..2f17176 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  */
@@ -456,7 +456,8 @@ static int ls_pcie_probe(struct udevice *dev)
 
 	pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -523,10 +524,12 @@ static int ls_pcie_probe(struct udevice *dev)
 	pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
 
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Endpoint");
 			ls_pcie_setup_ep(pcie);
 	} else {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Root Complex");
 			ls_pcie_setup_ctrl(pcie);
 	}
 
-- 
2.7.4

[PATCH 02/12] pci: ls_pcie_g4: Print pcie controller number starting from 1

[Wasim Khan]

Print pcie controller number starting from 1

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 drivers/pci/pcie_layerscape_gen4.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 428bfca..0226bde 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
  *
  * PCIe Gen4 driver for NXP Layerscape SoCs
  * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
@@ -472,7 +472,8 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 
 	pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 	if (!pcie->enabled) {
-		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+		printf("PCIe%d: %s disabled\n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name);
 		return 0;
 	}
 
@@ -522,10 +523,12 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	pcie->mode = readb(pcie->ccsr + PCI_HEADER_TYPE) & 0x7f;
 
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Endpoint");
 		ls_pcie_g4_setup_ep(pcie);
 	} else {
-		printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
+		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
+		       "Root Complex");
 		ls_pcie_g4_setup_ctrl(pcie);
 	}
 
-- 
2.7.4

[PATCH 03/12] arm: dts: lx2160a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-lx2160a.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index c62960e..dcf0073 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -279,7 +279,7 @@
 
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03480000 0x0 0x40000   /* LUT registers */
@@ -293,7 +293,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03580000 0x0 0x40000   /* LUT registers */
@@ -308,7 +308,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3600000 {
+	pcie3: pcie at 3600000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03680000 0x0 0x40000   /* LUT registers */
@@ -322,7 +322,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3700000 {
+	pcie4: pcie at 3700000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03700000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03780000 0x0 0x40000   /* LUT registers */
@@ -336,7 +336,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3800000 {
+	pcie5: pcie at 3800000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
@@ -350,7 +350,7 @@
 		ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
 	};
 
-	pcie at 3900000 {
+	pcie6: pcie at 3900000 {
 		compatible = "fsl,lx2160a-pcie";
 		reg = <0x00 0x03900000 0x0 0x80000   /* PAB registers */
 		       0x00 0x03980000 0x0 0x40000   /* LUT registers */
-- 
2.7.4

[PATCH 04/12] arm: dts: ls1046a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-ls1046a.dtsi | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 8673a5d..8a0c6fc 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Device Tree Include file for Freescale Layerscape-1046A family SoC.
+ * Device Tree Include file for NXP Layerscape-1046A family SoC.
  *
+ * Copyright 2020 NXP
  * Copyright (C) 2016, Freescale Semiconductor
  *
  * Mingkai Hu <mingkai.hu@nxp.com>
@@ -241,7 +242,7 @@
 			dr_mode = "host";
 		};
 
-		pcie at 3400000 {
+		pcie1: pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
@@ -257,7 +258,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie at 3500000 {
+		pcie2: pcie at 3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03580000 0x0 0x40000   /* lut registers */
@@ -274,7 +275,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie at 3600000 {
+		pcie3: pcie at 3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03680000 0x0 0x40000   /* lut registers */
-- 
2.7.4

[PATCH 05/12] arm: dts: ls2080a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-ls2080a.dtsi | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 90a0a3f..fae46c4 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
  *
+ * Copyright 2020 NXP
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  */
 
@@ -127,7 +128,7 @@
 		dr_mode = "host";
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@@ -142,7 +143,7 @@
 			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@@ -157,7 +158,7 @@
 			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3600000 {
+	pcie3: pcie at 3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */
@@ -172,7 +173,7 @@
 			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3700000 {
+	pcie4: pcie at 3700000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03780000 0x0 0x80000   /* lut registers */
-- 
2.7.4

[PATCH 06/12] arm: dts: ls1088a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-ls1088a.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index bf303c6..8de7998 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP ls1088a SOC common device tree source
  *
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
  */
 
 / {
@@ -129,7 +129,7 @@
 		dr_mode = "host";
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@@ -145,7 +145,7 @@
 			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@@ -161,7 +161,7 @@
 			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3600000 {
+	pcie3: pcie at 3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */
-- 
2.7.4

[PATCH 07/12] arm: dts: ls1012a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-ls1012a.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82..c401ba3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
+ * Copyright 2020 NXP
  * Copyright 2016 Freescale Semiconductor
  */
 
@@ -116,7 +117,7 @@
 			status = "disabled";
 		};
 
-		pcie at 3400000 {
+		pcie1: pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
-- 
2.7.4

[PATCH 08/12] arm: dts: ls1043a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-ls1043a.dtsi | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c..8ca57ea 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
  *
+ * Copyright 2020 NXP
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
@@ -240,7 +241,7 @@
 			dr_mode = "host";
 		};
 
-		pcie at 3400000 {
+		pcie1: pcie at 3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03410000 0x0 0x10000   /* lut registers */
@@ -255,7 +256,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie at 3500000 {
+		pcie2: pcie at 3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03510000 0x0 0x10000   /* lut registers */
@@ -271,7 +272,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie at 3600000 {
+		pcie3: pcie at 3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03610000 0x0 0x10000   /* lut registers */
-- 
2.7.4

[PATCH 09/12] arm: dts: ls1028a: add label to pcie nodes in dts

[Wasim Khan]

add label to pcie nodes in dts

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9911690..ccf1a8d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP ls1028a SOC common device tree source
  *
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  *
  */
 
@@ -85,7 +85,7 @@
 		status = "disabled";
 	};
 
-	pcie at 3400000 {
+	pcie1: pcie at 3400000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03400000 0x0 0x80000
 		       0x00 0x03480000 0x0 0x40000   /* lut registers */
@@ -101,7 +101,7 @@
 		       0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie at 3500000 {
+	pcie2: pcie at 3500000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03500000 0x0 0x80000
 		       0x00 0x03580000 0x0 0x40000   /* lut registers */
-- 
2.7.4

[PATCH 10/12] pci: layerscape: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 8KB space.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 drivers/pci/pcie_layerscape.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2f17176..8f64e53 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -493,6 +493,13 @@ static int ls_pcie_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie->cfg_res);
+	if (cfg_size < SZ_8K) {
+		printf("PCIe%d: %s Invalid size(0x%x) for resource \"config\",
+		       expected minimum 0x%x \n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name, cfg_size, SZ_8K);
+		return 0;
+	}
 	/*
 	 * Fix the pcie memory map address and PF control registers address
 	 * for LS2088A series SoCs
@@ -502,7 +509,6 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		cfg_size = fdt_resource_size(&pcie->cfg_res);
 		pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
-- 
2.7.4

[PATCH 11/12] pci: ls_pcie_g4: Add size check for config resource

[Wasim Khan]

resource "config" is required to have minimum 1KB space.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 drivers/pci/pcie_layerscape_gen4.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 0226bde..f9e3e04 100644
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -455,6 +455,7 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 	u32 link_ctrl_sta;
 	u32 val;
 	int ret;
+	fdt_size_t cfg_size;
 
 	pcie->bus = dev;
 
@@ -488,6 +489,14 @@ static int ls_pcie_g4_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie->cfg_res);
+	if (cfg_size < SZ_1K) {
+		printf("PCIe%d: %s Invalid size(0x%x) for resource \"config\",
+		       expected minimum 0x%x \n", PCIE_SRDS_PRTCL(pcie->idx),
+		       dev->name, cfg_size, SZ_1K);
+		return 0;
+	}
+
 	pcie->cfg = map_physmem(pcie->cfg_res.start,
 				fdt_resource_size(&pcie->cfg_res),
 				MAP_NOCACHE);
-- 
2.7.4

[PATCH 12/12] pci: layerscape: indentation correction

[Wasim Khan]

correct the indentation.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 drivers/pci/pcie_layerscape.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 8f64e53..60f5031 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -532,11 +532,11 @@ static int ls_pcie_probe(struct udevice *dev)
 	if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
 		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
 		       "Endpoint");
-			ls_pcie_setup_ep(pcie);
+		ls_pcie_setup_ep(pcie);
 	} else {
 		printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name,
 		       "Root Complex");
-			ls_pcie_setup_ctrl(pcie);
+		ls_pcie_setup_ctrl(pcie);
 	}
 
 	if (!ls_pcie_link_up(pcie)) {
-- 
2.7.4