* [v7, PATCH 0/7] add drm support for MT8183
@ 2020-07-23 2:03 ` Yongqiang Niu
0 siblings, 0 replies; 112+ messages in thread
From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu
This series are based on 5.8-rc1 and provide 7 patch
to support mediatek SOC MT8183
Change since v6
- move ddp component define into mtk_mmsys.h
- add mmsys private data to support different ic path connection
- add mt8183-mmsys.c to support 8183 path connection
- fix reviewed issue in v6
Change since v5
- fix reviewed issue in v5
base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219
Change since v4
- fix reviewed issue in v4
Change since v3
- fix reviewed issue in v3
- fix type error in v3
- fix conflict with iommu patch
Change since v2
- fix reviewed issue in v2
- add mutex node into dts file
Changes since v1:
- fix reviewed issue in v1
- add dts for mt8183 display nodes
- adjust display clock control flow in patch 22
- add vmap support for mediatek drm in patch 23
- fix page offset issue for mmap function in patch 24
- enable allow_fb_modifiers for mediatek drm in patch 25
Yongqiang Niu (7):
drm/mediatek: move ddp component define into mtk_mmsys.h
mtk-mmsys: add mmsys private data
mtk-mmsys: add mt8183 mmsys support
dt-bindings: mediatek: add rdma_fifo_size description for mt8183
display
arm64: dts: add display nodes for mt8183
drm/mediatek: add fifo_size into rdma private data
drm/mediatek: add support for mediatek SOC MT8183
.../bindings/display/mediatek/mediatek,disp.txt | 14 ++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +--
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 ++++
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mmsys/Makefile | 3 +
drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++
drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 276 ++++-----------------
include/linux/soc/mediatek/mtk-mmsys.h | 48 ++++
13 files changed, 756 insertions(+), 262 deletions(-)
create mode 100644 drivers/soc/mediatek/mmsys/Makefile
create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
--
1.8.1.1.dirty
^ permalink raw reply [flat|nested] 112+ messages in thread* [v7, PATCH 0/7] add drm support for MT8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel This series are based on 5.8-rc1 and provide 7 patch to support mediatek SOC MT8183 Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6 Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Yongqiang Niu (7): drm/mediatek: move ddp component define into mtk_mmsys.h mtk-mmsys: add mmsys private data mtk-mmsys: add mt8183 mmsys support dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display arm64: dts: add display nodes for mt8183 drm/mediatek: add fifo_size into rdma private data drm/mediatek: add support for mediatek SOC MT8183 .../bindings/display/mediatek/mediatek,disp.txt | 14 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 ++++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 3 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++ drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 276 ++++----------------- include/linux/soc/mediatek/mtk-mmsys.h | 48 ++++ 13 files changed, 756 insertions(+), 262 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 0/7] add drm support for MT8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This series are based on 5.8-rc1 and provide 7 patch to support mediatek SOC MT8183 Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6 Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Yongqiang Niu (7): drm/mediatek: move ddp component define into mtk_mmsys.h mtk-mmsys: add mmsys private data mtk-mmsys: add mt8183 mmsys support dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display arm64: dts: add display nodes for mt8183 drm/mediatek: add fifo_size into rdma private data drm/mediatek: add support for mediatek SOC MT8183 .../bindings/display/mediatek/mediatek,disp.txt | 14 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 ++++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 3 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++ drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 276 ++++----------------- include/linux/soc/mediatek/mtk-mmsys.h | 48 ++++ 13 files changed, 756 insertions(+), 262 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 0/7] add drm support for MT8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This series are based on 5.8-rc1 and provide 7 patch to support mediatek SOC MT8183 Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6 Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Yongqiang Niu (7): drm/mediatek: move ddp component define into mtk_mmsys.h mtk-mmsys: add mmsys private data mtk-mmsys: add mt8183 mmsys support dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display arm64: dts: add display nodes for mt8183 drm/mediatek: add fifo_size into rdma private data drm/mediatek: add support for mediatek SOC MT8183 .../bindings/display/mediatek/mediatek,disp.txt | 14 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 25 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 ++++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 3 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++ drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 276 ++++----------------- include/linux/soc/mediatek/mtk-mmsys.h | 48 ++++ 13 files changed, 756 insertions(+), 262 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu move ddp component defint into mtk_mmsys.h Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- drivers/soc/mediatek/mtk-mmsys.c | 4 +--- include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index debe363..161201f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H #include <linux/io.h> +#include <linux/soc/mediatek/mtk-mmsys.h> struct device; struct device_node; @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { MTK_DDP_COMP_TYPE_MAX, }; -enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL0, - DDP_COMPONENT_AAL1, - DDP_COMPONENT_BLS, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DPI0, - DDP_COMPONENT_DPI1, - DDP_COMPONENT_DSI0, - DDP_COMPONENT_DSI1, - DDP_COMPONENT_DSI2, - DDP_COMPONENT_DSI3, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD0, - DDP_COMPONENT_OD1, - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_OVL_2L1, - DDP_COMPONENT_OVL1, - DDP_COMPONENT_PWM0, - DDP_COMPONENT_PWM1, - DDP_COMPONENT_PWM2, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_RDMA2, - DDP_COMPONENT_UFOE, - DDP_COMPONENT_WDMA0, - DDP_COMPONENT_WDMA1, - DDP_COMPONENT_ID_MAX, -}; - struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a55f255..36ad66b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -5,13 +5,11 @@ */ #include <linux/device.h> +#include <linux/io.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" - #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 7bab5d9..2228bf6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,39 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_ddp_comp_id { + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_BLS, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSI0, + DDP_COMPONENT_DSI1, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_DSI3, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL1, + DDP_COMPONENT_PWM0, + DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_UFOE, + DDP_COMPONENT_WDMA0, + DDP_COMPONENT_WDMA1, + DDP_COMPONENT_ID_MAX, +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel move ddp component defint into mtk_mmsys.h Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- drivers/soc/mediatek/mtk-mmsys.c | 4 +--- include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index debe363..161201f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H #include <linux/io.h> +#include <linux/soc/mediatek/mtk-mmsys.h> struct device; struct device_node; @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { MTK_DDP_COMP_TYPE_MAX, }; -enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL0, - DDP_COMPONENT_AAL1, - DDP_COMPONENT_BLS, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DPI0, - DDP_COMPONENT_DPI1, - DDP_COMPONENT_DSI0, - DDP_COMPONENT_DSI1, - DDP_COMPONENT_DSI2, - DDP_COMPONENT_DSI3, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD0, - DDP_COMPONENT_OD1, - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_OVL_2L1, - DDP_COMPONENT_OVL1, - DDP_COMPONENT_PWM0, - DDP_COMPONENT_PWM1, - DDP_COMPONENT_PWM2, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_RDMA2, - DDP_COMPONENT_UFOE, - DDP_COMPONENT_WDMA0, - DDP_COMPONENT_WDMA1, - DDP_COMPONENT_ID_MAX, -}; - struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a55f255..36ad66b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -5,13 +5,11 @@ */ #include <linux/device.h> +#include <linux/io.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" - #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 7bab5d9..2228bf6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,39 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_ddp_comp_id { + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_BLS, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSI0, + DDP_COMPONENT_DSI1, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_DSI3, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL1, + DDP_COMPONENT_PWM0, + DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_UFOE, + DDP_COMPONENT_WDMA0, + DDP_COMPONENT_WDMA1, + DDP_COMPONENT_ID_MAX, +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel move ddp component defint into mtk_mmsys.h Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- drivers/soc/mediatek/mtk-mmsys.c | 4 +--- include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index debe363..161201f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H #include <linux/io.h> +#include <linux/soc/mediatek/mtk-mmsys.h> struct device; struct device_node; @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { MTK_DDP_COMP_TYPE_MAX, }; -enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL0, - DDP_COMPONENT_AAL1, - DDP_COMPONENT_BLS, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DPI0, - DDP_COMPONENT_DPI1, - DDP_COMPONENT_DSI0, - DDP_COMPONENT_DSI1, - DDP_COMPONENT_DSI2, - DDP_COMPONENT_DSI3, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD0, - DDP_COMPONENT_OD1, - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_OVL_2L1, - DDP_COMPONENT_OVL1, - DDP_COMPONENT_PWM0, - DDP_COMPONENT_PWM1, - DDP_COMPONENT_PWM2, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_RDMA2, - DDP_COMPONENT_UFOE, - DDP_COMPONENT_WDMA0, - DDP_COMPONENT_WDMA1, - DDP_COMPONENT_ID_MAX, -}; - struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a55f255..36ad66b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -5,13 +5,11 @@ */ #include <linux/device.h> +#include <linux/io.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" - #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 7bab5d9..2228bf6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,39 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_ddp_comp_id { + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_BLS, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSI0, + DDP_COMPONENT_DSI1, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_DSI3, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL1, + DDP_COMPONENT_PWM0, + DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_UFOE, + DDP_COMPONENT_WDMA0, + DDP_COMPONENT_WDMA1, + DDP_COMPONENT_ID_MAX, +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel move ddp component defint into mtk_mmsys.h Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- drivers/soc/mediatek/mtk-mmsys.c | 4 +--- include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index debe363..161201f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H #include <linux/io.h> +#include <linux/soc/mediatek/mtk-mmsys.h> struct device; struct device_node; @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { MTK_DDP_COMP_TYPE_MAX, }; -enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL0, - DDP_COMPONENT_AAL1, - DDP_COMPONENT_BLS, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DPI0, - DDP_COMPONENT_DPI1, - DDP_COMPONENT_DSI0, - DDP_COMPONENT_DSI1, - DDP_COMPONENT_DSI2, - DDP_COMPONENT_DSI3, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD0, - DDP_COMPONENT_OD1, - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_OVL_2L1, - DDP_COMPONENT_OVL1, - DDP_COMPONENT_PWM0, - DDP_COMPONENT_PWM1, - DDP_COMPONENT_PWM2, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_RDMA2, - DDP_COMPONENT_UFOE, - DDP_COMPONENT_WDMA0, - DDP_COMPONENT_WDMA1, - DDP_COMPONENT_ID_MAX, -}; - struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a55f255..36ad66b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -5,13 +5,11 @@ */ #include <linux/device.h> +#include <linux/io.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" - #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 7bab5d9..2228bf6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,39 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_ddp_comp_id { + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_BLS, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSI0, + DDP_COMPONENT_DSI1, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_DSI3, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL1, + DDP_COMPONENT_PWM0, + DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_UFOE, + DDP_COMPONENT_WDMA0, + DDP_COMPONENT_WDMA1, + DDP_COMPONENT_ID_MAX, +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 9:34 ` Enric Balletbo Serra -1 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:34 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, Linux ARM, moderated list:ARM/Mediatek SoC support Hi Yongqian Niu, Thank you for your patch Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > move ddp component defint into mtk_mmsys.h > There is a typo, should be "defines". But why you should move these defines to mtk-mmsys? > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index debe363..161201f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -7,6 +7,7 @@ > #define MTK_DRM_DDP_COMP_H > > #include <linux/io.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > > struct device; > struct device_node; > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > MTK_DDP_COMP_TYPE_MAX, > }; > > -enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL0, > - DDP_COMPONENT_AAL1, > - DDP_COMPONENT_BLS, > - DDP_COMPONENT_CCORR, > - DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_COLOR1, > - DDP_COMPONENT_DITHER, > - DDP_COMPONENT_DPI0, > - DDP_COMPONENT_DPI1, > - DDP_COMPONENT_DSI0, > - DDP_COMPONENT_DSI1, > - DDP_COMPONENT_DSI2, > - DDP_COMPONENT_DSI3, > - DDP_COMPONENT_GAMMA, > - DDP_COMPONENT_OD0, > - DDP_COMPONENT_OD1, > - DDP_COMPONENT_OVL0, > - DDP_COMPONENT_OVL_2L0, > - DDP_COMPONENT_OVL_2L1, > - DDP_COMPONENT_OVL1, > - DDP_COMPONENT_PWM0, > - DDP_COMPONENT_PWM1, > - DDP_COMPONENT_PWM2, > - DDP_COMPONENT_RDMA0, > - DDP_COMPONENT_RDMA1, > - DDP_COMPONENT_RDMA2, > - DDP_COMPONENT_UFOE, > - DDP_COMPONENT_WDMA0, > - DDP_COMPONENT_WDMA1, > - DDP_COMPONENT_ID_MAX, > -}; > - > struct mtk_ddp_comp; > struct cmdq_pkt; > struct mtk_ddp_comp_funcs { > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index a55f255..36ad66b 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,13 +5,11 @@ > */ > > #include <linux/device.h> > +#include <linux/io.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > - > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 7bab5d9..2228bf6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -9,6 +9,39 @@ > enum mtk_ddp_comp_id; > struct device; > > +enum mtk_ddp_comp_id { > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_BLS, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_DSI0, > + DDP_COMPONENT_DSI1, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_DSI3, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_PWM0, > + DDP_COMPONENT_PWM1, > + DDP_COMPONENT_PWM2, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_UFOE, > + DDP_COMPONENT_WDMA0, > + DDP_COMPONENT_WDMA1, > + DDP_COMPONENT_ID_MAX, > +}; > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 9:34 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:34 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi Yongqian Niu, Thank you for your patch Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > move ddp component defint into mtk_mmsys.h > There is a typo, should be "defines". But why you should move these defines to mtk-mmsys? > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index debe363..161201f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -7,6 +7,7 @@ > #define MTK_DRM_DDP_COMP_H > > #include <linux/io.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > > struct device; > struct device_node; > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > MTK_DDP_COMP_TYPE_MAX, > }; > > -enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL0, > - DDP_COMPONENT_AAL1, > - DDP_COMPONENT_BLS, > - DDP_COMPONENT_CCORR, > - DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_COLOR1, > - DDP_COMPONENT_DITHER, > - DDP_COMPONENT_DPI0, > - DDP_COMPONENT_DPI1, > - DDP_COMPONENT_DSI0, > - DDP_COMPONENT_DSI1, > - DDP_COMPONENT_DSI2, > - DDP_COMPONENT_DSI3, > - DDP_COMPONENT_GAMMA, > - DDP_COMPONENT_OD0, > - DDP_COMPONENT_OD1, > - DDP_COMPONENT_OVL0, > - DDP_COMPONENT_OVL_2L0, > - DDP_COMPONENT_OVL_2L1, > - DDP_COMPONENT_OVL1, > - DDP_COMPONENT_PWM0, > - DDP_COMPONENT_PWM1, > - DDP_COMPONENT_PWM2, > - DDP_COMPONENT_RDMA0, > - DDP_COMPONENT_RDMA1, > - DDP_COMPONENT_RDMA2, > - DDP_COMPONENT_UFOE, > - DDP_COMPONENT_WDMA0, > - DDP_COMPONENT_WDMA1, > - DDP_COMPONENT_ID_MAX, > -}; > - > struct mtk_ddp_comp; > struct cmdq_pkt; > struct mtk_ddp_comp_funcs { > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index a55f255..36ad66b 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,13 +5,11 @@ > */ > > #include <linux/device.h> > +#include <linux/io.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > - > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 7bab5d9..2228bf6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -9,6 +9,39 @@ > enum mtk_ddp_comp_id; > struct device; > > +enum mtk_ddp_comp_id { > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_BLS, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_DSI0, > + DDP_COMPONENT_DSI1, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_DSI3, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_PWM0, > + DDP_COMPONENT_PWM1, > + DDP_COMPONENT_PWM2, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_UFOE, > + DDP_COMPONENT_WDMA0, > + DDP_COMPONENT_WDMA1, > + DDP_COMPONENT_ID_MAX, > +}; > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 9:34 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:34 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, Linux ARM Hi Yongqian Niu, Thank you for your patch Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > move ddp component defint into mtk_mmsys.h > There is a typo, should be "defines". But why you should move these defines to mtk-mmsys? > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index debe363..161201f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -7,6 +7,7 @@ > #define MTK_DRM_DDP_COMP_H > > #include <linux/io.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > > struct device; > struct device_node; > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > MTK_DDP_COMP_TYPE_MAX, > }; > > -enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL0, > - DDP_COMPONENT_AAL1, > - DDP_COMPONENT_BLS, > - DDP_COMPONENT_CCORR, > - DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_COLOR1, > - DDP_COMPONENT_DITHER, > - DDP_COMPONENT_DPI0, > - DDP_COMPONENT_DPI1, > - DDP_COMPONENT_DSI0, > - DDP_COMPONENT_DSI1, > - DDP_COMPONENT_DSI2, > - DDP_COMPONENT_DSI3, > - DDP_COMPONENT_GAMMA, > - DDP_COMPONENT_OD0, > - DDP_COMPONENT_OD1, > - DDP_COMPONENT_OVL0, > - DDP_COMPONENT_OVL_2L0, > - DDP_COMPONENT_OVL_2L1, > - DDP_COMPONENT_OVL1, > - DDP_COMPONENT_PWM0, > - DDP_COMPONENT_PWM1, > - DDP_COMPONENT_PWM2, > - DDP_COMPONENT_RDMA0, > - DDP_COMPONENT_RDMA1, > - DDP_COMPONENT_RDMA2, > - DDP_COMPONENT_UFOE, > - DDP_COMPONENT_WDMA0, > - DDP_COMPONENT_WDMA1, > - DDP_COMPONENT_ID_MAX, > -}; > - > struct mtk_ddp_comp; > struct cmdq_pkt; > struct mtk_ddp_comp_funcs { > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index a55f255..36ad66b 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,13 +5,11 @@ > */ > > #include <linux/device.h> > +#include <linux/io.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > - > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 7bab5d9..2228bf6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -9,6 +9,39 @@ > enum mtk_ddp_comp_id; > struct device; > > +enum mtk_ddp_comp_id { > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_BLS, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_DSI0, > + DDP_COMPONENT_DSI1, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_DSI3, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_PWM0, > + DDP_COMPONENT_PWM1, > + DDP_COMPONENT_PWM2, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_UFOE, > + DDP_COMPONENT_WDMA0, > + DDP_COMPONENT_WDMA1, > + DDP_COMPONENT_ID_MAX, > +}; > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 9:34 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:34 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, Linux ARM Hi Yongqian Niu, Thank you for your patch Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > move ddp component defint into mtk_mmsys.h > There is a typo, should be "defines". But why you should move these defines to mtk-mmsys? > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index debe363..161201f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -7,6 +7,7 @@ > #define MTK_DRM_DDP_COMP_H > > #include <linux/io.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > > struct device; > struct device_node; > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > MTK_DDP_COMP_TYPE_MAX, > }; > > -enum mtk_ddp_comp_id { > - DDP_COMPONENT_AAL0, > - DDP_COMPONENT_AAL1, > - DDP_COMPONENT_BLS, > - DDP_COMPONENT_CCORR, > - DDP_COMPONENT_COLOR0, > - DDP_COMPONENT_COLOR1, > - DDP_COMPONENT_DITHER, > - DDP_COMPONENT_DPI0, > - DDP_COMPONENT_DPI1, > - DDP_COMPONENT_DSI0, > - DDP_COMPONENT_DSI1, > - DDP_COMPONENT_DSI2, > - DDP_COMPONENT_DSI3, > - DDP_COMPONENT_GAMMA, > - DDP_COMPONENT_OD0, > - DDP_COMPONENT_OD1, > - DDP_COMPONENT_OVL0, > - DDP_COMPONENT_OVL_2L0, > - DDP_COMPONENT_OVL_2L1, > - DDP_COMPONENT_OVL1, > - DDP_COMPONENT_PWM0, > - DDP_COMPONENT_PWM1, > - DDP_COMPONENT_PWM2, > - DDP_COMPONENT_RDMA0, > - DDP_COMPONENT_RDMA1, > - DDP_COMPONENT_RDMA2, > - DDP_COMPONENT_UFOE, > - DDP_COMPONENT_WDMA0, > - DDP_COMPONENT_WDMA1, > - DDP_COMPONENT_ID_MAX, > -}; > - > struct mtk_ddp_comp; > struct cmdq_pkt; > struct mtk_ddp_comp_funcs { > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index a55f255..36ad66b 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -5,13 +5,11 @@ > */ > > #include <linux/device.h> > +#include <linux/io.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > - > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 7bab5d9..2228bf6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -9,6 +9,39 @@ > enum mtk_ddp_comp_id; > struct device; > > +enum mtk_ddp_comp_id { > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_AAL1, > + DDP_COMPONENT_BLS, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_COLOR1, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DPI0, > + DDP_COMPONENT_DPI1, > + DDP_COMPONENT_DSI0, > + DDP_COMPONENT_DSI1, > + DDP_COMPONENT_DSI2, > + DDP_COMPONENT_DSI3, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_OD0, > + DDP_COMPONENT_OD1, > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL1, > + DDP_COMPONENT_PWM0, > + DDP_COMPONENT_PWM1, > + DDP_COMPONENT_PWM2, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_UFOE, > + DDP_COMPONENT_WDMA0, > + DDP_COMPONENT_WDMA1, > + DDP_COMPONENT_ID_MAX, > +}; > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h 2020-07-23 9:34 ` Enric Balletbo Serra (?) (?) @ 2020-07-23 10:04 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 10:04 UTC (permalink / raw) To: Enric Balletbo Serra Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, Linux ARM, moderated list:ARM/Mediatek SoC support On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include <linux/io.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include <linux/device.h> > > +#include <linux/io.h> > > #include <linux/of_device.h> > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 10:04 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 10:04 UTC (permalink / raw) To: Enric Balletbo Serra Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include <linux/io.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include <linux/device.h> > > +#include <linux/io.h> > > #include <linux/of_device.h> > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 10:04 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 10:04 UTC (permalink / raw) To: Enric Balletbo Serra Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, Linux ARM On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include <linux/io.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include <linux/device.h> > > +#include <linux/io.h> > > #include <linux/of_device.h> > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 10:04 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 10:04 UTC (permalink / raw) To: Enric Balletbo Serra Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, Linux ARM On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > Hi Yongqian Niu, > > Thank you for your patch > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > move ddp component defint into mtk_mmsys.h > > > > There is a typo, should be "defines". But why you should move these > defines to mtk-mmsys? > ck do not like this : > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" after remove this, we need move the ddp component define type error will fixed in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > index debe363..161201f 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > @@ -7,6 +7,7 @@ > > #define MTK_DRM_DDP_COMP_H > > > > #include <linux/io.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > struct device; > > struct device_node; > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > MTK_DDP_COMP_TYPE_MAX, > > }; > > > > -enum mtk_ddp_comp_id { > > - DDP_COMPONENT_AAL0, > > - DDP_COMPONENT_AAL1, > > - DDP_COMPONENT_BLS, > > - DDP_COMPONENT_CCORR, > > - DDP_COMPONENT_COLOR0, > > - DDP_COMPONENT_COLOR1, > > - DDP_COMPONENT_DITHER, > > - DDP_COMPONENT_DPI0, > > - DDP_COMPONENT_DPI1, > > - DDP_COMPONENT_DSI0, > > - DDP_COMPONENT_DSI1, > > - DDP_COMPONENT_DSI2, > > - DDP_COMPONENT_DSI3, > > - DDP_COMPONENT_GAMMA, > > - DDP_COMPONENT_OD0, > > - DDP_COMPONENT_OD1, > > - DDP_COMPONENT_OVL0, > > - DDP_COMPONENT_OVL_2L0, > > - DDP_COMPONENT_OVL_2L1, > > - DDP_COMPONENT_OVL1, > > - DDP_COMPONENT_PWM0, > > - DDP_COMPONENT_PWM1, > > - DDP_COMPONENT_PWM2, > > - DDP_COMPONENT_RDMA0, > > - DDP_COMPONENT_RDMA1, > > - DDP_COMPONENT_RDMA2, > > - DDP_COMPONENT_UFOE, > > - DDP_COMPONENT_WDMA0, > > - DDP_COMPONENT_WDMA1, > > - DDP_COMPONENT_ID_MAX, > > -}; > > - > > struct mtk_ddp_comp; > > struct cmdq_pkt; > > struct mtk_ddp_comp_funcs { > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index a55f255..36ad66b 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -5,13 +5,11 @@ > > */ > > > > #include <linux/device.h> > > +#include <linux/io.h> > > #include <linux/of_device.h> > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > - > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 7bab5d9..2228bf6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -9,6 +9,39 @@ > > enum mtk_ddp_comp_id; > > struct device; > > > > +enum mtk_ddp_comp_id { > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_AAL1, > > + DDP_COMPONENT_BLS, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_COLOR1, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DPI0, > > + DDP_COMPONENT_DPI1, > > + DDP_COMPONENT_DSI0, > > + DDP_COMPONENT_DSI1, > > + DDP_COMPONENT_DSI2, > > + DDP_COMPONENT_DSI3, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_OD0, > > + DDP_COMPONENT_OD1, > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL1, > > + DDP_COMPONENT_PWM0, > > + DDP_COMPONENT_PWM1, > > + DDP_COMPONENT_PWM2, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_RDMA2, > > + DDP_COMPONENT_UFOE, > > + DDP_COMPONENT_WDMA0, > > + DDP_COMPONENT_WDMA1, > > + DDP_COMPONENT_ID_MAX, > > +}; > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h 2020-07-23 10:04 ` Yongqiang Niu (?) (?) @ 2020-07-23 16:21 ` Chun-Kuang Hu -1 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-23 16:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Enric Balletbo Serra, Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, Linux ARM Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 下午6:06寫道： > > On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > > Hi Yongqian Niu, > > > > Thank you for your patch > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > move ddp component defint into mtk_mmsys.h > > > > > > > There is a typo, should be "defines". But why you should move these > > defines to mtk-mmsys? > > > > ck do not like this : > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" I think no one like this. > > after remove this, we need move the ddp component define > > type error will fixed in next version. > mmsys is the driver which control the routing of these ddp component, so the definition of mtk_ddp_comp_id should be placed in mtk-mmsys.h Regards, Chun-Kuang. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > index debe363..161201f 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > @@ -7,6 +7,7 @@ > > > #define MTK_DRM_DDP_COMP_H > > > > > > #include <linux/io.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > struct device; > > > struct device_node; > > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > > MTK_DDP_COMP_TYPE_MAX, > > > }; > > > > > > -enum mtk_ddp_comp_id { > > > - DDP_COMPONENT_AAL0, > > > - DDP_COMPONENT_AAL1, > > > - DDP_COMPONENT_BLS, > > > - DDP_COMPONENT_CCORR, > > > - DDP_COMPONENT_COLOR0, > > > - DDP_COMPONENT_COLOR1, > > > - DDP_COMPONENT_DITHER, > > > - DDP_COMPONENT_DPI0, > > > - DDP_COMPONENT_DPI1, > > > - DDP_COMPONENT_DSI0, > > > - DDP_COMPONENT_DSI1, > > > - DDP_COMPONENT_DSI2, > > > - DDP_COMPONENT_DSI3, > > > - DDP_COMPONENT_GAMMA, > > > - DDP_COMPONENT_OD0, > > > - DDP_COMPONENT_OD1, > > > - DDP_COMPONENT_OVL0, > > > - DDP_COMPONENT_OVL_2L0, > > > - DDP_COMPONENT_OVL_2L1, > > > - DDP_COMPONENT_OVL1, > > > - DDP_COMPONENT_PWM0, > > > - DDP_COMPONENT_PWM1, > > > - DDP_COMPONENT_PWM2, > > > - DDP_COMPONENT_RDMA0, > > > - DDP_COMPONENT_RDMA1, > > > - DDP_COMPONENT_RDMA2, > > > - DDP_COMPONENT_UFOE, > > > - DDP_COMPONENT_WDMA0, > > > - DDP_COMPONENT_WDMA1, > > > - DDP_COMPONENT_ID_MAX, > > > -}; > > > - > > > struct mtk_ddp_comp; > > > struct cmdq_pkt; > > > struct mtk_ddp_comp_funcs { > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > > index a55f255..36ad66b 100644 > > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > > @@ -5,13 +5,11 @@ > > > */ > > > > > > #include <linux/device.h> > > > +#include <linux/io.h> > > > #include <linux/of_device.h> > > > #include <linux/platform_device.h> > > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > > - > > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > > index 7bab5d9..2228bf6 100644 > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > > @@ -9,6 +9,39 @@ > > > enum mtk_ddp_comp_id; > > > struct device; > > > > > > +enum mtk_ddp_comp_id { > > > + DDP_COMPONENT_AAL0, > > > + DDP_COMPONENT_AAL1, > > > + DDP_COMPONENT_BLS, > > > + DDP_COMPONENT_CCORR, > > > + DDP_COMPONENT_COLOR0, > > > + DDP_COMPONENT_COLOR1, > > > + DDP_COMPONENT_DITHER, > > > + DDP_COMPONENT_DPI0, > > > + DDP_COMPONENT_DPI1, > > > + DDP_COMPONENT_DSI0, > > > + DDP_COMPONENT_DSI1, > > > + DDP_COMPONENT_DSI2, > > > + DDP_COMPONENT_DSI3, > > > + DDP_COMPONENT_GAMMA, > > > + DDP_COMPONENT_OD0, > > > + DDP_COMPONENT_OD1, > > > + DDP_COMPONENT_OVL0, > > > + DDP_COMPONENT_OVL_2L0, > > > + DDP_COMPONENT_OVL_2L1, > > > + DDP_COMPONENT_OVL1, > > > + DDP_COMPONENT_PWM0, > > > + DDP_COMPONENT_PWM1, > > > + DDP_COMPONENT_PWM2, > > > + DDP_COMPONENT_RDMA0, > > > + DDP_COMPONENT_RDMA1, > > > + DDP_COMPONENT_RDMA2, > > > + DDP_COMPONENT_UFOE, > > > + DDP_COMPONENT_WDMA0, > > > + DDP_COMPONENT_WDMA1, > > > + DDP_COMPONENT_ID_MAX, > > > +}; > > > + > > > void mtk_mmsys_ddp_connect(struct device *dev, > > > enum mtk_ddp_comp_id cur, > > > enum mtk_ddp_comp_id next); > > > -- > > > 1.8.1.1.dirty > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 16:21 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-23 16:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, linux-kernel, dri-devel, David Airlie, Rob Herring, moderated list:ARM/Mediatek SoC support, Matthias Brugger, Linux ARM Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 下午6:06寫道： > > On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > > Hi Yongqian Niu, > > > > Thank you for your patch > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > move ddp component defint into mtk_mmsys.h > > > > > > > There is a typo, should be "defines". But why you should move these > > defines to mtk-mmsys? > > > > ck do not like this : > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" I think no one like this. > > after remove this, we need move the ddp component define > > type error will fixed in next version. > mmsys is the driver which control the routing of these ddp component, so the definition of mtk_ddp_comp_id should be placed in mtk-mmsys.h Regards, Chun-Kuang. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > index debe363..161201f 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > @@ -7,6 +7,7 @@ > > > #define MTK_DRM_DDP_COMP_H > > > > > > #include <linux/io.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > struct device; > > > struct device_node; > > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > > MTK_DDP_COMP_TYPE_MAX, > > > }; > > > > > > -enum mtk_ddp_comp_id { > > > - DDP_COMPONENT_AAL0, > > > - DDP_COMPONENT_AAL1, > > > - DDP_COMPONENT_BLS, > > > - DDP_COMPONENT_CCORR, > > > - DDP_COMPONENT_COLOR0, > > > - DDP_COMPONENT_COLOR1, > > > - DDP_COMPONENT_DITHER, > > > - DDP_COMPONENT_DPI0, > > > - DDP_COMPONENT_DPI1, > > > - DDP_COMPONENT_DSI0, > > > - DDP_COMPONENT_DSI1, > > > - DDP_COMPONENT_DSI2, > > > - DDP_COMPONENT_DSI3, > > > - DDP_COMPONENT_GAMMA, > > > - DDP_COMPONENT_OD0, > > > - DDP_COMPONENT_OD1, > > > - DDP_COMPONENT_OVL0, > > > - DDP_COMPONENT_OVL_2L0, > > > - DDP_COMPONENT_OVL_2L1, > > > - DDP_COMPONENT_OVL1, > > > - DDP_COMPONENT_PWM0, > > > - DDP_COMPONENT_PWM1, > > > - DDP_COMPONENT_PWM2, > > > - DDP_COMPONENT_RDMA0, > > > - DDP_COMPONENT_RDMA1, > > > - DDP_COMPONENT_RDMA2, > > > - DDP_COMPONENT_UFOE, > > > - DDP_COMPONENT_WDMA0, > > > - DDP_COMPONENT_WDMA1, > > > - DDP_COMPONENT_ID_MAX, > > > -}; > > > - > > > struct mtk_ddp_comp; > > > struct cmdq_pkt; > > > struct mtk_ddp_comp_funcs { > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > > index a55f255..36ad66b 100644 > > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > > @@ -5,13 +5,11 @@ > > > */ > > > > > > #include <linux/device.h> > > > +#include <linux/io.h> > > > #include <linux/of_device.h> > > > #include <linux/platform_device.h> > > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > > - > > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > > index 7bab5d9..2228bf6 100644 > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > > @@ -9,6 +9,39 @@ > > > enum mtk_ddp_comp_id; > > > struct device; > > > > > > +enum mtk_ddp_comp_id { > > > + DDP_COMPONENT_AAL0, > > > + DDP_COMPONENT_AAL1, > > > + DDP_COMPONENT_BLS, > > > + DDP_COMPONENT_CCORR, > > > + DDP_COMPONENT_COLOR0, > > > + DDP_COMPONENT_COLOR1, > > > + DDP_COMPONENT_DITHER, > > > + DDP_COMPONENT_DPI0, > > > + DDP_COMPONENT_DPI1, > > > + DDP_COMPONENT_DSI0, > > > + DDP_COMPONENT_DSI1, > > > + DDP_COMPONENT_DSI2, > > > + DDP_COMPONENT_DSI3, > > > + DDP_COMPONENT_GAMMA, > > > + DDP_COMPONENT_OD0, > > > + DDP_COMPONENT_OD1, > > > + DDP_COMPONENT_OVL0, > > > + DDP_COMPONENT_OVL_2L0, > > > + DDP_COMPONENT_OVL_2L1, > > > + DDP_COMPONENT_OVL1, > > > + DDP_COMPONENT_PWM0, > > > + DDP_COMPONENT_PWM1, > > > + DDP_COMPONENT_PWM2, > > > + DDP_COMPONENT_RDMA0, > > > + DDP_COMPONENT_RDMA1, > > > + DDP_COMPONENT_RDMA2, > > > + DDP_COMPONENT_UFOE, > > > + DDP_COMPONENT_WDMA0, > > > + DDP_COMPONENT_WDMA1, > > > + DDP_COMPONENT_ID_MAX, > > > +}; > > > + > > > void mtk_mmsys_ddp_connect(struct device *dev, > > > enum mtk_ddp_comp_id cur, > > > enum mtk_ddp_comp_id next); > > > -- > > > 1.8.1.1.dirty > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 16:21 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-23 16:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, Enric Balletbo Serra, linux-kernel, dri-devel, David Airlie, CK Hu, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, Matthias Brugger, Linux ARM Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 下午6:06寫道： > > On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > > Hi Yongqian Niu, > > > > Thank you for your patch > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > move ddp component defint into mtk_mmsys.h > > > > > > > There is a typo, should be "defines". But why you should move these > > defines to mtk-mmsys? > > > > ck do not like this : > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" I think no one like this. > > after remove this, we need move the ddp component define > > type error will fixed in next version. > mmsys is the driver which control the routing of these ddp component, so the definition of mtk_ddp_comp_id should be placed in mtk-mmsys.h Regards, Chun-Kuang. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > index debe363..161201f 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > @@ -7,6 +7,7 @@ > > > #define MTK_DRM_DDP_COMP_H > > > > > > #include <linux/io.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > struct device; > > > struct device_node; > > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > > MTK_DDP_COMP_TYPE_MAX, > > > }; > > > > > > -enum mtk_ddp_comp_id { > > > - DDP_COMPONENT_AAL0, > > > - DDP_COMPONENT_AAL1, > > > - DDP_COMPONENT_BLS, > > > - DDP_COMPONENT_CCORR, > > > - DDP_COMPONENT_COLOR0, > > > - DDP_COMPONENT_COLOR1, > > > - DDP_COMPONENT_DITHER, > > > - DDP_COMPONENT_DPI0, > > > - DDP_COMPONENT_DPI1, > > > - DDP_COMPONENT_DSI0, > > > - DDP_COMPONENT_DSI1, > > > - DDP_COMPONENT_DSI2, > > > - DDP_COMPONENT_DSI3, > > > - DDP_COMPONENT_GAMMA, > > > - DDP_COMPONENT_OD0, > > > - DDP_COMPONENT_OD1, > > > - DDP_COMPONENT_OVL0, > > > - DDP_COMPONENT_OVL_2L0, > > > - DDP_COMPONENT_OVL_2L1, > > > - DDP_COMPONENT_OVL1, > > > - DDP_COMPONENT_PWM0, > > > - DDP_COMPONENT_PWM1, > > > - DDP_COMPONENT_PWM2, > > > - DDP_COMPONENT_RDMA0, > > > - DDP_COMPONENT_RDMA1, > > > - DDP_COMPONENT_RDMA2, > > > - DDP_COMPONENT_UFOE, > > > - DDP_COMPONENT_WDMA0, > > > - DDP_COMPONENT_WDMA1, > > > - DDP_COMPONENT_ID_MAX, > > > -}; > > > - > > > struct mtk_ddp_comp; > > > struct cmdq_pkt; > > > struct mtk_ddp_comp_funcs { > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > > index a55f255..36ad66b 100644 > > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > > @@ -5,13 +5,11 @@ > > > */ > > > > > > #include <linux/device.h> > > > +#include <linux/io.h> > > > #include <linux/of_device.h> > > > #include <linux/platform_device.h> > > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > > - > > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > > index 7bab5d9..2228bf6 100644 > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > > @@ -9,6 +9,39 @@ > > > enum mtk_ddp_comp_id; > > > struct device; > > > > > > +enum mtk_ddp_comp_id { > > > + DDP_COMPONENT_AAL0, > > > + DDP_COMPONENT_AAL1, > > > + DDP_COMPONENT_BLS, > > > + DDP_COMPONENT_CCORR, > > > + DDP_COMPONENT_COLOR0, > > > + DDP_COMPONENT_COLOR1, > > > + DDP_COMPONENT_DITHER, > > > + DDP_COMPONENT_DPI0, > > > + DDP_COMPONENT_DPI1, > > > + DDP_COMPONENT_DSI0, > > > + DDP_COMPONENT_DSI1, > > > + DDP_COMPONENT_DSI2, > > > + DDP_COMPONENT_DSI3, > > > + DDP_COMPONENT_GAMMA, > > > + DDP_COMPONENT_OD0, > > > + DDP_COMPONENT_OD1, > > > + DDP_COMPONENT_OVL0, > > > + DDP_COMPONENT_OVL_2L0, > > > + DDP_COMPONENT_OVL_2L1, > > > + DDP_COMPONENT_OVL1, > > > + DDP_COMPONENT_PWM0, > > > + DDP_COMPONENT_PWM1, > > > + DDP_COMPONENT_PWM2, > > > + DDP_COMPONENT_RDMA0, > > > + DDP_COMPONENT_RDMA1, > > > + DDP_COMPONENT_RDMA2, > > > + DDP_COMPONENT_UFOE, > > > + DDP_COMPONENT_WDMA0, > > > + DDP_COMPONENT_WDMA1, > > > + DDP_COMPONENT_ID_MAX, > > > +}; > > > + > > > void mtk_mmsys_ddp_connect(struct device *dev, > > > enum mtk_ddp_comp_id cur, > > > enum mtk_ddp_comp_id next); > > > -- > > > 1.8.1.1.dirty > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h @ 2020-07-23 16:21 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-23 16:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, Enric Balletbo Serra, linux-kernel, dri-devel, David Airlie, CK Hu, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, Matthias Brugger, Linux ARM Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 下午6:06寫道： > > On Thu, 2020-07-23 at 11:34 +0200, Enric Balletbo Serra wrote: > > Hi Yongqian Niu, > > > > Thank you for your patch > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > move ddp component defint into mtk_mmsys.h > > > > > > > There is a typo, should be "defines". But why you should move these > > defines to mtk-mmsys? > > > > ck do not like this : > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" I think no one like this. > > after remove this, we need move the ddp component define > > type error will fixed in next version. > mmsys is the driver which control the routing of these ddp component, so the definition of mtk_ddp_comp_id should be placed in mtk-mmsys.h Regards, Chun-Kuang. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- > > > drivers/soc/mediatek/mtk-mmsys.c | 4 +--- > > > include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ > > > 3 files changed, 35 insertions(+), 36 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > index debe363..161201f 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > > > @@ -7,6 +7,7 @@ > > > #define MTK_DRM_DDP_COMP_H > > > > > > #include <linux/io.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > struct device; > > > struct device_node; > > > @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { > > > MTK_DDP_COMP_TYPE_MAX, > > > }; > > > > > > -enum mtk_ddp_comp_id { > > > - DDP_COMPONENT_AAL0, > > > - DDP_COMPONENT_AAL1, > > > - DDP_COMPONENT_BLS, > > > - DDP_COMPONENT_CCORR, > > > - DDP_COMPONENT_COLOR0, > > > - DDP_COMPONENT_COLOR1, > > > - DDP_COMPONENT_DITHER, > > > - DDP_COMPONENT_DPI0, > > > - DDP_COMPONENT_DPI1, > > > - DDP_COMPONENT_DSI0, > > > - DDP_COMPONENT_DSI1, > > > - DDP_COMPONENT_DSI2, > > > - DDP_COMPONENT_DSI3, > > > - DDP_COMPONENT_GAMMA, > > > - DDP_COMPONENT_OD0, > > > - DDP_COMPONENT_OD1, > > > - DDP_COMPONENT_OVL0, > > > - DDP_COMPONENT_OVL_2L0, > > > - DDP_COMPONENT_OVL_2L1, > > > - DDP_COMPONENT_OVL1, > > > - DDP_COMPONENT_PWM0, > > > - DDP_COMPONENT_PWM1, > > > - DDP_COMPONENT_PWM2, > > > - DDP_COMPONENT_RDMA0, > > > - DDP_COMPONENT_RDMA1, > > > - DDP_COMPONENT_RDMA2, > > > - DDP_COMPONENT_UFOE, > > > - DDP_COMPONENT_WDMA0, > > > - DDP_COMPONENT_WDMA1, > > > - DDP_COMPONENT_ID_MAX, > > > -}; > > > - > > > struct mtk_ddp_comp; > > > struct cmdq_pkt; > > > struct mtk_ddp_comp_funcs { > > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > > index a55f255..36ad66b 100644 > > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > > @@ -5,13 +5,11 @@ > > > */ > > > > > > #include <linux/device.h> > > > +#include <linux/io.h> > > > #include <linux/of_device.h> > > > #include <linux/platform_device.h> > > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" > > > -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" > > > - > > > #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > > index 7bab5d9..2228bf6 100644 > > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > > @@ -9,6 +9,39 @@ > > > enum mtk_ddp_comp_id; > > > struct device; > > > > > > +enum mtk_ddp_comp_id { > > > + DDP_COMPONENT_AAL0, > > > + DDP_COMPONENT_AAL1, > > > + DDP_COMPONENT_BLS, > > > + DDP_COMPONENT_CCORR, > > > + DDP_COMPONENT_COLOR0, > > > + DDP_COMPONENT_COLOR1, > > > + DDP_COMPONENT_DITHER, > > > + DDP_COMPONENT_DPI0, > > > + DDP_COMPONENT_DPI1, > > > + DDP_COMPONENT_DSI0, > > > + DDP_COMPONENT_DSI1, > > > + DDP_COMPONENT_DSI2, > > > + DDP_COMPONENT_DSI3, > > > + DDP_COMPONENT_GAMMA, > > > + DDP_COMPONENT_OD0, > > > + DDP_COMPONENT_OD1, > > > + DDP_COMPONENT_OVL0, > > > + DDP_COMPONENT_OVL_2L0, > > > + DDP_COMPONENT_OVL_2L1, > > > + DDP_COMPONENT_OVL1, > > > + DDP_COMPONENT_PWM0, > > > + DDP_COMPONENT_PWM1, > > > + DDP_COMPONENT_PWM2, > > > + DDP_COMPONENT_RDMA0, > > > + DDP_COMPONENT_RDMA1, > > > + DDP_COMPONENT_RDMA2, > > > + DDP_COMPONENT_UFOE, > > > + DDP_COMPONENT_WDMA0, > > > + DDP_COMPONENT_WDMA1, > > > + DDP_COMPONENT_ID_MAX, > > > +}; > > > + > > > void mtk_mmsys_ddp_connect(struct device *dev, > > > enum mtk_ddp_comp_id cur, > > > enum mtk_ddp_comp_id next); > > > -- > > > 1.8.1.1.dirty > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 2/7] mtk-mmsys: add mmsys private data 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu add mmsys private data Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ 5 files changed, 314 insertions(+), 225 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 2afa7b9..b37ac2c 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..33b0dab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += mt2701-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..b8e53b0 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt2701-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 36ad66b..605b992 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -10,267 +10,63 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const char *mmsys_driver; +}; + +struct mtk_mmsys_private_data { + void __iomem *config_regs; + struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); + priv_funcs->sout_sel(config_regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs) +{ + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + + private->funcs = funcs; +} + static int mtk_mmsys_probe(struct platform_device *pdev) { const struct mtk_mmsys_driver_data *data; struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; + struct platform_device *mm; void __iomem *config_regs; struct resource *mem; int ret; + struct mtk_mmsys_private_data *private; + + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); + if (!private) + return -ENOMEM; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); config_regs = devm_ioremap_resource(dev, mem); @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) ret); return ret; } + private->config_regs = config_regs; - platform_set_drvdata(pdev, config_regs); + platform_set_drvdata(pdev, private); data = of_device_get_match_data(&pdev->dev); @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (IS_ERR(clks)) return PTR_ERR(clks); + mm = platform_device_register_data(&pdev->dev, + data->mmsys_driver, + PLATFORM_DEVID_AUTO, + NULL, + 0); + if (IS_ERR(mm)) + return PTR_ERR(mm); + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(drm)) { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..89185c6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs); + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel add mmsys private data Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ 5 files changed, 314 insertions(+), 225 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 2afa7b9..b37ac2c 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..33b0dab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += mt2701-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..b8e53b0 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt2701-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 36ad66b..605b992 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -10,267 +10,63 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const char *mmsys_driver; +}; + +struct mtk_mmsys_private_data { + void __iomem *config_regs; + struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); + priv_funcs->sout_sel(config_regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs) +{ + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + + private->funcs = funcs; +} + static int mtk_mmsys_probe(struct platform_device *pdev) { const struct mtk_mmsys_driver_data *data; struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; + struct platform_device *mm; void __iomem *config_regs; struct resource *mem; int ret; + struct mtk_mmsys_private_data *private; + + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); + if (!private) + return -ENOMEM; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); config_regs = devm_ioremap_resource(dev, mem); @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) ret); return ret; } + private->config_regs = config_regs; - platform_set_drvdata(pdev, config_regs); + platform_set_drvdata(pdev, private); data = of_device_get_match_data(&pdev->dev); @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (IS_ERR(clks)) return PTR_ERR(clks); + mm = platform_device_register_data(&pdev->dev, + data->mmsys_driver, + PLATFORM_DEVID_AUTO, + NULL, + 0); + if (IS_ERR(mm)) + return PTR_ERR(mm); + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(drm)) { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..89185c6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs); + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel add mmsys private data Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ 5 files changed, 314 insertions(+), 225 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 2afa7b9..b37ac2c 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..33b0dab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += mt2701-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..b8e53b0 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt2701-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 36ad66b..605b992 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -10,267 +10,63 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const char *mmsys_driver; +}; + +struct mtk_mmsys_private_data { + void __iomem *config_regs; + struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); + priv_funcs->sout_sel(config_regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs) +{ + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + + private->funcs = funcs; +} + static int mtk_mmsys_probe(struct platform_device *pdev) { const struct mtk_mmsys_driver_data *data; struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; + struct platform_device *mm; void __iomem *config_regs; struct resource *mem; int ret; + struct mtk_mmsys_private_data *private; + + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); + if (!private) + return -ENOMEM; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); config_regs = devm_ioremap_resource(dev, mem); @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) ret); return ret; } + private->config_regs = config_regs; - platform_set_drvdata(pdev, config_regs); + platform_set_drvdata(pdev, private); data = of_device_get_match_data(&pdev->dev); @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (IS_ERR(clks)) return PTR_ERR(clks); + mm = platform_device_register_data(&pdev->dev, + data->mmsys_driver, + PLATFORM_DEVID_AUTO, + NULL, + 0); + if (IS_ERR(mm)) + return PTR_ERR(mm); + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(drm)) { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..89185c6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs); + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel add mmsys private data Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ 5 files changed, 314 insertions(+), 225 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 2afa7b9..b37ac2c 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..33b0dab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += mt2701-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..b8e53b0 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt2701-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 36ad66b..605b992 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -10,267 +10,63 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const char *mmsys_driver; +}; + +struct mtk_mmsys_private_data { + void __iomem *config_regs; + struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .mmsys_driver = "mt2701-mmsys", }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); + priv_funcs->sout_sel(config_regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { - void __iomem *config_regs = dev_get_drvdata(dev); + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + void __iomem *config_regs = private->config_regs; + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; unsigned int addr, value, reg; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = priv_funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = priv_funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs) +{ + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); + + private->funcs = funcs; +} + static int mtk_mmsys_probe(struct platform_device *pdev) { const struct mtk_mmsys_driver_data *data; struct device *dev = &pdev->dev; struct platform_device *clks; struct platform_device *drm; + struct platform_device *mm; void __iomem *config_regs; struct resource *mem; int ret; + struct mtk_mmsys_private_data *private; + + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); + if (!private) + return -ENOMEM; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); config_regs = devm_ioremap_resource(dev, mem); @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) ret); return ret; } + private->config_regs = config_regs; - platform_set_drvdata(pdev, config_regs); + platform_set_drvdata(pdev, private); data = of_device_get_match_data(&pdev->dev); @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) if (IS_ERR(clks)) return PTR_ERR(clks); + mm = platform_device_register_data(&pdev->dev, + data->mmsys_driver, + PLATFORM_DEVID_AUTO, + NULL, + 0); + if (IS_ERR(mm)) + return PTR_ERR(mm); + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(drm)) { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..89185c6 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +void mtk_mmsys_register_conn_funcs(struct device *dev, + struct mtk_mmsys_conn_funcs *funcs); + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 9:32 ` Enric Balletbo Serra -1 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:32 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi Yongqiang Niu, Thank you for your patch. Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > add mmsys private data > I think this change requires a better explanation of what you are doing. Although I'm really uncomfortable with this change, why you need to create a new mt2701-mmsys file? > Feature: drm/mediatek Remove this. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ Can't be reused this function for all devices? You did in the previous series, why not now? > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) Same question for this function > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt2701-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 36ad66b..605b992 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -10,267 +10,63 @@ > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > - > struct mtk_mmsys_driver_data { > const char *clk_driver; > + const char *mmsys_driver; > +}; > + What about doing this +struct mtk_mmsys_reg_data { + u32 ovl0_mout_en; +}; > +struct mtk_mmsys_private_data { > + void __iomem *config_regs; > + struct mtk_mmsys_conn_funcs *funcs; And instead of point to the funcs add the registers data here. const struct mtk_mmsys_reg_data regs; > }; > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > + .mmsys_driver = "mt2701-mmsys", And here + .regs = { + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, + }, AFAICS these registers are only used here, so you can get them per SoC and configure properly > }; > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > .clk_driver = "clk-mt2712-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > .clk_driver = "clk-mt6779-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > .clk_driver = "clk-mt6797-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .clk_driver = "clk-mt8173-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > }; > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ And you can do here: + const struct mtk_mmsys_driver_data *data; + + data = of_device_get_match_data(dev); And then use data->regs.ovl0_mout_en where you need it. > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; + value = data->regs.ovl0_mout_en And do the same for all the different registers per SoC > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > } > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + priv_funcs->sout_sel(config_regs, cur, next); > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > } > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs) > +{ > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + > + private->funcs = funcs; > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > const struct mtk_mmsys_driver_data *data; > struct device *dev = &pdev->dev; > struct platform_device *clks; > struct platform_device *drm; > + struct platform_device *mm; > void __iomem *config_regs; > struct resource *mem; > int ret; > + struct mtk_mmsys_private_data *private; > + > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > + if (!private) > + return -ENOMEM; > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > config_regs = devm_ioremap_resource(dev, mem); > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > ret); > return ret; > } > + private->config_regs = config_regs; > > - platform_set_drvdata(pdev, config_regs); > + platform_set_drvdata(pdev, private); > > data = of_device_get_match_data(&pdev->dev); > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > if (IS_ERR(clks)) > return PTR_ERR(clks); > > + mm = platform_device_register_data(&pdev->dev, > + data->mmsys_driver, > + PLATFORM_DEVID_AUTO, > + NULL, > + 0); > + if (IS_ERR(mm)) > + return PTR_ERR(mm); > + > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > PLATFORM_DEVID_AUTO, NULL, 0); > if (IS_ERR(drm)) { > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..89185c6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_ID_MAX, > }; > > +struct mtk_mmsys_conn_funcs { > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + void (*sout_sel)(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > +}; > + > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs); > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-23 9:32 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:32 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi Yongqiang Niu, Thank you for your patch. Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > add mmsys private data > I think this change requires a better explanation of what you are doing. Although I'm really uncomfortable with this change, why you need to create a new mt2701-mmsys file? > Feature: drm/mediatek Remove this. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ Can't be reused this function for all devices? You did in the previous series, why not now? > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) Same question for this function > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt2701-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 36ad66b..605b992 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -10,267 +10,63 @@ > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > - > struct mtk_mmsys_driver_data { > const char *clk_driver; > + const char *mmsys_driver; > +}; > + What about doing this +struct mtk_mmsys_reg_data { + u32 ovl0_mout_en; +}; > +struct mtk_mmsys_private_data { > + void __iomem *config_regs; > + struct mtk_mmsys_conn_funcs *funcs; And instead of point to the funcs add the registers data here. const struct mtk_mmsys_reg_data regs; > }; > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > + .mmsys_driver = "mt2701-mmsys", And here + .regs = { + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, + }, AFAICS these registers are only used here, so you can get them per SoC and configure properly > }; > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > .clk_driver = "clk-mt2712-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > .clk_driver = "clk-mt6779-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > .clk_driver = "clk-mt6797-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .clk_driver = "clk-mt8173-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > }; > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ And you can do here: + const struct mtk_mmsys_driver_data *data; + + data = of_device_get_match_data(dev); And then use data->regs.ovl0_mout_en where you need it. > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; + value = data->regs.ovl0_mout_en And do the same for all the different registers per SoC > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > } > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + priv_funcs->sout_sel(config_regs, cur, next); > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > } > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs) > +{ > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + > + private->funcs = funcs; > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > const struct mtk_mmsys_driver_data *data; > struct device *dev = &pdev->dev; > struct platform_device *clks; > struct platform_device *drm; > + struct platform_device *mm; > void __iomem *config_regs; > struct resource *mem; > int ret; > + struct mtk_mmsys_private_data *private; > + > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > + if (!private) > + return -ENOMEM; > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > config_regs = devm_ioremap_resource(dev, mem); > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > ret); > return ret; > } > + private->config_regs = config_regs; > > - platform_set_drvdata(pdev, config_regs); > + platform_set_drvdata(pdev, private); > > data = of_device_get_match_data(&pdev->dev); > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > if (IS_ERR(clks)) > return PTR_ERR(clks); > > + mm = platform_device_register_data(&pdev->dev, > + data->mmsys_driver, > + PLATFORM_DEVID_AUTO, > + NULL, > + 0); > + if (IS_ERR(mm)) > + return PTR_ERR(mm); > + > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > PLATFORM_DEVID_AUTO, NULL, 0); > if (IS_ERR(drm)) { > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..89185c6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_ID_MAX, > }; > > +struct mtk_mmsys_conn_funcs { > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + void (*sout_sel)(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > +}; > + > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs); > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-23 9:32 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:32 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi Yongqiang Niu, Thank you for your patch. Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > add mmsys private data > I think this change requires a better explanation of what you are doing. Although I'm really uncomfortable with this change, why you need to create a new mt2701-mmsys file? > Feature: drm/mediatek Remove this. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ Can't be reused this function for all devices? You did in the previous series, why not now? > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) Same question for this function > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt2701-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 36ad66b..605b992 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -10,267 +10,63 @@ > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > - > struct mtk_mmsys_driver_data { > const char *clk_driver; > + const char *mmsys_driver; > +}; > + What about doing this +struct mtk_mmsys_reg_data { + u32 ovl0_mout_en; +}; > +struct mtk_mmsys_private_data { > + void __iomem *config_regs; > + struct mtk_mmsys_conn_funcs *funcs; And instead of point to the funcs add the registers data here. const struct mtk_mmsys_reg_data regs; > }; > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > + .mmsys_driver = "mt2701-mmsys", And here + .regs = { + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, + }, AFAICS these registers are only used here, so you can get them per SoC and configure properly > }; > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > .clk_driver = "clk-mt2712-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > .clk_driver = "clk-mt6779-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > .clk_driver = "clk-mt6797-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .clk_driver = "clk-mt8173-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > }; > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ And you can do here: + const struct mtk_mmsys_driver_data *data; + + data = of_device_get_match_data(dev); And then use data->regs.ovl0_mout_en where you need it. > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; + value = data->regs.ovl0_mout_en And do the same for all the different registers per SoC > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > } > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + priv_funcs->sout_sel(config_regs, cur, next); > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > } > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs) > +{ > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + > + private->funcs = funcs; > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > const struct mtk_mmsys_driver_data *data; > struct device *dev = &pdev->dev; > struct platform_device *clks; > struct platform_device *drm; > + struct platform_device *mm; > void __iomem *config_regs; > struct resource *mem; > int ret; > + struct mtk_mmsys_private_data *private; > + > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > + if (!private) > + return -ENOMEM; > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > config_regs = devm_ioremap_resource(dev, mem); > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > ret); > return ret; > } > + private->config_regs = config_regs; > > - platform_set_drvdata(pdev, config_regs); > + platform_set_drvdata(pdev, private); > > data = of_device_get_match_data(&pdev->dev); > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > if (IS_ERR(clks)) > return PTR_ERR(clks); > > + mm = platform_device_register_data(&pdev->dev, > + data->mmsys_driver, > + PLATFORM_DEVID_AUTO, > + NULL, > + 0); > + if (IS_ERR(mm)) > + return PTR_ERR(mm); > + > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > PLATFORM_DEVID_AUTO, NULL, 0); > if (IS_ERR(drm)) { > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..89185c6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_ID_MAX, > }; > > +struct mtk_mmsys_conn_funcs { > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + void (*sout_sel)(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > +}; > + > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs); > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-23 9:32 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-23 9:32 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi Yongqiang Niu, Thank you for your patch. Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 de jul. 2020 a les 4:05: > > add mmsys private data > I think this change requires a better explanation of what you are doing. Although I'm really uncomfortable with this change, why you need to create a new mt2701-mmsys file? > Feature: drm/mediatek Remove this. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ Can't be reused this function for all devices? You did in the previous series, why not now? > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) Same question for this function > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt2701-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 36ad66b..605b992 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -10,267 +10,63 @@ > #include <linux/platform_device.h> > #include <linux/soc/mediatek/mtk-mmsys.h> > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > - > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > - > -#define OVL0_MOUT_EN_COLOR0 0x1 > -#define OD_MOUT_EN_RDMA0 0x1 > -#define OD1_MOUT_EN_RDMA1 BIT(16) > -#define UFOE_MOUT_EN_DSI0 0x1 > -#define COLOR0_SEL_IN_OVL0 0x1 > -#define OVL1_MOUT_EN_COLOR1 0x1 > -#define GAMMA_MOUT_EN_RDMA1 0x1 > -#define RDMA0_SOUT_DPI0 0x2 > -#define RDMA0_SOUT_DPI1 0x3 > -#define RDMA0_SOUT_DSI1 0x1 > -#define RDMA0_SOUT_DSI2 0x4 > -#define RDMA0_SOUT_DSI3 0x5 > -#define RDMA1_SOUT_DPI0 0x2 > -#define RDMA1_SOUT_DPI1 0x3 > -#define RDMA1_SOUT_DSI1 0x1 > -#define RDMA1_SOUT_DSI2 0x4 > -#define RDMA1_SOUT_DSI3 0x5 > -#define RDMA2_SOUT_DPI0 0x2 > -#define RDMA2_SOUT_DPI1 0x3 > -#define RDMA2_SOUT_DSI1 0x1 > -#define RDMA2_SOUT_DSI2 0x4 > -#define RDMA2_SOUT_DSI3 0x5 > -#define DPI0_SEL_IN_RDMA1 0x1 > -#define DPI0_SEL_IN_RDMA2 0x3 > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > -#define DSI0_SEL_IN_RDMA1 0x1 > -#define DSI0_SEL_IN_RDMA2 0x4 > -#define DSI1_SEL_IN_RDMA1 0x1 > -#define DSI1_SEL_IN_RDMA2 0x4 > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > -#define COLOR1_SEL_IN_OVL1 0x1 > - > -#define OVL_MOUT_EN_RDMA 0x1 > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > -#define DSI_SEL_IN_BLS 0x0 > -#define DPI_SEL_IN_BLS 0x0 > -#define DSI_SEL_IN_RDMA 0x1 > - > struct mtk_mmsys_driver_data { > const char *clk_driver; > + const char *mmsys_driver; > +}; > + What about doing this +struct mtk_mmsys_reg_data { + u32 ovl0_mout_en; +}; > +struct mtk_mmsys_private_data { > + void __iomem *config_regs; > + struct mtk_mmsys_conn_funcs *funcs; And instead of point to the funcs add the registers data here. const struct mtk_mmsys_reg_data regs; > }; > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > + .mmsys_driver = "mt2701-mmsys", And here + .regs = { + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, + }, AFAICS these registers are only used here, so you can get them per SoC and configure properly > }; > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > .clk_driver = "clk-mt2712-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > .clk_driver = "clk-mt6779-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > .clk_driver = "clk-mt6797-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > .clk_driver = "clk-mt8173-mm", > + .mmsys_driver = "mt2701-mmsys", > }; > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > }; > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ And you can do here: + const struct mtk_mmsys_driver_data *data; + + data = of_device_get_match_data(dev); And then use data->regs.ovl0_mout_en where you need it. > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > - value = OVL0_MOUT_EN_COLOR0; > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > - value = OVL_MOUT_EN_RDMA; + value = data->regs.ovl0_mout_en And do the same for all the different registers per SoC > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD_MOUT_EN_RDMA0; > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > - value = UFOE_MOUT_EN_DSI0; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > - value = OVL1_MOUT_EN_COLOR1; > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > - value = GAMMA_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > - value = OD1_MOUT_EN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > - value = RDMA0_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DSI3; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > - value = RDMA1_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI0; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DPI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > - value = RDMA2_SOUT_DSI3; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next, > - unsigned int *addr) > -{ > - unsigned int value; > - > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > - value = COLOR0_SEL_IN_OVL0; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI3_SEL_IN_RDMA1; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > - value = DPI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI0_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > - value = DSI1_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI2_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > - value = DSI3_SEL_IN_RDMA2; > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > - value = COLOR1_SEL_IN_OVL1; > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - *addr = DISP_REG_CONFIG_DSI_SEL; > - value = DSI_SEL_IN_BLS; > - } else { > - value = 0; > - } > - > - return value; > -} > - > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > - enum mtk_ddp_comp_id cur, > - enum mtk_ddp_comp_id next) > -{ > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > - config_regs + DISP_REG_CONFIG_OUT_SEL); > - writel_relaxed(DSI_SEL_IN_RDMA, > - config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > - } > -} > - > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > } > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > + priv_funcs->sout_sel(config_regs, cur, next); > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) | value; > writel_relaxed(reg, config_regs + addr); > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next) > { > - void __iomem *config_regs = dev_get_drvdata(dev); > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + void __iomem *config_regs = private->config_regs; > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > unsigned int addr, value, reg; > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > + value = priv_funcs->mout_en(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > } > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > + value = priv_funcs->sel_in(cur, next, &addr); > if (value) { > reg = readl_relaxed(config_regs + addr) & ~value; > writel_relaxed(reg, config_regs + addr); > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs) > +{ > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > + > + private->funcs = funcs; > +} > + > static int mtk_mmsys_probe(struct platform_device *pdev) > { > const struct mtk_mmsys_driver_data *data; > struct device *dev = &pdev->dev; > struct platform_device *clks; > struct platform_device *drm; > + struct platform_device *mm; > void __iomem *config_regs; > struct resource *mem; > int ret; > + struct mtk_mmsys_private_data *private; > + > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > + if (!private) > + return -ENOMEM; > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > config_regs = devm_ioremap_resource(dev, mem); > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > ret); > return ret; > } > + private->config_regs = config_regs; > > - platform_set_drvdata(pdev, config_regs); > + platform_set_drvdata(pdev, private); > > data = of_device_get_match_data(&pdev->dev); > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > if (IS_ERR(clks)) > return PTR_ERR(clks); > > + mm = platform_device_register_data(&pdev->dev, > + data->mmsys_driver, > + PLATFORM_DEVID_AUTO, > + NULL, > + 0); > + if (IS_ERR(mm)) > + return PTR_ERR(mm); > + > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > PLATFORM_DEVID_AUTO, NULL, 0); > if (IS_ERR(drm)) { > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..89185c6 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_ID_MAX, > }; > > +struct mtk_mmsys_conn_funcs { > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > + void (*sout_sel)(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next); > +}; > + > +void mtk_mmsys_register_conn_funcs(struct device *dev, > + struct mtk_mmsys_conn_funcs *funcs); > + > void mtk_mmsys_ddp_connect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data 2020-07-23 9:32 ` Enric Balletbo Serra (?) (?) @ 2020-07-25 3:27 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:27 UTC (permalink / raw) To: Enric Balletbo Serra Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > Hi Yongqiang Niu, > > Thank you for your patch. > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > add mmsys private data > > > > I think this change requires a better explanation of what you are > doing. Although I'm really uncomfortable with this change, why you > need to create a new mt2701-mmsys file? reason: 1.there will more and more Mediatek Soc upstream, and the display path connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and mtk_mmsys_ddp_sout_sel will complicated more and more, 2. many of the connection are only used in some SoC, and useless for other SoC and not readable, 3. if we add a new SoC connection, we need check is this affect other Soc, > > > Feature: drm/mediatek > > Remove this. next version will remove this > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > Can't be reused this function for all devices? You did in the previous > series, why not now? can not reused, that why need add mmsys private data like before version. but that still not a good idea. the next path like this will be more readable, and more easy to maintain https://patchwork.kernel.org/patch/11679539/ > > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > Same question for this function > > > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > +}; > > + > > +static int mmsys_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + > > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > > + > > + return 0; > > +} > > + > > +static struct platform_driver mmsys_drv = { > > + .probe = mmsys_probe, > > + .driver = { > > + .name = "mt2701-mmsys", > > + }, > > +}; > > + > > +builtin_platform_driver(mmsys_drv); > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index 36ad66b..605b992 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -10,267 +10,63 @@ > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > - > > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > > - > > -#define OVL0_MOUT_EN_COLOR0 0x1 > > -#define OD_MOUT_EN_RDMA0 0x1 > > -#define OD1_MOUT_EN_RDMA1 BIT(16) > > -#define UFOE_MOUT_EN_DSI0 0x1 > > -#define COLOR0_SEL_IN_OVL0 0x1 > > -#define OVL1_MOUT_EN_COLOR1 0x1 > > -#define GAMMA_MOUT_EN_RDMA1 0x1 > > -#define RDMA0_SOUT_DPI0 0x2 > > -#define RDMA0_SOUT_DPI1 0x3 > > -#define RDMA0_SOUT_DSI1 0x1 > > -#define RDMA0_SOUT_DSI2 0x4 > > -#define RDMA0_SOUT_DSI3 0x5 > > -#define RDMA1_SOUT_DPI0 0x2 > > -#define RDMA1_SOUT_DPI1 0x3 > > -#define RDMA1_SOUT_DSI1 0x1 > > -#define RDMA1_SOUT_DSI2 0x4 > > -#define RDMA1_SOUT_DSI3 0x5 > > -#define RDMA2_SOUT_DPI0 0x2 > > -#define RDMA2_SOUT_DPI1 0x3 > > -#define RDMA2_SOUT_DSI1 0x1 > > -#define RDMA2_SOUT_DSI2 0x4 > > -#define RDMA2_SOUT_DSI3 0x5 > > -#define DPI0_SEL_IN_RDMA1 0x1 > > -#define DPI0_SEL_IN_RDMA2 0x3 > > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > -#define DSI0_SEL_IN_RDMA1 0x1 > > -#define DSI0_SEL_IN_RDMA2 0x4 > > -#define DSI1_SEL_IN_RDMA1 0x1 > > -#define DSI1_SEL_IN_RDMA2 0x4 > > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > -#define COLOR1_SEL_IN_OVL1 0x1 > > - > > -#define OVL_MOUT_EN_RDMA 0x1 > > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > -#define DSI_SEL_IN_BLS 0x0 > > -#define DPI_SEL_IN_BLS 0x0 > > -#define DSI_SEL_IN_RDMA 0x1 > > - > > struct mtk_mmsys_driver_data { > > const char *clk_driver; > > + const char *mmsys_driver; > > +}; > > + > > What about doing this > > +struct mtk_mmsys_reg_data { > + u32 ovl0_mout_en; > +}; > > > +struct mtk_mmsys_private_data { > > + void __iomem *config_regs; > > + struct mtk_mmsys_conn_funcs *funcs; > > And instead of point to the funcs add the registers data here. > > const struct mtk_mmsys_reg_data regs; > > > }; > > > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .clk_driver = "clk-mt2701-mm", > > + .mmsys_driver = "mt2701-mmsys", > > And here > + .regs = { > + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, > + }, > > AFAICS these registers are only used here, so you can get them per SoC > and configure properly > > > }; > > > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > .clk_driver = "clk-mt2712-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > > .clk_driver = "clk-mt6779-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > > .clk_driver = "clk-mt6797-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .clk_driver = "clk-mt8173-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > .clk_driver = "clk-mt8183-mm", > > }; > > > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > And you can do here: > > + const struct mtk_mmsys_driver_data *data; > + > + data = of_device_get_match_data(dev); > > And then use data->regs.ovl0_mout_en where you need it. > > > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > - value = OVL0_MOUT_EN_COLOR0; > > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > - value = OVL_MOUT_EN_RDMA; > > + value = data->regs.ovl0_mout_en > > And do the same for all the different registers per SoC > > > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD_MOUT_EN_RDMA0; > > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > - value = UFOE_MOUT_EN_DSI0; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > - value = OVL1_MOUT_EN_COLOR1; > > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > - value = GAMMA_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD1_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI3; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > - value = COLOR0_SEL_IN_OVL0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI3_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI3_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > - value = COLOR1_SEL_IN_OVL1; > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSI_SEL; > > - value = DSI_SEL_IN_BLS; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > - enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next) > > -{ > > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - writel_relaxed(DSI_SEL_IN_RDMA, > > - config_regs + DISP_REG_CONFIG_DSI_SEL); > > - writel_relaxed(DPI_SEL_IN_BLS, > > - config_regs + DISP_REG_CONFIG_DPI_SEL); > > - } > > -} > > - > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > > + priv_funcs->sout_sel(config_regs, cur, next); > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs) > > +{ > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + > > + private->funcs = funcs; > > +} > > + > > static int mtk_mmsys_probe(struct platform_device *pdev) > > { > > const struct mtk_mmsys_driver_data *data; > > struct device *dev = &pdev->dev; > > struct platform_device *clks; > > struct platform_device *drm; > > + struct platform_device *mm; > > void __iomem *config_regs; > > struct resource *mem; > > int ret; > > + struct mtk_mmsys_private_data *private; > > + > > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > > + if (!private) > > + return -ENOMEM; > > > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > config_regs = devm_ioremap_resource(dev, mem); > > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > ret); > > return ret; > > } > > + private->config_regs = config_regs; > > > > - platform_set_drvdata(pdev, config_regs); > > + platform_set_drvdata(pdev, private); > > > > data = of_device_get_match_data(&pdev->dev); > > > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > if (IS_ERR(clks)) > > return PTR_ERR(clks); > > > > + mm = platform_device_register_data(&pdev->dev, > > + data->mmsys_driver, > > + PLATFORM_DEVID_AUTO, > > + NULL, > > + 0); > > + if (IS_ERR(mm)) > > + return PTR_ERR(mm); > > + > > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > > PLATFORM_DEVID_AUTO, NULL, 0); > > if (IS_ERR(drm)) { > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 2228bf6..89185c6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_ID_MAX, > > }; > > > > +struct mtk_mmsys_conn_funcs { > > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + void (*sout_sel)(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next); > > +}; > > + > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs); > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 3:27 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:27 UTC (permalink / raw) To: Enric Balletbo Serra Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > Hi Yongqiang Niu, > > Thank you for your patch. > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > add mmsys private data > > > > I think this change requires a better explanation of what you are > doing. Although I'm really uncomfortable with this change, why you > need to create a new mt2701-mmsys file? reason: 1.there will more and more Mediatek Soc upstream, and the display path connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and mtk_mmsys_ddp_sout_sel will complicated more and more, 2. many of the connection are only used in some SoC, and useless for other SoC and not readable, 3. if we add a new SoC connection, we need check is this affect other Soc, > > > Feature: drm/mediatek > > Remove this. next version will remove this > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > Can't be reused this function for all devices? You did in the previous > series, why not now? can not reused, that why need add mmsys private data like before version. but that still not a good idea. the next path like this will be more readable, and more easy to maintain https://patchwork.kernel.org/patch/11679539/ > > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > Same question for this function > > > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > +}; > > + > > +static int mmsys_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + > > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > > + > > + return 0; > > +} > > + > > +static struct platform_driver mmsys_drv = { > > + .probe = mmsys_probe, > > + .driver = { > > + .name = "mt2701-mmsys", > > + }, > > +}; > > + > > +builtin_platform_driver(mmsys_drv); > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index 36ad66b..605b992 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -10,267 +10,63 @@ > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > - > > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > > - > > -#define OVL0_MOUT_EN_COLOR0 0x1 > > -#define OD_MOUT_EN_RDMA0 0x1 > > -#define OD1_MOUT_EN_RDMA1 BIT(16) > > -#define UFOE_MOUT_EN_DSI0 0x1 > > -#define COLOR0_SEL_IN_OVL0 0x1 > > -#define OVL1_MOUT_EN_COLOR1 0x1 > > -#define GAMMA_MOUT_EN_RDMA1 0x1 > > -#define RDMA0_SOUT_DPI0 0x2 > > -#define RDMA0_SOUT_DPI1 0x3 > > -#define RDMA0_SOUT_DSI1 0x1 > > -#define RDMA0_SOUT_DSI2 0x4 > > -#define RDMA0_SOUT_DSI3 0x5 > > -#define RDMA1_SOUT_DPI0 0x2 > > -#define RDMA1_SOUT_DPI1 0x3 > > -#define RDMA1_SOUT_DSI1 0x1 > > -#define RDMA1_SOUT_DSI2 0x4 > > -#define RDMA1_SOUT_DSI3 0x5 > > -#define RDMA2_SOUT_DPI0 0x2 > > -#define RDMA2_SOUT_DPI1 0x3 > > -#define RDMA2_SOUT_DSI1 0x1 > > -#define RDMA2_SOUT_DSI2 0x4 > > -#define RDMA2_SOUT_DSI3 0x5 > > -#define DPI0_SEL_IN_RDMA1 0x1 > > -#define DPI0_SEL_IN_RDMA2 0x3 > > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > -#define DSI0_SEL_IN_RDMA1 0x1 > > -#define DSI0_SEL_IN_RDMA2 0x4 > > -#define DSI1_SEL_IN_RDMA1 0x1 > > -#define DSI1_SEL_IN_RDMA2 0x4 > > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > -#define COLOR1_SEL_IN_OVL1 0x1 > > - > > -#define OVL_MOUT_EN_RDMA 0x1 > > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > -#define DSI_SEL_IN_BLS 0x0 > > -#define DPI_SEL_IN_BLS 0x0 > > -#define DSI_SEL_IN_RDMA 0x1 > > - > > struct mtk_mmsys_driver_data { > > const char *clk_driver; > > + const char *mmsys_driver; > > +}; > > + > > What about doing this > > +struct mtk_mmsys_reg_data { > + u32 ovl0_mout_en; > +}; > > > +struct mtk_mmsys_private_data { > > + void __iomem *config_regs; > > + struct mtk_mmsys_conn_funcs *funcs; > > And instead of point to the funcs add the registers data here. > > const struct mtk_mmsys_reg_data regs; > > > }; > > > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .clk_driver = "clk-mt2701-mm", > > + .mmsys_driver = "mt2701-mmsys", > > And here > + .regs = { > + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, > + }, > > AFAICS these registers are only used here, so you can get them per SoC > and configure properly > > > }; > > > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > .clk_driver = "clk-mt2712-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > > .clk_driver = "clk-mt6779-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > > .clk_driver = "clk-mt6797-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .clk_driver = "clk-mt8173-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > .clk_driver = "clk-mt8183-mm", > > }; > > > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > And you can do here: > > + const struct mtk_mmsys_driver_data *data; > + > + data = of_device_get_match_data(dev); > > And then use data->regs.ovl0_mout_en where you need it. > > > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > - value = OVL0_MOUT_EN_COLOR0; > > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > - value = OVL_MOUT_EN_RDMA; > > + value = data->regs.ovl0_mout_en > > And do the same for all the different registers per SoC > > > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD_MOUT_EN_RDMA0; > > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > - value = UFOE_MOUT_EN_DSI0; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > - value = OVL1_MOUT_EN_COLOR1; > > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > - value = GAMMA_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD1_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI3; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > - value = COLOR0_SEL_IN_OVL0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI3_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI3_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > - value = COLOR1_SEL_IN_OVL1; > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSI_SEL; > > - value = DSI_SEL_IN_BLS; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > - enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next) > > -{ > > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - writel_relaxed(DSI_SEL_IN_RDMA, > > - config_regs + DISP_REG_CONFIG_DSI_SEL); > > - writel_relaxed(DPI_SEL_IN_BLS, > > - config_regs + DISP_REG_CONFIG_DPI_SEL); > > - } > > -} > > - > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > > + priv_funcs->sout_sel(config_regs, cur, next); > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs) > > +{ > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + > > + private->funcs = funcs; > > +} > > + > > static int mtk_mmsys_probe(struct platform_device *pdev) > > { > > const struct mtk_mmsys_driver_data *data; > > struct device *dev = &pdev->dev; > > struct platform_device *clks; > > struct platform_device *drm; > > + struct platform_device *mm; > > void __iomem *config_regs; > > struct resource *mem; > > int ret; > > + struct mtk_mmsys_private_data *private; > > + > > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > > + if (!private) > > + return -ENOMEM; > > > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > config_regs = devm_ioremap_resource(dev, mem); > > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > ret); > > return ret; > > } > > + private->config_regs = config_regs; > > > > - platform_set_drvdata(pdev, config_regs); > > + platform_set_drvdata(pdev, private); > > > > data = of_device_get_match_data(&pdev->dev); > > > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > if (IS_ERR(clks)) > > return PTR_ERR(clks); > > > > + mm = platform_device_register_data(&pdev->dev, > > + data->mmsys_driver, > > + PLATFORM_DEVID_AUTO, > > + NULL, > > + 0); > > + if (IS_ERR(mm)) > > + return PTR_ERR(mm); > > + > > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > > PLATFORM_DEVID_AUTO, NULL, 0); > > if (IS_ERR(drm)) { > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 2228bf6..89185c6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_ID_MAX, > > }; > > > > +struct mtk_mmsys_conn_funcs { > > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + void (*sout_sel)(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next); > > +}; > > + > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs); > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 3:27 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:27 UTC (permalink / raw) To: Enric Balletbo Serra Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > Hi Yongqiang Niu, > > Thank you for your patch. > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > add mmsys private data > > > > I think this change requires a better explanation of what you are > doing. Although I'm really uncomfortable with this change, why you > need to create a new mt2701-mmsys file? reason: 1.there will more and more Mediatek Soc upstream, and the display path connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and mtk_mmsys_ddp_sout_sel will complicated more and more, 2. many of the connection are only used in some SoC, and useless for other SoC and not readable, 3. if we add a new SoC connection, we need check is this affect other Soc, > > > Feature: drm/mediatek > > Remove this. next version will remove this > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > Can't be reused this function for all devices? You did in the previous > series, why not now? can not reused, that why need add mmsys private data like before version. but that still not a good idea. the next path like this will be more readable, and more easy to maintain https://patchwork.kernel.org/patch/11679539/ > > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > Same question for this function > > > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > +}; > > + > > +static int mmsys_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + > > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > > + > > + return 0; > > +} > > + > > +static struct platform_driver mmsys_drv = { > > + .probe = mmsys_probe, > > + .driver = { > > + .name = "mt2701-mmsys", > > + }, > > +}; > > + > > +builtin_platform_driver(mmsys_drv); > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index 36ad66b..605b992 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -10,267 +10,63 @@ > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > - > > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > > - > > -#define OVL0_MOUT_EN_COLOR0 0x1 > > -#define OD_MOUT_EN_RDMA0 0x1 > > -#define OD1_MOUT_EN_RDMA1 BIT(16) > > -#define UFOE_MOUT_EN_DSI0 0x1 > > -#define COLOR0_SEL_IN_OVL0 0x1 > > -#define OVL1_MOUT_EN_COLOR1 0x1 > > -#define GAMMA_MOUT_EN_RDMA1 0x1 > > -#define RDMA0_SOUT_DPI0 0x2 > > -#define RDMA0_SOUT_DPI1 0x3 > > -#define RDMA0_SOUT_DSI1 0x1 > > -#define RDMA0_SOUT_DSI2 0x4 > > -#define RDMA0_SOUT_DSI3 0x5 > > -#define RDMA1_SOUT_DPI0 0x2 > > -#define RDMA1_SOUT_DPI1 0x3 > > -#define RDMA1_SOUT_DSI1 0x1 > > -#define RDMA1_SOUT_DSI2 0x4 > > -#define RDMA1_SOUT_DSI3 0x5 > > -#define RDMA2_SOUT_DPI0 0x2 > > -#define RDMA2_SOUT_DPI1 0x3 > > -#define RDMA2_SOUT_DSI1 0x1 > > -#define RDMA2_SOUT_DSI2 0x4 > > -#define RDMA2_SOUT_DSI3 0x5 > > -#define DPI0_SEL_IN_RDMA1 0x1 > > -#define DPI0_SEL_IN_RDMA2 0x3 > > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > -#define DSI0_SEL_IN_RDMA1 0x1 > > -#define DSI0_SEL_IN_RDMA2 0x4 > > -#define DSI1_SEL_IN_RDMA1 0x1 > > -#define DSI1_SEL_IN_RDMA2 0x4 > > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > -#define COLOR1_SEL_IN_OVL1 0x1 > > - > > -#define OVL_MOUT_EN_RDMA 0x1 > > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > -#define DSI_SEL_IN_BLS 0x0 > > -#define DPI_SEL_IN_BLS 0x0 > > -#define DSI_SEL_IN_RDMA 0x1 > > - > > struct mtk_mmsys_driver_data { > > const char *clk_driver; > > + const char *mmsys_driver; > > +}; > > + > > What about doing this > > +struct mtk_mmsys_reg_data { > + u32 ovl0_mout_en; > +}; > > > +struct mtk_mmsys_private_data { > > + void __iomem *config_regs; > > + struct mtk_mmsys_conn_funcs *funcs; > > And instead of point to the funcs add the registers data here. > > const struct mtk_mmsys_reg_data regs; > > > }; > > > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .clk_driver = "clk-mt2701-mm", > > + .mmsys_driver = "mt2701-mmsys", > > And here > + .regs = { > + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, > + }, > > AFAICS these registers are only used here, so you can get them per SoC > and configure properly > > > }; > > > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > .clk_driver = "clk-mt2712-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > > .clk_driver = "clk-mt6779-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > > .clk_driver = "clk-mt6797-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .clk_driver = "clk-mt8173-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > .clk_driver = "clk-mt8183-mm", > > }; > > > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > And you can do here: > > + const struct mtk_mmsys_driver_data *data; > + > + data = of_device_get_match_data(dev); > > And then use data->regs.ovl0_mout_en where you need it. > > > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > - value = OVL0_MOUT_EN_COLOR0; > > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > - value = OVL_MOUT_EN_RDMA; > > + value = data->regs.ovl0_mout_en > > And do the same for all the different registers per SoC > > > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD_MOUT_EN_RDMA0; > > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > - value = UFOE_MOUT_EN_DSI0; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > - value = OVL1_MOUT_EN_COLOR1; > > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > - value = GAMMA_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD1_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI3; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > - value = COLOR0_SEL_IN_OVL0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI3_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI3_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > - value = COLOR1_SEL_IN_OVL1; > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSI_SEL; > > - value = DSI_SEL_IN_BLS; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > - enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next) > > -{ > > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - writel_relaxed(DSI_SEL_IN_RDMA, > > - config_regs + DISP_REG_CONFIG_DSI_SEL); > > - writel_relaxed(DPI_SEL_IN_BLS, > > - config_regs + DISP_REG_CONFIG_DPI_SEL); > > - } > > -} > > - > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > > + priv_funcs->sout_sel(config_regs, cur, next); > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs) > > +{ > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + > > + private->funcs = funcs; > > +} > > + > > static int mtk_mmsys_probe(struct platform_device *pdev) > > { > > const struct mtk_mmsys_driver_data *data; > > struct device *dev = &pdev->dev; > > struct platform_device *clks; > > struct platform_device *drm; > > + struct platform_device *mm; > > void __iomem *config_regs; > > struct resource *mem; > > int ret; > > + struct mtk_mmsys_private_data *private; > > + > > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > > + if (!private) > > + return -ENOMEM; > > > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > config_regs = devm_ioremap_resource(dev, mem); > > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > ret); > > return ret; > > } > > + private->config_regs = config_regs; > > > > - platform_set_drvdata(pdev, config_regs); > > + platform_set_drvdata(pdev, private); > > > > data = of_device_get_match_data(&pdev->dev); > > > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > if (IS_ERR(clks)) > > return PTR_ERR(clks); > > > > + mm = platform_device_register_data(&pdev->dev, > > + data->mmsys_driver, > > + PLATFORM_DEVID_AUTO, > > + NULL, > > + 0); > > + if (IS_ERR(mm)) > > + return PTR_ERR(mm); > > + > > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > > PLATFORM_DEVID_AUTO, NULL, 0); > > if (IS_ERR(drm)) { > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 2228bf6..89185c6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_ID_MAX, > > }; > > > > +struct mtk_mmsys_conn_funcs { > > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + void (*sout_sel)(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next); > > +}; > > + > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs); > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 3:27 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:27 UTC (permalink / raw) To: Enric Balletbo Serra Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > Hi Yongqiang Niu, > > Thank you for your patch. > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > de jul. 2020 a les 4:05: > > > > add mmsys private data > > > > I think this change requires a better explanation of what you are > doing. Although I'm really uncomfortable with this change, why you > need to create a new mt2701-mmsys file? reason: 1.there will more and more Mediatek Soc upstream, and the display path connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and mtk_mmsys_ddp_sout_sel will complicated more and more, 2. many of the connection are only used in some SoC, and useless for other SoC and not readable, 3. if we add a new SoC connection, we need check is this affect other Soc, > > > Feature: drm/mediatek > > Remove this. next version will remove this > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > Can't be reused this function for all devices? You did in the previous > series, why not now? can not reused, that why need add mmsys private data like before version. but that still not a good idea. the next path like this will be more readable, and more easy to maintain https://patchwork.kernel.org/patch/11679539/ > > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > Same question for this function > > > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > +}; > > + > > +static int mmsys_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + > > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > > + > > + return 0; > > +} > > + > > +static struct platform_driver mmsys_drv = { > > + .probe = mmsys_probe, > > + .driver = { > > + .name = "mt2701-mmsys", > > + }, > > +}; > > + > > +builtin_platform_driver(mmsys_drv); > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > > index 36ad66b..605b992 100644 > > --- a/drivers/soc/mediatek/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mtk-mmsys.c > > @@ -10,267 +10,63 @@ > > #include <linux/platform_device.h> > > #include <linux/soc/mediatek/mtk-mmsys.h> > > > > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > - > > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > -#define DISP_REG_CONFIG_OUT_SEL 0x04c > > -#define DISP_REG_CONFIG_DSI_SEL 0x050 > > -#define DISP_REG_CONFIG_DPI_SEL 0x064 > > - > > -#define OVL0_MOUT_EN_COLOR0 0x1 > > -#define OD_MOUT_EN_RDMA0 0x1 > > -#define OD1_MOUT_EN_RDMA1 BIT(16) > > -#define UFOE_MOUT_EN_DSI0 0x1 > > -#define COLOR0_SEL_IN_OVL0 0x1 > > -#define OVL1_MOUT_EN_COLOR1 0x1 > > -#define GAMMA_MOUT_EN_RDMA1 0x1 > > -#define RDMA0_SOUT_DPI0 0x2 > > -#define RDMA0_SOUT_DPI1 0x3 > > -#define RDMA0_SOUT_DSI1 0x1 > > -#define RDMA0_SOUT_DSI2 0x4 > > -#define RDMA0_SOUT_DSI3 0x5 > > -#define RDMA1_SOUT_DPI0 0x2 > > -#define RDMA1_SOUT_DPI1 0x3 > > -#define RDMA1_SOUT_DSI1 0x1 > > -#define RDMA1_SOUT_DSI2 0x4 > > -#define RDMA1_SOUT_DSI3 0x5 > > -#define RDMA2_SOUT_DPI0 0x2 > > -#define RDMA2_SOUT_DPI1 0x3 > > -#define RDMA2_SOUT_DSI1 0x1 > > -#define RDMA2_SOUT_DSI2 0x4 > > -#define RDMA2_SOUT_DSI3 0x5 > > -#define DPI0_SEL_IN_RDMA1 0x1 > > -#define DPI0_SEL_IN_RDMA2 0x3 > > -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > -#define DSI0_SEL_IN_RDMA1 0x1 > > -#define DSI0_SEL_IN_RDMA2 0x4 > > -#define DSI1_SEL_IN_RDMA1 0x1 > > -#define DSI1_SEL_IN_RDMA2 0x4 > > -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > -#define COLOR1_SEL_IN_OVL1 0x1 > > - > > -#define OVL_MOUT_EN_RDMA 0x1 > > -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > -#define DSI_SEL_IN_BLS 0x0 > > -#define DPI_SEL_IN_BLS 0x0 > > -#define DSI_SEL_IN_RDMA 0x1 > > - > > struct mtk_mmsys_driver_data { > > const char *clk_driver; > > + const char *mmsys_driver; > > +}; > > + > > What about doing this > > +struct mtk_mmsys_reg_data { > + u32 ovl0_mout_en; > +}; > > > +struct mtk_mmsys_private_data { > > + void __iomem *config_regs; > > + struct mtk_mmsys_conn_funcs *funcs; > > And instead of point to the funcs add the registers data here. > > const struct mtk_mmsys_reg_data regs; > > > }; > > > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .clk_driver = "clk-mt2701-mm", > > + .mmsys_driver = "mt2701-mmsys", > > And here > + .regs = { > + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, > + }, > > AFAICS these registers are only used here, so you can get them per SoC > and configure properly > > > }; > > > > static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { > > .clk_driver = "clk-mt2712-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { > > .clk_driver = "clk-mt6779-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { > > .clk_driver = "clk-mt6797-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { > > .clk_driver = "clk-mt8173-mm", > > + .mmsys_driver = "mt2701-mmsys", > > }; > > > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > .clk_driver = "clk-mt8183-mm", > > }; > > > > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > And you can do here: > > + const struct mtk_mmsys_driver_data *data; > + > + data = of_device_get_match_data(dev); > > And then use data->regs.ovl0_mout_en where you need it. > > > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > - value = OVL0_MOUT_EN_COLOR0; > > - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > - value = OVL_MOUT_EN_RDMA; > > + value = data->regs.ovl0_mout_en > > And do the same for all the different registers per SoC > > > - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD_MOUT_EN_RDMA0; > > - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > - value = UFOE_MOUT_EN_DSI0; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > - value = OVL1_MOUT_EN_COLOR1; > > - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > - value = GAMMA_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > - value = OD1_MOUT_EN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > - value = RDMA0_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DSI3; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > - value = RDMA1_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI0; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DPI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > - value = RDMA2_SOUT_DSI3; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next, > > - unsigned int *addr) > > -{ > > - unsigned int value; > > - > > - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > - value = COLOR0_SEL_IN_OVL0; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI3_SEL_IN_RDMA1; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > - *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > - value = DPI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI0_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > - value = DSI1_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI2_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > - value = DSI3_SEL_IN_RDMA2; > > - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > - value = COLOR1_SEL_IN_OVL1; > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - *addr = DISP_REG_CONFIG_DSI_SEL; > > - value = DSI_SEL_IN_BLS; > > - } else { > > - value = 0; > > - } > > - > > - return value; > > -} > > - > > -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > - enum mtk_ddp_comp_id cur, > > - enum mtk_ddp_comp_id next) > > -{ > > - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > - config_regs + DISP_REG_CONFIG_OUT_SEL); > > - writel_relaxed(DSI_SEL_IN_RDMA, > > - config_regs + DISP_REG_CONFIG_DSI_SEL); > > - writel_relaxed(DPI_SEL_IN_BLS, > > - config_regs + DISP_REG_CONFIG_DPI_SEL); > > - } > > -} > > - > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - mtk_mmsys_ddp_sout_sel(config_regs, cur, next); > > + priv_funcs->sout_sel(config_regs, cur, next); > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) | value; > > writel_relaxed(reg, config_regs + addr); > > @@ -282,16 +78,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next) > > { > > - void __iomem *config_regs = dev_get_drvdata(dev); > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + void __iomem *config_regs = private->config_regs; > > + struct mtk_mmsys_conn_funcs *priv_funcs = private->funcs; > > unsigned int addr, value, reg; > > > > - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); > > + value = priv_funcs->mout_en(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > } > > > > - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); > > + value = priv_funcs->sel_in(cur, next, &addr); > > if (value) { > > reg = readl_relaxed(config_regs + addr) & ~value; > > writel_relaxed(reg, config_regs + addr); > > @@ -299,15 +97,29 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs) > > +{ > > + struct mtk_mmsys_private_data *private = dev_get_drvdata(dev); > > + > > + private->funcs = funcs; > > +} > > + > > static int mtk_mmsys_probe(struct platform_device *pdev) > > { > > const struct mtk_mmsys_driver_data *data; > > struct device *dev = &pdev->dev; > > struct platform_device *clks; > > struct platform_device *drm; > > + struct platform_device *mm; > > void __iomem *config_regs; > > struct resource *mem; > > int ret; > > + struct mtk_mmsys_private_data *private; > > + > > + private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); > > + if (!private) > > + return -ENOMEM; > > > > mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > config_regs = devm_ioremap_resource(dev, mem); > > @@ -317,8 +129,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > ret); > > return ret; > > } > > + private->config_regs = config_regs; > > > > - platform_set_drvdata(pdev, config_regs); > > + platform_set_drvdata(pdev, private); > > > > data = of_device_get_match_data(&pdev->dev); > > > > @@ -327,6 +140,14 @@ static int mtk_mmsys_probe(struct platform_device *pdev) > > if (IS_ERR(clks)) > > return PTR_ERR(clks); > > > > + mm = platform_device_register_data(&pdev->dev, > > + data->mmsys_driver, > > + PLATFORM_DEVID_AUTO, > > + NULL, > > + 0); > > + if (IS_ERR(mm)) > > + return PTR_ERR(mm); > > + > > drm = platform_device_register_data(&pdev->dev, "mediatek-drm", > > PLATFORM_DEVID_AUTO, NULL, 0); > > if (IS_ERR(drm)) { > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 2228bf6..89185c6 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -42,6 +42,21 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_ID_MAX, > > }; > > > > +struct mtk_mmsys_conn_funcs { > > + u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > + void (*sout_sel)(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next); > > +}; > > + > > +void mtk_mmsys_register_conn_funcs(struct device *dev, > > + struct mtk_mmsys_conn_funcs *funcs); > > + > > void mtk_mmsys_ddp_connect(struct device *dev, > > enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data 2020-07-25 3:27 ` Yongqiang Niu (?) (?) @ 2020-07-28 10:25 ` Enric Balletbo Serra -1 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-28 10:25 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi Yongqiang, Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia ds., 25 de jul. 2020 a les 5:29: > > On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > > Hi Yongqiang Niu, > > > > Thank you for your patch. > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > add mmsys private data > > > > > > > I think this change requires a better explanation of what you are > > doing. Although I'm really uncomfortable with this change, why you > > need to create a new mt2701-mmsys file? > > reason: > 1.there will more and more Mediatek Soc upstream, and the display path > connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and > mtk_mmsys_ddp_sout_sel will complicated more and more, > 2. many of the connection are only used in some SoC, and useless for > other SoC and not readable, > 3. if we add a new SoC connection, we need check is this affect other > Soc, > > > > > Feature: drm/mediatek > > > > Remove this. > next version will remove this > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/soc/mediatek/Makefile | 1 + > > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > > 5 files changed, 314 insertions(+), 225 deletions(-) > > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > > index 2afa7b9..b37ac2c 100644 > > > --- a/drivers/soc/mediatek/Makefile > > > +++ b/drivers/soc/mediatek/Makefile > > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > > new file mode 100644 > > > index 0000000..33b0dab > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > > @@ -0,0 +1,2 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only > > > +obj-y += mt2701-mmsys.o > > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > new file mode 100644 > > > index 0000000..b8e53b0 > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > @@ -0,0 +1,250 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +// > > > +// Copyright (c) 2020 MediaTek Inc. > > > + > > > +#include <linux/device.h> > > > +#include <linux/io.h> > > > +#include <linux/of_device.h> > > > +#include <linux/platform_device.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > > + > > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > > +#define OD_MOUT_EN_RDMA0 0x1 > > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > > +#define UFOE_MOUT_EN_DSI0 0x1 > > > +#define COLOR0_SEL_IN_OVL0 0x1 > > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > > +#define RDMA0_SOUT_DPI0 0x2 > > > +#define RDMA0_SOUT_DPI1 0x3 > > > +#define RDMA0_SOUT_DSI1 0x1 > > > +#define RDMA0_SOUT_DSI2 0x4 > > > +#define RDMA0_SOUT_DSI3 0x5 > > > +#define RDMA1_SOUT_DPI0 0x2 > > > +#define RDMA1_SOUT_DPI1 0x3 > > > +#define RDMA1_SOUT_DSI1 0x1 > > > +#define RDMA1_SOUT_DSI2 0x4 > > > +#define RDMA1_SOUT_DSI3 0x5 > > > +#define RDMA2_SOUT_DPI0 0x2 > > > +#define RDMA2_SOUT_DPI1 0x3 > > > +#define RDMA2_SOUT_DSI1 0x1 > > > +#define RDMA2_SOUT_DSI2 0x4 > > > +#define RDMA2_SOUT_DSI3 0x5 > > > +#define DPI0_SEL_IN_RDMA1 0x1 > > > +#define DPI0_SEL_IN_RDMA2 0x3 > > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > > +#define DSI0_SEL_IN_RDMA1 0x1 > > > +#define DSI0_SEL_IN_RDMA2 0x4 > > > +#define DSI1_SEL_IN_RDMA1 0x1 > > > +#define DSI1_SEL_IN_RDMA2 0x4 > > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > > +#define COLOR1_SEL_IN_OVL1 0x1 > > > + > > > +#define OVL_MOUT_EN_RDMA 0x1 > > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > > +#define DSI_SEL_IN_BLS 0x0 > > > +#define DPI_SEL_IN_BLS 0x0 > > > +#define DSI_SEL_IN_RDMA 0x1 > > > + > > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > > + enum mtk_ddp_comp_id next, > > > + unsigned int *addr) > > > +{ > > > > Can't be reused this function for all devices? You did in the previous > > series, why not now? > > can not reused, that why need add mmsys private data like before > version. You did in the previous series, would that mean that your previous series were wrong or nonworking or break on some SoCs? I agree that you need per SoC data, what I am complaining is the idea of having pointers to functions instead of just having the registers or the media paths per SoC. You can have private data for registers, something like this: static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .regs = { .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, }, }; And you can also have the media configuration paths in the driver data, similar to what you did for mt8183 but not for the others. But, I'd recommend to do this in a second step, and go step-by-step. Your v6 and v7 are quite different, but IMHO I'm more in favor of what you did for v6 (as a first step to support mt8183) than this patchset. For v7 I was expecting just to move the bits that needed to mtk-mmsys, not such rework. Said all that, I'm not the maintainer and is up to the maintainer to decide the direction that driver should take. > but that still not a good idea. > > the next path like this will be more readable, and more easy to maintain > https://patchwork.kernel.org/patch/11679539/ Ack, that's more readable and probably should be the direction to go, always assuming we have the *data* (mmsys_path_sel, etc.) per SoC and the functions mtk_mmsys_ddp_mout_en(), mtk_mmsys_ddp_sel_in(), mtk_mmsys_ddp_sout_sel() common for all SoCs. Thanks, Enric [snip] ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-28 10:25 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-28 10:25 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi Yongqiang, Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia ds., 25 de jul. 2020 a les 5:29: > > On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > > Hi Yongqiang Niu, > > > > Thank you for your patch. > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > add mmsys private data > > > > > > > I think this change requires a better explanation of what you are > > doing. Although I'm really uncomfortable with this change, why you > > need to create a new mt2701-mmsys file? > > reason: > 1.there will more and more Mediatek Soc upstream, and the display path > connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and > mtk_mmsys_ddp_sout_sel will complicated more and more, > 2. many of the connection are only used in some SoC, and useless for > other SoC and not readable, > 3. if we add a new SoC connection, we need check is this affect other > Soc, > > > > > Feature: drm/mediatek > > > > Remove this. > next version will remove this > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/soc/mediatek/Makefile | 1 + > > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > > 5 files changed, 314 insertions(+), 225 deletions(-) > > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > > index 2afa7b9..b37ac2c 100644 > > > --- a/drivers/soc/mediatek/Makefile > > > +++ b/drivers/soc/mediatek/Makefile > > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > > new file mode 100644 > > > index 0000000..33b0dab > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > > @@ -0,0 +1,2 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only > > > +obj-y += mt2701-mmsys.o > > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > new file mode 100644 > > > index 0000000..b8e53b0 > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > @@ -0,0 +1,250 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +// > > > +// Copyright (c) 2020 MediaTek Inc. > > > + > > > +#include <linux/device.h> > > > +#include <linux/io.h> > > > +#include <linux/of_device.h> > > > +#include <linux/platform_device.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > > + > > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > > +#define OD_MOUT_EN_RDMA0 0x1 > > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > > +#define UFOE_MOUT_EN_DSI0 0x1 > > > +#define COLOR0_SEL_IN_OVL0 0x1 > > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > > +#define RDMA0_SOUT_DPI0 0x2 > > > +#define RDMA0_SOUT_DPI1 0x3 > > > +#define RDMA0_SOUT_DSI1 0x1 > > > +#define RDMA0_SOUT_DSI2 0x4 > > > +#define RDMA0_SOUT_DSI3 0x5 > > > +#define RDMA1_SOUT_DPI0 0x2 > > > +#define RDMA1_SOUT_DPI1 0x3 > > > +#define RDMA1_SOUT_DSI1 0x1 > > > +#define RDMA1_SOUT_DSI2 0x4 > > > +#define RDMA1_SOUT_DSI3 0x5 > > > +#define RDMA2_SOUT_DPI0 0x2 > > > +#define RDMA2_SOUT_DPI1 0x3 > > > +#define RDMA2_SOUT_DSI1 0x1 > > > +#define RDMA2_SOUT_DSI2 0x4 > > > +#define RDMA2_SOUT_DSI3 0x5 > > > +#define DPI0_SEL_IN_RDMA1 0x1 > > > +#define DPI0_SEL_IN_RDMA2 0x3 > > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > > +#define DSI0_SEL_IN_RDMA1 0x1 > > > +#define DSI0_SEL_IN_RDMA2 0x4 > > > +#define DSI1_SEL_IN_RDMA1 0x1 > > > +#define DSI1_SEL_IN_RDMA2 0x4 > > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > > +#define COLOR1_SEL_IN_OVL1 0x1 > > > + > > > +#define OVL_MOUT_EN_RDMA 0x1 > > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > > +#define DSI_SEL_IN_BLS 0x0 > > > +#define DPI_SEL_IN_BLS 0x0 > > > +#define DSI_SEL_IN_RDMA 0x1 > > > + > > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > > + enum mtk_ddp_comp_id next, > > > + unsigned int *addr) > > > +{ > > > > Can't be reused this function for all devices? You did in the previous > > series, why not now? > > can not reused, that why need add mmsys private data like before > version. You did in the previous series, would that mean that your previous series were wrong or nonworking or break on some SoCs? I agree that you need per SoC data, what I am complaining is the idea of having pointers to functions instead of just having the registers or the media paths per SoC. You can have private data for registers, something like this: static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .regs = { .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, }, }; And you can also have the media configuration paths in the driver data, similar to what you did for mt8183 but not for the others. But, I'd recommend to do this in a second step, and go step-by-step. Your v6 and v7 are quite different, but IMHO I'm more in favor of what you did for v6 (as a first step to support mt8183) than this patchset. For v7 I was expecting just to move the bits that needed to mtk-mmsys, not such rework. Said all that, I'm not the maintainer and is up to the maintainer to decide the direction that driver should take. > but that still not a good idea. > > the next path like this will be more readable, and more easy to maintain > https://patchwork.kernel.org/patch/11679539/ Ack, that's more readable and probably should be the direction to go, always assuming we have the *data* (mmsys_path_sel, etc.) per SoC and the functions mtk_mmsys_ddp_mout_en(), mtk_mmsys_ddp_sel_in(), mtk_mmsys_ddp_sout_sel() common for all SoCs. Thanks, Enric [snip] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-28 10:25 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-28 10:25 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi Yongqiang, Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia ds., 25 de jul. 2020 a les 5:29: > > On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > > Hi Yongqiang Niu, > > > > Thank you for your patch. > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > add mmsys private data > > > > > > > I think this change requires a better explanation of what you are > > doing. Although I'm really uncomfortable with this change, why you > > need to create a new mt2701-mmsys file? > > reason: > 1.there will more and more Mediatek Soc upstream, and the display path > connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and > mtk_mmsys_ddp_sout_sel will complicated more and more, > 2. many of the connection are only used in some SoC, and useless for > other SoC and not readable, > 3. if we add a new SoC connection, we need check is this affect other > Soc, > > > > > Feature: drm/mediatek > > > > Remove this. > next version will remove this > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/soc/mediatek/Makefile | 1 + > > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > > 5 files changed, 314 insertions(+), 225 deletions(-) > > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > > index 2afa7b9..b37ac2c 100644 > > > --- a/drivers/soc/mediatek/Makefile > > > +++ b/drivers/soc/mediatek/Makefile > > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > > new file mode 100644 > > > index 0000000..33b0dab > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > > @@ -0,0 +1,2 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only > > > +obj-y += mt2701-mmsys.o > > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > new file mode 100644 > > > index 0000000..b8e53b0 > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > @@ -0,0 +1,250 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +// > > > +// Copyright (c) 2020 MediaTek Inc. > > > + > > > +#include <linux/device.h> > > > +#include <linux/io.h> > > > +#include <linux/of_device.h> > > > +#include <linux/platform_device.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > > + > > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > > +#define OD_MOUT_EN_RDMA0 0x1 > > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > > +#define UFOE_MOUT_EN_DSI0 0x1 > > > +#define COLOR0_SEL_IN_OVL0 0x1 > > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > > +#define RDMA0_SOUT_DPI0 0x2 > > > +#define RDMA0_SOUT_DPI1 0x3 > > > +#define RDMA0_SOUT_DSI1 0x1 > > > +#define RDMA0_SOUT_DSI2 0x4 > > > +#define RDMA0_SOUT_DSI3 0x5 > > > +#define RDMA1_SOUT_DPI0 0x2 > > > +#define RDMA1_SOUT_DPI1 0x3 > > > +#define RDMA1_SOUT_DSI1 0x1 > > > +#define RDMA1_SOUT_DSI2 0x4 > > > +#define RDMA1_SOUT_DSI3 0x5 > > > +#define RDMA2_SOUT_DPI0 0x2 > > > +#define RDMA2_SOUT_DPI1 0x3 > > > +#define RDMA2_SOUT_DSI1 0x1 > > > +#define RDMA2_SOUT_DSI2 0x4 > > > +#define RDMA2_SOUT_DSI3 0x5 > > > +#define DPI0_SEL_IN_RDMA1 0x1 > > > +#define DPI0_SEL_IN_RDMA2 0x3 > > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > > +#define DSI0_SEL_IN_RDMA1 0x1 > > > +#define DSI0_SEL_IN_RDMA2 0x4 > > > +#define DSI1_SEL_IN_RDMA1 0x1 > > > +#define DSI1_SEL_IN_RDMA2 0x4 > > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > > +#define COLOR1_SEL_IN_OVL1 0x1 > > > + > > > +#define OVL_MOUT_EN_RDMA 0x1 > > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > > +#define DSI_SEL_IN_BLS 0x0 > > > +#define DPI_SEL_IN_BLS 0x0 > > > +#define DSI_SEL_IN_RDMA 0x1 > > > + > > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > > + enum mtk_ddp_comp_id next, > > > + unsigned int *addr) > > > +{ > > > > Can't be reused this function for all devices? You did in the previous > > series, why not now? > > can not reused, that why need add mmsys private data like before > version. You did in the previous series, would that mean that your previous series were wrong or nonworking or break on some SoCs? I agree that you need per SoC data, what I am complaining is the idea of having pointers to functions instead of just having the registers or the media paths per SoC. You can have private data for registers, something like this: static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .regs = { .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, }, }; And you can also have the media configuration paths in the driver data, similar to what you did for mt8183 but not for the others. But, I'd recommend to do this in a second step, and go step-by-step. Your v6 and v7 are quite different, but IMHO I'm more in favor of what you did for v6 (as a first step to support mt8183) than this patchset. For v7 I was expecting just to move the bits that needed to mtk-mmsys, not such rework. Said all that, I'm not the maintainer and is up to the maintainer to decide the direction that driver should take. > but that still not a good idea. > > the next path like this will be more readable, and more easy to maintain > https://patchwork.kernel.org/patch/11679539/ Ack, that's more readable and probably should be the direction to go, always assuming we have the *data* (mmsys_path_sel, etc.) per SoC and the functions mtk_mmsys_ddp_mout_en(), mtk_mmsys_ddp_sel_in(), mtk_mmsys_ddp_sout_sel() common for all SoCs. Thanks, Enric [snip] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-28 10:25 ` Enric Balletbo Serra 0 siblings, 0 replies; 112+ messages in thread From: Enric Balletbo Serra @ 2020-07-28 10:25 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi Yongqiang, Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia ds., 25 de jul. 2020 a les 5:29: > > On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote: > > Hi Yongqiang Niu, > > > > Thank you for your patch. > > > > Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 23 > > de jul. 2020 a les 4:05: > > > > > > add mmsys private data > > > > > > > I think this change requires a better explanation of what you are > > doing. Although I'm really uncomfortable with this change, why you > > need to create a new mt2701-mmsys file? > > reason: > 1.there will more and more Mediatek Soc upstream, and the display path > connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and > mtk_mmsys_ddp_sout_sel will complicated more and more, > 2. many of the connection are only used in some SoC, and useless for > other SoC and not readable, > 3. if we add a new SoC connection, we need check is this affect other > Soc, > > > > > Feature: drm/mediatek > > > > Remove this. > next version will remove this > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/soc/mediatek/Makefile | 1 + > > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > > 5 files changed, 314 insertions(+), 225 deletions(-) > > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > > index 2afa7b9..b37ac2c 100644 > > > --- a/drivers/soc/mediatek/Makefile > > > +++ b/drivers/soc/mediatek/Makefile > > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > > new file mode 100644 > > > index 0000000..33b0dab > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > > @@ -0,0 +1,2 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only > > > +obj-y += mt2701-mmsys.o > > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > new file mode 100644 > > > index 0000000..b8e53b0 > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > @@ -0,0 +1,250 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +// > > > +// Copyright (c) 2020 MediaTek Inc. > > > + > > > +#include <linux/device.h> > > > +#include <linux/io.h> > > > +#include <linux/of_device.h> > > > +#include <linux/platform_device.h> > > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > > + > > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > > + > > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > > +#define OD_MOUT_EN_RDMA0 0x1 > > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > > +#define UFOE_MOUT_EN_DSI0 0x1 > > > +#define COLOR0_SEL_IN_OVL0 0x1 > > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > > +#define RDMA0_SOUT_DPI0 0x2 > > > +#define RDMA0_SOUT_DPI1 0x3 > > > +#define RDMA0_SOUT_DSI1 0x1 > > > +#define RDMA0_SOUT_DSI2 0x4 > > > +#define RDMA0_SOUT_DSI3 0x5 > > > +#define RDMA1_SOUT_DPI0 0x2 > > > +#define RDMA1_SOUT_DPI1 0x3 > > > +#define RDMA1_SOUT_DSI1 0x1 > > > +#define RDMA1_SOUT_DSI2 0x4 > > > +#define RDMA1_SOUT_DSI3 0x5 > > > +#define RDMA2_SOUT_DPI0 0x2 > > > +#define RDMA2_SOUT_DPI1 0x3 > > > +#define RDMA2_SOUT_DSI1 0x1 > > > +#define RDMA2_SOUT_DSI2 0x4 > > > +#define RDMA2_SOUT_DSI3 0x5 > > > +#define DPI0_SEL_IN_RDMA1 0x1 > > > +#define DPI0_SEL_IN_RDMA2 0x3 > > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > > +#define DSI0_SEL_IN_RDMA1 0x1 > > > +#define DSI0_SEL_IN_RDMA2 0x4 > > > +#define DSI1_SEL_IN_RDMA1 0x1 > > > +#define DSI1_SEL_IN_RDMA2 0x4 > > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > > +#define COLOR1_SEL_IN_OVL1 0x1 > > > + > > > +#define OVL_MOUT_EN_RDMA 0x1 > > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > > +#define DSI_SEL_IN_BLS 0x0 > > > +#define DPI_SEL_IN_BLS 0x0 > > > +#define DSI_SEL_IN_RDMA 0x1 > > > + > > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > > + enum mtk_ddp_comp_id next, > > > + unsigned int *addr) > > > +{ > > > > Can't be reused this function for all devices? You did in the previous > > series, why not now? > > can not reused, that why need add mmsys private data like before > version. You did in the previous series, would that mean that your previous series were wrong or nonworking or break on some SoCs? I agree that you need per SoC data, what I am complaining is the idea of having pointers to functions instead of just having the registers or the media paths per SoC. You can have private data for registers, something like this: static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .regs = { .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN, .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0, .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN, .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0, .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN, .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1, .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN, .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1, }, }; And you can also have the media configuration paths in the driver data, similar to what you did for mt8183 but not for the others. But, I'd recommend to do this in a second step, and go step-by-step. Your v6 and v7 are quite different, but IMHO I'm more in favor of what you did for v6 (as a first step to support mt8183) than this patchset. For v7 I was expecting just to move the bits that needed to mtk-mmsys, not such rework. Said all that, I'm not the maintainer and is up to the maintainer to decide the direction that driver should take. > but that still not a good idea. > > the next path like this will be more readable, and more easy to maintain > https://patchwork.kernel.org/patch/11679539/ Ack, that's more readable and probably should be the direction to go, always assuming we have the *data* (mmsys_path_sel, etc.) per SoC and the functions mtk_mmsys_ddp_mout_en(), mtk_mmsys_ddp_sel_in(), mtk_mmsys_ddp_sout_sel() common for all SoCs. Thanks, Enric [snip] _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-25 2:11 ` Chun-Kuang Hu -1 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 2:11 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > add mmsys private data > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, I think you could implement these three function to be the same as the three of mt8183 with mt2701 version of mmsys_mout_en[], mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test on mt2701, we could temporarily accept this and wait for someone has mt2701 (or mt8173) to rewrite these three function to be the same as mt8183. Regards, Chun-Kuang. > +}; > + ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 2:11 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 2:11 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > add mmsys private data > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, I think you could implement these three function to be the same as the three of mt8183 with mt2701 version of mmsys_mout_en[], mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test on mt2701, we could temporarily accept this and wait for someone has mt2701 (or mt8173) to rewrite these three function to be the same as mt8183. Regards, Chun-Kuang. > +}; > + _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 2:11 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 2:11 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > add mmsys private data > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, I think you could implement these three function to be the same as the three of mt8183 with mt2701 version of mmsys_mout_en[], mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test on mt2701, we could temporarily accept this and wait for someone has mt2701 (or mt8173) to rewrite these three function to be the same as mt8183. Regards, Chun-Kuang. > +}; > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 2:11 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 2:11 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > add mmsys private data > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 1 + > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > 5 files changed, 314 insertions(+), 225 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 2afa7b9..b37ac2c 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..33b0dab > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-y += mt2701-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > new file mode 100644 > index 0000000..b8e53b0 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > @@ -0,0 +1,250 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > + > +#define OVL0_MOUT_EN_COLOR0 0x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR1 0x1 > +#define GAMMA_MOUT_EN_RDMA1 0x1 > +#define RDMA0_SOUT_DPI0 0x2 > +#define RDMA0_SOUT_DPI1 0x3 > +#define RDMA0_SOUT_DSI1 0x1 > +#define RDMA0_SOUT_DSI2 0x4 > +#define RDMA0_SOUT_DSI3 0x5 > +#define RDMA1_SOUT_DPI0 0x2 > +#define RDMA1_SOUT_DPI1 0x3 > +#define RDMA1_SOUT_DSI1 0x1 > +#define RDMA1_SOUT_DSI2 0x4 > +#define RDMA1_SOUT_DSI3 0x5 > +#define RDMA2_SOUT_DPI0 0x2 > +#define RDMA2_SOUT_DPI1 0x3 > +#define RDMA2_SOUT_DSI1 0x1 > +#define RDMA2_SOUT_DSI2 0x4 > +#define RDMA2_SOUT_DSI3 0x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > +#define DSI0_SEL_IN_RDMA2 0x4 > +#define DSI1_SEL_IN_RDMA1 0x1 > +#define DSI1_SEL_IN_RDMA2 0x4 > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > +#define COLOR1_SEL_IN_OVL1 0x1 > + > +#define OVL_MOUT_EN_RDMA 0x1 > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > +#define DSI_SEL_IN_BLS 0x0 > +#define DPI_SEL_IN_BLS 0x0 > +#define DSI_SEL_IN_RDMA 0x1 > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > + value = OVL0_MOUT_EN_COLOR0; > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > + value = OVL_MOUT_EN_RDMA; > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD_MOUT_EN_RDMA0; > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > + value = UFOE_MOUT_EN_DSI0; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > + value = OVL1_MOUT_EN_COLOR1; > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > + value = GAMMA_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > + value = OD1_MOUT_EN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > + value = RDMA0_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DSI3; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > + value = RDMA1_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI0; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DPI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > + value = RDMA2_SOUT_DSI3; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + unsigned int value; > + > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > + value = COLOR0_SEL_IN_OVL0; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI3_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > + value = DPI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > + value = DSI1_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI2_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI3_SEL_IN_RDMA2; > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > + value = COLOR1_SEL_IN_OVL1; > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSI_SEL; > + value = DSI_SEL_IN_BLS; > + } else { > + value = 0; > + } > + > + return value; > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > + config_regs + DISP_REG_CONFIG_OUT_SEL); > + writel_relaxed(DSI_SEL_IN_RDMA, > + config_regs + DISP_REG_CONFIG_DSI_SEL); > + writel_relaxed(DPI_SEL_IN_BLS, > + config_regs + DISP_REG_CONFIG_DPI_SEL); > + } > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, I think you could implement these three function to be the same as the three of mt8183 with mt2701 version of mmsys_mout_en[], mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test on mt2701, we could temporarily accept this and wait for someone has mt2701 (or mt8173) to rewrite these three function to be the same as mt8183. Regards, Chun-Kuang. > +}; > + _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data 2020-07-25 2:11 ` Chun-Kuang Hu (?) (?) @ 2020-07-25 3:13 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:13 UTC (permalink / raw) To: Chun-Kuang Hu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM On Sat, 2020-07-25 at 10:11 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > > > add mmsys private data > > > > Feature: drm/mediatek > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > I think you could implement these three function to be the same as the > three of mt8183 with mt2701 version of mmsys_mout_en[], > mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test > on mt2701, we could temporarily accept this and wait for someone has > mt2701 (or mt8173) to rewrite these three function to be the same as > mt8183. > > Regards, > Chun-Kuang. hi Chun-Kuang. thanks very much for your understand. actually, the display path connection of mt2701, mt2712, mt8173, mt6779, mt6797 are all different with each other. there will be mtxx-mmsys.c for every SoC. and the corresponded SoC upstream member will coding these and test it on the SoC if it is need. > > > +}; > > + ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 3:13 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:13 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Sat, 2020-07-25 at 10:11 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > > > add mmsys private data > > > > Feature: drm/mediatek > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > I think you could implement these three function to be the same as the > three of mt8183 with mt2701 version of mmsys_mout_en[], > mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test > on mt2701, we could temporarily accept this and wait for someone has > mt2701 (or mt8173) to rewrite these three function to be the same as > mt8183. > > Regards, > Chun-Kuang. hi Chun-Kuang. thanks very much for your understand. actually, the display path connection of mt2701, mt2712, mt8173, mt6779, mt6797 are all different with each other. there will be mtxx-mmsys.c for every SoC. and the corresponded SoC upstream member will coding these and test it on the SoC if it is need. > > > +}; > > + _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 3:13 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:13 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Sat, 2020-07-25 at 10:11 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > > > add mmsys private data > > > > Feature: drm/mediatek > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > I think you could implement these three function to be the same as the > three of mt8183 with mt2701 version of mmsys_mout_en[], > mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test > on mt2701, we could temporarily accept this and wait for someone has > mt2701 (or mt8173) to rewrite these three function to be the same as > mt8183. > > Regards, > Chun-Kuang. hi Chun-Kuang. thanks very much for your understand. actually, the display path connection of mt2701, mt2712, mt8173, mt6779, mt6797 are all different with each other. there will be mtxx-mmsys.c for every SoC. and the corresponded SoC upstream member will coding these and test it on the SoC if it is need. > > > +}; > > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data @ 2020-07-25 3:13 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:13 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Sat, 2020-07-25 at 10:11 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:05寫道： > > > > add mmsys private data > > > > Feature: drm/mediatek > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 1 + > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 271 +++++------------------------- > > include/linux/soc/mediatek/mtk-mmsys.h | 15 ++ > > 5 files changed, 314 insertions(+), 225 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 2afa7b9..b37ac2c 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..33b0dab > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-y += mt2701-mmsys.o > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > new file mode 100644 > > index 0000000..b8e53b0 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c > > @@ -0,0 +1,250 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2020 MediaTek Inc. > > + > > +#include <linux/device.h> > > +#include <linux/io.h> > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > > +#include <linux/soc/mediatek/mtk-mmsys.h> > > + > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > > +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 > > +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > > + > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > > +#define DISP_REG_CONFIG_OUT_SEL 0x04c > > +#define DISP_REG_CONFIG_DSI_SEL 0x050 > > +#define DISP_REG_CONFIG_DPI_SEL 0x064 > > + > > +#define OVL0_MOUT_EN_COLOR0 0x1 > > +#define OD_MOUT_EN_RDMA0 0x1 > > +#define OD1_MOUT_EN_RDMA1 BIT(16) > > +#define UFOE_MOUT_EN_DSI0 0x1 > > +#define COLOR0_SEL_IN_OVL0 0x1 > > +#define OVL1_MOUT_EN_COLOR1 0x1 > > +#define GAMMA_MOUT_EN_RDMA1 0x1 > > +#define RDMA0_SOUT_DPI0 0x2 > > +#define RDMA0_SOUT_DPI1 0x3 > > +#define RDMA0_SOUT_DSI1 0x1 > > +#define RDMA0_SOUT_DSI2 0x4 > > +#define RDMA0_SOUT_DSI3 0x5 > > +#define RDMA1_SOUT_DPI0 0x2 > > +#define RDMA1_SOUT_DPI1 0x3 > > +#define RDMA1_SOUT_DSI1 0x1 > > +#define RDMA1_SOUT_DSI2 0x4 > > +#define RDMA1_SOUT_DSI3 0x5 > > +#define RDMA2_SOUT_DPI0 0x2 > > +#define RDMA2_SOUT_DPI1 0x3 > > +#define RDMA2_SOUT_DSI1 0x1 > > +#define RDMA2_SOUT_DSI2 0x4 > > +#define RDMA2_SOUT_DSI3 0x5 > > +#define DPI0_SEL_IN_RDMA1 0x1 > > +#define DPI0_SEL_IN_RDMA2 0x3 > > +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) > > +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) > > +#define DSI0_SEL_IN_RDMA1 0x1 > > +#define DSI0_SEL_IN_RDMA2 0x4 > > +#define DSI1_SEL_IN_RDMA1 0x1 > > +#define DSI1_SEL_IN_RDMA2 0x4 > > +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) > > +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) > > +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) > > +#define COLOR1_SEL_IN_OVL1 0x1 > > + > > +#define OVL_MOUT_EN_RDMA 0x1 > > +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 > > +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 > > +#define DSI_SEL_IN_BLS 0x0 > > +#define DPI_SEL_IN_BLS 0x0 > > +#define DSI_SEL_IN_RDMA 0x1 > > + > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; > > + value = OVL0_MOUT_EN_COLOR0; > > + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; > > + value = OVL_MOUT_EN_RDMA; > > + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD_MOUT_EN_RDMA0; > > + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; > > + value = UFOE_MOUT_EN_DSI0; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; > > + value = OVL1_MOUT_EN_COLOR1; > > + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; > > + value = GAMMA_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { > > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; > > + value = OD1_MOUT_EN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; > > + value = RDMA0_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DSI3; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; > > + value = RDMA1_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI0; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DPI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; > > + value = RDMA2_SOUT_DSI3; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr) > > +{ > > + unsigned int value; > > + > > + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; > > + value = COLOR0_SEL_IN_OVL0; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI3_SEL_IN_RDMA1; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { > > + *addr = DISP_REG_CONFIG_DPI_SEL_IN; > > + value = DPI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI0_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { > > + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > > + value = DSI1_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI2_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { > > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > > + value = DSI3_SEL_IN_RDMA2; > > + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { > > + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; > > + value = COLOR1_SEL_IN_OVL1; > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + *addr = DISP_REG_CONFIG_DSI_SEL; > > + value = DSI_SEL_IN_BLS; > > + } else { > > + value = 0; > > + } > > + > > + return value; > > +} > > + > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > > + enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next) > > +{ > > + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { > > + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > + config_regs + DISP_REG_CONFIG_OUT_SEL); > > + writel_relaxed(DSI_SEL_IN_RDMA, > > + config_regs + DISP_REG_CONFIG_DSI_SEL); > > + writel_relaxed(DPI_SEL_IN_BLS, > > + config_regs + DISP_REG_CONFIG_DPI_SEL); > > + } > > +} > > + > > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > > + .mout_en = mtk_mmsys_ddp_mout_en, > > + .sel_in = mtk_mmsys_ddp_sel_in, > > + .sout_sel = mtk_mmsys_ddp_sout_sel, > > I think you could implement these three function to be the same as the > three of mt8183 with mt2701 version of mmsys_mout_en[], > mmsys_sel_in[], mmsys_sout_sel[]. If you worry that you could not test > on mt2701, we could temporarily accept this and wait for someone has > mt2701 (or mt8173) to rewrite these three function to be the same as > mt8183. > > Regards, > Chun-Kuang. hi Chun-Kuang. thanks very much for your understand. actually, the display path connection of mt2701, mt2712, mt8173, mt6779, mt6797 are all different with each other. there will be mtxx-mmsys.c for every SoC. and the corresponded SoC upstream member will coding these and test it on the SoC if it is need. > > > +}; > > + _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu add mt8183 mmsys support Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 1 + 3 files changed, 163 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 33b0dab..62cfedf 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += mt2701-mmsys.o +obj-y += mt8183-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..9d5f276 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +struct mmsys_path_sel { + enum mtk_ddp_comp_id cur; + enum mtk_ddp_comp_id next; + u32 addr; + u32 val; +}; + +static struct mmsys_path_sel mmsys_mout_en[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, + }, + { + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, + }, +}; + +static struct mmsys_path_sel mmsys_sel_in[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, + }, +}; + +static struct mmsys_path_sel mmsys_sout_sel[] = { + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, + }, +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { + path = &mmsys_mout_en[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { + path = &mmsys_sel_in[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + u32 i; + u32 val = 0; + u32 addr = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { + path = &mmsys_sout_sel[i]; + if (cur == path->cur && next == path->next) { + addr = path->addr; + val = path->val; + break; + } + } + + if (val) + writel_relaxed(val, config_regs + addr); +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt8183-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 605b992..6a451ac 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .mmsys_driver = "mt8183-mmsys", }; void mtk_mmsys_ddp_connect(struct device *dev, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel add mt8183 mmsys support Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 1 + 3 files changed, 163 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 33b0dab..62cfedf 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += mt2701-mmsys.o +obj-y += mt8183-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..9d5f276 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +struct mmsys_path_sel { + enum mtk_ddp_comp_id cur; + enum mtk_ddp_comp_id next; + u32 addr; + u32 val; +}; + +static struct mmsys_path_sel mmsys_mout_en[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, + }, + { + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, + }, +}; + +static struct mmsys_path_sel mmsys_sel_in[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, + }, +}; + +static struct mmsys_path_sel mmsys_sout_sel[] = { + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, + }, +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { + path = &mmsys_mout_en[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { + path = &mmsys_sel_in[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + u32 i; + u32 val = 0; + u32 addr = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { + path = &mmsys_sout_sel[i]; + if (cur == path->cur && next == path->next) { + addr = path->addr; + val = path->val; + break; + } + } + + if (val) + writel_relaxed(val, config_regs + addr); +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt8183-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 605b992..6a451ac 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .mmsys_driver = "mt8183-mmsys", }; void mtk_mmsys_ddp_connect(struct device *dev, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel add mt8183 mmsys support Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 1 + 3 files changed, 163 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 33b0dab..62cfedf 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += mt2701-mmsys.o +obj-y += mt8183-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..9d5f276 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +struct mmsys_path_sel { + enum mtk_ddp_comp_id cur; + enum mtk_ddp_comp_id next; + u32 addr; + u32 val; +}; + +static struct mmsys_path_sel mmsys_mout_en[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, + }, + { + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, + }, +}; + +static struct mmsys_path_sel mmsys_sel_in[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, + }, +}; + +static struct mmsys_path_sel mmsys_sout_sel[] = { + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, + }, +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { + path = &mmsys_mout_en[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { + path = &mmsys_sel_in[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + u32 i; + u32 val = 0; + u32 addr = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { + path = &mmsys_sout_sel[i]; + if (cur == path->cur && next == path->next) { + addr = path->addr; + val = path->val; + break; + } + } + + if (val) + writel_relaxed(val, config_regs + addr); +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt8183-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 605b992..6a451ac 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .mmsys_driver = "mt8183-mmsys", }; void mtk_mmsys_ddp_connect(struct device *dev, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel add mt8183 mmsys support Feature: drm/mediatek Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 1 + 3 files changed, 163 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 33b0dab..62cfedf 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += mt2701-mmsys.o +obj-y += mt8183-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..9d5f276 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +struct mmsys_path_sel { + enum mtk_ddp_comp_id cur; + enum mtk_ddp_comp_id next; + u32 addr; + u32 val; +}; + +static struct mmsys_path_sel mmsys_mout_en[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, + }, + { + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, + }, +}; + +static struct mmsys_path_sel mmsys_sel_in[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, + }, +}; + +static struct mmsys_path_sel mmsys_sout_sel[] = { + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, + }, +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { + path = &mmsys_mout_en[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + u32 i; + u32 val = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { + path = &mmsys_sel_in[i]; + if (cur == path->cur && next == path->next) { + *addr = path->addr; + val = path->val; + break; + } + } + + return val; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + u32 i; + u32 val = 0; + u32 addr = 0; + struct mmsys_path_sel *path; + + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { + path = &mmsys_sout_sel[i]; + if (cur == path->cur && next == path->next) { + addr = path->addr; + val = path->val; + break; + } + } + + if (val) + writel_relaxed(val, config_regs + addr); +} + +static struct mtk_mmsys_conn_funcs mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; + +static int mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); + + return 0; +} + +static struct platform_driver mmsys_drv = { + .probe = mmsys_probe, + .driver = { + .name = "mt8183-mmsys", + }, +}; + +builtin_platform_driver(mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 605b992..6a451ac 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .mmsys_driver = "mt8183-mmsys", }; void mtk_mmsys_ddp_connect(struct device *dev, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-24 13:49 ` Nicolas Boichat -1 siblings, 0 replies; 112+ messages in thread From: Nicolas Boichat @ 2020-07-24 13:49 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, Devicetree List, lkml, linux-arm Mailing List, moderated list:ARM/Mediatek SoC support On Thu, Jul 23, 2020 at 10:05 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > add mt8183 mmsys support > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/Makefile | 1 + > drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 1 + > 3 files changed, 163 insertions(+) > create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > index 33b0dab..62cfedf 100644 > --- a/drivers/soc/mediatek/mmsys/Makefile > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-y += mt2701-mmsys.o > +obj-y += mt8183-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > new file mode 100644 > index 0000000..9d5f276 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > @@ -0,0 +1,161 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_OVL0_MOUT_EN 0xf00 > +#define DISP_OVL0_2L_MOUT_EN 0xf04 > +#define DISP_OVL1_2L_MOUT_EN 0xf08 > +#define DISP_DITHER0_MOUT_EN 0xf0c > +#define DISP_PATH0_SEL_IN 0xf24 > +#define DISP_DSI0_SEL_IN 0xf2c > +#define DISP_DPI0_SEL_IN 0xf30 > +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 > +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 > + > +#define OVL0_MOUT_EN_OVL0_2L BIT(4) > +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) > +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) > +#define DITHER0_MOUT_IN_DSI0 BIT(0) > +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 > +#define DSI0_SEL_IN_RDMA0 0x1 > +#define DSI0_SEL_IN_RDMA1 0x3 > +#define DPI0_SEL_IN_RDMA0 0x1 > +#define DPI0_SEL_IN_RDMA1 0x2 > +#define RDMA0_SOUT_COLOR0 0x1 > +#define RDMA1_SOUT_DSI0 0x1 > + > +struct mmsys_path_sel { > + enum mtk_ddp_comp_id cur; > + enum mtk_ddp_comp_id next; > + u32 addr; > + u32 val; > +}; > + > +static struct mmsys_path_sel mmsys_mout_en[] = { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, > + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, > + }, > + { > + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, > + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, > + }, > + { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sel_in[] = { > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, > + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sout_sel[] = { > + { > + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, > + }, > +}; > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { > + path = &mmsys_mout_en[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; return path->val? > + break; > + } > + } > + > + return val; Then this becomes just return 0; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { > + path = &mmsys_sel_in[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; > + break; > + } > + } > + > + return val; ditto > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + u32 i; > + u32 val = 0; > + u32 addr = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { > + path = &mmsys_sout_sel[i]; > + if (cur == path->cur && next == path->next) { > + addr = path->addr; > + val = path->val; > + break; writel_relaxed(path->val, config_regs + path->addr); return; > + } > + } > + > + if (val) > + writel_relaxed(val, config_regs + addr); > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt8183-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 605b992..6a451ac 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > + .mmsys_driver = "mt8183-mmsys", > }; > > void mtk_mmsys_ddp_connect(struct device *dev, > -- > 1.8.1.1.dirty ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support @ 2020-07-24 13:49 ` Nicolas Boichat 0 siblings, 0 replies; 112+ messages in thread From: Nicolas Boichat @ 2020-07-24 13:49 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, linux-arm Mailing List On Thu, Jul 23, 2020 at 10:05 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > add mt8183 mmsys support > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/Makefile | 1 + > drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 1 + > 3 files changed, 163 insertions(+) > create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > index 33b0dab..62cfedf 100644 > --- a/drivers/soc/mediatek/mmsys/Makefile > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-y += mt2701-mmsys.o > +obj-y += mt8183-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > new file mode 100644 > index 0000000..9d5f276 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > @@ -0,0 +1,161 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_OVL0_MOUT_EN 0xf00 > +#define DISP_OVL0_2L_MOUT_EN 0xf04 > +#define DISP_OVL1_2L_MOUT_EN 0xf08 > +#define DISP_DITHER0_MOUT_EN 0xf0c > +#define DISP_PATH0_SEL_IN 0xf24 > +#define DISP_DSI0_SEL_IN 0xf2c > +#define DISP_DPI0_SEL_IN 0xf30 > +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 > +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 > + > +#define OVL0_MOUT_EN_OVL0_2L BIT(4) > +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) > +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) > +#define DITHER0_MOUT_IN_DSI0 BIT(0) > +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 > +#define DSI0_SEL_IN_RDMA0 0x1 > +#define DSI0_SEL_IN_RDMA1 0x3 > +#define DPI0_SEL_IN_RDMA0 0x1 > +#define DPI0_SEL_IN_RDMA1 0x2 > +#define RDMA0_SOUT_COLOR0 0x1 > +#define RDMA1_SOUT_DSI0 0x1 > + > +struct mmsys_path_sel { > + enum mtk_ddp_comp_id cur; > + enum mtk_ddp_comp_id next; > + u32 addr; > + u32 val; > +}; > + > +static struct mmsys_path_sel mmsys_mout_en[] = { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, > + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, > + }, > + { > + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, > + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, > + }, > + { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sel_in[] = { > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, > + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sout_sel[] = { > + { > + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, > + }, > +}; > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { > + path = &mmsys_mout_en[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; return path->val? > + break; > + } > + } > + > + return val; Then this becomes just return 0; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { > + path = &mmsys_sel_in[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; > + break; > + } > + } > + > + return val; ditto > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + u32 i; > + u32 val = 0; > + u32 addr = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { > + path = &mmsys_sout_sel[i]; > + if (cur == path->cur && next == path->next) { > + addr = path->addr; > + val = path->val; > + break; writel_relaxed(path->val, config_regs + path->addr); return; > + } > + } > + > + if (val) > + writel_relaxed(val, config_regs + addr); > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt8183-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 605b992..6a451ac 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > + .mmsys_driver = "mt8183-mmsys", > }; > > void mtk_mmsys_ddp_connect(struct device *dev, > -- > 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support @ 2020-07-24 13:49 ` Nicolas Boichat 0 siblings, 0 replies; 112+ messages in thread From: Nicolas Boichat @ 2020-07-24 13:49 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Devicetree List, Philipp Zabel, David Airlie, lkml, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, linux-arm Mailing List On Thu, Jul 23, 2020 at 10:05 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > add mt8183 mmsys support > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/Makefile | 1 + > drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 1 + > 3 files changed, 163 insertions(+) > create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > index 33b0dab..62cfedf 100644 > --- a/drivers/soc/mediatek/mmsys/Makefile > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-y += mt2701-mmsys.o > +obj-y += mt8183-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > new file mode 100644 > index 0000000..9d5f276 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > @@ -0,0 +1,161 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_OVL0_MOUT_EN 0xf00 > +#define DISP_OVL0_2L_MOUT_EN 0xf04 > +#define DISP_OVL1_2L_MOUT_EN 0xf08 > +#define DISP_DITHER0_MOUT_EN 0xf0c > +#define DISP_PATH0_SEL_IN 0xf24 > +#define DISP_DSI0_SEL_IN 0xf2c > +#define DISP_DPI0_SEL_IN 0xf30 > +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 > +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 > + > +#define OVL0_MOUT_EN_OVL0_2L BIT(4) > +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) > +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) > +#define DITHER0_MOUT_IN_DSI0 BIT(0) > +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 > +#define DSI0_SEL_IN_RDMA0 0x1 > +#define DSI0_SEL_IN_RDMA1 0x3 > +#define DPI0_SEL_IN_RDMA0 0x1 > +#define DPI0_SEL_IN_RDMA1 0x2 > +#define RDMA0_SOUT_COLOR0 0x1 > +#define RDMA1_SOUT_DSI0 0x1 > + > +struct mmsys_path_sel { > + enum mtk_ddp_comp_id cur; > + enum mtk_ddp_comp_id next; > + u32 addr; > + u32 val; > +}; > + > +static struct mmsys_path_sel mmsys_mout_en[] = { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, > + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, > + }, > + { > + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, > + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, > + }, > + { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sel_in[] = { > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, > + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sout_sel[] = { > + { > + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, > + }, > +}; > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { > + path = &mmsys_mout_en[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; return path->val? > + break; > + } > + } > + > + return val; Then this becomes just return 0; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { > + path = &mmsys_sel_in[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; > + break; > + } > + } > + > + return val; ditto > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + u32 i; > + u32 val = 0; > + u32 addr = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { > + path = &mmsys_sout_sel[i]; > + if (cur == path->cur && next == path->next) { > + addr = path->addr; > + val = path->val; > + break; writel_relaxed(path->val, config_regs + path->addr); return; > + } > + } > + > + if (val) > + writel_relaxed(val, config_regs + addr); > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt8183-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 605b992..6a451ac 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > + .mmsys_driver = "mt8183-mmsys", > }; > > void mtk_mmsys_ddp_connect(struct device *dev, > -- > 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support @ 2020-07-24 13:49 ` Nicolas Boichat 0 siblings, 0 replies; 112+ messages in thread From: Nicolas Boichat @ 2020-07-24 13:49 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Devicetree List, Philipp Zabel, David Airlie, lkml, dri-devel, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Daniel Vetter, CK Hu, linux-arm Mailing List On Thu, Jul 23, 2020 at 10:05 AM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > add mt8183 mmsys support > > Feature: drm/mediatek > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/Makefile | 1 + > drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 161 ++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 1 + > 3 files changed, 163 insertions(+) > create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > index 33b0dab..62cfedf 100644 > --- a/drivers/soc/mediatek/mmsys/Makefile > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0-only > obj-y += mt2701-mmsys.o > +obj-y += mt8183-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > new file mode 100644 > index 0000000..9d5f276 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c > @@ -0,0 +1,161 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2020 MediaTek Inc. > + > +#include <linux/device.h> > +#include <linux/io.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-mmsys.h> > + > +#define DISP_OVL0_MOUT_EN 0xf00 > +#define DISP_OVL0_2L_MOUT_EN 0xf04 > +#define DISP_OVL1_2L_MOUT_EN 0xf08 > +#define DISP_DITHER0_MOUT_EN 0xf0c > +#define DISP_PATH0_SEL_IN 0xf24 > +#define DISP_DSI0_SEL_IN 0xf2c > +#define DISP_DPI0_SEL_IN 0xf30 > +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 > +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 > + > +#define OVL0_MOUT_EN_OVL0_2L BIT(4) > +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) > +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) > +#define DITHER0_MOUT_IN_DSI0 BIT(0) > +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 > +#define DSI0_SEL_IN_RDMA0 0x1 > +#define DSI0_SEL_IN_RDMA1 0x3 > +#define DPI0_SEL_IN_RDMA0 0x1 > +#define DPI0_SEL_IN_RDMA1 0x2 > +#define RDMA0_SOUT_COLOR0 0x1 > +#define RDMA1_SOUT_DSI0 0x1 > + > +struct mmsys_path_sel { > + enum mtk_ddp_comp_id cur; > + enum mtk_ddp_comp_id next; > + u32 addr; > + u32 val; > +}; > + > +static struct mmsys_path_sel mmsys_mout_en[] = { > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, > + DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_OVL0_2L_MOUT_EN, OVL0_2L_MOUT_EN_DISP_PATH0, > + }, > + { > + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, > + DISP_OVL1_2L_MOUT_EN, OVL1_2L_MOUT_EN_RDMA1, > + }, > + { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + DISP_DITHER0_MOUT_EN, DITHER0_MOUT_IN_DSI0, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sel_in[] = { > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + DISP_PATH0_SEL_IN, DISP_PATH0_SEL_IN_OVL0_2L, > + }, > + { > + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, > + DISP_DPI0_SEL_IN, DPI0_SEL_IN_RDMA1, > + }, > +}; > + > +static struct mmsys_path_sel mmsys_sout_sel[] = { > + { > + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > + DISP_RDMA0_SOUT_SEL_IN, RDMA0_SOUT_COLOR0, > + }, > +}; > + > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_mout_en); i++) { > + path = &mmsys_mout_en[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; return path->val? > + break; > + } > + } > + > + return val; Then this becomes just return 0; > +} > + > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr) > +{ > + u32 i; > + u32 val = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sel_in); i++) { > + path = &mmsys_sel_in[i]; > + if (cur == path->cur && next == path->next) { > + *addr = path->addr; > + val = path->val; > + break; > + } > + } > + > + return val; ditto > +} > + > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, > + enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next) > +{ > + u32 i; > + u32 val = 0; > + u32 addr = 0; > + struct mmsys_path_sel *path; > + > + for (i = 0; i < ARRAY_SIZE(mmsys_sout_sel); i++) { > + path = &mmsys_sout_sel[i]; > + if (cur == path->cur && next == path->next) { > + addr = path->addr; > + val = path->val; > + break; writel_relaxed(path->val, config_regs + path->addr); return; > + } > + } > + > + if (val) > + writel_relaxed(val, config_regs + addr); > +} > + > +static struct mtk_mmsys_conn_funcs mmsys_funcs = { > + .mout_en = mtk_mmsys_ddp_mout_en, > + .sel_in = mtk_mmsys_ddp_sel_in, > + .sout_sel = mtk_mmsys_ddp_sout_sel, > +}; > + > +static int mmsys_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + > + mtk_mmsys_register_conn_funcs(dev->parent, &mmsys_funcs); > + > + return 0; > +} > + > +static struct platform_driver mmsys_drv = { > + .probe = mmsys_probe, > + .driver = { > + .name = "mt8183-mmsys", > + }, > +}; > + > +builtin_platform_driver(mmsys_drv); > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 605b992..6a451ac 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -47,6 +47,7 @@ struct mtk_mmsys_private_data { > > static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .clk_driver = "clk-mt8183-mm", > + .mmsys_driver = "mt8183-mmsys", > }; > > void mtk_mmsys_ddp_connect(struct device *dev, > -- > 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu Update device tree binding document for rdma_fifo_size Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709..e6bbe32 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -66,6 +66,11 @@ Required properties (DMA function blocks): argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details. +Optional properties (RDMA function blocks): +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this + property to the corresponding rdma + the value is the Max value which defined in hardware data sheet. + Examples: mmsys: clock-controller@14000000 { @@ -207,3 +212,12 @@ od@14023000 { power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OD>; }; + +rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; +}; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel Update device tree binding document for rdma_fifo_size Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709..e6bbe32 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -66,6 +66,11 @@ Required properties (DMA function blocks): argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details. +Optional properties (RDMA function blocks): +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this + property to the corresponding rdma + the value is the Max value which defined in hardware data sheet. + Examples: mmsys: clock-controller@14000000 { @@ -207,3 +212,12 @@ od@14023000 { power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OD>; }; + +rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; +}; -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel Update device tree binding document for rdma_fifo_size Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709..e6bbe32 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -66,6 +66,11 @@ Required properties (DMA function blocks): argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details. +Optional properties (RDMA function blocks): +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this + property to the corresponding rdma + the value is the Max value which defined in hardware data sheet. + Examples: mmsys: clock-controller@14000000 { @@ -207,3 +212,12 @@ od@14023000 { power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OD>; }; + +rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; +}; -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel Update device tree binding document for rdma_fifo_size Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index b91e709..e6bbe32 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -66,6 +66,11 @@ Required properties (DMA function blocks): argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details. +Optional properties (RDMA function blocks): +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this + property to the corresponding rdma + the value is the Max value which defined in hardware data sheet. + Examples: mmsys: clock-controller@14000000 { @@ -207,3 +212,12 @@ od@14023000 { power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OD>; }; + +rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; +}; -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 15:41 ` Matthias Brugger -1 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:41 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek On 23/07/2020 04:03, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > Please explain better what you are doing in the patch. Also DT binding patches should normally go as the first of a series, as this helps Rob to review them. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 15:41 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:41 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > Please explain better what you are doing in the patch. Also DT binding patches should normally go as the first of a series, as this helps Rob to review them. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 15:41 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:41 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > Please explain better what you are doing in the patch. Also DT binding patches should normally go as the first of a series, as this helps Rob to review them. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 15:41 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:41 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > Please explain better what you are doing in the patch. Also DT binding patches should normally go as the first of a series, as this helps Rob to review them. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 16:59 ` Rob Herring -1 siblings, 0 replies; 112+ messages in thread From: Rob Herring @ 2020-07-23 16:59 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek On Thu, Jul 23, 2020 at 10:03:15AM +0800, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this s/_/-/ > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > -- > 1.8.1.1.dirty ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 16:59 ` Rob Herring 0 siblings, 0 replies; 112+ messages in thread From: Rob Herring @ 2020-07-23 16:59 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, linux-mediatek, linux-arm-kernel On Thu, Jul 23, 2020 at 10:03:15AM +0800, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this s/_/-/ > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > -- > 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 16:59 ` Rob Herring 0 siblings, 0 replies; 112+ messages in thread From: Rob Herring @ 2020-07-23 16:59 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, linux-mediatek, Daniel Vetter, CK Hu, linux-arm-kernel On Thu, Jul 23, 2020 at 10:03:15AM +0800, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this s/_/-/ > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > -- > 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display @ 2020-07-23 16:59 ` Rob Herring 0 siblings, 0 replies; 112+ messages in thread From: Rob Herring @ 2020-07-23 16:59 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, linux-mediatek, Daniel Vetter, CK Hu, linux-arm-kernel On Thu, Jul 23, 2020 at 10:03:15AM +0800, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this s/_/-/ > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > -- > 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu This patch add display nodes for mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 7b781eb..440cf22 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -31,6 +31,11 @@ i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; + ovl0 = &ovl0; + ovl_2l0 = &ovl_2l0; + ovl_2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; }; cpus { @@ -707,9 +712,102 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; #clock-cells = <1>; }; + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + mediatek,rdma_fifo_size = <5120>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel This patch add display nodes for mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 7b781eb..440cf22 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -31,6 +31,11 @@ i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; + ovl0 = &ovl0; + ovl_2l0 = &ovl_2l0; + ovl_2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; }; cpus { @@ -707,9 +712,102 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; #clock-cells = <1>; }; + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + mediatek,rdma_fifo_size = <5120>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add display nodes for mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 7b781eb..440cf22 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -31,6 +31,11 @@ i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; + ovl0 = &ovl0; + ovl_2l0 = &ovl_2l0; + ovl_2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; }; cpus { @@ -707,9 +712,102 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; #clock-cells = <1>; }; + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + mediatek,rdma_fifo_size = <5120>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add display nodes for mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 7b781eb..440cf22 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -31,6 +31,11 @@ i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; + ovl0 = &ovl0; + ovl_2l0 = &ovl_2l0; + ovl_2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; }; cpus { @@ -707,9 +712,102 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; #clock-cells = <1>; }; + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + mediatek,rdma_fifo_size = <5120>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + mediatek,rdma_fifo_size = <2048>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 15:42 ` Matthias Brugger -1 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:42 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add display nodes for mt8183 > In comparison, DTS patches should go last in a series as you will need the driver patches to make it work. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ > 1 file changed, 98 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 7b781eb..440cf22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -31,6 +31,11 @@ > i2c9 = &i2c9; > i2c10 = &i2c10; > i2c11 = &i2c11; > + ovl0 = &ovl0; > + ovl_2l0 = &ovl_2l0; > + ovl_2l1 = &ovl_2l1; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > }; > > cpus { > @@ -707,9 +712,102 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8183-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > #clock-cells = <1>; > }; > > + ovl0: ovl@14008000 { > + compatible = "mediatek,mt8183-disp-ovl"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + }; > + > + ovl_2l0: ovl@14009000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + }; > + > + ovl_2l1: ovl@1400a000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; > + }; > + > + rdma0: rdma@1400b000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + mediatek,rdma_fifo_size = <5120>; > + }; > + > + rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > + }; > + > + color0: color@1400e000 { > + compatible = "mediatek,mt8183-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400f000 { > + compatible = "mediatek,mt8183-disp-ccorr"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@14010000 { > + compatible = "mediatek,mt8183-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@14011000 { > + compatible = "mediatek,mt8183-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + dither0: dither@14012000 { > + compatible = "mediatek,mt8183-disp-dither"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > + mutex: mutex@14016000 { > + compatible = "mediatek,mt8183-disp-mutex"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + }; > + > smi_common: smi@14019000 { > compatible = "mediatek,mt8183-smi-common", "syscon"; > reg = <0 0x14019000 0 0x1000>; > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 @ 2020-07-23 15:42 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:42 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add display nodes for mt8183 > In comparison, DTS patches should go last in a series as you will need the driver patches to make it work. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ > 1 file changed, 98 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 7b781eb..440cf22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -31,6 +31,11 @@ > i2c9 = &i2c9; > i2c10 = &i2c10; > i2c11 = &i2c11; > + ovl0 = &ovl0; > + ovl_2l0 = &ovl_2l0; > + ovl_2l1 = &ovl_2l1; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > }; > > cpus { > @@ -707,9 +712,102 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8183-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > #clock-cells = <1>; > }; > > + ovl0: ovl@14008000 { > + compatible = "mediatek,mt8183-disp-ovl"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + }; > + > + ovl_2l0: ovl@14009000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + }; > + > + ovl_2l1: ovl@1400a000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; > + }; > + > + rdma0: rdma@1400b000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + mediatek,rdma_fifo_size = <5120>; > + }; > + > + rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > + }; > + > + color0: color@1400e000 { > + compatible = "mediatek,mt8183-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400f000 { > + compatible = "mediatek,mt8183-disp-ccorr"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@14010000 { > + compatible = "mediatek,mt8183-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@14011000 { > + compatible = "mediatek,mt8183-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + dither0: dither@14012000 { > + compatible = "mediatek,mt8183-disp-dither"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > + mutex: mutex@14016000 { > + compatible = "mediatek,mt8183-disp-mutex"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + }; > + > smi_common: smi@14019000 { > compatible = "mediatek,mt8183-smi-common", "syscon"; > reg = <0 0x14019000 0 0x1000>; > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 @ 2020-07-23 15:42 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:42 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add display nodes for mt8183 > In comparison, DTS patches should go last in a series as you will need the driver patches to make it work. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ > 1 file changed, 98 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 7b781eb..440cf22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -31,6 +31,11 @@ > i2c9 = &i2c9; > i2c10 = &i2c10; > i2c11 = &i2c11; > + ovl0 = &ovl0; > + ovl_2l0 = &ovl_2l0; > + ovl_2l1 = &ovl_2l1; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > }; > > cpus { > @@ -707,9 +712,102 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8183-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > #clock-cells = <1>; > }; > > + ovl0: ovl@14008000 { > + compatible = "mediatek,mt8183-disp-ovl"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + }; > + > + ovl_2l0: ovl@14009000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + }; > + > + ovl_2l1: ovl@1400a000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; > + }; > + > + rdma0: rdma@1400b000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + mediatek,rdma_fifo_size = <5120>; > + }; > + > + rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > + }; > + > + color0: color@1400e000 { > + compatible = "mediatek,mt8183-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400f000 { > + compatible = "mediatek,mt8183-disp-ccorr"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@14010000 { > + compatible = "mediatek,mt8183-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@14011000 { > + compatible = "mediatek,mt8183-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + dither0: dither@14012000 { > + compatible = "mediatek,mt8183-disp-dither"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > + mutex: mutex@14016000 { > + compatible = "mediatek,mt8183-disp-mutex"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + }; > + > smi_common: smi@14019000 { > compatible = "mediatek,mt8183-smi-common", "syscon"; > reg = <0 0x14019000 0 0x1000>; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 @ 2020-07-23 15:42 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:42 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add display nodes for mt8183 > In comparison, DTS patches should go last in a series as you will need the driver patches to make it work. Regards, Matthias > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++ > 1 file changed, 98 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 7b781eb..440cf22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -31,6 +31,11 @@ > i2c9 = &i2c9; > i2c10 = &i2c10; > i2c11 = &i2c11; > + ovl0 = &ovl0; > + ovl_2l0 = &ovl_2l0; > + ovl_2l1 = &ovl_2l1; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > }; > > cpus { > @@ -707,9 +712,102 @@ > mmsys: syscon@14000000 { > compatible = "mediatek,mt8183-mmsys", "syscon"; > reg = <0 0x14000000 0 0x1000>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > #clock-cells = <1>; > }; > > + ovl0: ovl@14008000 { > + compatible = "mediatek,mt8183-disp-ovl"; > + reg = <0 0x14008000 0 0x1000>; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + }; > + > + ovl_2l0: ovl@14009000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + }; > + > + ovl_2l1: ovl@1400a000 { > + compatible = "mediatek,mt8183-disp-ovl-2l"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; > + }; > + > + rdma0: rdma@1400b000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + mediatek,rdma_fifo_size = <5120>; > + }; > + > + rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > + }; > + > + color0: color@1400e000 { > + compatible = "mediatek,mt8183-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; > + > + ccorr0: ccorr@1400f000 { > + compatible = "mediatek,mt8183-disp-ccorr"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@14010000 { > + compatible = "mediatek,mt8183-disp-aal", > + "mediatek,mt8173-disp-aal"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@14011000 { > + compatible = "mediatek,mt8183-disp-gamma", > + "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + dither0: dither@14012000 { > + compatible = "mediatek,mt8183-disp-dither"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > + mutex: mutex@14016000 { > + compatible = "mediatek,mt8183-disp-mutex"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + }; > + > smi_common: smi@14019000 { > compatible = "mediatek,mt8183-smi-common", "syscon"; > reg = <0 0x14019000 0 0x1000>; > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu the fifo size of rdma in mt8183 is different. rdma0 fifo size is 5k rdma1 fifo size is 2k Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index e04319f..794acc5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -63,6 +63,7 @@ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; const struct mtk_disp_rdma_data *data; + u32 fifo_size; }; static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + u32 rdma_fifo_size; mtk_ddp_write_mask(cmdq_pkt, width, comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff); mtk_ddp_write_mask(cmdq_pkt, height, comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); + if (rdma->fifo_size) + rdma_fifo_size = rdma->fifo_size; + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, */ threshold = width * height * vrefresh * 4 * 7 / 1000000; reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); } @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { + ret = of_property_read_u32(dev->of_node, + "mediatek,rdma_fifo_size", + &priv->fifo_size); + if (ret) { + dev_err(dev, "Failed to get rdma fifo size\n"); + return ret; + } + } + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_rdma_funcs); if (ret) { -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel the fifo size of rdma in mt8183 is different. rdma0 fifo size is 5k rdma1 fifo size is 2k Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index e04319f..794acc5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -63,6 +63,7 @@ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; const struct mtk_disp_rdma_data *data; + u32 fifo_size; }; static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + u32 rdma_fifo_size; mtk_ddp_write_mask(cmdq_pkt, width, comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff); mtk_ddp_write_mask(cmdq_pkt, height, comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); + if (rdma->fifo_size) + rdma_fifo_size = rdma->fifo_size; + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, */ threshold = width * height * vrefresh * 4 * 7 / 1000000; reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); } @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { + ret = of_property_read_u32(dev->of_node, + "mediatek,rdma_fifo_size", + &priv->fifo_size); + if (ret) { + dev_err(dev, "Failed to get rdma fifo size\n"); + return ret; + } + } + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_rdma_funcs); if (ret) { -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel the fifo size of rdma in mt8183 is different. rdma0 fifo size is 5k rdma1 fifo size is 2k Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index e04319f..794acc5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -63,6 +63,7 @@ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; const struct mtk_disp_rdma_data *data; + u32 fifo_size; }; static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + u32 rdma_fifo_size; mtk_ddp_write_mask(cmdq_pkt, width, comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff); mtk_ddp_write_mask(cmdq_pkt, height, comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); + if (rdma->fifo_size) + rdma_fifo_size = rdma->fifo_size; + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, */ threshold = width * height * vrefresh * 4 * 7 / 1000000; reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); } @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { + ret = of_property_read_u32(dev->of_node, + "mediatek,rdma_fifo_size", + &priv->fifo_size); + if (ret) { + dev_err(dev, "Failed to get rdma fifo size\n"); + return ret; + } + } + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_rdma_funcs); if (ret) { -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel the fifo size of rdma in mt8183 is different. rdma0 fifo size is 5k rdma1 fifo size is 2k Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index e04319f..794acc5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -63,6 +63,7 @@ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; const struct mtk_disp_rdma_data *data; + u32 fifo_size; }; static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + u32 rdma_fifo_size; mtk_ddp_write_mask(cmdq_pkt, width, comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff); mtk_ddp_write_mask(cmdq_pkt, height, comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); + if (rdma->fifo_size) + rdma_fifo_size = rdma->fifo_size; + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, */ threshold = width * height * vrefresh * 4 * 7 / 1000000; reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); } @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { + ret = of_property_read_u32(dev->of_node, + "mediatek,rdma_fifo_size", + &priv->fifo_size); + if (ret) { + dev_err(dev, "Failed to get rdma fifo size\n"); + return ret; + } + } + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_rdma_funcs); if (ret) { -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-25 3:50 ` Chun-Kuang Hu -1 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:50 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM The primary thing of this patch is to get fifo size from device tree. So you may modify title to show the primary thing. Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:12寫道： > > the fifo size of rdma in mt8183 is different. > rdma0 fifo size is 5k > rdma1 fifo size is 2k I would like the description to be "Get the fifo size from device tree because each rdma in the same SoC may have different fifo size." Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index e04319f..794acc5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -63,6 +63,7 @@ struct mtk_disp_rdma { > struct mtk_ddp_comp ddp_comp; > struct drm_crtc *crtc; > const struct mtk_disp_rdma_data *data; > + u32 fifo_size; > }; > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) > @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > unsigned int threshold; > unsigned int reg; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > + u32 rdma_fifo_size; > > mtk_ddp_write_mask(cmdq_pkt, width, comp, > DISP_REG_RDMA_SIZE_CON_0, 0xfff); > mtk_ddp_write_mask(cmdq_pkt, height, comp, > DISP_REG_RDMA_SIZE_CON_1, 0xfffff); > > + if (rdma->fifo_size) > + rdma_fifo_size = rdma->fifo_size; > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); > + > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); > } > @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) > return comp_id; > } > > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { > + ret = of_property_read_u32(dev->of_node, > + "mediatek,rdma_fifo_size", > + &priv->fifo_size); > + if (ret) { > + dev_err(dev, "Failed to get rdma fifo size\n"); > + return ret; > + } > + } > + > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, > &mtk_disp_rdma_funcs); > if (ret) { > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data @ 2020-07-25 3:50 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM The primary thing of this patch is to get fifo size from device tree. So you may modify title to show the primary thing. Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:12寫道： > > the fifo size of rdma in mt8183 is different. > rdma0 fifo size is 5k > rdma1 fifo size is 2k I would like the description to be "Get the fifo size from device tree because each rdma in the same SoC may have different fifo size." Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index e04319f..794acc5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -63,6 +63,7 @@ struct mtk_disp_rdma { > struct mtk_ddp_comp ddp_comp; > struct drm_crtc *crtc; > const struct mtk_disp_rdma_data *data; > + u32 fifo_size; > }; > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) > @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > unsigned int threshold; > unsigned int reg; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > + u32 rdma_fifo_size; > > mtk_ddp_write_mask(cmdq_pkt, width, comp, > DISP_REG_RDMA_SIZE_CON_0, 0xfff); > mtk_ddp_write_mask(cmdq_pkt, height, comp, > DISP_REG_RDMA_SIZE_CON_1, 0xfffff); > > + if (rdma->fifo_size) > + rdma_fifo_size = rdma->fifo_size; > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); > + > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); > } > @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) > return comp_id; > } > > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { > + ret = of_property_read_u32(dev->of_node, > + "mediatek,rdma_fifo_size", > + &priv->fifo_size); > + if (ret) { > + dev_err(dev, "Failed to get rdma fifo size\n"); > + return ret; > + } > + } > + > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, > &mtk_disp_rdma_funcs); > if (ret) { > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data @ 2020-07-25 3:50 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM The primary thing of this patch is to get fifo size from device tree. So you may modify title to show the primary thing. Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:12寫道： > > the fifo size of rdma in mt8183 is different. > rdma0 fifo size is 5k > rdma1 fifo size is 2k I would like the description to be "Get the fifo size from device tree because each rdma in the same SoC may have different fifo size." Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index e04319f..794acc5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -63,6 +63,7 @@ struct mtk_disp_rdma { > struct mtk_ddp_comp ddp_comp; > struct drm_crtc *crtc; > const struct mtk_disp_rdma_data *data; > + u32 fifo_size; > }; > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) > @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > unsigned int threshold; > unsigned int reg; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > + u32 rdma_fifo_size; > > mtk_ddp_write_mask(cmdq_pkt, width, comp, > DISP_REG_RDMA_SIZE_CON_0, 0xfff); > mtk_ddp_write_mask(cmdq_pkt, height, comp, > DISP_REG_RDMA_SIZE_CON_1, 0xfffff); > > + if (rdma->fifo_size) > + rdma_fifo_size = rdma->fifo_size; > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); > + > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); > } > @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) > return comp_id; > } > > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { > + ret = of_property_read_u32(dev->of_node, > + "mediatek,rdma_fifo_size", > + &priv->fifo_size); > + if (ret) { > + dev_err(dev, "Failed to get rdma fifo size\n"); > + return ret; > + } > + } > + > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, > &mtk_disp_rdma_funcs); > if (ret) { > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data @ 2020-07-25 3:50 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM The primary thing of this patch is to get fifo size from device tree. So you may modify title to show the primary thing. Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:12寫道： > > the fifo size of rdma in mt8183 is different. > rdma0 fifo size is 5k > rdma1 fifo size is 2k I would like the description to be "Get the fifo size from device tree because each rdma in the same SoC may have different fifo size." Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index e04319f..794acc5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -63,6 +63,7 @@ struct mtk_disp_rdma { > struct mtk_ddp_comp ddp_comp; > struct drm_crtc *crtc; > const struct mtk_disp_rdma_data *data; > + u32 fifo_size; > }; > > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) > @@ -131,12 +132,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > unsigned int threshold; > unsigned int reg; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > + u32 rdma_fifo_size; > > mtk_ddp_write_mask(cmdq_pkt, width, comp, > DISP_REG_RDMA_SIZE_CON_0, 0xfff); > mtk_ddp_write_mask(cmdq_pkt, height, comp, > DISP_REG_RDMA_SIZE_CON_1, 0xfffff); > > + if (rdma->fifo_size) > + rdma_fifo_size = rdma->fifo_size; > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); > + > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -145,7 +152,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); > } > @@ -291,6 +298,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) > return comp_id; > } > > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) { > + ret = of_property_read_u32(dev->of_node, > + "mediatek,rdma_fifo_size", > + &priv->fifo_size); > + if (ret) { > + dev_err(dev, "Failed to get rdma fifo size\n"); > + return ret; > + } > + } > + > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, > &mtk_disp_rdma_funcs); > if (ret) { > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 2:03 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu This patch add support for mediatek SOC MT8183 1.ovl_2l share driver with ovl 2.rdma1 share drive with rdma0, but fifo size is different 3.add mt8183 mutex private data, and mmsys private data 4.add mt8183 main and external path module for crtc create Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 28651bc..8cf9f3b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..51f2a0c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) .fifo_size = SZ_8K, }; +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 014c1bb..60788c1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -15,6 +15,8 @@ #define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -25,6 +27,18 @@ #define INT_MUTEX BIT(1) +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -74,6 +88,10 @@ #define MUTEX_SOF_DSI2 5 #define MUTEX_SOF_DSI3 6 +#define MT8183_MUTEX_SOF_DPI0 2 +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) + struct mtk_disp_mutex { int id; @@ -153,6 +171,20 @@ struct mtk_ddp { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -163,6 +195,12 @@ struct mtk_ddp { [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, +}; + static const struct mtk_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -184,6 +222,13 @@ struct mtk_ddp { .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, }; +static const struct mtk_ddp_data mt8183_ddp_driver_data = { + .mutex_mod = mt8183_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, +}; + struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) { struct mtk_ddp *ddp = dev_get_drvdata(dev); @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) .data = &mt2712_ddp_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data}, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = &mt8183_ddp_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6bd3694..267e91e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -119,6 +119,24 @@ DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -143,6 +161,13 @@ .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, { } }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel This patch add support for mediatek SOC MT8183 1.ovl_2l share driver with ovl 2.rdma1 share drive with rdma0, but fifo size is different 3.add mt8183 mutex private data, and mmsys private data 4.add mt8183 main and external path module for crtc create Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 28651bc..8cf9f3b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..51f2a0c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) .fifo_size = SZ_8K, }; +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 014c1bb..60788c1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -15,6 +15,8 @@ #define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -25,6 +27,18 @@ #define INT_MUTEX BIT(1) +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -74,6 +88,10 @@ #define MUTEX_SOF_DSI2 5 #define MUTEX_SOF_DSI3 6 +#define MT8183_MUTEX_SOF_DPI0 2 +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) + struct mtk_disp_mutex { int id; @@ -153,6 +171,20 @@ struct mtk_ddp { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -163,6 +195,12 @@ struct mtk_ddp { [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, +}; + static const struct mtk_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -184,6 +222,13 @@ struct mtk_ddp { .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, }; +static const struct mtk_ddp_data mt8183_ddp_driver_data = { + .mutex_mod = mt8183_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, +}; + struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) { struct mtk_ddp *ddp = dev_get_drvdata(dev); @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) .data = &mt2712_ddp_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data}, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = &mt8183_ddp_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6bd3694..267e91e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -119,6 +119,24 @@ DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -143,6 +161,13 @@ .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, { } }; -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add support for mediatek SOC MT8183 1.ovl_2l share driver with ovl 2.rdma1 share drive with rdma0, but fifo size is different 3.add mt8183 mutex private data, and mmsys private data 4.add mt8183 main and external path module for crtc create Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 28651bc..8cf9f3b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..51f2a0c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) .fifo_size = SZ_8K, }; +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 014c1bb..60788c1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -15,6 +15,8 @@ #define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -25,6 +27,18 @@ #define INT_MUTEX BIT(1) +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -74,6 +88,10 @@ #define MUTEX_SOF_DSI2 5 #define MUTEX_SOF_DSI3 6 +#define MT8183_MUTEX_SOF_DPI0 2 +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) + struct mtk_disp_mutex { int id; @@ -153,6 +171,20 @@ struct mtk_ddp { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -163,6 +195,12 @@ struct mtk_ddp { [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, +}; + static const struct mtk_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -184,6 +222,13 @@ struct mtk_ddp { .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, }; +static const struct mtk_ddp_data mt8183_ddp_driver_data = { + .mutex_mod = mt8183_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, +}; + struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) { struct mtk_ddp *ddp = dev_get_drvdata(dev); @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) .data = &mt2712_ddp_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data}, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = &mt8183_ddp_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6bd3694..267e91e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -119,6 +119,24 @@ DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -143,6 +161,13 @@ .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, { } }; -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 112+ messages in thread
* [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-23 2:03 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-23 2:03 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add support for mediatek SOC MT8183 1.ovl_2l share driver with ovl 2.rdma1 share drive with rdma0, but fifo size is different 3.add mt8183 mutex private data, and mmsys private data 4.add mt8183 main and external path module for crtc create Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 28651bc..8cf9f3b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 794acc5..51f2a0c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) .fifo_size = SZ_8K, }; +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 014c1bb..60788c1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -15,6 +15,8 @@ #define MT2701_DISP_MUTEX0_MOD0 0x2c #define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT8183_DISP_MUTEX0_MOD0 0x30 +#define MT8183_DISP_MUTEX0_SOF0 0x2c #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -25,6 +27,18 @@ #define INT_MUTEX BIT(1) +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + #define MT8173_MUTEX_MOD_DISP_OVL0 11 #define MT8173_MUTEX_MOD_DISP_OVL1 12 #define MT8173_MUTEX_MOD_DISP_RDMA0 13 @@ -74,6 +88,10 @@ #define MUTEX_SOF_DSI2 5 #define MUTEX_SOF_DSI3 6 +#define MT8183_MUTEX_SOF_DPI0 2 +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) + struct mtk_disp_mutex { int id; @@ -153,6 +171,20 @@ struct mtk_ddp { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, +}; + static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -163,6 +195,12 @@ struct mtk_ddp { [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, +}; + static const struct mtk_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -184,6 +222,13 @@ struct mtk_ddp { .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, }; +static const struct mtk_ddp_data mt8183_ddp_driver_data = { + .mutex_mod = mt8183_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, +}; + struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) { struct mtk_ddp *ddp = dev_get_drvdata(dev); @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) .data = &mt2712_ddp_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data}, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = &mt8183_ddp_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6bd3694..267e91e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -119,6 +119,24 @@ DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -143,6 +161,13 @@ .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, { } }; -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-23 15:40 ` Matthias Brugger -1 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:40 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create Please fix your commit message, this is seems to describe what the whole series is doing. Regards, Matthias > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 28651bc..8cf9f3b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = &mt8173_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = &mt8183_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = &mt8183_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 794acc5..51f2a0c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > .fifo_size = SZ_8K, > }; > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = &mt8173_rdma_driver_data}, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = &mt8183_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > + .mutex_mod = mt8183_mutex_mod, > + .mutex_sof = mt8183_mutex_sof, > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > +}; > + > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > .data = &mt2712_ddp_driver_data}, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = &mt8173_ddp_driver_data}, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = &mt8183_ddp_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 6bd3694..267e91e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -119,6 +119,24 @@ > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -143,6 +161,13 @@ > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > + .main_path = mt8183_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > + .ext_path = mt8183_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > + { .compatible = "mediatek,mt8183-disp-dither", > + .data = (void *)MTK_DISP_DITHER }, > { .compatible = "mediatek,mt8173-disp-ufoe", > .data = (void *)MTK_DISP_UFOE }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > .data = (void *)MTK_DSI }, > + { .compatible = "mediatek,mt8183-dsi", > + .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt2701-dpi", > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8173-dpi", > .data = (void *)MTK_DPI }, > + { .compatible = "mediatek,mt8183-dpi", > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2712-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > + { .compatible = "mediatek,mt8183-mmsys", > + .data = &mt8183_mmsys_driver_data}, > { } > }; > > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-23 15:40 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:40 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create Please fix your commit message, this is seems to describe what the whole series is doing. Regards, Matthias > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 28651bc..8cf9f3b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = &mt8173_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = &mt8183_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = &mt8183_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 794acc5..51f2a0c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > .fifo_size = SZ_8K, > }; > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = &mt8173_rdma_driver_data}, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = &mt8183_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > + .mutex_mod = mt8183_mutex_mod, > + .mutex_sof = mt8183_mutex_sof, > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > +}; > + > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > .data = &mt2712_ddp_driver_data}, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = &mt8173_ddp_driver_data}, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = &mt8183_ddp_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 6bd3694..267e91e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -119,6 +119,24 @@ > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -143,6 +161,13 @@ > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > + .main_path = mt8183_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > + .ext_path = mt8183_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > + { .compatible = "mediatek,mt8183-disp-dither", > + .data = (void *)MTK_DISP_DITHER }, > { .compatible = "mediatek,mt8173-disp-ufoe", > .data = (void *)MTK_DISP_UFOE }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > .data = (void *)MTK_DSI }, > + { .compatible = "mediatek,mt8183-dsi", > + .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt2701-dpi", > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8173-dpi", > .data = (void *)MTK_DPI }, > + { .compatible = "mediatek,mt8183-dpi", > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2712-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > + { .compatible = "mediatek,mt8183-mmsys", > + .data = &mt8183_mmsys_driver_data}, > { } > }; > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-23 15:40 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:40 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create Please fix your commit message, this is seems to describe what the whole series is doing. Regards, Matthias > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 28651bc..8cf9f3b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = &mt8173_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = &mt8183_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = &mt8183_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 794acc5..51f2a0c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > .fifo_size = SZ_8K, > }; > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = &mt8173_rdma_driver_data}, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = &mt8183_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > + .mutex_mod = mt8183_mutex_mod, > + .mutex_sof = mt8183_mutex_sof, > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > +}; > + > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > .data = &mt2712_ddp_driver_data}, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = &mt8173_ddp_driver_data}, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = &mt8183_ddp_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 6bd3694..267e91e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -119,6 +119,24 @@ > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -143,6 +161,13 @@ > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > + .main_path = mt8183_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > + .ext_path = mt8183_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > + { .compatible = "mediatek,mt8183-disp-dither", > + .data = (void *)MTK_DISP_DITHER }, > { .compatible = "mediatek,mt8173-disp-ufoe", > .data = (void *)MTK_DISP_UFOE }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > .data = (void *)MTK_DSI }, > + { .compatible = "mediatek,mt8183-dsi", > + .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt2701-dpi", > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8173-dpi", > .data = (void *)MTK_DPI }, > + { .compatible = "mediatek,mt8183-dpi", > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2712-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > + { .compatible = "mediatek,mt8183-mmsys", > + .data = &mt8183_mmsys_driver_data}, > { } > }; > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-23 15:40 ` Matthias Brugger 0 siblings, 0 replies; 112+ messages in thread From: Matthias Brugger @ 2020-07-23 15:40 UTC (permalink / raw) To: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On 23/07/2020 04:03, Yongqiang Niu wrote: > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl > 2.rdma1 share drive with rdma0, but fifo size is different > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create Please fix your commit message, this is seems to describe what the whole series is doing. Regards, Matthias > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 28651bc..8cf9f3b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = &mt8173_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = &mt8183_ovl_driver_data}, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = &mt8183_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 794acc5..51f2a0c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > .fifo_size = SZ_8K, > }; > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = &mt8173_rdma_driver_data}, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = &mt8183_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > + .mutex_mod = mt8183_mutex_mod, > + .mutex_sof = mt8183_mutex_sof, > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > +}; > + > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > { > struct mtk_ddp *ddp = dev_get_drvdata(dev); > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > .data = &mt2712_ddp_driver_data}, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = &mt8173_ddp_driver_data}, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = &mt8183_ddp_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 6bd3694..267e91e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -119,6 +119,24 @@ > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_RDMA1, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -143,6 +161,13 @@ > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > + .main_path = mt8183_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > + .ext_path = mt8183_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8173-disp-ovl", > .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8183-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > + { .compatible = "mediatek,mt8183-disp-dither", > + .data = (void *)MTK_DISP_DITHER }, > { .compatible = "mediatek,mt8173-disp-ufoe", > .data = (void *)MTK_DISP_UFOE }, > { .compatible = "mediatek,mt2701-dsi", > .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt8173-dsi", > .data = (void *)MTK_DSI }, > + { .compatible = "mediatek,mt8183-dsi", > + .data = (void *)MTK_DSI }, > { .compatible = "mediatek,mt2701-dpi", > .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt8173-dpi", > .data = (void *)MTK_DPI }, > + { .compatible = "mediatek,mt8183-dpi", > + .data = (void *)MTK_DPI }, > { .compatible = "mediatek,mt2701-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2712-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8173-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8183-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > .data = &mt2712_mmsys_driver_data}, > { .compatible = "mediatek,mt8173-mmsys", > .data = &mt8173_mmsys_driver_data}, > + { .compatible = "mediatek,mt8183-mmsys", > + .data = &mt8183_mmsys_driver_data}, > { } > }; > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-23 15:40 ` Matthias Brugger (?) (?) @ 2020-07-25 3:31 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:31 UTC (permalink / raw) To: Matthias Brugger Cc: CK Hu, Philipp Zabel, Rob Herring, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek On Thu, 2020-07-23 at 17:40 +0200, Matthias Brugger wrote: > > On 23/07/2020 04:03, Yongqiang Niu wrote: > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > 2.rdma1 share drive with rdma0, but fifo size is different > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > Please fix your commit message, this is seems to describe what the whole series > is doing. will fix in next version > > Regards, > Matthias > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > index 28651bc..8cf9f3b 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > > .fmt_rgb565_is_0 = true, > > }; > > > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 4, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 2, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-ovl", > > .data = &mt2701_ovl_driver_data}, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = &mt8173_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = &mt8183_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = &mt8183_ovl_2l_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > index 794acc5..51f2a0c 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > > .fifo_size = SZ_8K, > > }; > > > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > > + .fifo_size = 5 * SZ_1K, > > +}; > > + > > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = &mt2701_rdma_driver_data}, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = &mt8173_rdma_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = &mt8183_rdma_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > +}; > > + > > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > > { > > struct mtk_ddp *ddp = dev_get_drvdata(dev); > > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > .data = &mt2712_ddp_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_ddp_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_ddp_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index 6bd3694..267e91e 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -119,6 +119,24 @@ > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DSI0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI0, > > +}; > > + > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .main_path = mt2701_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > > @@ -143,6 +161,13 @@ > > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > > }; > > > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > + .main_path = mt8183_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > > + .ext_path = mt8183_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > > +}; > > + > > static int mtk_drm_kms_init(struct drm_device *drm) > > { > > struct mtk_drm_private *private = drm->dev_private; > > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_OVL }, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = (void *)MTK_DISP_OVL_2L }, > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-wdma", > > .data = (void *)MTK_DISP_WDMA }, > > + { .compatible = "mediatek,mt8183-disp-ccorr", > > + .data = (void *)MTK_DISP_CCORR }, > > { .compatible = "mediatek,mt2701-disp-color", > > .data = (void *)MTK_DISP_COLOR }, > > { .compatible = "mediatek,mt8173-disp-color", > > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_AAL}, > > { .compatible = "mediatek,mt8173-disp-gamma", > > .data = (void *)MTK_DISP_GAMMA, }, > > + { .compatible = "mediatek,mt8183-disp-dither", > > + .data = (void *)MTK_DISP_DITHER }, > > { .compatible = "mediatek,mt8173-disp-ufoe", > > .data = (void *)MTK_DISP_UFOE }, > > { .compatible = "mediatek,mt2701-dsi", > > .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dsi", > > .data = (void *)MTK_DSI }, > > + { .compatible = "mediatek,mt8183-dsi", > > + .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt2701-dpi", > > .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt8173-dpi", > > .data = (void *)MTK_DPI }, > > + { .compatible = "mediatek,mt8183-dpi", > > + .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2712-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", > > .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", > > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > > .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > + { .compatible = "mediatek,mt8183-mmsys", > > + .data = &mt8183_mmsys_driver_data}, > > { } > > }; > > > > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:31 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:31 UTC (permalink / raw) To: Matthias Brugger Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, linux-arm-kernel On Thu, 2020-07-23 at 17:40 +0200, Matthias Brugger wrote: > > On 23/07/2020 04:03, Yongqiang Niu wrote: > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > 2.rdma1 share drive with rdma0, but fifo size is different > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > Please fix your commit message, this is seems to describe what the whole series > is doing. will fix in next version > > Regards, > Matthias > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > index 28651bc..8cf9f3b 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > > .fmt_rgb565_is_0 = true, > > }; > > > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 4, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 2, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-ovl", > > .data = &mt2701_ovl_driver_data}, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = &mt8173_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = &mt8183_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = &mt8183_ovl_2l_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > index 794acc5..51f2a0c 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > > .fifo_size = SZ_8K, > > }; > > > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > > + .fifo_size = 5 * SZ_1K, > > +}; > > + > > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = &mt2701_rdma_driver_data}, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = &mt8173_rdma_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = &mt8183_rdma_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > +}; > > + > > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > > { > > struct mtk_ddp *ddp = dev_get_drvdata(dev); > > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > .data = &mt2712_ddp_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_ddp_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_ddp_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index 6bd3694..267e91e 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -119,6 +119,24 @@ > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DSI0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI0, > > +}; > > + > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .main_path = mt2701_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > > @@ -143,6 +161,13 @@ > > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > > }; > > > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > + .main_path = mt8183_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > > + .ext_path = mt8183_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > > +}; > > + > > static int mtk_drm_kms_init(struct drm_device *drm) > > { > > struct mtk_drm_private *private = drm->dev_private; > > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_OVL }, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = (void *)MTK_DISP_OVL_2L }, > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-wdma", > > .data = (void *)MTK_DISP_WDMA }, > > + { .compatible = "mediatek,mt8183-disp-ccorr", > > + .data = (void *)MTK_DISP_CCORR }, > > { .compatible = "mediatek,mt2701-disp-color", > > .data = (void *)MTK_DISP_COLOR }, > > { .compatible = "mediatek,mt8173-disp-color", > > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_AAL}, > > { .compatible = "mediatek,mt8173-disp-gamma", > > .data = (void *)MTK_DISP_GAMMA, }, > > + { .compatible = "mediatek,mt8183-disp-dither", > > + .data = (void *)MTK_DISP_DITHER }, > > { .compatible = "mediatek,mt8173-disp-ufoe", > > .data = (void *)MTK_DISP_UFOE }, > > { .compatible = "mediatek,mt2701-dsi", > > .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dsi", > > .data = (void *)MTK_DSI }, > > + { .compatible = "mediatek,mt8183-dsi", > > + .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt2701-dpi", > > .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt8173-dpi", > > .data = (void *)MTK_DPI }, > > + { .compatible = "mediatek,mt8183-dpi", > > + .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2712-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", > > .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", > > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > > .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > + { .compatible = "mediatek,mt8183-mmsys", > > + .data = &mt8183_mmsys_driver_data}, > > { } > > }; > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:31 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:31 UTC (permalink / raw) To: Matthias Brugger Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Daniel Vetter, CK Hu, linux-arm-kernel On Thu, 2020-07-23 at 17:40 +0200, Matthias Brugger wrote: > > On 23/07/2020 04:03, Yongqiang Niu wrote: > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > 2.rdma1 share drive with rdma0, but fifo size is different > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > Please fix your commit message, this is seems to describe what the whole series > is doing. will fix in next version > > Regards, > Matthias > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > index 28651bc..8cf9f3b 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > > .fmt_rgb565_is_0 = true, > > }; > > > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 4, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 2, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-ovl", > > .data = &mt2701_ovl_driver_data}, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = &mt8173_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = &mt8183_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = &mt8183_ovl_2l_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > index 794acc5..51f2a0c 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > > .fifo_size = SZ_8K, > > }; > > > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > > + .fifo_size = 5 * SZ_1K, > > +}; > > + > > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = &mt2701_rdma_driver_data}, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = &mt8173_rdma_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = &mt8183_rdma_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > +}; > > + > > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > > { > > struct mtk_ddp *ddp = dev_get_drvdata(dev); > > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > .data = &mt2712_ddp_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_ddp_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_ddp_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index 6bd3694..267e91e 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -119,6 +119,24 @@ > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DSI0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI0, > > +}; > > + > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .main_path = mt2701_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > > @@ -143,6 +161,13 @@ > > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > > }; > > > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > + .main_path = mt8183_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > > + .ext_path = mt8183_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > > +}; > > + > > static int mtk_drm_kms_init(struct drm_device *drm) > > { > > struct mtk_drm_private *private = drm->dev_private; > > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_OVL }, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = (void *)MTK_DISP_OVL_2L }, > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-wdma", > > .data = (void *)MTK_DISP_WDMA }, > > + { .compatible = "mediatek,mt8183-disp-ccorr", > > + .data = (void *)MTK_DISP_CCORR }, > > { .compatible = "mediatek,mt2701-disp-color", > > .data = (void *)MTK_DISP_COLOR }, > > { .compatible = "mediatek,mt8173-disp-color", > > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_AAL}, > > { .compatible = "mediatek,mt8173-disp-gamma", > > .data = (void *)MTK_DISP_GAMMA, }, > > + { .compatible = "mediatek,mt8183-disp-dither", > > + .data = (void *)MTK_DISP_DITHER }, > > { .compatible = "mediatek,mt8173-disp-ufoe", > > .data = (void *)MTK_DISP_UFOE }, > > { .compatible = "mediatek,mt2701-dsi", > > .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dsi", > > .data = (void *)MTK_DSI }, > > + { .compatible = "mediatek,mt8183-dsi", > > + .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt2701-dpi", > > .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt8173-dpi", > > .data = (void *)MTK_DPI }, > > + { .compatible = "mediatek,mt8183-dpi", > > + .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2712-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", > > .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", > > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > > .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > + { .compatible = "mediatek,mt8183-mmsys", > > + .data = &mt8183_mmsys_driver_data}, > > { } > > }; > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:31 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:31 UTC (permalink / raw) To: Matthias Brugger Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Rob Herring, linux-mediatek, Daniel Vetter, CK Hu, linux-arm-kernel On Thu, 2020-07-23 at 17:40 +0200, Matthias Brugger wrote: > > On 23/07/2020 04:03, Yongqiang Niu wrote: > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > 2.rdma1 share drive with rdma0, but fifo size is different > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > Please fix your commit message, this is seems to describe what the whole series > is doing. will fix in next version > > Regards, > Matthias > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > index 28651bc..8cf9f3b 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > @@ -430,11 +430,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > > .fmt_rgb565_is_0 = true, > > }; > > > > +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 4, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > > + .addr = DISP_REG_OVL_ADDR_MT8173, > > + .gmc_bits = 10, > > + .layer_nr = 2, > > + .fmt_rgb565_is_0 = true, > > +}; > > + > > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-ovl", > > .data = &mt2701_ovl_driver_data}, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = &mt8173_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = &mt8183_ovl_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = &mt8183_ovl_2l_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > index 794acc5..51f2a0c 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > > @@ -355,11 +355,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > > .fifo_size = SZ_8K, > > }; > > > > +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > > + .fifo_size = 5 * SZ_1K, > > +}; > > + > > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = &mt2701_rdma_driver_data}, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = &mt8173_rdma_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = &mt8183_rdma_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > > > +static const struct mtk_ddp_data mt8183_ddp_driver_data = { > > + .mutex_mod = mt8183_mutex_mod, > > + .mutex_sof = mt8183_mutex_sof, > > + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0, > > +}; > > + > > struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) > > { > > struct mtk_ddp *ddp = dev_get_drvdata(dev); > > @@ -402,6 +447,8 @@ static int mtk_ddp_remove(struct platform_device *pdev) > > .data = &mt2712_ddp_driver_data}, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = &mt8173_ddp_driver_data}, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = &mt8183_ddp_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index 6bd3694..267e91e 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -119,6 +119,24 @@ > > DDP_COMPONENT_DPI0, > > }; > > > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { > > + DDP_COMPONENT_OVL0, > > + DDP_COMPONENT_OVL_2L0, > > + DDP_COMPONENT_RDMA0, > > + DDP_COMPONENT_COLOR0, > > + DDP_COMPONENT_CCORR, > > + DDP_COMPONENT_AAL0, > > + DDP_COMPONENT_GAMMA, > > + DDP_COMPONENT_DITHER, > > + DDP_COMPONENT_DSI0, > > +}; > > + > > +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > > + DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_RDMA1, > > + DDP_COMPONENT_DPI0, > > +}; > > + > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > > .main_path = mt2701_mtk_ddp_main, > > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > > @@ -143,6 +161,13 @@ > > .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), > > }; > > > > +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > > + .main_path = mt8183_mtk_ddp_main, > > + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), > > + .ext_path = mt8183_mtk_ddp_ext, > > + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > > +}; > > + > > static int mtk_drm_kms_init(struct drm_device *drm) > > { > > struct mtk_drm_private *private = drm->dev_private; > > @@ -380,12 +405,20 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_OVL }, > > { .compatible = "mediatek,mt8173-disp-ovl", > > .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl", > > + .data = (void *)MTK_DISP_OVL }, > > + { .compatible = "mediatek,mt8183-disp-ovl-2l", > > + .data = (void *)MTK_DISP_OVL_2L }, > > { .compatible = "mediatek,mt2701-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-rdma", > > .data = (void *)MTK_DISP_RDMA }, > > + { .compatible = "mediatek,mt8183-disp-rdma", > > + .data = (void *)MTK_DISP_RDMA }, > > { .compatible = "mediatek,mt8173-disp-wdma", > > .data = (void *)MTK_DISP_WDMA }, > > + { .compatible = "mediatek,mt8183-disp-ccorr", > > + .data = (void *)MTK_DISP_CCORR }, > > { .compatible = "mediatek,mt2701-disp-color", > > .data = (void *)MTK_DISP_COLOR }, > > { .compatible = "mediatek,mt8173-disp-color", > > @@ -394,22 +427,30 @@ static void mtk_drm_unbind(struct device *dev) > > .data = (void *)MTK_DISP_AAL}, > > { .compatible = "mediatek,mt8173-disp-gamma", > > .data = (void *)MTK_DISP_GAMMA, }, > > + { .compatible = "mediatek,mt8183-disp-dither", > > + .data = (void *)MTK_DISP_DITHER }, > > { .compatible = "mediatek,mt8173-disp-ufoe", > > .data = (void *)MTK_DISP_UFOE }, > > { .compatible = "mediatek,mt2701-dsi", > > .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt8173-dsi", > > .data = (void *)MTK_DSI }, > > + { .compatible = "mediatek,mt8183-dsi", > > + .data = (void *)MTK_DSI }, > > { .compatible = "mediatek,mt2701-dpi", > > .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt8173-dpi", > > .data = (void *)MTK_DPI }, > > + { .compatible = "mediatek,mt8183-dpi", > > + .data = (void *)MTK_DPI }, > > { .compatible = "mediatek,mt2701-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2712-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8173-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt8183-disp-mutex", > > + .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", > > .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", > > @@ -426,6 +467,8 @@ static void mtk_drm_unbind(struct device *dev) > > .data = &mt2712_mmsys_driver_data}, > > { .compatible = "mediatek,mt8173-mmsys", > > .data = &mt8173_mmsys_driver_data}, > > + { .compatible = "mediatek,mt8183-mmsys", > > + .data = &mt8183_mmsys_driver_data}, > > { } > > }; > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-23 2:03 ` Yongqiang Niu (?) (?) @ 2020-07-24 23:24 ` Chun-Kuang Hu -1 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-24 23:24 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl I think this is done in [1], [2], [3], this patch just add the support of mt8183-ovl and mt8183-ovl-2l. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > 2.rdma1 share drive with rdma0, but fifo size is different I think this is done in [4], this patch just add the support of mt8183-rdma. [4] https://patchwork.kernel.org/patch/11679549/ > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create The fourth item is the mmsys private data in third item, so you need not to repeat it. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > [snip] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, Ditto. Regards, Chun-Kuang. > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-24 23:24 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-24 23:24 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl I think this is done in [1], [2], [3], this patch just add the support of mt8183-ovl and mt8183-ovl-2l. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > 2.rdma1 share drive with rdma0, but fifo size is different I think this is done in [4], this patch just add the support of mt8183-rdma. [4] https://patchwork.kernel.org/patch/11679549/ > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create The fourth item is the mmsys private data in third item, so you need not to repeat it. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > [snip] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, Ditto. Regards, Chun-Kuang. > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-24 23:24 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-24 23:24 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl I think this is done in [1], [2], [3], this patch just add the support of mt8183-ovl and mt8183-ovl-2l. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > 2.rdma1 share drive with rdma0, but fifo size is different I think this is done in [4], this patch just add the support of mt8183-rdma. [4] https://patchwork.kernel.org/patch/11679549/ > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create The fourth item is the mmsys private data in third item, so you need not to repeat it. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > [snip] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, Ditto. Regards, Chun-Kuang. > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-24 23:24 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-24 23:24 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > This patch add support for mediatek SOC MT8183 > 1.ovl_2l share driver with ovl I think this is done in [1], [2], [3], this patch just add the support of mt8183-ovl and mt8183-ovl-2l. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > 2.rdma1 share drive with rdma0, but fifo size is different I think this is done in [4], this patch just add the support of mt8183-rdma. [4] https://patchwork.kernel.org/patch/11679549/ > 3.add mt8183 mutex private data, and mmsys private data > 4.add mt8183 main and external path module for crtc create The fourth item is the mmsys private data in third item, so you need not to repeat it. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > 4 files changed, 114 insertions(+) > [snip] > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 014c1bb..60788c1 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -15,6 +15,8 @@ > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > #define MT2701_DISP_MUTEX0_SOF0 0x30 > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > @@ -25,6 +27,18 @@ > > #define INT_MUTEX BIT(1) > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > + > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > @@ -74,6 +88,10 @@ > #define MUTEX_SOF_DSI2 5 > #define MUTEX_SOF_DSI3 6 > > +#define MT8183_MUTEX_SOF_DPI0 2 > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > + > > struct mtk_disp_mutex { > int id; > @@ -153,6 +171,20 @@ struct mtk_ddp { > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > }; > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > +}; > + > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > @@ -163,6 +195,12 @@ struct mtk_ddp { > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, Ditto. Regards, Chun-Kuang. > +}; > + > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -184,6 +222,13 @@ struct mtk_ddp { > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > }; > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-24 23:24 ` Chun-Kuang Hu (?) (?) @ 2020-07-25 3:30 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:30 UTC (permalink / raw) To: Chun-Kuang Hu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > i will remove some useless description in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. we need set EOF at the same on MT8183, that is different with before SoC EOF and SOF are location in the same hardware register. > > Regards, > Chun-Kuang. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:30 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:30 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > i will remove some useless description in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. we need set EOF at the same on MT8183, that is different with before SoC EOF and SOF are location in the same hardware register. > > Regards, > Chun-Kuang. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:30 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:30 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > i will remove some useless description in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. we need set EOF at the same on MT8183, that is different with before SoC EOF and SOF are location in the same hardware register. > > Regards, > Chun-Kuang. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:30 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-25 3:30 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > i will remove some useless description in next version. > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. we need set EOF at the same on MT8183, that is different with before SoC EOF and SOF are location in the same hardware register. > > Regards, > Chun-Kuang. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-25 3:30 ` Yongqiang Niu (?) (?) @ 2020-07-25 3:45 ` Chun-Kuang Hu -1 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:45 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月25日 週六 上午11:32寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > i will remove some useless description in next version. > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > we need set EOF at the same on MT8183, that is different with before SoC > EOF and SOF are location in the same hardware register. Even though EOF and SOF are located in the same hardware register, why should we set EOF? We just need mutex hardware to send SOF to MODs, we don't need mutex to send EOF. > > > > Regards, > > Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:45 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:45 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Chun-Kuang Hu, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月25日 週六 上午11:32寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > i will remove some useless description in next version. > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > we need set EOF at the same on MT8183, that is different with before SoC > EOF and SOF are location in the same hardware register. Even though EOF and SOF are located in the same hardware register, why should we set EOF? We just need mutex hardware to send SOF to MODs, we don't need mutex to send EOF. > > > > Regards, > > Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:45 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:45 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Chun-Kuang Hu, Daniel Vetter, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月25日 週六 上午11:32寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > i will remove some useless description in next version. > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > we need set EOF at the same on MT8183, that is different with before SoC > EOF and SOF are location in the same hardware register. Even though EOF and SOF are located in the same hardware register, why should we set EOF? We just need mutex hardware to send SOF to MODs, we don't need mutex to send EOF. > > > > Regards, > > Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-25 3:45 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-25 3:45 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Chun-Kuang Hu, Daniel Vetter, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月25日 週六 上午11:32寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > i will remove some useless description in next version. > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > we need set EOF at the same on MT8183, that is different with before SoC > EOF and SOF are location in the same hardware register. Even though EOF and SOF are located in the same hardware register, why should we set EOF? We just need mutex hardware to send SOF to MODs, we don't need mutex to send EOF. > > > > Regards, > > Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-24 23:24 ` Chun-Kuang Hu (?) (?) @ 2020-07-27 7:52 ` Yongqiang Niu -1 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-27 7:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. > > Regards, > Chun-Kuang. MT8183 mutex setting is different with before SoC. if we do not set EOF, Overlay hardware will not receive frame done irq, and will display error. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-27 7:52 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-27 7:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. > > Regards, > Chun-Kuang. MT8183 mutex setting is different with before SoC. if we do not set EOF, Overlay hardware will not receive frame done irq, and will display error. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-27 7:52 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-27 7:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. > > Regards, > Chun-Kuang. MT8183 mutex setting is different with before SoC. if we do not set EOF, Overlay hardware will not receive frame done irq, and will display error. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-27 7:52 ` Yongqiang Niu 0 siblings, 0 replies; 112+ messages in thread From: Yongqiang Niu @ 2020-07-27 7:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, devicetree, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > Hi Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > This patch add support for mediatek SOC MT8183 > > 1.ovl_2l share driver with ovl > > I think this is done in [1], [2], [3], this patch just add the support > of mt8183-ovl and mt8183-ovl-2l. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > 2.rdma1 share drive with rdma0, but fifo size is different > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > [4] https://patchwork.kernel.org/patch/11679549/ > > > 3.add mt8183 mutex private data, and mmsys private data > > 4.add mt8183 main and external path module for crtc create > > The fourth item is the mmsys private data in third item, so you need > not to repeat it. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > 4 files changed, 114 insertions(+) > > > > [snip] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index 014c1bb..60788c1 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -15,6 +15,8 @@ > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > @@ -25,6 +27,18 @@ > > > > #define INT_MUTEX BIT(1) > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > + > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > @@ -74,6 +88,10 @@ > > #define MUTEX_SOF_DSI2 5 > > #define MUTEX_SOF_DSI3 6 > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > + > > > > struct mtk_disp_mutex { > > int id; > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > }; > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > +}; > > + > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > Ditto. > > Regards, > Chun-Kuang. MT8183 mutex setting is different with before SoC. if we do not set EOF, Overlay hardware will not receive frame done irq, and will display error. > > > +}; > > + > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > }; > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 2020-07-27 7:52 ` Yongqiang Niu (?) (?) @ 2020-07-27 14:50 ` Chun-Kuang Hu -1 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-27 14:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, devicetree, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月27日 週一 下午3:54寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > > > Regards, > > Chun-Kuang. > > MT8183 mutex setting is different with before SoC. > if we do not set EOF, Overlay hardware will not receive frame done irq, > and will display error. Please add comment for this because this is not a trivial thing. Regards, Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-27 14:50 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-27 14:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Chun-Kuang Hu, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月27日 週一 下午3:54寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > > > Regards, > > Chun-Kuang. > > MT8183 mutex setting is different with before SoC. > if we do not set EOF, Overlay hardware will not receive frame done irq, > and will display error. Please add comment for this because this is not a trivial thing. Regards, Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-27 14:50 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-27 14:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Chun-Kuang Hu, Daniel Vetter, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月27日 週一 下午3:54寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > > > Regards, > > Chun-Kuang. > > MT8183 mutex setting is different with before SoC. > if we do not set EOF, Overlay hardware will not receive frame done irq, > and will display error. Please add comment for this because this is not a trivial thing. Regards, Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 @ 2020-07-27 14:50 ` Chun-Kuang Hu 0 siblings, 0 replies; 112+ messages in thread From: Chun-Kuang Hu @ 2020-07-27 14:50 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Chun-Kuang Hu, Daniel Vetter, devicetree, David Airlie, linux-kernel, DRI Development, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月27日 週一 下午3:54寫道： > > On Sat, 2020-07-25 at 07:24 +0800, Chun-Kuang Hu wrote: > > Hi Yongqiang: > > > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年7月23日 週四 上午10:15寫道： > > > > > > This patch add support for mediatek SOC MT8183 > > > 1.ovl_2l share driver with ovl > > > > I think this is done in [1], [2], [3], this patch just add the support > > of mt8183-ovl and mt8183-ovl-2l. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=132c6e250ed745443973cada8db17cdbaebdf551 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=318462d1a568634ba09263cc730cb0fb1d56c2b3 > > [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mediatek?h=v5.8-rc6&id=57148baac8b78461e394953cfd5317bde8f795ab > > > > > 2.rdma1 share drive with rdma0, but fifo size is different > > > > I think this is done in [4], this patch just add the support of mt8183-rdma. > > > > [4] https://patchwork.kernel.org/patch/11679549/ > > > > > 3.add mt8183 mutex private data, and mmsys private data > > > 4.add mt8183 main and external path module for crtc create > > > > The fourth item is the mmsys private data in third item, so you need > > not to repeat it. > > > > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++++++++ > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 43 +++++++++++++++++++++++++++++ > > > 4 files changed, 114 insertions(+) > > > > > > > [snip] > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > index 014c1bb..60788c1 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > > @@ -15,6 +15,8 @@ > > > > > > #define MT2701_DISP_MUTEX0_MOD0 0x2c > > > #define MT2701_DISP_MUTEX0_SOF0 0x30 > > > +#define MT8183_DISP_MUTEX0_MOD0 0x30 > > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c > > > > > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > > @@ -25,6 +27,18 @@ > > > > > > #define INT_MUTEX BIT(1) > > > > > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 > > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9 > > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 > > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 > > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 > > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 > > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 > > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15 > > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 > > > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 > > > + > > > #define MT8173_MUTEX_MOD_DISP_OVL0 11 > > > #define MT8173_MUTEX_MOD_DISP_OVL1 12 > > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13 > > > @@ -74,6 +88,10 @@ > > > #define MUTEX_SOF_DSI2 5 > > > #define MUTEX_SOF_DSI3 6 > > > > > > +#define MT8183_MUTEX_SOF_DPI0 2 > > > +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6) > > > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > > > + > > > > > > struct mtk_disp_mutex { > > > int id; > > > @@ -153,6 +171,20 @@ struct mtk_ddp { > > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, > > > }; > > > > > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0, > > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0, > > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0, > > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0, > > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0, > > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0, > > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L, > > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L, > > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0, > > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1, > > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > > +}; > > > + > > > static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > > @@ -163,6 +195,12 @@ struct mtk_ddp { > > > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > > }; > > > > > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { > > > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > > > I think this array is for 'sof', so you should drop MT8183_MUTEX_EOF_DSI0. > > > > > + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > > > > Ditto. > > > > Regards, > > Chun-Kuang. > > MT8183 mutex setting is different with before SoC. > if we do not set EOF, Overlay hardware will not receive frame done irq, > and will display error. Please add comment for this because this is not a trivial thing. Regards, Chun-Kuang. > > > > > +}; > > > + > > > static const struct mtk_ddp_data mt2701_ddp_driver_data = { > > > .mutex_mod = mt2701_mutex_mod, > > > .mutex_sof = mt2712_mutex_sof, > > > @@ -184,6 +222,13 @@ struct mtk_ddp { > > > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, > > > }; > > > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 112+ messages in thread
end of thread, other threads:[~2020-07-28 10:27 UTC | newest] Thread overview: 112+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-23 2:03 [v7, PATCH 0/7] add drm support for MT8183 Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 9:34 ` Enric Balletbo Serra 2020-07-23 9:34 ` Enric Balletbo Serra 2020-07-23 9:34 ` Enric Balletbo Serra 2020-07-23 9:34 ` Enric Balletbo Serra 2020-07-23 10:04 ` Yongqiang Niu 2020-07-23 10:04 ` Yongqiang Niu 2020-07-23 10:04 ` Yongqiang Niu 2020-07-23 10:04 ` Yongqiang Niu 2020-07-23 16:21 ` Chun-Kuang Hu 2020-07-23 16:21 ` Chun-Kuang Hu 2020-07-23 16:21 ` Chun-Kuang Hu 2020-07-23 16:21 ` Chun-Kuang Hu 2020-07-23 2:03 ` [v7, PATCH 2/7] mtk-mmsys: add mmsys private data Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 9:32 ` Enric Balletbo Serra 2020-07-23 9:32 ` Enric Balletbo Serra 2020-07-23 9:32 ` Enric Balletbo Serra 2020-07-23 9:32 ` Enric Balletbo Serra 2020-07-25 3:27 ` Yongqiang Niu 2020-07-25 3:27 ` Yongqiang Niu 2020-07-25 3:27 ` Yongqiang Niu 2020-07-25 3:27 ` Yongqiang Niu 2020-07-28 10:25 ` Enric Balletbo Serra 2020-07-28 10:25 ` Enric Balletbo Serra 2020-07-28 10:25 ` Enric Balletbo Serra 2020-07-28 10:25 ` Enric Balletbo Serra 2020-07-25 2:11 ` Chun-Kuang Hu 2020-07-25 2:11 ` Chun-Kuang Hu 2020-07-25 2:11 ` Chun-Kuang Hu 2020-07-25 2:11 ` Chun-Kuang Hu 2020-07-25 3:13 ` Yongqiang Niu 2020-07-25 3:13 ` Yongqiang Niu 2020-07-25 3:13 ` Yongqiang Niu 2020-07-25 3:13 ` Yongqiang Niu 2020-07-23 2:03 ` [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-24 13:49 ` Nicolas Boichat 2020-07-24 13:49 ` Nicolas Boichat 2020-07-24 13:49 ` Nicolas Boichat 2020-07-24 13:49 ` Nicolas Boichat 2020-07-23 2:03 ` [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 15:41 ` Matthias Brugger 2020-07-23 15:41 ` Matthias Brugger 2020-07-23 15:41 ` Matthias Brugger 2020-07-23 15:41 ` Matthias Brugger 2020-07-23 16:59 ` Rob Herring 2020-07-23 16:59 ` Rob Herring 2020-07-23 16:59 ` Rob Herring 2020-07-23 16:59 ` Rob Herring 2020-07-23 2:03 ` [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 15:42 ` Matthias Brugger 2020-07-23 15:42 ` Matthias Brugger 2020-07-23 15:42 ` Matthias Brugger 2020-07-23 15:42 ` Matthias Brugger 2020-07-23 2:03 ` [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-25 3:50 ` Chun-Kuang Hu 2020-07-25 3:50 ` Chun-Kuang Hu 2020-07-25 3:50 ` Chun-Kuang Hu 2020-07-25 3:50 ` Chun-Kuang Hu 2020-07-23 2:03 ` [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 2:03 ` Yongqiang Niu 2020-07-23 15:40 ` Matthias Brugger 2020-07-23 15:40 ` Matthias Brugger 2020-07-23 15:40 ` Matthias Brugger 2020-07-23 15:40 ` Matthias Brugger 2020-07-25 3:31 ` Yongqiang Niu 2020-07-25 3:31 ` Yongqiang Niu 2020-07-25 3:31 ` Yongqiang Niu 2020-07-25 3:31 ` Yongqiang Niu 2020-07-24 23:24 ` Chun-Kuang Hu 2020-07-24 23:24 ` Chun-Kuang Hu 2020-07-24 23:24 ` Chun-Kuang Hu 2020-07-24 23:24 ` Chun-Kuang Hu 2020-07-25 3:30 ` Yongqiang Niu 2020-07-25 3:30 ` Yongqiang Niu 2020-07-25 3:30 ` Yongqiang Niu 2020-07-25 3:30 ` Yongqiang Niu 2020-07-25 3:45 ` Chun-Kuang Hu 2020-07-25 3:45 ` Chun-Kuang Hu 2020-07-25 3:45 ` Chun-Kuang Hu 2020-07-25 3:45 ` Chun-Kuang Hu 2020-07-27 7:52 ` Yongqiang Niu 2020-07-27 7:52 ` Yongqiang Niu 2020-07-27 7:52 ` Yongqiang Niu 2020-07-27 7:52 ` Yongqiang Niu 2020-07-27 14:50 ` Chun-Kuang Hu 2020-07-27 14:50 ` Chun-Kuang Hu 2020-07-27 14:50 ` Chun-Kuang Hu 2020-07-27 14:50 ` Chun-Kuang Hu
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