* [Bug 1863526] [NEW] NVIC CCR register not 8-bit accessible using Cortex-M4
@ 2020-02-16 22:53 Philippe Mathieu-Daudé
2020-02-16 22:56 ` [Bug 1863526] " Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-16 22:53 UTC (permalink / raw)
To: qemu-devel
Public bug reported:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data 0xf00000 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data 0xf00000 size 4
8871@1581892794.297780:nvic_sysreg_write NVIC sysreg write addr 0xd08 data 0x4200 size 4
8871@1581892794.298040:nvic_sysreg_write NVIC sysreg write addr 0xd15 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd15
8871@1581892794.298081:nvic_sysreg_write NVIC sysreg write addr 0xd16 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd16
8871@1581892794.298116:nvic_sysreg_write NVIC sysreg write addr 0xd17 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd17
8871@1581892794.298156:nvic_sysreg_write NVIC sysreg write addr 0xd18 data 0x0 size 1
8871@1581892794.298161:nvic_set_prio NVIC set irq 4 secure-bank 0 priority 0
8871@1581892794.298164:nvic_recompute_state NVIC state recomputed: vectpending 0 vectpending_prio 256 exception_prio 256
8871@1581892794.298168:nvic_irq_update NVIC vectpending 0 pending prio 256 exception_prio 256: setting irq line to 0
8871@1581892794.298201:nvic_sysreg_write NVIC sysreg write addr 0xd19 data 0x0 size 1
8871@1581892794.298206:nvic_set_prio NVIC set irq 5 secure-bank 0 priority 0
** Affects: qemu
Importance: Undecided
Status: New
** Tags: arm nvic
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https://bugs.launchpad.net/bugs/1863526
Title:
NVIC CCR register not 8-bit accessible using Cortex-M4
Status in QEMU:
New
Bug description:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data 0xf00000 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data 0xf00000 size 4
8871@1581892794.297780:nvic_sysreg_write NVIC sysreg write addr 0xd08 data 0x4200 size 4
8871@1581892794.298040:nvic_sysreg_write NVIC sysreg write addr 0xd15 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd15
8871@1581892794.298081:nvic_sysreg_write NVIC sysreg write addr 0xd16 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd16
8871@1581892794.298116:nvic_sysreg_write NVIC sysreg write addr 0xd17 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd17
8871@1581892794.298156:nvic_sysreg_write NVIC sysreg write addr 0xd18 data 0x0 size 1
8871@1581892794.298161:nvic_set_prio NVIC set irq 4 secure-bank 0 priority 0
8871@1581892794.298164:nvic_recompute_state NVIC state recomputed: vectpending 0 vectpending_prio 256 exception_prio 256
8871@1581892794.298168:nvic_irq_update NVIC vectpending 0 pending prio 256 exception_prio 256: setting irq line to 0
8871@1581892794.298201:nvic_sysreg_write NVIC sysreg write addr 0xd19 data 0x0 size 1
8871@1581892794.298206:nvic_set_prio NVIC set irq 5 secure-bank 0 priority 0
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug 1863526] Re: NVIC CCR register not 8-bit accessible using Cortex-M4
2020-02-16 22:53 [Bug 1863526] [NEW] NVIC CCR register not 8-bit accessible using Cortex-M4 Philippe Mathieu-Daudé
@ 2020-02-16 22:56 ` Philippe Mathieu-Daudé
2020-07-27 13:46 ` Peter Maydell
2020-07-27 14:32 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-02-16 22:56 UTC (permalink / raw)
To: qemu-devel
I am not sure this register can not be accessed differently than 32-bit.
Still I used this patch as a kludge, but it doesn't seem a clean fix:
-- >8 --
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2160,6 +2161,10 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
}
}
break;
+ case 0xd14 ... 0xd17: /* Configuration and Control Register */
+ val = extract32(nvic_readl(s, offset & ~3, attrs),
+ (offset - 0xd14) * 8, size * 8);
+ break;
case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
val = 0;
@@ -2282,6 +2287,11 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
}
nvic_irq_update(s);
goto exit_ok;
+ case 0xd14 ... 0xd17: /* Configuration and Control Register */
+ value = deposit32(value, (offset - 0xd14) * 8, size * 8,
+ nvic_readl(s, offset & ~3, attrs));
+ nvic_writel(s, offset & ~3, value, attrs);
+ goto exit_ok;
case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
goto exit_ok;
---
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1863526
Title:
NVIC CCR register not 8-bit accessible using Cortex-M4
Status in QEMU:
New
Bug description:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data 0xf00000 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data 0xf00000 size 4
8871@1581892794.297780:nvic_sysreg_write NVIC sysreg write addr 0xd08 data 0x4200 size 4
8871@1581892794.298040:nvic_sysreg_write NVIC sysreg write addr 0xd15 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd15
8871@1581892794.298081:nvic_sysreg_write NVIC sysreg write addr 0xd16 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd16
8871@1581892794.298116:nvic_sysreg_write NVIC sysreg write addr 0xd17 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd17
8871@1581892794.298156:nvic_sysreg_write NVIC sysreg write addr 0xd18 data 0x0 size 1
8871@1581892794.298161:nvic_set_prio NVIC set irq 4 secure-bank 0 priority 0
8871@1581892794.298164:nvic_recompute_state NVIC state recomputed: vectpending 0 vectpending_prio 256 exception_prio 256
8871@1581892794.298168:nvic_irq_update NVIC vectpending 0 pending prio 256 exception_prio 256: setting irq line to 0
8871@1581892794.298201:nvic_sysreg_write NVIC sysreg write addr 0xd19 data 0x0 size 1
8871@1581892794.298206:nvic_set_prio NVIC set irq 5 secure-bank 0 priority 0
To manage notifications about this bug go to:
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug 1863526] Re: NVIC CCR register not 8-bit accessible using Cortex-M4
2020-02-16 22:53 [Bug 1863526] [NEW] NVIC CCR register not 8-bit accessible using Cortex-M4 Philippe Mathieu-Daudé
2020-02-16 22:56 ` [Bug 1863526] " Philippe Mathieu-Daudé
@ 2020-07-27 13:46 ` Peter Maydell
2020-07-27 14:32 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2020-07-27 13:46 UTC (permalink / raw)
To: qemu-devel
Architecturally the CCR is not byte-accessible. The v7M Arm ARM defines
in B3.1.1 "General rules for PPB register accesses" that unless
otherwise stated, register support word accesses only, and the CCR
register definition does not say that byte access is supported. This is
true also in v8M, where the CCR register definition explicitly marks
halfword and byte accesses to CCR as UNPREDICTABLE.
So this looks like buggy guest code to me...
** Changed in: qemu
Status: New => Incomplete
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1863526
Title:
NVIC CCR register not 8-bit accessible using Cortex-M4
Status in QEMU:
Incomplete
Bug description:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data 0xf00000 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data 0xf00000 size 4
8871@1581892794.297780:nvic_sysreg_write NVIC sysreg write addr 0xd08 data 0x4200 size 4
8871@1581892794.298040:nvic_sysreg_write NVIC sysreg write addr 0xd15 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd15
8871@1581892794.298081:nvic_sysreg_write NVIC sysreg write addr 0xd16 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd16
8871@1581892794.298116:nvic_sysreg_write NVIC sysreg write addr 0xd17 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd17
8871@1581892794.298156:nvic_sysreg_write NVIC sysreg write addr 0xd18 data 0x0 size 1
8871@1581892794.298161:nvic_set_prio NVIC set irq 4 secure-bank 0 priority 0
8871@1581892794.298164:nvic_recompute_state NVIC state recomputed: vectpending 0 vectpending_prio 256 exception_prio 256
8871@1581892794.298168:nvic_irq_update NVIC vectpending 0 pending prio 256 exception_prio 256: setting irq line to 0
8871@1581892794.298201:nvic_sysreg_write NVIC sysreg write addr 0xd19 data 0x0 size 1
8871@1581892794.298206:nvic_set_prio NVIC set irq 5 secure-bank 0 priority 0
To manage notifications about this bug go to:
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [Bug 1863526] Re: NVIC CCR register not 8-bit accessible using Cortex-M4
2020-02-16 22:53 [Bug 1863526] [NEW] NVIC CCR register not 8-bit accessible using Cortex-M4 Philippe Mathieu-Daudé
2020-02-16 22:56 ` [Bug 1863526] " Philippe Mathieu-Daudé
2020-07-27 13:46 ` Peter Maydell
@ 2020-07-27 14:32 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-27 14:32 UTC (permalink / raw)
To: qemu-devel
** Changed in: qemu
Status: Incomplete => Invalid
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1863526
Title:
NVIC CCR register not 8-bit accessible using Cortex-M4
Status in QEMU:
Invalid
Bug description:
Head at commit b29c3e23f64938.
Running with '-d unimp,guest_errors -trace nvic\*' I get:
8871@1581892794.295746:nvic_sysreg_read NVIC sysreg read addr 0xd88 data 0xf00000 size 4
8871@1581892794.295752:nvic_sysreg_write NVIC sysreg write addr 0xd88 data 0xf00000 size 4
8871@1581892794.297780:nvic_sysreg_write NVIC sysreg write addr 0xd08 data 0x4200 size 4
8871@1581892794.298040:nvic_sysreg_write NVIC sysreg write addr 0xd15 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd15
8871@1581892794.298081:nvic_sysreg_write NVIC sysreg write addr 0xd16 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd16
8871@1581892794.298116:nvic_sysreg_write NVIC sysreg write addr 0xd17 data 0x0 size 1
NVIC: Bad write of size 1 at offset 0xd17
8871@1581892794.298156:nvic_sysreg_write NVIC sysreg write addr 0xd18 data 0x0 size 1
8871@1581892794.298161:nvic_set_prio NVIC set irq 4 secure-bank 0 priority 0
8871@1581892794.298164:nvic_recompute_state NVIC state recomputed: vectpending 0 vectpending_prio 256 exception_prio 256
8871@1581892794.298168:nvic_irq_update NVIC vectpending 0 pending prio 256 exception_prio 256: setting irq line to 0
8871@1581892794.298201:nvic_sysreg_write NVIC sysreg write addr 0xd19 data 0x0 size 1
8871@1581892794.298206:nvic_set_prio NVIC set irq 5 secure-bank 0 priority 0
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1863526/+subscriptions
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-07-27 14:42 UTC | newest]
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2020-02-16 22:53 [Bug 1863526] [NEW] NVIC CCR register not 8-bit accessible using Cortex-M4 Philippe Mathieu-Daudé
2020-02-16 22:56 ` [Bug 1863526] " Philippe Mathieu-Daudé
2020-07-27 13:46 ` Peter Maydell
2020-07-27 14:32 ` Philippe Mathieu-Daudé
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