* [PATCH 0/3] float16 APIs and alternative sNaN handling
@ 2020-07-30 9:52 Chih-Min Chao
2020-07-30 9:52 ` Chih-Min Chao
` (2 more replies)
0 siblings, 3 replies; 18+ messages in thread
From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Chih-Min Chao
These patches are separated from riscv vector extension 0.9 patchset.
The set includes
1. alternative NaN handlding
2. float16 comparision APIs.
3. float16 to int8/uint8 conversion APIs
Chih-Min Chao (1):
softfloat: add APIs to handle alternative sNaN propagation
Frank Chang (1):
softfloat: add fp16 and uint8/int8 interconvert functions
Kito Cheng (1):
softfloat: target/riscv: implement full set fp16 comparision
fpu/softfloat.c | 109 ++++++++++++++++++++++++++++++++-----------
include/fpu/softfloat.h | 55 ++++++++++++++++++++++
target/riscv/vector_helper.c | 25 ----------
3 files changed, 137 insertions(+), 52 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision 2020-07-30 9:52 [PATCH 0/3] float16 APIs and alternative sNaN handling Chih-Min Chao @ 2020-07-30 9:52 ` Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann, Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng, Alex Bennée, Aurelien Jarno From: Kito Cheng <kito.cheng@sifive.com> Implement them in softfloat and remove local version in riscv Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> --- include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ target/riscv/vector_helper.c | 25 ------------------------- 2 files changed, 41 insertions(+), 25 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 659218b..573fce9 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int sign) return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); } +static inline bool float16_eq(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) == float_relation_equal; +} + +static inline bool float16_le(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) <= float_relation_equal; +} + +static inline bool float16_lt(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) < float_relation_equal; +} + +static inline bool float16_unordered(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) == float_relation_unordered; +} + +static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) == float_relation_equal; +} + +static inline bool float16_le_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) <= float_relation_equal; +} + +static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) < float_relation_equal; +} + +static inline bool float16_unordered_quiet(float16 a, float16 b, + float_status *s) +{ + return float16_compare_quiet(a, b, s) == float_relation_unordered; +} + #define float16_zero make_float16(0) #define float16_half make_float16(0x3800) #define float16_one make_float16(0x3c00) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39f44d1..c68e6c4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3955,12 +3955,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ } \ } -static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare_quiet(a, b, s); - return compare == float_relation_equal; -} - GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) @@ -4017,12 +4011,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) -static bool float16_lt(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare(a, b, s); - return compare == float_relation_less; -} - GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) @@ -4030,13 +4018,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) -static bool float16_le(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare(a, b, s); - return compare == float_relation_less || - compare == float_relation_equal; -} - GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) @@ -4091,12 +4072,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) -static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare_quiet(a, b, s); - return compare == float_relation_unordered; -} - GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) -- 2.7.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision @ 2020-07-30 9:52 ` Chih-Min Chao 0 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Kito Cheng, Chih-Min Chao, Aurelien Jarno, Peter Maydell, Alex Bennée, Palmer Dabbelt, Alistair Francis, Sagar Karandikar, Bastian Koppelmann From: Kito Cheng <kito.cheng@sifive.com> Implement them in softfloat and remove local version in riscv Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> --- include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ target/riscv/vector_helper.c | 25 ------------------------- 2 files changed, 41 insertions(+), 25 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 659218b..573fce9 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int sign) return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); } +static inline bool float16_eq(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) == float_relation_equal; +} + +static inline bool float16_le(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) <= float_relation_equal; +} + +static inline bool float16_lt(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) < float_relation_equal; +} + +static inline bool float16_unordered(float16 a, float16 b, float_status *s) +{ + return float16_compare(a, b, s) == float_relation_unordered; +} + +static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) == float_relation_equal; +} + +static inline bool float16_le_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) <= float_relation_equal; +} + +static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s) +{ + return float16_compare_quiet(a, b, s) < float_relation_equal; +} + +static inline bool float16_unordered_quiet(float16 a, float16 b, + float_status *s) +{ + return float16_compare_quiet(a, b, s) == float_relation_unordered; +} + #define float16_zero make_float16(0) #define float16_half make_float16(0x3800) #define float16_one make_float16(0x3c00) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39f44d1..c68e6c4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3955,12 +3955,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ } \ } -static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare_quiet(a, b, s); - return compare == float_relation_equal; -} - GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) @@ -4017,12 +4011,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) -static bool float16_lt(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare(a, b, s); - return compare == float_relation_less; -} - GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) @@ -4030,13 +4018,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) -static bool float16_le(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare(a, b, s); - return compare == float_relation_less || - compare == float_relation_equal; -} - GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) @@ -4091,12 +4072,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) -static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s) -{ - FloatRelation compare = float16_compare_quiet(a, b, s); - return compare == float_relation_unordered; -} - GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) -- 2.7.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision 2020-07-30 9:52 ` Chih-Min Chao @ 2020-08-12 16:30 ` Alistair Francis -1 siblings, 0 replies; 18+ messages in thread From: Alistair Francis @ 2020-08-12 16:30 UTC (permalink / raw) To: Chih-Min Chao Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, qemu-devel@nongnu.org Developers, Palmer Dabbelt, Alistair Francis, Kito Cheng, Alex Bennée, Aurelien Jarno On Thu, Jul 30, 2020 at 2:54 AM Chih-Min Chao <chihmin.chao@sifive.com> wrote: > > From: Kito Cheng <kito.cheng@sifive.com> > > Implement them in softfloat and remove local version in riscv > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> > Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ > target/riscv/vector_helper.c | 25 ------------------------- > 2 files changed, 41 insertions(+), 25 deletions(-) > > diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h > index 659218b..573fce9 100644 > --- a/include/fpu/softfloat.h > +++ b/include/fpu/softfloat.h > @@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int sign) > return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); > } > > +static inline bool float16_eq(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) == float_relation_equal; > +} > + > +static inline bool float16_le(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) <= float_relation_equal; > +} > + > +static inline bool float16_lt(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) < float_relation_equal; > +} > + > +static inline bool float16_unordered(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) == float_relation_unordered; > +} > + > +static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s) > +{ > + return float16_compare_quiet(a, b, s) == float_relation_equal; > +} > + > +static inline bool float16_le_quiet(float16 a, float16 b, float_status *s) > +{ > + return float16_compare_quiet(a, b, s) <= float_relation_equal; > +} > + > +static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s) > +{ > + return float16_compare_quiet(a, b, s) < float_relation_equal; > +} > + > +static inline bool float16_unordered_quiet(float16 a, float16 b, > + float_status *s) > +{ > + return float16_compare_quiet(a, b, s) == float_relation_unordered; > +} > + > #define float16_zero make_float16(0) > #define float16_half make_float16(0x3800) > #define float16_one make_float16(0x3c00) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 39f44d1..c68e6c4 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -3955,12 +3955,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ > } \ > } > > -static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare_quiet(a, b, s); > - return compare == float_relation_equal; > -} > - > GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) > GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) > GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) > @@ -4017,12 +4011,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) > GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) > GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) > > -static bool float16_lt(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare(a, b, s); > - return compare == float_relation_less; > -} > - > GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) > GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) > GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) > @@ -4030,13 +4018,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) > GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) > GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) > > -static bool float16_le(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare(a, b, s); > - return compare == float_relation_less || > - compare == float_relation_equal; > -} > - > GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) > GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) > GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) > @@ -4091,12 +4072,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) > GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) > GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) > > -static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare_quiet(a, b, s); > - return compare == float_relation_unordered; > -} > - > GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) > GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) > GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) > -- > 2.7.4 > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision @ 2020-08-12 16:30 ` Alistair Francis 0 siblings, 0 replies; 18+ messages in thread From: Alistair Francis @ 2020-08-12 16:30 UTC (permalink / raw) To: Chih-Min Chao Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Peter Maydell, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, Alistair Francis, Kito Cheng, Alex Bennée, Aurelien Jarno On Thu, Jul 30, 2020 at 2:54 AM Chih-Min Chao <chihmin.chao@sifive.com> wrote: > > From: Kito Cheng <kito.cheng@sifive.com> > > Implement them in softfloat and remove local version in riscv > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> > Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ > target/riscv/vector_helper.c | 25 ------------------------- > 2 files changed, 41 insertions(+), 25 deletions(-) > > diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h > index 659218b..573fce9 100644 > --- a/include/fpu/softfloat.h > +++ b/include/fpu/softfloat.h > @@ -285,6 +285,47 @@ static inline float16 float16_set_sign(float16 a, int sign) > return make_float16((float16_val(a) & 0x7fff) | (sign << 15)); > } > > +static inline bool float16_eq(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) == float_relation_equal; > +} > + > +static inline bool float16_le(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) <= float_relation_equal; > +} > + > +static inline bool float16_lt(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) < float_relation_equal; > +} > + > +static inline bool float16_unordered(float16 a, float16 b, float_status *s) > +{ > + return float16_compare(a, b, s) == float_relation_unordered; > +} > + > +static inline bool float16_eq_quiet(float16 a, float16 b, float_status *s) > +{ > + return float16_compare_quiet(a, b, s) == float_relation_equal; > +} > + > +static inline bool float16_le_quiet(float16 a, float16 b, float_status *s) > +{ > + return float16_compare_quiet(a, b, s) <= float_relation_equal; > +} > + > +static inline bool float16_lt_quiet(float16 a, float16 b, float_status *s) > +{ > + return float16_compare_quiet(a, b, s) < float_relation_equal; > +} > + > +static inline bool float16_unordered_quiet(float16 a, float16 b, > + float_status *s) > +{ > + return float16_compare_quiet(a, b, s) == float_relation_unordered; > +} > + > #define float16_zero make_float16(0) > #define float16_half make_float16(0x3800) > #define float16_one make_float16(0x3c00) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 39f44d1..c68e6c4 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -3955,12 +3955,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ > } \ > } > > -static bool float16_eq_quiet(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare_quiet(a, b, s); > - return compare == float_relation_equal; > -} > - > GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) > GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) > GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) > @@ -4017,12 +4011,6 @@ GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) > GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) > GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) > > -static bool float16_lt(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare(a, b, s); > - return compare == float_relation_less; > -} > - > GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) > GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) > GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) > @@ -4030,13 +4018,6 @@ GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) > GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) > GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) > > -static bool float16_le(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare(a, b, s); > - return compare == float_relation_less || > - compare == float_relation_equal; > -} > - > GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) > GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) > GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) > @@ -4091,12 +4072,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) > GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) > GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) > > -static bool float16_unordered_quiet(uint16_t a, uint16_t b, float_status *s) > -{ > - FloatRelation compare = float16_compare_quiet(a, b, s); > - return compare == float_relation_unordered; > -} > - > GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) > GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) > GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) > -- > 2.7.4 > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision 2020-07-30 9:52 ` Chih-Min Chao @ 2020-08-13 17:22 ` Richard Henderson -1 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-13 17:22 UTC (permalink / raw) To: Chih-Min Chao, qemu-devel, qemu-riscv Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Kito Cheng, Alex Bennée, Aurelien Jarno On 7/30/20 2:52 AM, Chih-Min Chao wrote: > From: Kito Cheng <kito.cheng@sifive.com> > > Implement them in softfloat and remove local version in riscv > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> > Acked-by: Alex Bennée <alex.bennee@linaro.org> > --- > include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ > target/riscv/vector_helper.c | 25 ------------------------- > 2 files changed, 41 insertions(+), 25 deletions(-) Queued to softfloat-next. If it happens to get in via a riscv pull first, that's fine. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision @ 2020-08-13 17:22 ` Richard Henderson 0 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-13 17:22 UTC (permalink / raw) To: Chih-Min Chao, qemu-devel, qemu-riscv Cc: Peter Maydell, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, Alistair Francis, Kito Cheng, Alex Bennée, Aurelien Jarno On 7/30/20 2:52 AM, Chih-Min Chao wrote: > From: Kito Cheng <kito.cheng@sifive.com> > > Implement them in softfloat and remove local version in riscv > > Signed-off-by: Kito Cheng <kito.cheng@sifive.com> > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> > Acked-by: Alex Bennée <alex.bennee@linaro.org> > --- > include/fpu/softfloat.h | 41 +++++++++++++++++++++++++++++++++++++++++ > target/riscv/vector_helper.c | 25 ------------------------- > 2 files changed, 41 insertions(+), 25 deletions(-) Queued to softfloat-next. If it happens to get in via a riscv pull first, that's fine. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation 2020-07-30 9:52 [PATCH 0/3] float16 APIs and alternative sNaN handling Chih-Min Chao @ 2020-07-30 9:52 ` Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Chih-Min Chao, Alex Bennée, Aurelien Jarno, Peter Maydell For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan The alternative path set invalid flag if ft1 == sNaN || ft2 == sNaN return NaN if ft1 == sNaN && ft2 == sNaN The ieee754 spec allows both implementation and some architecture such as riscv choose differenct defintion in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> --- fpu/softfloat.c | 75 +++++++++++++++++++++++++++++++------------------ include/fpu/softfloat.h | 6 ++++ 2 files changed, 54 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 79be4f5..4466ece 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -870,11 +870,16 @@ static FloatParts return_nan(FloatParts a, float_status *s) return a; } -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static void set_snan_flag(FloatParts a, FloatParts b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { s->float_exception_flags |= float_flag_invalid; } +} + +static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +{ + set_snan_flag(a, b, s); if (s->default_nan_mode) { return parts_default_nan(s); @@ -2743,23 +2748,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status) * and minNumMag() from the IEEE-754 2008. */ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, - bool ieee, bool ismag, float_status *s) + bool ieee, bool ismag, bool issnan_prop, + float_status *s) { if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { if (ieee) { /* Takes two floating-point values `a' and `b', one of * which is a NaN, and returns the appropriate NaN * result. If either `a' or `b' is a signaling NaN, - * the invalid exception is raised. + * the invalid exception is raised but the NaN + * propagation is 'shall'. */ if (is_snan(a.cls) || is_snan(b.cls)) { - return pick_nan(a, b, s); - } else if (is_nan(a.cls) && !is_nan(b.cls)) { + if (issnan_prop) { + return pick_nan(a, b, s); + } else { + set_snan_flag(a, b, s); + } + } + + if (is_nan(a.cls) && !is_nan(b.cls)) { return b; } else if (is_nan(b.cls) && !is_nan(a.cls)) { return a; } } + return pick_nan(a, b, s); } else { int a_exp, b_exp; @@ -2813,37 +2827,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, } } -#define MINMAX(sz, name, ismin, isiee, ismag) \ +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \ float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ FloatParts pa = float ## sz ## _unpack_canonical(a, s); \ FloatParts pb = float ## sz ## _unpack_canonical(b, s); \ - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \ + issnan_prop, s); \ \ return float ## sz ## _round_pack_canonical(pr, s); \ } -MINMAX(16, min, true, false, false) -MINMAX(16, minnum, true, true, false) -MINMAX(16, minnummag, true, true, true) -MINMAX(16, max, false, false, false) -MINMAX(16, maxnum, false, true, false) -MINMAX(16, maxnummag, false, true, true) - -MINMAX(32, min, true, false, false) -MINMAX(32, minnum, true, true, false) -MINMAX(32, minnummag, true, true, true) -MINMAX(32, max, false, false, false) -MINMAX(32, maxnum, false, true, false) -MINMAX(32, maxnummag, false, true, true) - -MINMAX(64, min, true, false, false) -MINMAX(64, minnum, true, true, false) -MINMAX(64, minnummag, true, true, true) -MINMAX(64, max, false, false, false) -MINMAX(64, maxnum, false, true, false) -MINMAX(64, maxnummag, false, true, true) +MINMAX(16, min, true, false, false, true) +MINMAX(16, minnum, true, true, false, true) +MINMAX(16, minnum_noprop, true, true, false, false) +MINMAX(16, minnummag, true, true, true, true) +MINMAX(16, max, false, false, false, true) +MINMAX(16, maxnum, false, true, false, true) +MINMAX(16, maxnum_noprop, false, true, false, false) +MINMAX(16, maxnummag, false, true, true, true) + +MINMAX(32, min, true, false, false, true) +MINMAX(32, minnum, true, true, false, true) +MINMAX(32, minnum_noprop, true, true, false, false) +MINMAX(32, minnummag, true, true, true, true) +MINMAX(32, max, false, false, false, true) +MINMAX(32, maxnum, false, true, false, true) +MINMAX(32, maxnum_noprop, false, true, false, false) +MINMAX(32, maxnummag, false, true, true, true) + +MINMAX(64, min, true, false, false, true) +MINMAX(64, minnum, true, true, false, true) +MINMAX(64, minnum_noprop, true, true, false, false) +MINMAX(64, minnummag, true, true, true, true) +MINMAX(64, max, false, false, false, true) +MINMAX(64, maxnum, false, true, false, true) +MINMAX(64, maxnum_noprop, false, true, false, false) +MINMAX(64, maxnummag, false, true, true, true) #undef MINMAX diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 573fce9..65842b0 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -231,6 +231,8 @@ float16 float16_minnum(float16, float16, float_status *status); float16 float16_maxnum(float16, float16, float_status *status); float16 float16_minnummag(float16, float16, float_status *status); float16 float16_maxnummag(float16, float16, float_status *status); +float16 float16_minnum_noprop(float16, float16, float_status *status); +float16 float16_maxnum_noprop(float16, float16, float_status *status); float16 float16_sqrt(float16, float_status *status); FloatRelation float16_compare(float16, float16, float_status *status); FloatRelation float16_compare_quiet(float16, float16, float_status *status); @@ -392,6 +394,8 @@ float32 float32_minnum(float32, float32, float_status *status); float32 float32_maxnum(float32, float32, float_status *status); float32 float32_minnummag(float32, float32, float_status *status); float32 float32_maxnummag(float32, float32, float_status *status); +float32 float32_minnum_noprop(float32, float32, float_status *status); +float32 float32_maxnum_noprop(float32, float32, float_status *status); bool float32_is_quiet_nan(float32, float_status *status); bool float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); @@ -581,6 +585,8 @@ float64 float64_minnum(float64, float64, float_status *status); float64 float64_maxnum(float64, float64, float_status *status); float64 float64_minnummag(float64, float64, float_status *status); float64 float64_maxnummag(float64, float64, float_status *status); +float64 float64_minnum_noprop(float64, float64, float_status *status); +float64 float64_maxnum_noprop(float64, float64, float_status *status); bool float64_is_quiet_nan(float64 a, float_status *status); bool float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -- 2.7.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation @ 2020-07-30 9:52 ` Chih-Min Chao 0 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Chih-Min Chao, Aurelien Jarno, Peter Maydell, Alex Bennée For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan The alternative path set invalid flag if ft1 == sNaN || ft2 == sNaN return NaN if ft1 == sNaN && ft2 == sNaN The ieee754 spec allows both implementation and some architecture such as riscv choose differenct defintion in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> --- fpu/softfloat.c | 75 +++++++++++++++++++++++++++++++------------------ include/fpu/softfloat.h | 6 ++++ 2 files changed, 54 insertions(+), 27 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 79be4f5..4466ece 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -870,11 +870,16 @@ static FloatParts return_nan(FloatParts a, float_status *s) return a; } -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static void set_snan_flag(FloatParts a, FloatParts b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { s->float_exception_flags |= float_flag_invalid; } +} + +static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +{ + set_snan_flag(a, b, s); if (s->default_nan_mode) { return parts_default_nan(s); @@ -2743,23 +2748,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status) * and minNumMag() from the IEEE-754 2008. */ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, - bool ieee, bool ismag, float_status *s) + bool ieee, bool ismag, bool issnan_prop, + float_status *s) { if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { if (ieee) { /* Takes two floating-point values `a' and `b', one of * which is a NaN, and returns the appropriate NaN * result. If either `a' or `b' is a signaling NaN, - * the invalid exception is raised. + * the invalid exception is raised but the NaN + * propagation is 'shall'. */ if (is_snan(a.cls) || is_snan(b.cls)) { - return pick_nan(a, b, s); - } else if (is_nan(a.cls) && !is_nan(b.cls)) { + if (issnan_prop) { + return pick_nan(a, b, s); + } else { + set_snan_flag(a, b, s); + } + } + + if (is_nan(a.cls) && !is_nan(b.cls)) { return b; } else if (is_nan(b.cls) && !is_nan(a.cls)) { return a; } } + return pick_nan(a, b, s); } else { int a_exp, b_exp; @@ -2813,37 +2827,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, } } -#define MINMAX(sz, name, ismin, isiee, ismag) \ +#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \ float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ FloatParts pa = float ## sz ## _unpack_canonical(a, s); \ FloatParts pb = float ## sz ## _unpack_canonical(b, s); \ - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \ + issnan_prop, s); \ \ return float ## sz ## _round_pack_canonical(pr, s); \ } -MINMAX(16, min, true, false, false) -MINMAX(16, minnum, true, true, false) -MINMAX(16, minnummag, true, true, true) -MINMAX(16, max, false, false, false) -MINMAX(16, maxnum, false, true, false) -MINMAX(16, maxnummag, false, true, true) - -MINMAX(32, min, true, false, false) -MINMAX(32, minnum, true, true, false) -MINMAX(32, minnummag, true, true, true) -MINMAX(32, max, false, false, false) -MINMAX(32, maxnum, false, true, false) -MINMAX(32, maxnummag, false, true, true) - -MINMAX(64, min, true, false, false) -MINMAX(64, minnum, true, true, false) -MINMAX(64, minnummag, true, true, true) -MINMAX(64, max, false, false, false) -MINMAX(64, maxnum, false, true, false) -MINMAX(64, maxnummag, false, true, true) +MINMAX(16, min, true, false, false, true) +MINMAX(16, minnum, true, true, false, true) +MINMAX(16, minnum_noprop, true, true, false, false) +MINMAX(16, minnummag, true, true, true, true) +MINMAX(16, max, false, false, false, true) +MINMAX(16, maxnum, false, true, false, true) +MINMAX(16, maxnum_noprop, false, true, false, false) +MINMAX(16, maxnummag, false, true, true, true) + +MINMAX(32, min, true, false, false, true) +MINMAX(32, minnum, true, true, false, true) +MINMAX(32, minnum_noprop, true, true, false, false) +MINMAX(32, minnummag, true, true, true, true) +MINMAX(32, max, false, false, false, true) +MINMAX(32, maxnum, false, true, false, true) +MINMAX(32, maxnum_noprop, false, true, false, false) +MINMAX(32, maxnummag, false, true, true, true) + +MINMAX(64, min, true, false, false, true) +MINMAX(64, minnum, true, true, false, true) +MINMAX(64, minnum_noprop, true, true, false, false) +MINMAX(64, minnummag, true, true, true, true) +MINMAX(64, max, false, false, false, true) +MINMAX(64, maxnum, false, true, false, true) +MINMAX(64, maxnum_noprop, false, true, false, false) +MINMAX(64, maxnummag, false, true, true, true) #undef MINMAX diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 573fce9..65842b0 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -231,6 +231,8 @@ float16 float16_minnum(float16, float16, float_status *status); float16 float16_maxnum(float16, float16, float_status *status); float16 float16_minnummag(float16, float16, float_status *status); float16 float16_maxnummag(float16, float16, float_status *status); +float16 float16_minnum_noprop(float16, float16, float_status *status); +float16 float16_maxnum_noprop(float16, float16, float_status *status); float16 float16_sqrt(float16, float_status *status); FloatRelation float16_compare(float16, float16, float_status *status); FloatRelation float16_compare_quiet(float16, float16, float_status *status); @@ -392,6 +394,8 @@ float32 float32_minnum(float32, float32, float_status *status); float32 float32_maxnum(float32, float32, float_status *status); float32 float32_minnummag(float32, float32, float_status *status); float32 float32_maxnummag(float32, float32, float_status *status); +float32 float32_minnum_noprop(float32, float32, float_status *status); +float32 float32_maxnum_noprop(float32, float32, float_status *status); bool float32_is_quiet_nan(float32, float_status *status); bool float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); @@ -581,6 +585,8 @@ float64 float64_minnum(float64, float64, float_status *status); float64 float64_maxnum(float64, float64, float_status *status); float64 float64_minnummag(float64, float64, float_status *status); float64 float64_maxnummag(float64, float64, float_status *status); +float64 float64_minnum_noprop(float64, float64, float_status *status); +float64 float64_maxnum_noprop(float64, float64, float_status *status); bool float64_is_quiet_nan(float64 a, float_status *status); bool float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -- 2.7.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation 2020-07-30 9:52 ` Chih-Min Chao @ 2020-08-13 17:21 ` Richard Henderson -1 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-13 17:21 UTC (permalink / raw) To: Chih-Min Chao, qemu-devel, qemu-riscv Cc: Peter Maydell, Alex Bennée, Aurelien Jarno On 7/30/20 2:52 AM, Chih-Min Chao wrote: > For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, > The original logic > return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan > > The alternative path > set invalid flag if ft1 == sNaN || ft2 == sNaN > return NaN if ft1 == sNaN && ft2 == sNaN > > The ieee754 spec allows both implementation and some architecture such > as riscv choose differenct defintion in two spec versions. > (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to > alternative) > > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> If both ft1 and ft2 are SNaN, surely the returned result is silenced? That is something that is handled by pick_nan, but is not handled here. Also, the patch subject should be modified to emphasize that this only applies to min/max and not propagation of all SNaN. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation @ 2020-08-13 17:21 ` Richard Henderson 0 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-13 17:21 UTC (permalink / raw) To: Chih-Min Chao, qemu-devel, qemu-riscv Cc: Alex Bennée, Aurelien Jarno, Peter Maydell On 7/30/20 2:52 AM, Chih-Min Chao wrote: > For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, > The original logic > return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan > > The alternative path > set invalid flag if ft1 == sNaN || ft2 == sNaN > return NaN if ft1 == sNaN && ft2 == sNaN > > The ieee754 spec allows both implementation and some architecture such > as riscv choose differenct defintion in two spec versions. > (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to > alternative) > > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> If both ft1 and ft2 are SNaN, surely the returned result is silenced? That is something that is handled by pick_nan, but is not handled here. Also, the patch subject should be modified to emphasize that this only applies to min/max and not propagation of all SNaN. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation 2020-08-13 17:21 ` Richard Henderson @ 2020-08-14 8:59 ` Chih-Min Chao -1 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-08-14 8:59 UTC (permalink / raw) To: Richard Henderson Cc: Alex Bennée, open list:RISC-V, qemu-devel@nongnu.org Developers, Aurelien Jarno, Peter Maydell [-- Attachment #1: Type: text/plain, Size: 1284 bytes --] On Fri, Aug 14, 2020 at 1:21 AM Richard Henderson < richard.henderson@linaro.org> wrote: > On 7/30/20 2:52 AM, Chih-Min Chao wrote: > > For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, > > The original logic > > return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan > > > > The alternative path > > set invalid flag if ft1 == sNaN || ft2 == sNaN > > return NaN if ft1 == sNaN && ft2 == sNaN > > > > The ieee754 spec allows both implementation and some architecture such > > as riscv choose differenct defintion in two spec versions. > > (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to > > alternative) > > > > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> > > If both ft1 and ft2 are SNaN, surely the returned result is silenced? > That is > something that is handled by pick_nan, but is not handled here. > Yes, it returns the default_nan, qNaN. > > Also, the patch subject should be modified to emphasize that this only > applies > to min/max and not propagation of all SNaN. > > Will be fixed in the next version. By the way, the other patches have been queued in softfloat-next. Do I need to resend the other two patches in the next version or just this one ? Chih-Min Chao > > > r~ > > > [-- Attachment #2: Type: text/html, Size: 2332 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation @ 2020-08-14 8:59 ` Chih-Min Chao 0 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-08-14 8:59 UTC (permalink / raw) To: Richard Henderson Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alex Bennée, Aurelien Jarno, Peter Maydell [-- Attachment #1: Type: text/plain, Size: 1284 bytes --] On Fri, Aug 14, 2020 at 1:21 AM Richard Henderson < richard.henderson@linaro.org> wrote: > On 7/30/20 2:52 AM, Chih-Min Chao wrote: > > For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, > > The original logic > > return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan > > > > The alternative path > > set invalid flag if ft1 == sNaN || ft2 == sNaN > > return NaN if ft1 == sNaN && ft2 == sNaN > > > > The ieee754 spec allows both implementation and some architecture such > > as riscv choose differenct defintion in two spec versions. > > (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to > > alternative) > > > > Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> > > If both ft1 and ft2 are SNaN, surely the returned result is silenced? > That is > something that is handled by pick_nan, but is not handled here. > Yes, it returns the default_nan, qNaN. > > Also, the patch subject should be modified to emphasize that this only > applies > to min/max and not propagation of all SNaN. > > Will be fixed in the next version. By the way, the other patches have been queued in softfloat-next. Do I need to resend the other two patches in the next version or just this one ? Chih-Min Chao > > > r~ > > > [-- Attachment #2: Type: text/html, Size: 2332 bytes --] ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation 2020-08-14 8:59 ` Chih-Min Chao @ 2020-08-14 16:15 ` Richard Henderson -1 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-14 16:15 UTC (permalink / raw) To: Chih-Min Chao Cc: Alex Bennée, open list:RISC-V, qemu-devel@nongnu.org Developers, Aurelien Jarno, Peter Maydell On 8/14/20 1:59 AM, Chih-Min Chao wrote: > By the way, the other patches have been queued in softfloat-next. > Do I need to resend the other two patches in the next version or just this one ? Just this one. Thanks. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation @ 2020-08-14 16:15 ` Richard Henderson 0 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-14 16:15 UTC (permalink / raw) To: Chih-Min Chao Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alex Bennée, Aurelien Jarno, Peter Maydell On 8/14/20 1:59 AM, Chih-Min Chao wrote: > By the way, the other patches have been queued in softfloat-next. > Do I need to resend the other two patches in the next version or just this one ? Just this one. Thanks. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/3] softfloat: add fp16 and uint8/int8 interconvert functions 2020-07-30 9:52 [PATCH 0/3] float16 APIs and alternative sNaN handling Chih-Min Chao @ 2020-07-30 9:52 ` Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Frank Chang, Peter Maydell, Alex Bennée, Aurelien Jarno From: Frank Chang <frank.chang@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> --- fpu/softfloat.c | 34 ++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 8 ++++++++ 2 files changed, 42 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4466ece..c700a39 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2114,6 +2114,13 @@ static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode, } } +int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + return round_to_int_and_pack(float16_unpack_canonical(a, s), + rmode, scale, INT8_MIN, INT8_MAX, s); +} + int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { @@ -2177,6 +2184,11 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, rmode, scale, INT64_MIN, INT64_MAX, s); } +int8_t float16_to_int8(float16 a, float_status *s) +{ + return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16(float16 a, float_status *s) { return float16_to_int16_scalbn(a, s->float_rounding_mode, 0, s); @@ -2327,6 +2339,13 @@ static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode, } } +uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + return round_to_uint_and_pack(float16_unpack_canonical(a, s), + rmode, scale, UINT8_MAX, s); +} + uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { @@ -2390,6 +2409,11 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale, rmode, scale, UINT64_MAX, s); } +uint8_t float16_to_uint8(float16 a, float_status *s) +{ + return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s); +} + uint16_t float16_to_uint16(float16 a, float_status *s) { return float16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s); @@ -2544,6 +2568,11 @@ float16 int16_to_float16(int16_t a, float_status *status) return int64_to_float16_scalbn(a, 0, status); } +float16 int8_to_float16(int8_t a, float_status *status) +{ + return int64_to_float16_scalbn(a, 0, status); +} + float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { FloatParts pa = int_to_float(a, scale, status); @@ -2669,6 +2698,11 @@ float16 uint16_to_float16(uint16_t a, float_status *status) return uint64_to_float16_scalbn(a, 0, status); } +float16 uint8_to_float16(uint8_t a, float_status *status) +{ + return uint64_to_float16_scalbn(a, 0, status); +} + float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status) { FloatParts pa = uint_to_float(a, scale, status); diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 65842b0..fec670a 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -136,9 +136,11 @@ float16 uint16_to_float16_scalbn(uint16_t a, int, float_status *status); float16 uint32_to_float16_scalbn(uint32_t a, int, float_status *status); float16 uint64_to_float16_scalbn(uint64_t a, int, float_status *status); +float16 int8_to_float16(int8_t a, float_status *status); float16 int16_to_float16(int16_t a, float_status *status); float16 int32_to_float16(int32_t a, float_status *status); float16 int64_to_float16(int64_t a, float_status *status); +float16 uint8_to_float16(uint8_t a, float_status *status); float16 uint16_to_float16(uint16_t a, float_status *status); float16 uint32_to_float16(uint32_t a, float_status *status); float16 uint64_to_float16(uint64_t a, float_status *status); @@ -187,10 +189,13 @@ float32 float16_to_float32(float16, bool ieee, float_status *status); float16 float64_to_float16(float64 a, bool ieee, float_status *status); float64 float16_to_float64(float16 a, bool ieee, float_status *status); +int8_t float16_to_int8_scalbn(float16, FloatRoundMode, int, + float_status *status); int16_t float16_to_int16_scalbn(float16, FloatRoundMode, int, float_status *); int32_t float16_to_int32_scalbn(float16, FloatRoundMode, int, float_status *); int64_t float16_to_int64_scalbn(float16, FloatRoundMode, int, float_status *); +int8_t float16_to_int8(float16, float_status *status); int16_t float16_to_int16(float16, float_status *status); int32_t float16_to_int32(float16, float_status *status); int64_t float16_to_int64(float16, float_status *status); @@ -199,6 +204,8 @@ int16_t float16_to_int16_round_to_zero(float16, float_status *status); int32_t float16_to_int32_round_to_zero(float16, float_status *status); int64_t float16_to_int64_round_to_zero(float16, float_status *status); +uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode, + int, float_status *status); uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode, int, float_status *status); uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode, @@ -206,6 +213,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode, uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode, int, float_status *status); +uint8_t float16_to_uint8(float16 a, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); uint32_t float16_to_uint32(float16 a, float_status *status); uint64_t float16_to_uint64(float16 a, float_status *status); -- 2.7.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/3] softfloat: add fp16 and uint8/int8 interconvert functions @ 2020-07-30 9:52 ` Chih-Min Chao 0 siblings, 0 replies; 18+ messages in thread From: Chih-Min Chao @ 2020-07-30 9:52 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: Frank Chang, Aurelien Jarno, Peter Maydell, Alex Bennée From: Frank Chang <frank.chang@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> --- fpu/softfloat.c | 34 ++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 8 ++++++++ 2 files changed, 42 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4466ece..c700a39 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2114,6 +2114,13 @@ static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode, } } +int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + return round_to_int_and_pack(float16_unpack_canonical(a, s), + rmode, scale, INT8_MIN, INT8_MAX, s); +} + int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { @@ -2177,6 +2184,11 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, rmode, scale, INT64_MIN, INT64_MAX, s); } +int8_t float16_to_int8(float16 a, float_status *s) +{ + return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16(float16 a, float_status *s) { return float16_to_int16_scalbn(a, s->float_rounding_mode, 0, s); @@ -2327,6 +2339,13 @@ static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode, } } +uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + return round_to_uint_and_pack(float16_unpack_canonical(a, s), + rmode, scale, UINT8_MAX, s); +} + uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { @@ -2390,6 +2409,11 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale, rmode, scale, UINT64_MAX, s); } +uint8_t float16_to_uint8(float16 a, float_status *s) +{ + return float16_to_uint8_scalbn(a, s->float_rounding_mode, 0, s); +} + uint16_t float16_to_uint16(float16 a, float_status *s) { return float16_to_uint16_scalbn(a, s->float_rounding_mode, 0, s); @@ -2544,6 +2568,11 @@ float16 int16_to_float16(int16_t a, float_status *status) return int64_to_float16_scalbn(a, 0, status); } +float16 int8_to_float16(int8_t a, float_status *status) +{ + return int64_to_float16_scalbn(a, 0, status); +} + float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { FloatParts pa = int_to_float(a, scale, status); @@ -2669,6 +2698,11 @@ float16 uint16_to_float16(uint16_t a, float_status *status) return uint64_to_float16_scalbn(a, 0, status); } +float16 uint8_to_float16(uint8_t a, float_status *status) +{ + return uint64_to_float16_scalbn(a, 0, status); +} + float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status) { FloatParts pa = uint_to_float(a, scale, status); diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 65842b0..fec670a 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -136,9 +136,11 @@ float16 uint16_to_float16_scalbn(uint16_t a, int, float_status *status); float16 uint32_to_float16_scalbn(uint32_t a, int, float_status *status); float16 uint64_to_float16_scalbn(uint64_t a, int, float_status *status); +float16 int8_to_float16(int8_t a, float_status *status); float16 int16_to_float16(int16_t a, float_status *status); float16 int32_to_float16(int32_t a, float_status *status); float16 int64_to_float16(int64_t a, float_status *status); +float16 uint8_to_float16(uint8_t a, float_status *status); float16 uint16_to_float16(uint16_t a, float_status *status); float16 uint32_to_float16(uint32_t a, float_status *status); float16 uint64_to_float16(uint64_t a, float_status *status); @@ -187,10 +189,13 @@ float32 float16_to_float32(float16, bool ieee, float_status *status); float16 float64_to_float16(float64 a, bool ieee, float_status *status); float64 float16_to_float64(float16 a, bool ieee, float_status *status); +int8_t float16_to_int8_scalbn(float16, FloatRoundMode, int, + float_status *status); int16_t float16_to_int16_scalbn(float16, FloatRoundMode, int, float_status *); int32_t float16_to_int32_scalbn(float16, FloatRoundMode, int, float_status *); int64_t float16_to_int64_scalbn(float16, FloatRoundMode, int, float_status *); +int8_t float16_to_int8(float16, float_status *status); int16_t float16_to_int16(float16, float_status *status); int32_t float16_to_int32(float16, float_status *status); int64_t float16_to_int64(float16, float_status *status); @@ -199,6 +204,8 @@ int16_t float16_to_int16_round_to_zero(float16, float_status *status); int32_t float16_to_int32_round_to_zero(float16, float_status *status); int64_t float16_to_int64_round_to_zero(float16, float_status *status); +uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode, + int, float_status *status); uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode, int, float_status *status); uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode, @@ -206,6 +213,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode, uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode, int, float_status *status); +uint8_t float16_to_uint8(float16 a, float_status *status); uint16_t float16_to_uint16(float16 a, float_status *status); uint32_t float16_to_uint32(float16 a, float_status *status); uint64_t float16_to_uint64(float16 a, float_status *status); -- 2.7.4 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/3] softfloat: add fp16 and uint8/int8 interconvert functions 2020-07-30 9:52 ` Chih-Min Chao (?) @ 2020-08-13 17:25 ` Richard Henderson -1 siblings, 0 replies; 18+ messages in thread From: Richard Henderson @ 2020-08-13 17:25 UTC (permalink / raw) To: Chih-Min Chao, qemu-devel, qemu-riscv Cc: Frank Chang, Peter Maydell, Alex Bennée, Aurelien Jarno On 7/30/20 2:52 AM, Chih-Min Chao wrote: > From: Frank Chang <frank.chang@sifive.com> > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Queued to softfloat-next. r~ ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2020-08-14 16:16 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-07-30 9:52 [PATCH 0/3] float16 APIs and alternative sNaN handling Chih-Min Chao 2020-07-30 9:52 ` [PATCH 1/3] softfloat: target/riscv: implement full set fp16 comparision Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2020-08-12 16:30 ` Alistair Francis 2020-08-12 16:30 ` Alistair Francis 2020-08-13 17:22 ` Richard Henderson 2020-08-13 17:22 ` Richard Henderson 2020-07-30 9:52 ` [PATCH 2/3] softfloat: add APIs to handle alternative sNaN propagation Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2020-08-13 17:21 ` Richard Henderson 2020-08-13 17:21 ` Richard Henderson 2020-08-14 8:59 ` Chih-Min Chao 2020-08-14 8:59 ` Chih-Min Chao 2020-08-14 16:15 ` Richard Henderson 2020-08-14 16:15 ` Richard Henderson 2020-07-30 9:52 ` [PATCH 3/3] softfloat: add fp16 and uint8/int8 interconvert functions Chih-Min Chao 2020-07-30 9:52 ` Chih-Min Chao 2020-08-13 17:25 ` Richard Henderson
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