From: Alain Volmat <alain.volmat@st.com> To: <broonie@kernel.org>, <amelie.delaunay@st.com> Cc: <mcoquelin.stm32@gmail.com>, <alexandre.torgue@st.com>, <linux-spi@vger.kernel.org>, <linux-stm32@st-md-mailman.stormreply.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <fabrice.gasnier@st.com>, <alain.volmat@st.com> Subject: [PATCH 13/18] spi: stm32h7: fix handling of dma transfer completed Date: Wed, 5 Aug 2020 09:02:08 +0200 [thread overview] Message-ID: <1596610933-32599-14-git-send-email-alain.volmat@st.com> (raw) In-Reply-To: <1596610933-32599-1-git-send-email-alain.volmat@st.com> From: Amelie Delaunay <amelie.delaunay@st.com> The rx dma is completed "after" the last data is received from spi. Thus, to avoid loss of rx data, it's mandatory to wait for the dma callback before tearing down the rx dma in stm32_spi_disable(). The tx dma is of course already completed when last data is sent from spi. But both spi and dma use threaded interrupts, thus there is no guarantee that the dma irq handler is already executed when the spi irq handler triggers stm32_spi_disable(). Waiting for dma callback will allow a clean termination of the dma. Remove the unused code in the current dma callback, signal the end of dma through completion, then delay spi disable until the dma callback has been executed. Signed-off-by: Antonio Borneo <antonio.borneo@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alain Volmat <alain.volmat@st.com> --- drivers/spi/spi-stm32.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 1a703c4a65db..b0a9642392e9 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -275,6 +275,7 @@ struct stm32_spi_cfg { * @rx_len: number of data to be read in bytes * @dma_tx: dma channel for TX transfer * @dma_rx: dma channel for RX transfer + * @dma_completion: completion to wait for end of DMA transfer * @phys_addr: SPI registers physical base address * @xfer_completion: completion to wait for end of transfer * @xfer_status: current transfer status @@ -304,6 +305,7 @@ struct stm32_spi { int rx_len; struct dma_chan *dma_tx; struct dma_chan *dma_rx; + struct completion dma_completion; dma_addr_t phys_addr; struct completion xfer_completion; int xfer_status; @@ -1062,25 +1064,18 @@ static void stm32f4_spi_dma_rx_cb(void *data) * stm32h7_spi_dma_cb - dma callback * @data: pointer to the spi controller data structure * - * DMA callback is called when the transfer is complete or when an error - * occurs. If the transfer is complete, EOT flag is raised. + * DMA callback is called when the transfer is complete. */ static void stm32h7_spi_dma_cb(void *data) { struct stm32_spi *spi = data; unsigned long flags; - u32 sr; spin_lock_irqsave(&spi->lock, flags); - sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + complete(&spi->dma_completion); spin_unlock_irqrestore(&spi->lock, flags); - - if (!(sr & STM32H7_SPI_SR_EOT)) - dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); - - /* Now wait for EOT, or SUSP or OVR in case of error */ } /** @@ -1274,12 +1269,20 @@ static int stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, struct spi_transfer *xfer) { + dma_async_tx_callback rx_done = NULL, tx_done = NULL; struct dma_slave_config tx_dma_conf, rx_dma_conf; struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; unsigned long flags; spin_lock_irqsave(&spi->lock, flags); + if (spi->rx_buf) + rx_done = spi->cfg->dma_rx_cb; + else if (spi->tx_buf) + tx_done = spi->cfg->dma_tx_cb; + + reinit_completion(&spi->dma_completion); + rx_dma_desc = NULL; if (spi->rx_buf && spi->dma_rx) { stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); @@ -1316,7 +1319,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, goto dma_desc_error; if (rx_dma_desc) { - rx_dma_desc->callback = spi->cfg->dma_rx_cb; + rx_dma_desc->callback = rx_done; rx_dma_desc->callback_param = spi; if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { @@ -1330,7 +1333,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, if (tx_dma_desc) { if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { - tx_dma_desc->callback = spi->cfg->dma_tx_cb; + tx_dma_desc->callback = tx_done; tx_dma_desc->callback_param = spi; } @@ -1658,6 +1661,7 @@ static int stm32_spi_transfer_one(struct spi_master *master, { struct stm32_spi *spi = spi_master_get_devdata(master); u32 xfer_time, midi_delay_ns; + unsigned long timeout; int ret; spi->tx_buf = transfer->tx_buf; @@ -1690,10 +1694,14 @@ static int stm32_spi_transfer_one(struct spi_master *master, midi_delay_ns = spi->cur_xferlen * 8 / spi->cur_bpw * spi->cur_midi; xfer_time += DIV_ROUND_UP(midi_delay_ns, NSEC_PER_MSEC); xfer_time = max(2 * xfer_time, 100U); + timeout = msecs_to_jiffies(xfer_time); + + timeout = wait_for_completion_timeout(&spi->xfer_completion, timeout); + if (timeout && spi->cur_usedma) + timeout = wait_for_completion_timeout(&spi->dma_completion, + timeout); - ret = wait_for_completion_timeout(&spi->xfer_completion, - (msecs_to_jiffies(xfer_time))); - if (!ret) { + if (!timeout) { dev_err(spi->dev, "SPI transfer timeout (%u ms)\n", xfer_time); spi->xfer_status = -ETIMEDOUT; } @@ -1854,6 +1862,7 @@ static int stm32_spi_probe(struct platform_device *pdev) spi->master = master; spin_lock_init(&spi->lock); init_completion(&spi->xfer_completion); + init_completion(&spi->dma_completion); spi->cfg = (const struct stm32_spi_cfg *) of_match_device(pdev->dev.driver->of_match_table, -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Alain Volmat <alain.volmat@st.com> To: <broonie@kernel.org>, <amelie.delaunay@st.com> Cc: alexandre.torgue@st.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, alain.volmat@st.com, mcoquelin.stm32@gmail.com, fabrice.gasnier@st.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/18] spi: stm32h7: fix handling of dma transfer completed Date: Wed, 5 Aug 2020 09:02:08 +0200 [thread overview] Message-ID: <1596610933-32599-14-git-send-email-alain.volmat@st.com> (raw) In-Reply-To: <1596610933-32599-1-git-send-email-alain.volmat@st.com> From: Amelie Delaunay <amelie.delaunay@st.com> The rx dma is completed "after" the last data is received from spi. Thus, to avoid loss of rx data, it's mandatory to wait for the dma callback before tearing down the rx dma in stm32_spi_disable(). The tx dma is of course already completed when last data is sent from spi. But both spi and dma use threaded interrupts, thus there is no guarantee that the dma irq handler is already executed when the spi irq handler triggers stm32_spi_disable(). Waiting for dma callback will allow a clean termination of the dma. Remove the unused code in the current dma callback, signal the end of dma through completion, then delay spi disable until the dma callback has been executed. Signed-off-by: Antonio Borneo <antonio.borneo@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alain Volmat <alain.volmat@st.com> --- drivers/spi/spi-stm32.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 1a703c4a65db..b0a9642392e9 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -275,6 +275,7 @@ struct stm32_spi_cfg { * @rx_len: number of data to be read in bytes * @dma_tx: dma channel for TX transfer * @dma_rx: dma channel for RX transfer + * @dma_completion: completion to wait for end of DMA transfer * @phys_addr: SPI registers physical base address * @xfer_completion: completion to wait for end of transfer * @xfer_status: current transfer status @@ -304,6 +305,7 @@ struct stm32_spi { int rx_len; struct dma_chan *dma_tx; struct dma_chan *dma_rx; + struct completion dma_completion; dma_addr_t phys_addr; struct completion xfer_completion; int xfer_status; @@ -1062,25 +1064,18 @@ static void stm32f4_spi_dma_rx_cb(void *data) * stm32h7_spi_dma_cb - dma callback * @data: pointer to the spi controller data structure * - * DMA callback is called when the transfer is complete or when an error - * occurs. If the transfer is complete, EOT flag is raised. + * DMA callback is called when the transfer is complete. */ static void stm32h7_spi_dma_cb(void *data) { struct stm32_spi *spi = data; unsigned long flags; - u32 sr; spin_lock_irqsave(&spi->lock, flags); - sr = readl_relaxed(spi->base + STM32H7_SPI_SR); + complete(&spi->dma_completion); spin_unlock_irqrestore(&spi->lock, flags); - - if (!(sr & STM32H7_SPI_SR_EOT)) - dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); - - /* Now wait for EOT, or SUSP or OVR in case of error */ } /** @@ -1274,12 +1269,20 @@ static int stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, struct spi_transfer *xfer) { + dma_async_tx_callback rx_done = NULL, tx_done = NULL; struct dma_slave_config tx_dma_conf, rx_dma_conf; struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; unsigned long flags; spin_lock_irqsave(&spi->lock, flags); + if (spi->rx_buf) + rx_done = spi->cfg->dma_rx_cb; + else if (spi->tx_buf) + tx_done = spi->cfg->dma_tx_cb; + + reinit_completion(&spi->dma_completion); + rx_dma_desc = NULL; if (spi->rx_buf && spi->dma_rx) { stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); @@ -1316,7 +1319,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, goto dma_desc_error; if (rx_dma_desc) { - rx_dma_desc->callback = spi->cfg->dma_rx_cb; + rx_dma_desc->callback = rx_done; rx_dma_desc->callback_param = spi; if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { @@ -1330,7 +1333,7 @@ static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, if (tx_dma_desc) { if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { - tx_dma_desc->callback = spi->cfg->dma_tx_cb; + tx_dma_desc->callback = tx_done; tx_dma_desc->callback_param = spi; } @@ -1658,6 +1661,7 @@ static int stm32_spi_transfer_one(struct spi_master *master, { struct stm32_spi *spi = spi_master_get_devdata(master); u32 xfer_time, midi_delay_ns; + unsigned long timeout; int ret; spi->tx_buf = transfer->tx_buf; @@ -1690,10 +1694,14 @@ static int stm32_spi_transfer_one(struct spi_master *master, midi_delay_ns = spi->cur_xferlen * 8 / spi->cur_bpw * spi->cur_midi; xfer_time += DIV_ROUND_UP(midi_delay_ns, NSEC_PER_MSEC); xfer_time = max(2 * xfer_time, 100U); + timeout = msecs_to_jiffies(xfer_time); + + timeout = wait_for_completion_timeout(&spi->xfer_completion, timeout); + if (timeout && spi->cur_usedma) + timeout = wait_for_completion_timeout(&spi->dma_completion, + timeout); - ret = wait_for_completion_timeout(&spi->xfer_completion, - (msecs_to_jiffies(xfer_time))); - if (!ret) { + if (!timeout) { dev_err(spi->dev, "SPI transfer timeout (%u ms)\n", xfer_time); spi->xfer_status = -ETIMEDOUT; } @@ -1854,6 +1862,7 @@ static int stm32_spi_probe(struct platform_device *pdev) spi->master = master; spin_lock_init(&spi->lock); init_completion(&spi->xfer_completion); + init_completion(&spi->dma_completion); spi->cfg = (const struct stm32_spi_cfg *) of_match_device(pdev->dev.driver->of_match_table, -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-08-05 7:05 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-08-05 7:01 [PATCH 00/18] spi: stm32: various driver enhancements Alain Volmat 2020-08-05 7:01 ` Alain Volmat 2020-08-05 7:01 ` [PATCH 01/18] spi: stm32-spi: driver uses reset controller only at init Alain Volmat 2020-08-05 7:01 ` Alain Volmat 2020-08-05 7:01 ` [PATCH 02/18] spi: stm32-spi: defer probe for reset Alain Volmat 2020-08-05 7:01 ` Alain Volmat 2020-08-05 10:49 ` Mark Brown 2020-08-05 10:49 ` Mark Brown 2020-08-07 13:42 ` Alain Volmat 2020-08-07 13:42 ` Alain Volmat 2020-08-07 14:01 ` Mark Brown 2020-08-07 14:01 ` Mark Brown 2020-08-05 7:01 ` [PATCH 03/18] spi: stm32h7: remove unused mode fault MODF event handling Alain Volmat 2020-08-05 7:01 ` Alain Volmat 2020-08-05 10:51 ` Mark Brown 2020-08-05 10:51 ` Mark Brown 2020-08-05 7:01 ` [PATCH 04/18] spi: stm32: use bitfield macros Alain Volmat 2020-08-05 7:01 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 05/18] spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 06/18] spi: stm32h7: fix irq handler Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 07/18] spi: stm32h7: rework rx fifo read function Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 08/18] spi: stm32h7: fix dbg/warn/err conditions in irq handler Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 09/18] spi: stm32h7: fix race condition at end of transfer Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 10:53 ` Mark Brown 2020-08-05 10:53 ` Mark Brown 2020-08-05 7:02 ` [PATCH 10/18] spi: stm32: wait for completion in transfer_one() Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 10:58 ` Mark Brown 2020-08-05 10:58 ` Mark Brown 2020-08-05 7:02 ` [PATCH 11/18] spi: stm32: fix fifo threshold level in case of short transfer Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 10:59 ` Mark Brown 2020-08-05 10:59 ` Mark Brown 2020-08-05 7:02 ` [PATCH 12/18] spi: stm32: move spi disable out of irq handler Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 11:01 ` Mark Brown 2020-08-05 11:01 ` Mark Brown 2020-08-05 7:02 ` Alain Volmat [this message] 2020-08-05 7:02 ` [PATCH 13/18] spi: stm32h7: fix handling of dma transfer completed Alain Volmat 2020-08-05 11:02 ` Mark Brown 2020-08-05 11:02 ` Mark Brown 2020-08-05 7:02 ` [PATCH 14/18] spi: stm32: improve suspend/resume management Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 15/18] spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 11:02 ` Mark Brown 2020-08-05 11:02 ` Mark Brown 2020-08-05 7:02 ` [PATCH 16/18] spi: stm32: always perform registers configuration prior to transfer Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 11:03 ` Mark Brown 2020-08-05 11:03 ` Mark Brown 2020-08-05 7:02 ` [PATCH 17/18] spi: stm32: properly handle 0 byte transfer Alain Volmat 2020-08-05 7:02 ` Alain Volmat 2020-08-05 7:02 ` [PATCH 18/18] spi: stm32h7: ensure message are smaller than max size Alain Volmat 2020-08-05 7:02 ` Alain Volmat
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