* [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock @ 2020-08-11 9:17 Chris Wilson 2020-08-11 10:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) Patchwork ` (3 more replies) 0 siblings, 4 replies; 6+ messages in thread From: Chris Wilson @ 2020-08-11 9:17 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson We assume that both timestamps are driven off the same clock [reported to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is so by reading the timestamp registers around a busywait (on an otherwise idle engine so there should be no preemptions). v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval for, and only for, CTX_TIMESTAMP. As far as I can tell, this behaviour is undocumented. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 157 +++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index b08fc5390e8a..9d5778238015 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -5,12 +5,168 @@ */ #include "i915_selftest.h" +#include "intel_gt_clock_utils.h" #include "selftest_engine.h" #include "selftest_engine_heartbeat.h" #include "selftests/igt_atomic.h" #include "selftests/igt_flush_test.h" #include "selftests/igt_spinner.h" +static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) +{ + *cs++ = MI_SEMAPHORE_WAIT | + MI_SEMAPHORE_GLOBAL_GTT | + MI_SEMAPHORE_POLL | + op; + *cs++ = value; + *cs++ = offset; + *cs++ = 0; + + return cs; +} + +static u32 *emit_store(u32 *cs, u32 offset, u32 value) +{ + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = offset; + *cs++ = 0; + *cs++ = value; + + return cs; +} + +static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset) +{ + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; + *cs++ = i915_mmio_reg_offset(reg); + *cs++ = offset; + *cs++ = 0; + + return cs; +} + +static void write_semaphore(u32 *x, u32 value) +{ + WRITE_ONCE(*x, value); + wmb(); +} + +static int __live_engine_timestamps(struct intel_engine_cs *engine) +{ + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); + u32 offset = i915_ggtt_offset(engine->status_page.vma); + struct intel_context *ce; + struct i915_request *rq; + u64 d_ring, d_ctx, dt; + u32 *cs; + + ce = intel_context_create(engine); + if (IS_ERR(ce)) + return PTR_ERR(ce); + + rq = intel_context_create_request(ce); + intel_context_put(ce); + if (IS_ERR(rq)) + return PTR_ERR(rq); + + cs = intel_ring_begin(rq, 28); + if (IS_ERR(cs)) { + i915_request_add(rq); + return PTR_ERR(cs); + } + + /* Signal & wait for start */ + cs = emit_store(cs, offset + 4008, 1); + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1); + + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); + + /* Busy wait */ + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1); + + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); + + intel_ring_advance(rq, cs); + i915_request_get(rq); + i915_request_add(rq); + intel_engine_flush_submission(engine); + + /* Wait for the request to start executing, that then waits for us */ + while (READ_ONCE(sema[2]) == 0) + cpu_relax(); + + /* Run the request for a 100us, sampling timestamps before/after */ + preempt_disable(); + dt = ktime_get_mono_fast_ns(); + write_semaphore(&sema[2], 0); + udelay(100); + write_semaphore(&sema[2], 1); + dt = ktime_get_mono_fast_ns() - dt; + preempt_enable(); + + if (i915_request_wait(rq, 0, HZ / 2) < 0) { + i915_request_put(rq); + return -ETIME; + } + i915_request_put(rq); + + pr_debug("%s CTX_TIMESTAMP: [%x, %x]\n", + engine->name, sema[1], sema[3]); + pr_debug("%s RING_TIMESTAMP: [%x, %x]\n", + engine->name, sema[0], sema[4]); + + d_ctx = sema[3] - sema[1]; + d_ring = sema[4] - sema[0]; + + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n", + engine->name, dt, + intel_gt_clock_interval_to_ns(engine->gt, d_ctx), + intel_gt_clock_interval_to_ns(engine->gt, d_ring)); + + d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; + if (IS_ICELAKE(engine->i915)) + d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ + else + d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; + + if (4 * d_ctx > 5 * d_ring || 5 * d_ctx < 4 * d_ring) { + pr_err("%s Mismatch between ring and context timestamps!\n", + engine->name); + return -EINVAL; + } + + return 0; +} + +static int live_engine_timestamps(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + + /* + * Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share + * the same CS clock. + */ + + if (INTEL_GEN(gt->i915) < 8) + return 0; + + for_each_engine(engine, gt, id) { + int err; + + st_engine_heartbeat_disable(engine); + err = __live_engine_timestamps(engine); + st_engine_heartbeat_enable(engine); + if (err) + return err; + } + + return 0; +} + static int live_engine_busy_stats(void *arg) { struct intel_gt *gt = arg; @@ -177,6 +333,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_timestamps), SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) 2020-08-11 9:17 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson @ 2020-08-11 10:03 ` Patchwork 2020-08-11 10:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-08-11 10:03 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) URL : https://patchwork.freedesktop.org/series/80475/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6f2c2821cb2d drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock -:70: WARNING:MEMORY_BARRIER: memory barrier without comment #70: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:51: + wmb(); -:123: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #123: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:104: + udelay(100); total: 0 errors, 1 warnings, 1 checks, 175 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) 2020-08-11 9:17 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson 2020-08-11 10:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) Patchwork @ 2020-08-11 10:28 ` Patchwork 2020-08-11 13:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-08-11 15:37 ` [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Lionel Landwerlin 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-08-11 10:28 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 6219 bytes --] == Series Details == Series: drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) URL : https://patchwork.freedesktop.org/series/80475/ State : success == Summary == CI Bug Log - changes from CI_DRM_8868 -> Patchwork_18342 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/index.html Known issues ------------ Here are the changes found in Patchwork_18342 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html * igt@i915_module_load@reload: - fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-apl-guc/igt@i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-apl-guc/igt@i915_module_load@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@i915_pm_rpm@module-reload: - fi-bsw-n3050: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@execlists: - fi-skl-lmem: [PASS][9] -> [INCOMPLETE][10] ([CI#80]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-skl-lmem/igt@i915_selftest@live@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-skl-lmem/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_lrc: - fi-tgl-u2: [PASS][11] -> [DMESG-FAIL][12] ([i915#1233]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1: - fi-icl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-icl-y: [INCOMPLETE][15] ([i915#2276]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-icl-y/igt@i915_selftest@live@execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-icl-y/igt@i915_selftest@live@execlists.html * igt@kms_force_connector_basic@force-connector-state: - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-tgl-dsi/igt@kms_force_connector_basic@force-connector-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-tgl-dsi/igt@kms_force_connector_basic@force-connector-state.html #### Warnings #### * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (43 -> 37) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8868 -> Patchwork_18342 CI-20190529: 20190529 CI_DRM_8868: 8013d0a5f31046f2be4ea965ec59c70b39c54186 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5766: fc9f95086fc23f7f2226f7603241fbad3a214ee1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18342: 6f2c2821cb2dee2a31d655a408c505cdffd6a8b8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6f2c2821cb2d drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/index.html [-- Attachment #1.2: Type: text/html, Size: 7823 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) 2020-08-11 9:17 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson 2020-08-11 10:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) Patchwork 2020-08-11 10:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2020-08-11 13:16 ` Patchwork 2020-08-11 15:37 ` [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Lionel Landwerlin 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-08-11 13:16 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 14570 bytes --] == Series Details == Series: drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) URL : https://patchwork.freedesktop.org/series/80475/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8868_full -> Patchwork_18342_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18342_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18342_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18342_full: ### IGT changes ### #### Possible regressions #### * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl10/igt@gem_ctx_isolation@preservation-s3@vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl4/igt@gem_ctx_isolation@preservation-s3@vecs0.html Known issues ------------ Here are the changes found in Patchwork_18342_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-glk1/igt@gem_exec_whisper@basic-queues-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-glk4/igt@gem_exec_whisper@basic-queues-forked.html * igt@i915_module_load@reload: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-tglb6/igt@i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-tglb2/igt@i915_module_load@reload.html * igt@kms_busy@basic-flip-pipe-c: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +15 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl1/igt@kms_busy@basic-flip-pipe-c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl3/igt@kms_busy@basic-flip-pipe-c.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][9] -> [FAIL][10] ([IGT#5]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset@ab-vga1-hdmi-a1: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-hsw7/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset@ab-vga1-hdmi-a1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset@ab-vga1-hdmi-a1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([i915#2055]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2122]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * igt@kms_flip_tiling@flip-to-y-tiled: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#167]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl6/igt@kms_flip_tiling@flip-to-y-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl10/igt@kms_flip_tiling@flip-to-y-tiled.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#49]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +8 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-kbl: [PASS][27] -> [FAIL][28] ([i915#31]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-kbl3/igt@kms_setmode@basic.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-kbl6/igt@kms_setmode@basic.html * igt@perf@polling-parameterized: - shard-tglb: [PASS][29] -> [FAIL][30] ([i915#1542]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-tglb1/igt@perf@polling-parameterized.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-tglb1/igt@perf@polling-parameterized.html * igt@perf@polling-small-buf: - shard-iclb: [PASS][31] -> [FAIL][32] ([i915#1722]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb2/igt@perf@polling-small-buf.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb5/igt@perf@polling-small-buf.html #### Possible fixes #### * {igt@feature_discovery@psr2}: - shard-iclb: [SKIP][33] ([i915#658]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb1/igt@feature_discovery@psr2.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb2/igt@feature_discovery@psr2.html * igt@kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][35] ([i915#118] / [i915#95]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-glk7/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html * igt@kms_color@pipe-b-ctm-0-25: - shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +4 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl2/igt@kms_color@pipe-b-ctm-0-25.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl3/igt@kms_color@pipe-b-ctm-0-25.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [FAIL][39] ([i915#96]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +8 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-tglb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb3/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb2/igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt@kms_psr2_su@page_flip: - shard-iclb: [SKIP][49] ([fdo#109642] / [fdo#111068]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb3/igt@kms_psr2_su@page_flip.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb2/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb1/igt@kms_psr@psr2_sprite_plane_onoff.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@perf@blocking-parameterized: - shard-iclb: [FAIL][53] ([i915#1542]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb8/igt@perf@blocking-parameterized.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb1/igt@perf@blocking-parameterized.html #### Warnings #### * igt@gem_exec_reloc@basic-concurrent16: - shard-apl: [TIMEOUT][55] ([i915#1635] / [i915#1958]) -> [INCOMPLETE][56] ([i915#1635] / [i915#1958]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-apl2/igt@gem_exec_reloc@basic-concurrent16.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-apl6/igt@gem_exec_reloc@basic-concurrent16.html * igt@kms_color@pipe-a-ctm-0-75: - shard-iclb: [DMESG-FAIL][57] ([i915#1149] / [i915#1226]) -> [FAIL][58] ([i915#1149] / [i915#315]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb1/igt@kms_color@pipe-a-ctm-0-75.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb2/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [DMESG-WARN][59] ([i915#1226]) -> [SKIP][60] ([fdo#109349]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8868/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8868 -> Patchwork_18342 CI-20190529: 20190529 CI_DRM_8868: 8013d0a5f31046f2be4ea965ec59c70b39c54186 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5766: fc9f95086fc23f7f2226f7603241fbad3a214ee1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18342: 6f2c2821cb2dee2a31d655a408c505cdffd6a8b8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18342/index.html [-- Attachment #1.2: Type: text/html, Size: 16989 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-08-11 9:17 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson ` (2 preceding siblings ...) 2020-08-11 13:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2020-08-11 15:37 ` Lionel Landwerlin 2020-08-11 15:47 ` Chris Wilson 3 siblings, 1 reply; 6+ messages in thread From: Lionel Landwerlin @ 2020-08-11 15:37 UTC (permalink / raw) To: Chris Wilson, intel-gfx On 11/08/2020 12:17, Chris Wilson wrote: > We assume that both timestamps are driven off the same clock [reported > to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is > so by reading the timestamp registers around a busywait (on an otherwise > idle engine so there should be no preemptions). > > v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval > for, and only for, CTX_TIMESTAMP. As far as I can tell, this behaviour > is undocumented. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> I really thought the CTX_TIMESTAMP was running 8 times slower : For the 2015 - 2016 Intel CoreTM Processors, CeleronTM Processors, and PentiumTM Processors based on the "Skylake" Platform Volume 2c: Command Reference: Registers Part 1 – Registers A through L May 2016, Revision 1.0 CTX_TIMESTAMP - Context Timestamp Count: The granularity of this toggle is at the rate of the bit 3 in the "Reported Timestamp Count" register(0x2358).. The toggle will be 8 times slower that "Reported Timestamp Count". The granularity of the time stamp base unit for "Reported Timestamp Count" is defined in the “Timestamp Bases” subsection in Power Management chapter. > --- > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 157 +++++++++++++++++++ > 1 file changed, 157 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > index b08fc5390e8a..9d5778238015 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -5,12 +5,168 @@ > */ > > #include "i915_selftest.h" > +#include "intel_gt_clock_utils.h" > #include "selftest_engine.h" > #include "selftest_engine_heartbeat.h" > #include "selftests/igt_atomic.h" > #include "selftests/igt_flush_test.h" > #include "selftests/igt_spinner.h" > > +static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) > +{ > + *cs++ = MI_SEMAPHORE_WAIT | > + MI_SEMAPHORE_GLOBAL_GTT | > + MI_SEMAPHORE_POLL | > + op; > + *cs++ = value; > + *cs++ = offset; > + *cs++ = 0; > + > + return cs; > +} > + > +static u32 *emit_store(u32 *cs, u32 offset, u32 value) > +{ > + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > + *cs++ = offset; > + *cs++ = 0; > + *cs++ = value; > + > + return cs; > +} > + > +static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset) > +{ > + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; > + *cs++ = i915_mmio_reg_offset(reg); > + *cs++ = offset; > + *cs++ = 0; > + > + return cs; > +} > + > +static void write_semaphore(u32 *x, u32 value) > +{ > + WRITE_ONCE(*x, value); > + wmb(); > +} > + > +static int __live_engine_timestamps(struct intel_engine_cs *engine) > +{ > + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); > + u32 offset = i915_ggtt_offset(engine->status_page.vma); > + struct intel_context *ce; > + struct i915_request *rq; > + u64 d_ring, d_ctx, dt; > + u32 *cs; > + > + ce = intel_context_create(engine); > + if (IS_ERR(ce)) > + return PTR_ERR(ce); > + > + rq = intel_context_create_request(ce); > + intel_context_put(ce); > + if (IS_ERR(rq)) > + return PTR_ERR(rq); > + > + cs = intel_ring_begin(rq, 28); > + if (IS_ERR(cs)) { > + i915_request_add(rq); > + return PTR_ERR(cs); > + } > + > + /* Signal & wait for start */ > + cs = emit_store(cs, offset + 4008, 1); > + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1); > + > + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); > + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); > + > + /* Busy wait */ > + cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1); > + > + cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); > + cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); > + > + intel_ring_advance(rq, cs); > + i915_request_get(rq); > + i915_request_add(rq); > + intel_engine_flush_submission(engine); > + > + /* Wait for the request to start executing, that then waits for us */ > + while (READ_ONCE(sema[2]) == 0) > + cpu_relax(); > + > + /* Run the request for a 100us, sampling timestamps before/after */ > + preempt_disable(); > + dt = ktime_get_mono_fast_ns(); > + write_semaphore(&sema[2], 0); > + udelay(100); > + write_semaphore(&sema[2], 1); > + dt = ktime_get_mono_fast_ns() - dt; > + preempt_enable(); > + > + if (i915_request_wait(rq, 0, HZ / 2) < 0) { > + i915_request_put(rq); > + return -ETIME; > + } > + i915_request_put(rq); > + > + pr_debug("%s CTX_TIMESTAMP: [%x, %x]\n", > + engine->name, sema[1], sema[3]); > + pr_debug("%s RING_TIMESTAMP: [%x, %x]\n", > + engine->name, sema[0], sema[4]); > + > + d_ctx = sema[3] - sema[1]; > + d_ring = sema[4] - sema[0]; > + > + pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%dns, RING_TIMESTAMP:%dns\n", > + engine->name, dt, > + intel_gt_clock_interval_to_ns(engine->gt, d_ctx), > + intel_gt_clock_interval_to_ns(engine->gt, d_ring)); > + > + d_ctx *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > + if (IS_ICELAKE(engine->i915)) > + d_ring *= 12500000; /* Fixed 80ns for icl ctx timestamp? */ > + else > + d_ring *= RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz; > + > + if (4 * d_ctx > 5 * d_ring || 5 * d_ctx < 4 * d_ring) { > + pr_err("%s Mismatch between ring and context timestamps!\n", > + engine->name); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int live_engine_timestamps(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + > + /* > + * Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share > + * the same CS clock. > + */ > + > + if (INTEL_GEN(gt->i915) < 8) > + return 0; > + > + for_each_engine(engine, gt, id) { > + int err; > + > + st_engine_heartbeat_disable(engine); > + err = __live_engine_timestamps(engine); > + st_engine_heartbeat_enable(engine); > + if (err) > + return err; > + } > + > + return 0; > +} > + > static int live_engine_busy_stats(void *arg) > { > struct intel_gt *gt = arg; > @@ -177,6 +333,7 @@ static int live_engine_pm(void *arg) > int live_engine_pm_selftests(struct intel_gt *gt) > { > static const struct i915_subtest tests[] = { > + SUBTEST(live_engine_timestamps), > SUBTEST(live_engine_busy_stats), > SUBTEST(live_engine_pm), > }; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock 2020-08-11 15:37 ` [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Lionel Landwerlin @ 2020-08-11 15:47 ` Chris Wilson 0 siblings, 0 replies; 6+ messages in thread From: Chris Wilson @ 2020-08-11 15:47 UTC (permalink / raw) To: Lionel Landwerlin, intel-gfx Quoting Lionel Landwerlin (2020-08-11 16:37:10) > On 11/08/2020 12:17, Chris Wilson wrote: > > We assume that both timestamps are driven off the same clock [reported > > to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is > > so by reading the timestamp registers around a busywait (on an otherwise > > idle engine so there should be no preemptions). > > > > v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval > > for, and only for, CTX_TIMESTAMP. As far as I can tell, this behaviour > > is undocumented. > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > > I really thought the CTX_TIMESTAMP was running 8 times slower : > > > For the 2015 - 2016 Intel CoreTM Processors, CeleronTM Processors, > and PentiumTM Processors based on the "Skylake" Platform > > Volume 2c: Command Reference: Registers > Part 1 – Registers A through L > > May 2016, Revision 1.0 > > CTX_TIMESTAMP - Context Timestamp Count: > > The granularity of this toggle is at the rate of the bit 3 in the > "Reported Timestamp Count" > register(0x2358).. The toggle will be 8 times slower that "Reported > Timestamp Count". The > granularity of the time stamp base unit for "Reported Timestamp Count" > is defined in the > “Timestamp Bases” subsection in Power Management chapter. I read that paragraph in the same way, that the CTX_TIMESTAMP is only being advanced [by 1 tick] on every 8th tick of CS_TIMESTAMP. That turns out to be not what happens... So I guess they mean that CTX_TIMESTAMP increments by 8 every 8th tick. I haven't bothered to check to see if there's anything in the low 2 bits of CTX_TIMESTAMP. Still nothing mentions that Icelake has a completely different behaviour afaict. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-08-11 15:47 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-08-11 9:17 [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Chris Wilson 2020-08-11 10:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock (rev2) Patchwork 2020-08-11 10:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-08-11 13:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2020-08-11 15:37 ` [Intel-gfx] [PATCH] drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock Lionel Landwerlin 2020-08-11 15:47 ` Chris Wilson
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