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* [PATCH 00/12] hw/riscv: Clean up the directory
@ 2020-09-03 10:40 Bin Meng
  2020-09-03 10:40 ` [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc Bin Meng
                   ` (13 more replies)
  0 siblings, 14 replies; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Peripheral models for a specific SoC are moved to its
corresponding hw/* subdirectories.

This series should be applied after the PolarFire SoC series:
http://patchwork.ozlabs.org/project/qemu-devel/list/?series=198727


Bin Meng (12):
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Sort the Kconfig options in alphabetical order

 {include/hw/riscv => hw/intc}/sifive_plic.h |  0
 hw/riscv/trace.h                            |  1 -
 include/hw/{riscv => char}/riscv_htif.h     |  0
 include/hw/{riscv => char}/sifive_uart.h    |  0
 include/hw/{riscv => gpio}/sifive_gpio.h    |  0
 include/hw/{riscv => intc}/sifive_clint.h   |  0
 include/hw/{riscv => misc}/sifive_e_prci.h  |  0
 include/hw/{riscv => misc}/sifive_test.h    |  0
 include/hw/{riscv => misc}/sifive_u_otp.h   |  0
 include/hw/{riscv => misc}/sifive_u_prci.h  |  0
 include/hw/riscv/sifive_e.h                 |  2 +-
 include/hw/riscv/sifive_u.h                 |  6 +--
 hw/{riscv => char}/riscv_htif.c             |  2 +-
 hw/{riscv => char}/sifive_uart.c            |  2 +-
 hw/{riscv => gpio}/sifive_gpio.c            |  2 +-
 hw/{riscv => intc}/sifive_clint.c           |  2 +-
 hw/{riscv => intc}/sifive_plic.c            |  2 +-
 hw/{riscv => misc}/sifive_e_prci.c          |  2 +-
 hw/{riscv => misc}/sifive_test.c            |  2 +-
 hw/{riscv => misc}/sifive_u_otp.c           |  2 +-
 hw/{riscv => misc}/sifive_u_prci.c          |  2 +-
 hw/riscv/microchip_pfsoc.c                  |  4 +-
 hw/riscv/sifive_e.c                         |  8 ++--
 hw/riscv/sifive_u.c                         |  6 +--
 hw/riscv/spike.c                            |  4 +-
 hw/riscv/virt.c                             |  6 +--
 hw/char/Kconfig                             |  6 +++
 hw/char/meson.build                         |  2 +
 hw/gpio/Kconfig                             |  3 ++
 hw/gpio/meson.build                         |  1 +
 hw/gpio/trace-events                        |  6 +++
 hw/intc/Kconfig                             |  6 +++
 hw/intc/meson.build                         |  2 +
 hw/misc/Kconfig                             | 12 +++++
 hw/misc/meson.build                         |  6 +++
 hw/riscv/Kconfig                            | 74 +++++++++++++++--------------
 hw/riscv/meson.build                        | 11 +----
 hw/riscv/trace-events                       |  7 ---
 meson.build                                 |  1 -
 39 files changed, 110 insertions(+), 82 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 delete mode 100644 hw/riscv/trace.h
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename include/hw/{riscv => intc}/sifive_clint.h (100%)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 rename hw/{riscv => char}/riscv_htif.c (99%)
 rename hw/{riscv => char}/sifive_uart.c (99%)
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 rename hw/{riscv => intc}/sifive_clint.c (99%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)
 rename hw/{riscv => misc}/sifive_test.c (98%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)
 delete mode 100644 hw/riscv/trace-events

-- 
2.7.4



^ permalink raw reply	[flat|nested] 41+ messages in thread
* [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:24     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 02/12] hw/riscv: Move sifive_u_prci " Bin Meng
                   ` (12 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => misc}/sifive_e_prci.h | 0
 hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
 hw/riscv/sifive_e.c                        | 2 +-
 hw/misc/Kconfig                            | 3 +++
 hw/misc/meson.build                        | 3 +++
 hw/riscv/Kconfig                           | 1 +
 hw/riscv/meson.build                       | 1 -
 7 files changed, 9 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)

diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_e_prci.h
rename to include/hw/misc/sifive_e_prci.h
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
similarity index 99%
rename from hw/riscv/sifive_e_prci.c
rename to hw/misc/sifive_e_prci.c
index 17dfa74..8ec4ee4 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -24,7 +24,7 @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_e_prci.h"
+#include "hw/misc/sifive_e_prci.h"
 
 static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 36ccfb2..7f43ed9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -43,8 +43,8 @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
-#include "hw/riscv/sifive_e_prci.h"
 #include "hw/riscv/boot.h"
+#include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 92c397c..5073986 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,4 +134,7 @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_E_PRCI
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index e1576b8..b6b2e57 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 # Mac devices
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
+# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+
 # PKUnity SoC devices
 softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
 
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index e53ab1e..5855e99 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_E_PRCI
     select UNIMP
 
 config SIFIVE_U
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index cf1aa99..d73ea99 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
  2020-09-03 10:40 ` [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:25     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 03/12] hw/riscv: Move sifive_u_otp " Bin Meng
                   ` (11 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => misc}/sifive_u_prci.h | 0
 include/hw/riscv/sifive_u.h                | 2 +-
 hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
 hw/misc/Kconfig                            | 3 +++
 hw/misc/meson.build                        | 1 +
 hw/riscv/Kconfig                           | 1 +
 hw/riscv/meson.build                       | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)

diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_u_prci.h
rename to include/hw/misc/sifive_u_prci.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 793000a..cbeb228 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -24,8 +24,8 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_prci.h"
 #include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
similarity index 99%
rename from hw/riscv/sifive_u_prci.c
rename to hw/misc/sifive_u_prci.c
index 4fa590c..5d9d446 100644
--- a/hw/riscv/sifive_u_prci.c
+++ b/hw/misc/sifive_u_prci.c
@@ -22,7 +22,7 @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "hw/riscv/sifive_u_prci.h"
+#include "hw/misc/sifive_u_prci.h"
 
 static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 5073986..65f3fdd 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -137,4 +137,7 @@ config AVR_POWER
 config SIFIVE_E_PRCI
     bool
 
+config SIFIVE_U_PRCI
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index b6b2e57..9e9550e 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
 # PKUnity SoC devices
 softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 5855e99..109364b 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -24,6 +24,7 @@ config SIFIVE_U
     select HART
     select SIFIVE
     select SIFIVE_PDMA
+    select SIFIVE_U_PRCI
     select UNIMP
 
 config SPIKE
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index d73ea99..e6c8af0 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
  2020-09-03 10:40 ` [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc Bin Meng
  2020-09-03 10:40 ` [PATCH 02/12] hw/riscv: Move sifive_u_prci " Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:26     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio Bin Meng
                   ` (10 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => misc}/sifive_u_otp.h | 0
 include/hw/riscv/sifive_u.h               | 2 +-
 hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
 hw/misc/Kconfig                           | 3 +++
 hw/misc/meson.build                       | 1 +
 hw/riscv/Kconfig                          | 1 +
 hw/riscv/meson.build                      | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)

diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
similarity index 100%
rename from include/hw/riscv/sifive_u_otp.h
rename to include/hw/misc/sifive_u_otp.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index cbeb228..936a3bd 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -24,7 +24,7 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
similarity index 99%
rename from hw/riscv/sifive_u_otp.c
rename to hw/misc/sifive_u_otp.c
index f6ecbaa..c2f3c8e 100644
--- a/hw/riscv/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -23,7 +23,7 @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
 
 static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 65f3fdd..fa3d0f4 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -137,6 +137,9 @@ config AVR_POWER
 config SIFIVE_E_PRCI
     bool
 
+config SIFIVE_U_OTP
+    bool
+
 config SIFIVE_U_PRCI
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 9e9550e..018a88c 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
 # PKUnity SoC devices
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 109364b..76eaf77 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -24,6 +24,7 @@ config SIFIVE_U
     select HART
     select SIFIVE
     select SIFIVE_PDMA
+    select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
 
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index e6c8af0..2ba4757 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (2 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 03/12] hw/riscv: Move sifive_u_otp " Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:28     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc Bin Meng
                   ` (9 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.

Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/trace.h                         | 1 -
 include/hw/{riscv => gpio}/sifive_gpio.h | 0
 include/hw/riscv/sifive_e.h              | 2 +-
 include/hw/riscv/sifive_u.h              | 2 +-
 hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
 hw/gpio/Kconfig                          | 3 +++
 hw/gpio/meson.build                      | 1 +
 hw/gpio/trace-events                     | 6 ++++++
 hw/riscv/Kconfig                         | 2 ++
 hw/riscv/meson.build                     | 1 -
 hw/riscv/trace-events                    | 7 -------
 meson.build                              | 1 -
 12 files changed, 15 insertions(+), 13 deletions(-)
 delete mode 100644 hw/riscv/trace.h
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 delete mode 100644 hw/riscv/trace-events

diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
deleted file mode 100644
index 8c0e3ca..0000000
--- a/hw/riscv/trace.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "trace/trace-hw_riscv.h"
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
similarity index 100%
rename from include/hw/riscv/sifive_gpio.h
rename to include/hw/gpio/sifive_gpio.h
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 6374141..b140084 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -21,7 +21,7 @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
 #define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 936a3bd..fe5c580 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -23,7 +23,7 @@
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
 
diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
similarity index 99%
rename from hw/riscv/sifive_gpio.c
rename to hw/gpio/sifive_gpio.c
index aac6b44..78bf29e 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/gpio/sifive_gpio.c
@@ -15,7 +15,7 @@
 #include "qemu/log.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "migration/vmstate.h"
 #include "trace.h"
 
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index 9227cb5..b6fdaa2 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -7,3 +7,6 @@ config PL061
 
 config GPIO_KEY
     bool
+
+config SIFIVE_GPIO
+    bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 6bcdfa6..86cae9a 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index c1271fd..6e3f048 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
 nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+
+# sifive_gpio.c
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 76eaf77..5a8335b 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_GPIO
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -23,6 +24,7 @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 2ba4757..24177ef 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
deleted file mode 100644
index 6d59233..0000000
--- a/hw/riscv/trace-events
+++ /dev/null
@@ -1,7 +0,0 @@
-# See docs/devel/tracing.txt for syntax documentation.
-
-# hw/gpio/sifive_gpio.c
-sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
-sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/meson.build b/meson.build
index 1e7aee8..66bbb75 100644
--- a/meson.build
+++ b/meson.build
@@ -706,7 +706,6 @@ if have_system
     'hw/watchdog',
     'hw/xen',
     'hw/gpio',
-    'hw/riscv',
     'migration',
     'net',
     'ui',
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (3 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:30     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 06/12] hw/riscv: Move sifive_plic " Bin Meng
                   ` (8 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => intc}/sifive_clint.h | 0
 hw/{riscv => intc}/sifive_clint.c         | 2 +-
 hw/riscv/microchip_pfsoc.c                | 2 +-
 hw/riscv/sifive_e.c                       | 2 +-
 hw/riscv/sifive_u.c                       | 2 +-
 hw/riscv/spike.c                          | 2 +-
 hw/riscv/virt.c                           | 2 +-
 hw/intc/Kconfig                           | 3 +++
 hw/intc/meson.build                       | 1 +
 hw/riscv/Kconfig                          | 5 +++++
 hw/riscv/meson.build                      | 1 -
 11 files changed, 15 insertions(+), 7 deletions(-)
 rename include/hw/{riscv => intc}/sifive_clint.h (100%)
 rename hw/{riscv => intc}/sifive_clint.c (99%)

diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
similarity index 100%
rename from include/hw/riscv/sifive_clint.h
rename to include/hw/intc/sifive_clint.h
diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
similarity index 99%
rename from hw/riscv/sifive_clint.c
rename to hw/intc/sifive_clint.c
index fa1ddf2..0f41e5e 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/intc/sifive_clint.c
@@ -26,7 +26,7 @@
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
 #include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_clint.h"
+#include "hw/intc/sifive_clint.h"
 #include "qemu/timer.h"
 
 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index da6bd29..131eea1 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -48,9 +48,9 @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
+#include "hw/intc/sifive_clint.h"
 #include "sysemu/sysemu.h"
 
 /*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7f43ed9..3bdb16e 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,10 +40,10 @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
 #include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7997537..7187d1a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -47,10 +47,10 @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "net/eth.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b54a396..59d9d87 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -33,10 +33,10 @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_htif.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c67a910..bce2020 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -31,11 +31,11 @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 2ae1e89..f499d0f 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -67,3 +67,6 @@ config RX_ICU
 
 config LOONGSON_LIOINTC
     bool
+
+config SIFIVE_CLINT
+    bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index c16f7f0..1e20daa 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
 specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 5a8335b..f8bb7e7 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_E_PRCI
     select UNIMP
@@ -24,6 +25,7 @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_U_OTP
@@ -35,6 +37,7 @@ config SPIKE
     select HART
     select HTIF
     select SIFIVE
+    select SIFIVE_CLINT
 
 config OPENTITAN
     bool
@@ -54,11 +57,13 @@ config RISCV_VIRT
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
     select SIFIVE
+    select SIFIVE_CLINT
 
 config MICROCHIP_PFSOC
     bool
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select UNIMP
     select MCHP_PFSOC_MMUART
     select SIFIVE_PDMA
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 24177ef..ea72178 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (4 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:34     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char Bin Meng
                   ` (7 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 {include/hw/riscv => hw/intc}/sifive_plic.h | 0
 hw/{riscv => intc}/sifive_plic.c            | 2 +-
 hw/riscv/microchip_pfsoc.c                  | 2 +-
 hw/riscv/sifive_e.c                         | 2 +-
 hw/riscv/sifive_u.c                         | 2 +-
 hw/riscv/virt.c                             | 2 +-
 hw/intc/Kconfig                             | 3 +++
 hw/intc/meson.build                         | 1 +
 hw/riscv/Kconfig                            | 5 +++++
 hw/riscv/meson.build                        | 1 -
 10 files changed, 14 insertions(+), 6 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)

diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
similarity index 100%
rename from include/hw/riscv/sifive_plic.h
rename to hw/intc/sifive_plic.h
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
similarity index 99%
rename from hw/riscv/sifive_plic.c
rename to hw/intc/sifive_plic.c
index 11ef147..af611f8 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -27,9 +27,9 @@
 #include "hw/pci/msi.h"
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
+#include "hw/intc/sifive_plic.h"
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
-#include "hw/riscv/sifive_plic.h"
 
 #define RISCV_DEBUG_PLIC 0
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 131eea1..4627179 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -48,9 +48,9 @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "sysemu/sysemu.h"
 
 /*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 3bdb16e..0ddcf15 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -39,11 +39,11 @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7187d1a..faca2e8 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -46,11 +46,11 @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
 #include "net/eth.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bce2020..0caab8e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,12 +30,12 @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index f499d0f..d079540 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
 
 config SIFIVE_CLINT
     bool
+
+config SIFIVE_PLIC
+    bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 1e20daa..3f82cc2 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
 specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
 specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index f8bb7e7..23b7027 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -17,6 +17,7 @@ config SIFIVE_E
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
+    select SIFIVE_PLIC
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -28,6 +29,7 @@ config SIFIVE_U
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
+    select SIFIVE_PLIC
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
@@ -38,6 +40,7 @@ config SPIKE
     select HTIF
     select SIFIVE
     select SIFIVE_CLINT
+    select SIFIVE_PLIC
 
 config OPENTITAN
     bool
@@ -58,6 +61,7 @@ config RISCV_VIRT
     select PFLASH_CFI01
     select SIFIVE
     select SIFIVE_CLINT
+    select SIFIVE_PLIC
 
 config MICROCHIP_PFSOC
     bool
@@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
     select UNIMP
     select MCHP_PFSOC_MMUART
     select SIFIVE_PDMA
+    select SIFIVE_PLIC
     select CADENCE_SDHCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index ea72178..535a142 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (5 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 06/12] hw/riscv: Move sifive_plic " Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:36     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 08/12] hw/riscv: Move sifive_uart " Bin Meng
                   ` (6 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => char}/riscv_htif.h | 0
 hw/{riscv => char}/riscv_htif.c         | 2 +-
 hw/riscv/spike.c                        | 2 +-
 hw/char/Kconfig                         | 3 +++
 hw/char/meson.build                     | 1 +
 hw/riscv/Kconfig                        | 3 ---
 hw/riscv/meson.build                    | 1 -
 7 files changed, 6 insertions(+), 6 deletions(-)
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename hw/{riscv => char}/riscv_htif.c (99%)

diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
similarity index 100%
rename from include/hw/riscv/riscv_htif.h
rename to include/hw/char/riscv_htif.h
diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
similarity index 99%
rename from hw/riscv/riscv_htif.c
rename to hw/char/riscv_htif.c
index ca87a5c..ba1af1c 100644
--- a/hw/riscv/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -24,10 +24,10 @@
 #include "qapi/error.h"
 #include "qemu/log.h"
 #include "hw/sysbus.h"
+#include "hw/char/riscv_htif.h"
 #include "hw/char/serial.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
-#include "hw/riscv/riscv_htif.h"
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 59d9d87..3fd152a 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -31,11 +31,11 @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
-#include "hw/riscv/riscv_htif.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/char/riscv_htif.h"
 #include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 1d64555..91da92f 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -1,6 +1,9 @@
 config ESCC
     bool
 
+config HTIF
+    bool
+
 config PARALLEL
     bool
     default y
diff --git a/hw/char/meson.build b/hw/char/meson.build
index ae27932..3db623e 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 
+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
 specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 23b7027..a0e256c 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,6 +1,3 @@
-config HTIF
-    bool
-
 config HART
     bool
 
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 535a142..619bf80 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (6 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:36     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc Bin Meng
                   ` (5 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => char}/sifive_uart.h | 0
 hw/{riscv => char}/sifive_uart.c         | 2 +-
 hw/riscv/sifive_e.c                      | 2 +-
 hw/riscv/sifive_u.c                      | 2 +-
 hw/char/Kconfig                          | 3 +++
 hw/char/meson.build                      | 1 +
 hw/riscv/Kconfig                         | 2 ++
 hw/riscv/meson.build                     | 1 -
 8 files changed, 9 insertions(+), 4 deletions(-)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 rename hw/{riscv => char}/sifive_uart.c (99%)

diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
similarity index 100%
rename from include/hw/riscv/sifive_uart.h
rename to include/hw/char/sifive_uart.h
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
similarity index 99%
rename from hw/riscv/sifive_uart.c
rename to hw/char/sifive_uart.c
index 9350482..3a00ba7 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -24,7 +24,7 @@
 #include "chardev/char-fe.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
-#include "hw/riscv/sifive_uart.h"
+#include "hw/char/sifive_uart.h"
 
 /*
  * Not yet implemented:
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 0ddcf15..40bbf53 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -39,9 +39,9 @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_e_prci.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index faca2e8..4f12a93 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -46,9 +46,9 @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 91da92f..939bc44 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -58,3 +58,6 @@ config AVR_USART
 
 config MCHP_PFSOC_MMUART
     bool
+
+config SIFIVE_UART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 3db623e..196ac91 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
 softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
 softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a0e256c..a046157 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PLIC
+    select SIFIVE_UART
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -27,6 +28,7 @@ config SIFIVE_U
     select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
+    select SIFIVE_UART
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 619bf80..da32148 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (7 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 08/12] hw/riscv: Move sifive_uart " Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:41     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 10/12] hw/riscv: Always build riscv_hart.c Bin Meng
                   ` (4 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 include/hw/{riscv => misc}/sifive_test.h | 0
 hw/{riscv => misc}/sifive_test.c         | 2 +-
 hw/riscv/virt.c                          | 2 +-
 hw/misc/Kconfig                          | 3 +++
 hw/misc/meson.build                      | 1 +
 hw/riscv/Kconfig                         | 1 +
 hw/riscv/meson.build                     | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename hw/{riscv => misc}/sifive_test.c (98%)

diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
similarity index 100%
rename from include/hw/riscv/sifive_test.h
rename to include/hw/misc/sifive_test.h
diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
similarity index 98%
rename from hw/riscv/sifive_test.c
rename to hw/misc/sifive_test.c
index 0c78fb2..45d9399 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/misc/sifive_test.c
@@ -25,7 +25,7 @@
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_test.h"
+#include "hw/misc/sifive_test.h"
 
 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0caab8e..41bd2f3 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -30,12 +30,12 @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index fa3d0f4..3185456 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,6 +134,9 @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_TEST
+    bool
+
 config SIFIVE_E_PRCI
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 018a88c..bd24132 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a046157..8e07100 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -61,6 +61,7 @@ config RISCV_VIRT
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_PLIC
+    select SIFIVE_TEST
 
 config MICROCHIP_PFSOC
     bool
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index da32148..3cf9380 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 10/12] hw/riscv: Always build riscv_hart.c
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (8 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:42     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE Bin Meng
                   ` (3 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/Kconfig     | 9 ---------
 hw/riscv/meson.build | 2 +-
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8e07100..7d017bc 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,6 +1,3 @@
-config HART
-    bool
-
 config IBEX
     bool
 
@@ -10,7 +7,6 @@ config SIFIVE
 
 config SIFIVE_E
     bool
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
@@ -22,7 +18,6 @@ config SIFIVE_E
 config SIFIVE_U
     bool
     select CADENCE
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
@@ -35,7 +30,6 @@ config SIFIVE_U
 
 config SPIKE
     bool
-    select HART
     select HTIF
     select SIFIVE
     select SIFIVE_CLINT
@@ -44,7 +38,6 @@ config SPIKE
 config OPENTITAN
     bool
     select IBEX
-    select HART
     select UNIMP
 
 config RISCV_VIRT
@@ -52,7 +45,6 @@ config RISCV_VIRT
     imply PCI_DEVICES
     imply TEST_DEVICES
     select PCI
-    select HART
     select SERIAL
     select GOLDFISH_RTC
     select VIRTIO_MMIO
@@ -65,7 +57,6 @@ config RISCV_VIRT
 
 config MICROCHIP_PFSOC
     bool
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 3cf9380..dbedf9b 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -1,7 +1,7 @@
 riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'))
 riscv_ss.add(files('numa.c'))
-riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
+riscv_ss.add(files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (9 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 10/12] hw/riscv: Always build riscv_hart.c Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:42     ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order Bin Meng
                   ` (2 subsequent siblings)
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/Kconfig | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 7d017bc..e152fdc 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,13 +1,9 @@
 config IBEX
     bool
 
-config SIFIVE
-    bool
-    select MSI_NONBROKEN
-
 config SIFIVE_E
     bool
-    select SIFIVE
+    select MSI_NONBROKEN
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PLIC
@@ -18,7 +14,7 @@ config SIFIVE_E
 config SIFIVE_U
     bool
     select CADENCE
-    select SIFIVE
+    select MSI_NONBROKEN
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
@@ -31,7 +27,7 @@ config SIFIVE_U
 config SPIKE
     bool
     select HTIF
-    select SIFIVE
+    select MSI_NONBROKEN
     select SIFIVE_CLINT
     select SIFIVE_PLIC
 
@@ -44,20 +40,20 @@ config RISCV_VIRT
     bool
     imply PCI_DEVICES
     imply TEST_DEVICES
+    select MSI_NONBROKEN
     select PCI
     select SERIAL
     select GOLDFISH_RTC
     select VIRTIO_MMIO
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
-    select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_PLIC
     select SIFIVE_TEST
 
 config MICROCHIP_PFSOC
     bool
-    select SIFIVE
+    select MSI_NONBROKEN
     select SIFIVE_CLINT
     select UNIMP
     select MCHP_PFSOC_MMUART
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
                   ` (10 preceding siblings ...)
  2020-09-03 10:40 ` [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE Bin Meng
@ 2020-09-03 10:40 ` Bin Meng
  2020-09-04 17:44     ` Alistair Francis
  2020-09-03 10:56   ` Peter Maydell
  2020-09-06 16:05   ` Alistair Francis
  13 siblings, 1 reply; 41+ messages in thread
From: Bin Meng @ 2020-09-03 10:40 UTC (permalink / raw)
  To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng

From: Bin Meng <bin.meng@windriver.com>

At present the Kconfig file is in disorder. Let's sort the options.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

---

 hw/riscv/Kconfig | 58 ++++++++++++++++++++++++++++----------------------------
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index e152fdc..2df978f 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -1,36 +1,16 @@
 config IBEX
     bool
 
-config SIFIVE_E
-    bool
-    select MSI_NONBROKEN
-    select SIFIVE_CLINT
-    select SIFIVE_GPIO
-    select SIFIVE_PLIC
-    select SIFIVE_UART
-    select SIFIVE_E_PRCI
-    select UNIMP
-
-config SIFIVE_U
+config MICROCHIP_PFSOC
     bool
-    select CADENCE
+    select CADENCE_SDHCI
+    select MCHP_PFSOC_MMUART
     select MSI_NONBROKEN
     select SIFIVE_CLINT
-    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
-    select SIFIVE_UART
-    select SIFIVE_U_OTP
-    select SIFIVE_U_PRCI
     select UNIMP
 
-config SPIKE
-    bool
-    select HTIF
-    select MSI_NONBROKEN
-    select SIFIVE_CLINT
-    select SIFIVE_PLIC
-
 config OPENTITAN
     bool
     select IBEX
@@ -40,23 +20,43 @@ config RISCV_VIRT
     bool
     imply PCI_DEVICES
     imply TEST_DEVICES
+    select GOLDFISH_RTC
     select MSI_NONBROKEN
     select PCI
-    select SERIAL
-    select GOLDFISH_RTC
-    select VIRTIO_MMIO
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
+    select SERIAL
     select SIFIVE_CLINT
     select SIFIVE_PLIC
     select SIFIVE_TEST
+    select VIRTIO_MMIO
 
-config MICROCHIP_PFSOC
+config SIFIVE_E
     bool
     select MSI_NONBROKEN
     select SIFIVE_CLINT
+    select SIFIVE_GPIO
+    select SIFIVE_PLIC
+    select SIFIVE_UART
+    select SIFIVE_E_PRCI
     select UNIMP
-    select MCHP_PFSOC_MMUART
+
+config SIFIVE_U
+    bool
+    select CADENCE
+    select MSI_NONBROKEN
+    select SIFIVE_CLINT
+    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
-    select CADENCE_SDHCI
+    select SIFIVE_UART
+    select SIFIVE_U_OTP
+    select SIFIVE_U_PRCI
+    select UNIMP
+
+config SPIKE
+    bool
+    select HTIF
+    select MSI_NONBROKEN
+    select SIFIVE_CLINT
+    select SIFIVE_PLIC
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] hw/riscv: Clean up the directory
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
@ 2020-09-03 10:56   ` Peter Maydell
  2020-09-03 10:40 ` [PATCH 02/12] hw/riscv: Move sifive_u_prci " Bin Meng
                     ` (12 subsequent siblings)
  13 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2020-09-03 10:56 UTC (permalink / raw)
  To: Bin Meng; +Cc: open list:RISC-V, Bin Meng, Alistair Francis, QEMU Developers

On Thu, 3 Sep 2020 at 11:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Peripheral models for a specific SoC are moved to its
> corresponding hw/* subdirectories.

Ah, thanks for taking on this cleanup -- it's been something
that was unfortunately missed in code review for the initial
riscv work that we never got round to fixing later, so it's
nice to see things being moved into their proper places.

thanks
-- PMM


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] hw/riscv: Clean up the directory
@ 2020-09-03 10:56   ` Peter Maydell
  0 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2020-09-03 10:56 UTC (permalink / raw)
  To: Bin Meng; +Cc: Alistair Francis, QEMU Developers, open list:RISC-V, Bin Meng

On Thu, 3 Sep 2020 at 11:42, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Peripheral models for a specific SoC are moved to its
> corresponding hw/* subdirectories.

Ah, thanks for taking on this cleanup -- it's been something
that was unfortunately missed in code review for the initial
riscv work that we never got round to fixing later, so it's
nice to see things being moved into their proper places.

thanks
-- PMM


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc
  2020-09-03 10:40 ` [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc Bin Meng
@ 2020-09-04 17:24     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:24 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_e_prci model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_e_prci.h | 0
>  hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
>  hw/riscv/sifive_e.c                        | 2 +-
>  hw/misc/Kconfig                            | 3 +++
>  hw/misc/meson.build                        | 3 +++
>  hw/riscv/Kconfig                           | 1 +
>  hw/riscv/meson.build                       | 1 -
>  7 files changed, 9 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
>  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
>
> diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
> similarity index 100%
> rename from include/hw/riscv/sifive_e_prci.h
> rename to include/hw/misc/sifive_e_prci.h
> diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
> similarity index 99%
> rename from hw/riscv/sifive_e_prci.c
> rename to hw/misc/sifive_e_prci.c
> index 17dfa74..8ec4ee4 100644
> --- a/hw/riscv/sifive_e_prci.c
> +++ b/hw/misc/sifive_e_prci.c
> @@ -24,7 +24,7 @@
>  #include "qemu/log.h"
>  #include "qemu/module.h"
>  #include "hw/hw.h"
> -#include "hw/riscv/sifive_e_prci.h"
> +#include "hw/misc/sifive_e_prci.h"
>
>  static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 36ccfb2..7f43ed9 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -43,8 +43,8 @@
>  #include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
> -#include "hw/riscv/sifive_e_prci.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/sysemu.h"
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 92c397c..5073986 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -134,4 +134,7 @@ config MAC_VIA
>  config AVR_POWER
>      bool
>
> +config SIFIVE_E_PRCI
> +    bool
> +
>  source macio/Kconfig
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index e1576b8..b6b2e57 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>  # Mac devices
>  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
> +# RISC-V devices
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> +
>  # PKUnity SoC devices
>  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index e53ab1e..5855e99 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_E_PRCI
>      select UNIMP
>
>  config SIFIVE_U
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index cf1aa99..d73ea99 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc
@ 2020-09-04 17:24     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:24 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_e_prci model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_e_prci.h | 0
>  hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
>  hw/riscv/sifive_e.c                        | 2 +-
>  hw/misc/Kconfig                            | 3 +++
>  hw/misc/meson.build                        | 3 +++
>  hw/riscv/Kconfig                           | 1 +
>  hw/riscv/meson.build                       | 1 -
>  7 files changed, 9 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
>  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
>
> diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
> similarity index 100%
> rename from include/hw/riscv/sifive_e_prci.h
> rename to include/hw/misc/sifive_e_prci.h
> diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
> similarity index 99%
> rename from hw/riscv/sifive_e_prci.c
> rename to hw/misc/sifive_e_prci.c
> index 17dfa74..8ec4ee4 100644
> --- a/hw/riscv/sifive_e_prci.c
> +++ b/hw/misc/sifive_e_prci.c
> @@ -24,7 +24,7 @@
>  #include "qemu/log.h"
>  #include "qemu/module.h"
>  #include "hw/hw.h"
> -#include "hw/riscv/sifive_e_prci.h"
> +#include "hw/misc/sifive_e_prci.h"
>
>  static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 36ccfb2..7f43ed9 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -43,8 +43,8 @@
>  #include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
> -#include "hw/riscv/sifive_e_prci.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/sysemu.h"
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 92c397c..5073986 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -134,4 +134,7 @@ config MAC_VIA
>  config AVR_POWER
>      bool
>
> +config SIFIVE_E_PRCI
> +    bool
> +
>  source macio/Kconfig
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index e1576b8..b6b2e57 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>  # Mac devices
>  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
> +# RISC-V devices
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> +
>  # PKUnity SoC devices
>  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index e53ab1e..5855e99 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_E_PRCI
>      select UNIMP
>
>  config SIFIVE_U
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index cf1aa99..d73ea99 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc
  2020-09-03 10:40 ` [PATCH 02/12] hw/riscv: Move sifive_u_prci " Bin Meng
@ 2020-09-04 17:25     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:25 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_u_prci model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_u_prci.h | 0
>  include/hw/riscv/sifive_u.h                | 2 +-
>  hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
>  hw/misc/Kconfig                            | 3 +++
>  hw/misc/meson.build                        | 1 +
>  hw/riscv/Kconfig                           | 1 +
>  hw/riscv/meson.build                       | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
>  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
>
> diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
> similarity index 100%
> rename from include/hw/riscv/sifive_u_prci.h
> rename to include/hw/misc/sifive_u_prci.h
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 793000a..cbeb228 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,8 +24,8 @@
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
>  #include "hw/riscv/sifive_gpio.h"
> -#include "hw/riscv/sifive_u_prci.h"
>  #include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_prci.h"
>
>  #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
>  #define RISCV_U_SOC(obj) \
> diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
> similarity index 99%
> rename from hw/riscv/sifive_u_prci.c
> rename to hw/misc/sifive_u_prci.c
> index 4fa590c..5d9d446 100644
> --- a/hw/riscv/sifive_u_prci.c
> +++ b/hw/misc/sifive_u_prci.c
> @@ -22,7 +22,7 @@
>  #include "hw/sysbus.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> -#include "hw/riscv/sifive_u_prci.h"
> +#include "hw/misc/sifive_u_prci.h"
>
>  static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 5073986..65f3fdd 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,4 +137,7 @@ config AVR_POWER
>  config SIFIVE_E_PRCI
>      bool
>
> +config SIFIVE_U_PRCI
> +    bool
> +
>  source macio/Kconfig
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index b6b2e57..9e9550e 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
>
>  # PKUnity SoC devices
>  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 5855e99..109364b 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -24,6 +24,7 @@ config SIFIVE_U
>      select HART
>      select SIFIVE
>      select SIFIVE_PDMA
> +    select SIFIVE_U_PRCI
>      select UNIMP
>
>  config SPIKE
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index d73ea99..e6c8af0 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc
@ 2020-09-04 17:25     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:25 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_u_prci model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_u_prci.h | 0
>  include/hw/riscv/sifive_u.h                | 2 +-
>  hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
>  hw/misc/Kconfig                            | 3 +++
>  hw/misc/meson.build                        | 1 +
>  hw/riscv/Kconfig                           | 1 +
>  hw/riscv/meson.build                       | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
>  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
>
> diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
> similarity index 100%
> rename from include/hw/riscv/sifive_u_prci.h
> rename to include/hw/misc/sifive_u_prci.h
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 793000a..cbeb228 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,8 +24,8 @@
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
>  #include "hw/riscv/sifive_gpio.h"
> -#include "hw/riscv/sifive_u_prci.h"
>  #include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_prci.h"
>
>  #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
>  #define RISCV_U_SOC(obj) \
> diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
> similarity index 99%
> rename from hw/riscv/sifive_u_prci.c
> rename to hw/misc/sifive_u_prci.c
> index 4fa590c..5d9d446 100644
> --- a/hw/riscv/sifive_u_prci.c
> +++ b/hw/misc/sifive_u_prci.c
> @@ -22,7 +22,7 @@
>  #include "hw/sysbus.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> -#include "hw/riscv/sifive_u_prci.h"
> +#include "hw/misc/sifive_u_prci.h"
>
>  static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 5073986..65f3fdd 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,4 +137,7 @@ config AVR_POWER
>  config SIFIVE_E_PRCI
>      bool
>
> +config SIFIVE_U_PRCI
> +    bool
> +
>  source macio/Kconfig
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index b6b2e57..9e9550e 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
>
>  # PKUnity SoC devices
>  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 5855e99..109364b 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -24,6 +24,7 @@ config SIFIVE_U
>      select HART
>      select SIFIVE
>      select SIFIVE_PDMA
> +    select SIFIVE_U_PRCI
>      select UNIMP
>
>  config SPIKE
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index d73ea99..e6c8af0 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc
  2020-09-03 10:40 ` [PATCH 03/12] hw/riscv: Move sifive_u_otp " Bin Meng
@ 2020-09-04 17:26     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:26 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_u_otp model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_u_otp.h | 0
>  include/hw/riscv/sifive_u.h               | 2 +-
>  hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
>  hw/misc/Kconfig                           | 3 +++
>  hw/misc/meson.build                       | 1 +
>  hw/riscv/Kconfig                          | 1 +
>  hw/riscv/meson.build                      | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
>  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
>
> diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
> similarity index 100%
> rename from include/hw/riscv/sifive_u_otp.h
> rename to include/hw/misc/sifive_u_otp.h
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index cbeb228..936a3bd 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,7 +24,7 @@
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
>  #include "hw/riscv/sifive_gpio.h"
> -#include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_otp.h"
>  #include "hw/misc/sifive_u_prci.h"
>
>  #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
> diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
> similarity index 99%
> rename from hw/riscv/sifive_u_otp.c
> rename to hw/misc/sifive_u_otp.c
> index f6ecbaa..c2f3c8e 100644
> --- a/hw/riscv/sifive_u_otp.c
> +++ b/hw/misc/sifive_u_otp.c
> @@ -23,7 +23,7 @@
>  #include "hw/sysbus.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> -#include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_otp.h"
>
>  static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 65f3fdd..fa3d0f4 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,6 +137,9 @@ config AVR_POWER
>  config SIFIVE_E_PRCI
>      bool
>
> +config SIFIVE_U_OTP
> +    bool
> +
>  config SIFIVE_U_PRCI
>      bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 9e9550e..018a88c 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
>
>  # PKUnity SoC devices
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 109364b..76eaf77 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -24,6 +24,7 @@ config SIFIVE_U
>      select HART
>      select SIFIVE
>      select SIFIVE_PDMA
> +    select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
>
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index e6c8af0..2ba4757 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc
@ 2020-09-04 17:26     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:26 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_u_otp model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_u_otp.h | 0
>  include/hw/riscv/sifive_u.h               | 2 +-
>  hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
>  hw/misc/Kconfig                           | 3 +++
>  hw/misc/meson.build                       | 1 +
>  hw/riscv/Kconfig                          | 1 +
>  hw/riscv/meson.build                      | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
>  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
>
> diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
> similarity index 100%
> rename from include/hw/riscv/sifive_u_otp.h
> rename to include/hw/misc/sifive_u_otp.h
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index cbeb228..936a3bd 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -24,7 +24,7 @@
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
>  #include "hw/riscv/sifive_gpio.h"
> -#include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_otp.h"
>  #include "hw/misc/sifive_u_prci.h"
>
>  #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
> diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
> similarity index 99%
> rename from hw/riscv/sifive_u_otp.c
> rename to hw/misc/sifive_u_otp.c
> index f6ecbaa..c2f3c8e 100644
> --- a/hw/riscv/sifive_u_otp.c
> +++ b/hw/misc/sifive_u_otp.c
> @@ -23,7 +23,7 @@
>  #include "hw/sysbus.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> -#include "hw/riscv/sifive_u_otp.h"
> +#include "hw/misc/sifive_u_otp.h"
>
>  static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 65f3fdd..fa3d0f4 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,6 +137,9 @@ config AVR_POWER
>  config SIFIVE_E_PRCI
>      bool
>
> +config SIFIVE_U_OTP
> +    bool
> +
>  config SIFIVE_U_PRCI
>      bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 9e9550e..018a88c 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
>
>  # PKUnity SoC devices
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 109364b..76eaf77 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -24,6 +24,7 @@ config SIFIVE_U
>      select HART
>      select SIFIVE
>      select SIFIVE_PDMA
> +    select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
>
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index e6c8af0..2ba4757 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio
  2020-09-03 10:40 ` [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio Bin Meng
@ 2020-09-04 17:28     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:28 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_gpio model to hw/gpio directory.
>
> Note this also removes the trace-events in the hw/riscv directory,
> since gpio is the only supported trace target in that directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/trace.h                         | 1 -
>  include/hw/{riscv => gpio}/sifive_gpio.h | 0
>  include/hw/riscv/sifive_e.h              | 2 +-
>  include/hw/riscv/sifive_u.h              | 2 +-
>  hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
>  hw/gpio/Kconfig                          | 3 +++
>  hw/gpio/meson.build                      | 1 +
>  hw/gpio/trace-events                     | 6 ++++++
>  hw/riscv/Kconfig                         | 2 ++
>  hw/riscv/meson.build                     | 1 -
>  hw/riscv/trace-events                    | 7 -------
>  meson.build                              | 1 -
>  12 files changed, 15 insertions(+), 13 deletions(-)
>  delete mode 100644 hw/riscv/trace.h
>  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
>  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
>  delete mode 100644 hw/riscv/trace-events
>
> diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
> deleted file mode 100644
> index 8c0e3ca..0000000
> --- a/hw/riscv/trace.h
> +++ /dev/null
> @@ -1 +0,0 @@
> -#include "trace/trace-hw_riscv.h"
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
> similarity index 100%
> rename from include/hw/riscv/sifive_gpio.h
> rename to include/hw/gpio/sifive_gpio.h
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 6374141..b140084 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -21,7 +21,7 @@
>
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
> -#include "hw/riscv/sifive_gpio.h"
> +#include "hw/gpio/sifive_gpio.h"
>
>  #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
>  #define RISCV_E_SOC(obj) \
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 936a3bd..fe5c580 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -23,7 +23,7 @@
>  #include "hw/net/cadence_gem.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
> -#include "hw/riscv/sifive_gpio.h"
> +#include "hw/gpio/sifive_gpio.h"
>  #include "hw/misc/sifive_u_otp.h"
>  #include "hw/misc/sifive_u_prci.h"
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
> similarity index 99%
> rename from hw/riscv/sifive_gpio.c
> rename to hw/gpio/sifive_gpio.c
> index aac6b44..78bf29e 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/gpio/sifive_gpio.c
> @@ -15,7 +15,7 @@
>  #include "qemu/log.h"
>  #include "hw/irq.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/riscv/sifive_gpio.h"
> +#include "hw/gpio/sifive_gpio.h"
>  #include "migration/vmstate.h"
>  #include "trace.h"
>
> diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
> index 9227cb5..b6fdaa2 100644
> --- a/hw/gpio/Kconfig
> +++ b/hw/gpio/Kconfig
> @@ -7,3 +7,6 @@ config PL061
>
>  config GPIO_KEY
>      bool
> +
> +config SIFIVE_GPIO
> +    bool
> diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
> index 6bcdfa6..86cae9a 100644
> --- a/hw/gpio/meson.build
> +++ b/hw/gpio/meson.build
> @@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
> diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
> index c1271fd..6e3f048 100644
> --- a/hw/gpio/trace-events
> +++ b/hw/gpio/trace-events
> @@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
>  nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
>  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
>  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> +
> +# sifive_gpio.c
> +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
> +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
> +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 76eaf77..5a8335b 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_GPIO
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -23,6 +24,7 @@ config SIFIVE_U
>      select CADENCE
>      select HART
>      select SIFIVE
> +    select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 2ba4757..24177ef 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
> diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
> deleted file mode 100644
> index 6d59233..0000000
> --- a/hw/riscv/trace-events
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# See docs/devel/tracing.txt for syntax documentation.
> -
> -# hw/gpio/sifive_gpio.c
> -sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
> -sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
> -sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> -sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> diff --git a/meson.build b/meson.build
> index 1e7aee8..66bbb75 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -706,7 +706,6 @@ if have_system
>      'hw/watchdog',
>      'hw/xen',
>      'hw/gpio',
> -    'hw/riscv',
>      'migration',
>      'net',
>      'ui',
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio
@ 2020-09-04 17:28     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:28 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_gpio model to hw/gpio directory.
>
> Note this also removes the trace-events in the hw/riscv directory,
> since gpio is the only supported trace target in that directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/trace.h                         | 1 -
>  include/hw/{riscv => gpio}/sifive_gpio.h | 0
>  include/hw/riscv/sifive_e.h              | 2 +-
>  include/hw/riscv/sifive_u.h              | 2 +-
>  hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
>  hw/gpio/Kconfig                          | 3 +++
>  hw/gpio/meson.build                      | 1 +
>  hw/gpio/trace-events                     | 6 ++++++
>  hw/riscv/Kconfig                         | 2 ++
>  hw/riscv/meson.build                     | 1 -
>  hw/riscv/trace-events                    | 7 -------
>  meson.build                              | 1 -
>  12 files changed, 15 insertions(+), 13 deletions(-)
>  delete mode 100644 hw/riscv/trace.h
>  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
>  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
>  delete mode 100644 hw/riscv/trace-events
>
> diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
> deleted file mode 100644
> index 8c0e3ca..0000000
> --- a/hw/riscv/trace.h
> +++ /dev/null
> @@ -1 +0,0 @@
> -#include "trace/trace-hw_riscv.h"
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
> similarity index 100%
> rename from include/hw/riscv/sifive_gpio.h
> rename to include/hw/gpio/sifive_gpio.h
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 6374141..b140084 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -21,7 +21,7 @@
>
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
> -#include "hw/riscv/sifive_gpio.h"
> +#include "hw/gpio/sifive_gpio.h"
>
>  #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
>  #define RISCV_E_SOC(obj) \
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 936a3bd..fe5c580 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -23,7 +23,7 @@
>  #include "hw/net/cadence_gem.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_cpu.h"
> -#include "hw/riscv/sifive_gpio.h"
> +#include "hw/gpio/sifive_gpio.h"
>  #include "hw/misc/sifive_u_otp.h"
>  #include "hw/misc/sifive_u_prci.h"
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
> similarity index 99%
> rename from hw/riscv/sifive_gpio.c
> rename to hw/gpio/sifive_gpio.c
> index aac6b44..78bf29e 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/gpio/sifive_gpio.c
> @@ -15,7 +15,7 @@
>  #include "qemu/log.h"
>  #include "hw/irq.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/riscv/sifive_gpio.h"
> +#include "hw/gpio/sifive_gpio.h"
>  #include "migration/vmstate.h"
>  #include "trace.h"
>
> diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
> index 9227cb5..b6fdaa2 100644
> --- a/hw/gpio/Kconfig
> +++ b/hw/gpio/Kconfig
> @@ -7,3 +7,6 @@ config PL061
>
>  config GPIO_KEY
>      bool
> +
> +config SIFIVE_GPIO
> +    bool
> diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
> index 6bcdfa6..86cae9a 100644
> --- a/hw/gpio/meson.build
> +++ b/hw/gpio/meson.build
> @@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
>  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
> diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
> index c1271fd..6e3f048 100644
> --- a/hw/gpio/trace-events
> +++ b/hw/gpio/trace-events
> @@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
>  nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
>  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
>  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> +
> +# sifive_gpio.c
> +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
> +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
> +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 76eaf77..5a8335b 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_GPIO
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -23,6 +24,7 @@ config SIFIVE_U
>      select CADENCE
>      select HART
>      select SIFIVE
> +    select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 2ba4757..24177ef 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
> diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
> deleted file mode 100644
> index 6d59233..0000000
> --- a/hw/riscv/trace-events
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# See docs/devel/tracing.txt for syntax documentation.
> -
> -# hw/gpio/sifive_gpio.c
> -sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
> -sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
> -sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> -sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
> diff --git a/meson.build b/meson.build
> index 1e7aee8..66bbb75 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -706,7 +706,6 @@ if have_system
>      'hw/watchdog',
>      'hw/xen',
>      'hw/gpio',
> -    'hw/riscv',
>      'migration',
>      'net',
>      'ui',
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc
  2020-09-03 10:40 ` [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc Bin Meng
@ 2020-09-04 17:30     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:30 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_clint model to hw/intc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => intc}/sifive_clint.h | 0
>  hw/{riscv => intc}/sifive_clint.c         | 2 +-
>  hw/riscv/microchip_pfsoc.c                | 2 +-
>  hw/riscv/sifive_e.c                       | 2 +-
>  hw/riscv/sifive_u.c                       | 2 +-
>  hw/riscv/spike.c                          | 2 +-
>  hw/riscv/virt.c                           | 2 +-
>  hw/intc/Kconfig                           | 3 +++
>  hw/intc/meson.build                       | 1 +
>  hw/riscv/Kconfig                          | 5 +++++
>  hw/riscv/meson.build                      | 1 -
>  11 files changed, 15 insertions(+), 7 deletions(-)
>  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
>  rename hw/{riscv => intc}/sifive_clint.c (99%)
>
> diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
> similarity index 100%
> rename from include/hw/riscv/sifive_clint.h
> rename to include/hw/intc/sifive_clint.h
> diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
> similarity index 99%
> rename from hw/riscv/sifive_clint.c
> rename to hw/intc/sifive_clint.c
> index fa1ddf2..0f41e5e 100644
> --- a/hw/riscv/sifive_clint.c
> +++ b/hw/intc/sifive_clint.c
> @@ -26,7 +26,7 @@
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/riscv/sifive_clint.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "qemu/timer.h"
>
>  static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index da6bd29..131eea1 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 7f43ed9..3bdb16e 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -40,10 +40,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7997537..7187d1a 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -47,10 +47,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b54a396..59d9d87 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -33,10 +33,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c67a910..bce2020 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -31,11 +31,11 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 2ae1e89..f499d0f 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -67,3 +67,6 @@ config RX_ICU
>
>  config LOONGSON_LIOINTC
>      bool
> +
> +config SIFIVE_CLINT
> +    bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index c16f7f0..1e20daa 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 5a8335b..f8bb7e7 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_E_PRCI
>      select UNIMP
> @@ -24,6 +25,7 @@ config SIFIVE_U
>      select CADENCE
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_U_OTP
> @@ -35,6 +37,7 @@ config SPIKE
>      select HART
>      select HTIF
>      select SIFIVE
> +    select SIFIVE_CLINT
>
>  config OPENTITAN
>      bool
> @@ -54,11 +57,13 @@ config RISCV_VIRT
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
>      select SIFIVE
> +    select SIFIVE_CLINT
>
>  config MICROCHIP_PFSOC
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select UNIMP
>      select MCHP_PFSOC_MMUART
>      select SIFIVE_PDMA
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 24177ef..ea72178 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc
@ 2020-09-04 17:30     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:30 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_clint model to hw/intc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => intc}/sifive_clint.h | 0
>  hw/{riscv => intc}/sifive_clint.c         | 2 +-
>  hw/riscv/microchip_pfsoc.c                | 2 +-
>  hw/riscv/sifive_e.c                       | 2 +-
>  hw/riscv/sifive_u.c                       | 2 +-
>  hw/riscv/spike.c                          | 2 +-
>  hw/riscv/virt.c                           | 2 +-
>  hw/intc/Kconfig                           | 3 +++
>  hw/intc/meson.build                       | 1 +
>  hw/riscv/Kconfig                          | 5 +++++
>  hw/riscv/meson.build                      | 1 -
>  11 files changed, 15 insertions(+), 7 deletions(-)
>  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
>  rename hw/{riscv => intc}/sifive_clint.c (99%)
>
> diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
> similarity index 100%
> rename from include/hw/riscv/sifive_clint.h
> rename to include/hw/intc/sifive_clint.h
> diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
> similarity index 99%
> rename from hw/riscv/sifive_clint.c
> rename to hw/intc/sifive_clint.c
> index fa1ddf2..0f41e5e 100644
> --- a/hw/riscv/sifive_clint.c
> +++ b/hw/intc/sifive_clint.c
> @@ -26,7 +26,7 @@
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/qdev-properties.h"
> -#include "hw/riscv/sifive_clint.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "qemu/timer.h"
>
>  static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index da6bd29..131eea1 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 7f43ed9..3bdb16e 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -40,10 +40,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7997537..7187d1a 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -47,10 +47,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b54a396..59d9d87 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -33,10 +33,10 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index c67a910..bce2020 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -31,11 +31,11 @@
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/sifive_plic.h"
> -#include "hw/riscv/sifive_clint.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index 2ae1e89..f499d0f 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -67,3 +67,6 @@ config RX_ICU
>
>  config LOONGSON_LIOINTC
>      bool
> +
> +config SIFIVE_CLINT
> +    bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index c16f7f0..1e20daa 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 5a8335b..f8bb7e7 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_E_PRCI
>      select UNIMP
> @@ -24,6 +25,7 @@ config SIFIVE_U
>      select CADENCE
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_U_OTP
> @@ -35,6 +37,7 @@ config SPIKE
>      select HART
>      select HTIF
>      select SIFIVE
> +    select SIFIVE_CLINT
>
>  config OPENTITAN
>      bool
> @@ -54,11 +57,13 @@ config RISCV_VIRT
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
>      select SIFIVE
> +    select SIFIVE_CLINT
>
>  config MICROCHIP_PFSOC
>      bool
>      select HART
>      select SIFIVE
> +    select SIFIVE_CLINT
>      select UNIMP
>      select MCHP_PFSOC_MMUART
>      select SIFIVE_PDMA
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 24177ef..ea72178 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc
  2020-09-03 10:40 ` [PATCH 06/12] hw/riscv: Move sifive_plic " Bin Meng
@ 2020-09-04 17:34     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:34 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_plic model to hw/intc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  {include/hw/riscv => hw/intc}/sifive_plic.h | 0
>  hw/{riscv => intc}/sifive_plic.c            | 2 +-
>  hw/riscv/microchip_pfsoc.c                  | 2 +-
>  hw/riscv/sifive_e.c                         | 2 +-
>  hw/riscv/sifive_u.c                         | 2 +-
>  hw/riscv/virt.c                             | 2 +-
>  hw/intc/Kconfig                             | 3 +++
>  hw/intc/meson.build                         | 1 +
>  hw/riscv/Kconfig                            | 5 +++++
>  hw/riscv/meson.build                        | 1 -
>  10 files changed, 14 insertions(+), 6 deletions(-)
>  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
>  rename hw/{riscv => intc}/sifive_plic.c (99%)
>
> diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
> similarity index 100%
> rename from include/hw/riscv/sifive_plic.h
> rename to hw/intc/sifive_plic.h
> diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
> similarity index 99%
> rename from hw/riscv/sifive_plic.c
> rename to hw/intc/sifive_plic.c
> index 11ef147..af611f8 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -27,9 +27,9 @@
>  #include "hw/pci/msi.h"
>  #include "hw/boards.h"
>  #include "hw/qdev-properties.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "target/riscv/cpu.h"
>  #include "sysemu/sysemu.h"
> -#include "hw/riscv/sifive_plic.h"
>
>  #define RISCV_DEBUG_PLIC 0
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 131eea1..4627179 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 3bdb16e..0ddcf15 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,11 +39,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7187d1a..faca2e8 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,11 +46,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index bce2020..0caab8e 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f499d0f..d079540 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
>
>  config SIFIVE_CLINT
>      bool
> +
> +config SIFIVE_PLIC
> +    bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 1e20daa..3f82cc2 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
>  specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index f8bb7e7..23b7027 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -17,6 +17,7 @@ config SIFIVE_E
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> +    select SIFIVE_PLIC
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -28,6 +29,7 @@ config SIFIVE_U
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
> +    select SIFIVE_PLIC
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
> @@ -38,6 +40,7 @@ config SPIKE
>      select HTIF
>      select SIFIVE
>      select SIFIVE_CLINT
> +    select SIFIVE_PLIC
>
>  config OPENTITAN
>      bool
> @@ -58,6 +61,7 @@ config RISCV_VIRT
>      select PFLASH_CFI01
>      select SIFIVE
>      select SIFIVE_CLINT
> +    select SIFIVE_PLIC
>
>  config MICROCHIP_PFSOC
>      bool
> @@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
>      select UNIMP
>      select MCHP_PFSOC_MMUART
>      select SIFIVE_PDMA
> +    select SIFIVE_PLIC
>      select CADENCE_SDHCI
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index ea72178..535a142 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc
@ 2020-09-04 17:34     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:34 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:44 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_plic model to hw/intc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  {include/hw/riscv => hw/intc}/sifive_plic.h | 0
>  hw/{riscv => intc}/sifive_plic.c            | 2 +-
>  hw/riscv/microchip_pfsoc.c                  | 2 +-
>  hw/riscv/sifive_e.c                         | 2 +-
>  hw/riscv/sifive_u.c                         | 2 +-
>  hw/riscv/virt.c                             | 2 +-
>  hw/intc/Kconfig                             | 3 +++
>  hw/intc/meson.build                         | 1 +
>  hw/riscv/Kconfig                            | 5 +++++
>  hw/riscv/meson.build                        | 1 -
>  10 files changed, 14 insertions(+), 6 deletions(-)
>  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
>  rename hw/{riscv => intc}/sifive_plic.c (99%)
>
> diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
> similarity index 100%
> rename from include/hw/riscv/sifive_plic.h
> rename to hw/intc/sifive_plic.h
> diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
> similarity index 99%
> rename from hw/riscv/sifive_plic.c
> rename to hw/intc/sifive_plic.c
> index 11ef147..af611f8 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -27,9 +27,9 @@
>  #include "hw/pci/msi.h"
>  #include "hw/boards.h"
>  #include "hw/qdev-properties.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "target/riscv/cpu.h"
>  #include "sysemu/sysemu.h"
> -#include "hw/riscv/sifive_plic.h"
>
>  #define RISCV_DEBUG_PLIC 0
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 131eea1..4627179 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -48,9 +48,9 @@
>  #include "hw/misc/unimp.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/microchip_pfsoc.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "sysemu/sysemu.h"
>
>  /*
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 3bdb16e..0ddcf15 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,11 +39,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 7187d1a..faca2e8 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,11 +46,11 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "net/eth.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index bce2020..0caab8e 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_plic.h"
>  #include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
> +#include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f499d0f..d079540 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
>
>  config SIFIVE_CLINT
>      bool
> +
> +config SIFIVE_PLIC
> +    bool
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 1e20daa..3f82cc2 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
>  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
>  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
>  specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
> +specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
>  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
>  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
>  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index f8bb7e7..23b7027 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -17,6 +17,7 @@ config SIFIVE_E
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> +    select SIFIVE_PLIC
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -28,6 +29,7 @@ config SIFIVE_U
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
> +    select SIFIVE_PLIC
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
> @@ -38,6 +40,7 @@ config SPIKE
>      select HTIF
>      select SIFIVE
>      select SIFIVE_CLINT
> +    select SIFIVE_PLIC
>
>  config OPENTITAN
>      bool
> @@ -58,6 +61,7 @@ config RISCV_VIRT
>      select PFLASH_CFI01
>      select SIFIVE
>      select SIFIVE_CLINT
> +    select SIFIVE_PLIC
>
>  config MICROCHIP_PFSOC
>      bool
> @@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
>      select UNIMP
>      select MCHP_PFSOC_MMUART
>      select SIFIVE_PDMA
> +    select SIFIVE_PLIC
>      select CADENCE_SDHCI
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index ea72178..535a142 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char
  2020-09-03 10:40 ` [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char Bin Meng
@ 2020-09-04 17:36     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:36 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move riscv_htif model to hw/char directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => char}/riscv_htif.h | 0
>  hw/{riscv => char}/riscv_htif.c         | 2 +-
>  hw/riscv/spike.c                        | 2 +-
>  hw/char/Kconfig                         | 3 +++
>  hw/char/meson.build                     | 1 +
>  hw/riscv/Kconfig                        | 3 ---
>  hw/riscv/meson.build                    | 1 -
>  7 files changed, 6 insertions(+), 6 deletions(-)
>  rename include/hw/{riscv => char}/riscv_htif.h (100%)
>  rename hw/{riscv => char}/riscv_htif.c (99%)
>
> diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
> similarity index 100%
> rename from include/hw/riscv/riscv_htif.h
> rename to include/hw/char/riscv_htif.h
> diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
> similarity index 99%
> rename from hw/riscv/riscv_htif.c
> rename to hw/char/riscv_htif.c
> index ca87a5c..ba1af1c 100644
> --- a/hw/riscv/riscv_htif.c
> +++ b/hw/char/riscv_htif.c
> @@ -24,10 +24,10 @@
>  #include "qapi/error.h"
>  #include "qemu/log.h"
>  #include "hw/sysbus.h"
> +#include "hw/char/riscv_htif.h"
>  #include "hw/char/serial.h"
>  #include "chardev/char.h"
>  #include "chardev/char-fe.h"
> -#include "hw/riscv/riscv_htif.h"
>  #include "qemu/timer.h"
>  #include "qemu/error-report.h"
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 59d9d87..3fd152a 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -31,11 +31,11 @@
>  #include "hw/loader.h"
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
> -#include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/char/riscv_htif.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/char/Kconfig b/hw/char/Kconfig
> index 1d64555..91da92f 100644
> --- a/hw/char/Kconfig
> +++ b/hw/char/Kconfig
> @@ -1,6 +1,9 @@
>  config ESCC
>      bool
>
> +config HTIF
> +    bool
> +
>  config PARALLEL
>      bool
>      default y
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index ae27932..3db623e 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
>  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
>
> +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
>  specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
>  specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
>  specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 23b7027..a0e256c 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,6 +1,3 @@
> -config HTIF
> -    bool
> -
>  config HART
>      bool
>
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 535a142..619bf80 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
>
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char
@ 2020-09-04 17:36     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:36 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move riscv_htif model to hw/char directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => char}/riscv_htif.h | 0
>  hw/{riscv => char}/riscv_htif.c         | 2 +-
>  hw/riscv/spike.c                        | 2 +-
>  hw/char/Kconfig                         | 3 +++
>  hw/char/meson.build                     | 1 +
>  hw/riscv/Kconfig                        | 3 ---
>  hw/riscv/meson.build                    | 1 -
>  7 files changed, 6 insertions(+), 6 deletions(-)
>  rename include/hw/{riscv => char}/riscv_htif.h (100%)
>  rename hw/{riscv => char}/riscv_htif.c (99%)
>
> diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
> similarity index 100%
> rename from include/hw/riscv/riscv_htif.h
> rename to include/hw/char/riscv_htif.h
> diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
> similarity index 99%
> rename from hw/riscv/riscv_htif.c
> rename to hw/char/riscv_htif.c
> index ca87a5c..ba1af1c 100644
> --- a/hw/riscv/riscv_htif.c
> +++ b/hw/char/riscv_htif.c
> @@ -24,10 +24,10 @@
>  #include "qapi/error.h"
>  #include "qemu/log.h"
>  #include "hw/sysbus.h"
> +#include "hw/char/riscv_htif.h"
>  #include "hw/char/serial.h"
>  #include "chardev/char.h"
>  #include "chardev/char-fe.h"
> -#include "hw/riscv/riscv_htif.h"
>  #include "qemu/timer.h"
>  #include "qemu/error-report.h"
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 59d9d87..3fd152a 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -31,11 +31,11 @@
>  #include "hw/loader.h"
>  #include "hw/sysbus.h"
>  #include "target/riscv/cpu.h"
> -#include "hw/riscv/riscv_htif.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/spike.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
> +#include "hw/char/riscv_htif.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
> diff --git a/hw/char/Kconfig b/hw/char/Kconfig
> index 1d64555..91da92f 100644
> --- a/hw/char/Kconfig
> +++ b/hw/char/Kconfig
> @@ -1,6 +1,9 @@
>  config ESCC
>      bool
>
> +config HTIF
> +    bool
> +
>  config PARALLEL
>      bool
>      default y
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index ae27932..3db623e 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
>  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
>
> +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
>  specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
>  specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
>  specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 23b7027..a0e256c 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,6 +1,3 @@
> -config HTIF
> -    bool
> -
>  config HART
>      bool
>
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 535a142..619bf80 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
>  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
>
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char
  2020-09-03 10:40 ` [PATCH 08/12] hw/riscv: Move sifive_uart " Bin Meng
@ 2020-09-04 17:36     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:36 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_uart model to hw/char directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => char}/sifive_uart.h | 0
>  hw/{riscv => char}/sifive_uart.c         | 2 +-
>  hw/riscv/sifive_e.c                      | 2 +-
>  hw/riscv/sifive_u.c                      | 2 +-
>  hw/char/Kconfig                          | 3 +++
>  hw/char/meson.build                      | 1 +
>  hw/riscv/Kconfig                         | 2 ++
>  hw/riscv/meson.build                     | 1 -
>  8 files changed, 9 insertions(+), 4 deletions(-)
>  rename include/hw/{riscv => char}/sifive_uart.h (100%)
>  rename hw/{riscv => char}/sifive_uart.c (99%)
>
> diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
> similarity index 100%
> rename from include/hw/riscv/sifive_uart.h
> rename to include/hw/char/sifive_uart.h
> diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
> similarity index 99%
> rename from hw/riscv/sifive_uart.c
> rename to hw/char/sifive_uart.c
> index 9350482..3a00ba7 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -24,7 +24,7 @@
>  #include "chardev/char-fe.h"
>  #include "hw/hw.h"
>  #include "hw/irq.h"
> -#include "hw/riscv/sifive_uart.h"
> +#include "hw/char/sifive_uart.h"
>
>  /*
>   * Not yet implemented:
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 0ddcf15..40bbf53 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,9 +39,9 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/char/sifive_uart.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index faca2e8..4f12a93 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,9 +46,9 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/char/sifive_uart.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
> diff --git a/hw/char/Kconfig b/hw/char/Kconfig
> index 91da92f..939bc44 100644
> --- a/hw/char/Kconfig
> +++ b/hw/char/Kconfig
> @@ -58,3 +58,6 @@ config AVR_USART
>
>  config MCHP_PFSOC_MMUART
>      bool
> +
> +config SIFIVE_UART
> +    bool
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index 3db623e..196ac91 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
>  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
>  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index a0e256c..a046157 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PLIC
> +    select SIFIVE_UART
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -27,6 +28,7 @@ config SIFIVE_U
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_PLIC
> +    select SIFIVE_UART
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 619bf80..da32148 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char
@ 2020-09-04 17:36     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:36 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_uart model to hw/char directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => char}/sifive_uart.h | 0
>  hw/{riscv => char}/sifive_uart.c         | 2 +-
>  hw/riscv/sifive_e.c                      | 2 +-
>  hw/riscv/sifive_u.c                      | 2 +-
>  hw/char/Kconfig                          | 3 +++
>  hw/char/meson.build                      | 1 +
>  hw/riscv/Kconfig                         | 2 ++
>  hw/riscv/meson.build                     | 1 -
>  8 files changed, 9 insertions(+), 4 deletions(-)
>  rename include/hw/{riscv => char}/sifive_uart.h (100%)
>  rename hw/{riscv => char}/sifive_uart.c (99%)
>
> diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
> similarity index 100%
> rename from include/hw/riscv/sifive_uart.h
> rename to include/hw/char/sifive_uart.h
> diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
> similarity index 99%
> rename from hw/riscv/sifive_uart.c
> rename to hw/char/sifive_uart.c
> index 9350482..3a00ba7 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -24,7 +24,7 @@
>  #include "chardev/char-fe.h"
>  #include "hw/hw.h"
>  #include "hw/irq.h"
> -#include "hw/riscv/sifive_uart.h"
> +#include "hw/char/sifive_uart.h"
>
>  /*
>   * Not yet implemented:
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 0ddcf15..40bbf53 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -39,9 +39,9 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_e.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/char/sifive_uart.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "hw/misc/sifive_e_prci.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index faca2e8..4f12a93 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -46,9 +46,9 @@
>  #include "hw/misc/unimp.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_uart.h"
>  #include "hw/riscv/sifive_u.h"
>  #include "hw/riscv/boot.h"
> +#include "hw/char/sifive_uart.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
>  #include "chardev/char.h"
> diff --git a/hw/char/Kconfig b/hw/char/Kconfig
> index 91da92f..939bc44 100644
> --- a/hw/char/Kconfig
> +++ b/hw/char/Kconfig
> @@ -58,3 +58,6 @@ config AVR_USART
>
>  config MCHP_PFSOC_MMUART
>      bool
> +
> +config SIFIVE_UART
> +    bool
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index 3db623e..196ac91 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
>  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
>  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
>  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
>  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index a0e256c..a046157 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -15,6 +15,7 @@ config SIFIVE_E
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PLIC
> +    select SIFIVE_UART
>      select SIFIVE_E_PRCI
>      select UNIMP
>
> @@ -27,6 +28,7 @@ config SIFIVE_U
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_PLIC
> +    select SIFIVE_UART
>      select SIFIVE_U_OTP
>      select SIFIVE_U_PRCI
>      select UNIMP
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 619bf80..da32148 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc
  2020-09-03 10:40 ` [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc Bin Meng
@ 2020-09-04 17:41     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:41 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_test model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_test.h | 0
>  hw/{riscv => misc}/sifive_test.c         | 2 +-
>  hw/riscv/virt.c                          | 2 +-
>  hw/misc/Kconfig                          | 3 +++
>  hw/misc/meson.build                      | 1 +
>  hw/riscv/Kconfig                         | 1 +
>  hw/riscv/meson.build                     | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_test.h (100%)
>  rename hw/{riscv => misc}/sifive_test.c (98%)
>
> diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
> similarity index 100%
> rename from include/hw/riscv/sifive_test.h
> rename to include/hw/misc/sifive_test.h
> diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
> similarity index 98%
> rename from hw/riscv/sifive_test.c
> rename to hw/misc/sifive_test.c
> index 0c78fb2..45d9399 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/misc/sifive_test.c
> @@ -25,7 +25,7 @@
>  #include "qemu/module.h"
>  #include "sysemu/runstate.h"
>  #include "hw/hw.h"
> -#include "hw/riscv/sifive_test.h"
> +#include "hw/misc/sifive_test.h"
>
>  static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 0caab8e..41bd2f3 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
> +#include "hw/misc/sifive_test.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index fa3d0f4..3185456 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -134,6 +134,9 @@ config MAC_VIA
>  config AVR_POWER
>      bool
>
> +config SIFIVE_TEST
> +    bool
> +
>  config SIFIVE_E_PRCI
>      bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 018a88c..bd24132 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index a046157..8e07100 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -61,6 +61,7 @@ config RISCV_VIRT
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
> +    select SIFIVE_TEST
>
>  config MICROCHIP_PFSOC
>      bool
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index da32148..3cf9380 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc
@ 2020-09-04 17:41     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:41 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Let's move sifive_test model to hw/misc directory.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  include/hw/{riscv => misc}/sifive_test.h | 0
>  hw/{riscv => misc}/sifive_test.c         | 2 +-
>  hw/riscv/virt.c                          | 2 +-
>  hw/misc/Kconfig                          | 3 +++
>  hw/misc/meson.build                      | 1 +
>  hw/riscv/Kconfig                         | 1 +
>  hw/riscv/meson.build                     | 1 -
>  7 files changed, 7 insertions(+), 3 deletions(-)
>  rename include/hw/{riscv => misc}/sifive_test.h (100%)
>  rename hw/{riscv => misc}/sifive_test.c (98%)
>
> diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
> similarity index 100%
> rename from include/hw/riscv/sifive_test.h
> rename to include/hw/misc/sifive_test.h
> diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
> similarity index 98%
> rename from hw/riscv/sifive_test.c
> rename to hw/misc/sifive_test.c
> index 0c78fb2..45d9399 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/misc/sifive_test.c
> @@ -25,7 +25,7 @@
>  #include "qemu/module.h"
>  #include "sysemu/runstate.h"
>  #include "hw/hw.h"
> -#include "hw/riscv/sifive_test.h"
> +#include "hw/misc/sifive_test.h"
>
>  static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
>  {
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 0caab8e..41bd2f3 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -30,12 +30,12 @@
>  #include "hw/char/serial.h"
>  #include "target/riscv/cpu.h"
>  #include "hw/riscv/riscv_hart.h"
> -#include "hw/riscv/sifive_test.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
>  #include "hw/riscv/numa.h"
>  #include "hw/intc/sifive_clint.h"
>  #include "hw/intc/sifive_plic.h"
> +#include "hw/misc/sifive_test.h"
>  #include "chardev/char.h"
>  #include "sysemu/arch_init.h"
>  #include "sysemu/device_tree.h"
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index fa3d0f4..3185456 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -134,6 +134,9 @@ config MAC_VIA
>  config AVR_POWER
>      bool
>
> +config SIFIVE_TEST
> +    bool
> +
>  config SIFIVE_E_PRCI
>      bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 018a88c..bd24132 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>  # RISC-V devices
> +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
>  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index a046157..8e07100 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -61,6 +61,7 @@ config RISCV_VIRT
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
> +    select SIFIVE_TEST
>
>  config MICROCHIP_PFSOC
>      bool
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index da32148..3cf9380 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
>  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
>  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 10/12] hw/riscv: Always build riscv_hart.c
  2020-09-03 10:40 ` [PATCH 10/12] hw/riscv: Always build riscv_hart.c Bin Meng
@ 2020-09-04 17:42     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:42 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Every RISC-V machine needs riscv_hart hence there is no need to
> have a dedicated Kconfig option for it. Drop the Kconfig option
> and always build riscv_hart.c.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/Kconfig     | 9 ---------
>  hw/riscv/meson.build | 2 +-
>  2 files changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 8e07100..7d017bc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,6 +1,3 @@
> -config HART
> -    bool
> -
>  config IBEX
>      bool
>
> @@ -10,7 +7,6 @@ config SIFIVE
>
>  config SIFIVE_E
>      bool
> -    select HART
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> @@ -22,7 +18,6 @@ config SIFIVE_E
>  config SIFIVE_U
>      bool
>      select CADENCE
> -    select HART
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> @@ -35,7 +30,6 @@ config SIFIVE_U
>
>  config SPIKE
>      bool
> -    select HART
>      select HTIF
>      select SIFIVE
>      select SIFIVE_CLINT
> @@ -44,7 +38,6 @@ config SPIKE
>  config OPENTITAN
>      bool
>      select IBEX
> -    select HART
>      select UNIMP
>
>  config RISCV_VIRT
> @@ -52,7 +45,6 @@ config RISCV_VIRT
>      imply PCI_DEVICES
>      imply TEST_DEVICES
>      select PCI
> -    select HART
>      select SERIAL
>      select GOLDFISH_RTC
>      select VIRTIO_MMIO
> @@ -65,7 +57,6 @@ config RISCV_VIRT
>
>  config MICROCHIP_PFSOC
>      bool
> -    select HART
>      select SIFIVE
>      select SIFIVE_CLINT
>      select UNIMP
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 3cf9380..dbedf9b 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -1,7 +1,7 @@
>  riscv_ss = ss.source_set()
>  riscv_ss.add(files('boot.c'))
>  riscv_ss.add(files('numa.c'))
> -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
> +riscv_ss.add(files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 10/12] hw/riscv: Always build riscv_hart.c
@ 2020-09-04 17:42     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:42 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:42 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Every RISC-V machine needs riscv_hart hence there is no need to
> have a dedicated Kconfig option for it. Drop the Kconfig option
> and always build riscv_hart.c.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/Kconfig     | 9 ---------
>  hw/riscv/meson.build | 2 +-
>  2 files changed, 1 insertion(+), 10 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 8e07100..7d017bc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,6 +1,3 @@
> -config HART
> -    bool
> -
>  config IBEX
>      bool
>
> @@ -10,7 +7,6 @@ config SIFIVE
>
>  config SIFIVE_E
>      bool
> -    select HART
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> @@ -22,7 +18,6 @@ config SIFIVE_E
>  config SIFIVE_U
>      bool
>      select CADENCE
> -    select HART
>      select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
> @@ -35,7 +30,6 @@ config SIFIVE_U
>
>  config SPIKE
>      bool
> -    select HART
>      select HTIF
>      select SIFIVE
>      select SIFIVE_CLINT
> @@ -44,7 +38,6 @@ config SPIKE
>  config OPENTITAN
>      bool
>      select IBEX
> -    select HART
>      select UNIMP
>
>  config RISCV_VIRT
> @@ -52,7 +45,6 @@ config RISCV_VIRT
>      imply PCI_DEVICES
>      imply TEST_DEVICES
>      select PCI
> -    select HART
>      select SERIAL
>      select GOLDFISH_RTC
>      select VIRTIO_MMIO
> @@ -65,7 +57,6 @@ config RISCV_VIRT
>
>  config MICROCHIP_PFSOC
>      bool
> -    select HART
>      select SIFIVE
>      select SIFIVE_CLINT
>      select UNIMP
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 3cf9380..dbedf9b 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -1,7 +1,7 @@
>  riscv_ss = ss.source_set()
>  riscv_ss.add(files('boot.c'))
>  riscv_ss.add(files('numa.c'))
> -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
> +riscv_ss.add(files('riscv_hart.c'))
>  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
>  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
>  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE
  2020-09-03 10:40 ` [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE Bin Meng
@ 2020-09-04 17:42     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:42 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:49 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The name SIFIVE is too vague to convey the required component of
> MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
> each machine instead.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/Kconfig | 14 +++++---------
>  1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 7d017bc..e152fdc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,13 +1,9 @@
>  config IBEX
>      bool
>
> -config SIFIVE
> -    bool
> -    select MSI_NONBROKEN
> -
>  config SIFIVE_E
>      bool
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PLIC
> @@ -18,7 +14,7 @@ config SIFIVE_E
>  config SIFIVE_U
>      bool
>      select CADENCE
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
> @@ -31,7 +27,7 @@ config SIFIVE_U
>  config SPIKE
>      bool
>      select HTIF
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
>
> @@ -44,20 +40,20 @@ config RISCV_VIRT
>      bool
>      imply PCI_DEVICES
>      imply TEST_DEVICES
> +    select MSI_NONBROKEN
>      select PCI
>      select SERIAL
>      select GOLDFISH_RTC
>      select VIRTIO_MMIO
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
> -    select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
>      select SIFIVE_TEST
>
>  config MICROCHIP_PFSOC
>      bool
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select UNIMP
>      select MCHP_PFSOC_MMUART
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE
@ 2020-09-04 17:42     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:42 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:49 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The name SIFIVE is too vague to convey the required component of
> MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
> each machine instead.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/Kconfig | 14 +++++---------
>  1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 7d017bc..e152fdc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,13 +1,9 @@
>  config IBEX
>      bool
>
> -config SIFIVE
> -    bool
> -    select MSI_NONBROKEN
> -
>  config SIFIVE_E
>      bool
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PLIC
> @@ -18,7 +14,7 @@ config SIFIVE_E
>  config SIFIVE_U
>      bool
>      select CADENCE
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select SIFIVE_GPIO
>      select SIFIVE_PDMA
> @@ -31,7 +27,7 @@ config SIFIVE_U
>  config SPIKE
>      bool
>      select HTIF
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
>
> @@ -44,20 +40,20 @@ config RISCV_VIRT
>      bool
>      imply PCI_DEVICES
>      imply TEST_DEVICES
> +    select MSI_NONBROKEN
>      select PCI
>      select SERIAL
>      select GOLDFISH_RTC
>      select VIRTIO_MMIO
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
> -    select SIFIVE
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
>      select SIFIVE_TEST
>
>  config MICROCHIP_PFSOC
>      bool
> -    select SIFIVE
> +    select MSI_NONBROKEN
>      select SIFIVE_CLINT
>      select UNIMP
>      select MCHP_PFSOC_MMUART
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order
  2020-09-03 10:40 ` [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order Bin Meng
@ 2020-09-04 17:44     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:44 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the Kconfig file is in disorder. Let's sort the options.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
>  hw/riscv/Kconfig | 58 ++++++++++++++++++++++++++++----------------------------
>  1 file changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index e152fdc..2df978f 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,36 +1,16 @@
>  config IBEX
>      bool
>
> -config SIFIVE_E
> -    bool
> -    select MSI_NONBROKEN
> -    select SIFIVE_CLINT
> -    select SIFIVE_GPIO
> -    select SIFIVE_PLIC
> -    select SIFIVE_UART
> -    select SIFIVE_E_PRCI
> -    select UNIMP
> -
> -config SIFIVE_U
> +config MICROCHIP_PFSOC
>      bool
> -    select CADENCE
> +    select CADENCE_SDHCI
> +    select MCHP_PFSOC_MMUART
>      select MSI_NONBROKEN
>      select SIFIVE_CLINT
> -    select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_PLIC
> -    select SIFIVE_UART
> -    select SIFIVE_U_OTP
> -    select SIFIVE_U_PRCI
>      select UNIMP
>
> -config SPIKE
> -    bool
> -    select HTIF
> -    select MSI_NONBROKEN
> -    select SIFIVE_CLINT
> -    select SIFIVE_PLIC
> -
>  config OPENTITAN
>      bool
>      select IBEX
> @@ -40,23 +20,43 @@ config RISCV_VIRT
>      bool
>      imply PCI_DEVICES
>      imply TEST_DEVICES
> +    select GOLDFISH_RTC
>      select MSI_NONBROKEN
>      select PCI
> -    select SERIAL
> -    select GOLDFISH_RTC
> -    select VIRTIO_MMIO
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
> +    select SERIAL
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
>      select SIFIVE_TEST
> +    select VIRTIO_MMIO
>
> -config MICROCHIP_PFSOC
> +config SIFIVE_E
>      bool
>      select MSI_NONBROKEN
>      select SIFIVE_CLINT
> +    select SIFIVE_GPIO
> +    select SIFIVE_PLIC
> +    select SIFIVE_UART
> +    select SIFIVE_E_PRCI
>      select UNIMP
> -    select MCHP_PFSOC_MMUART
> +
> +config SIFIVE_U
> +    bool
> +    select CADENCE
> +    select MSI_NONBROKEN
> +    select SIFIVE_CLINT
> +    select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_PLIC
> -    select CADENCE_SDHCI
> +    select SIFIVE_UART
> +    select SIFIVE_U_OTP
> +    select SIFIVE_U_PRCI
> +    select UNIMP
> +
> +config SPIKE
> +    bool
> +    select HTIF
> +    select MSI_NONBROKEN
> +    select SIFIVE_CLINT
> +    select SIFIVE_PLIC
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order
@ 2020-09-04 17:44     ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-04 17:44 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the Kconfig file is in disorder. Let's sort the options.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
>  hw/riscv/Kconfig | 58 ++++++++++++++++++++++++++++----------------------------
>  1 file changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index e152fdc..2df978f 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -1,36 +1,16 @@
>  config IBEX
>      bool
>
> -config SIFIVE_E
> -    bool
> -    select MSI_NONBROKEN
> -    select SIFIVE_CLINT
> -    select SIFIVE_GPIO
> -    select SIFIVE_PLIC
> -    select SIFIVE_UART
> -    select SIFIVE_E_PRCI
> -    select UNIMP
> -
> -config SIFIVE_U
> +config MICROCHIP_PFSOC
>      bool
> -    select CADENCE
> +    select CADENCE_SDHCI
> +    select MCHP_PFSOC_MMUART
>      select MSI_NONBROKEN
>      select SIFIVE_CLINT
> -    select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_PLIC
> -    select SIFIVE_UART
> -    select SIFIVE_U_OTP
> -    select SIFIVE_U_PRCI
>      select UNIMP
>
> -config SPIKE
> -    bool
> -    select HTIF
> -    select MSI_NONBROKEN
> -    select SIFIVE_CLINT
> -    select SIFIVE_PLIC
> -
>  config OPENTITAN
>      bool
>      select IBEX
> @@ -40,23 +20,43 @@ config RISCV_VIRT
>      bool
>      imply PCI_DEVICES
>      imply TEST_DEVICES
> +    select GOLDFISH_RTC
>      select MSI_NONBROKEN
>      select PCI
> -    select SERIAL
> -    select GOLDFISH_RTC
> -    select VIRTIO_MMIO
>      select PCI_EXPRESS_GENERIC_BRIDGE
>      select PFLASH_CFI01
> +    select SERIAL
>      select SIFIVE_CLINT
>      select SIFIVE_PLIC
>      select SIFIVE_TEST
> +    select VIRTIO_MMIO
>
> -config MICROCHIP_PFSOC
> +config SIFIVE_E
>      bool
>      select MSI_NONBROKEN
>      select SIFIVE_CLINT
> +    select SIFIVE_GPIO
> +    select SIFIVE_PLIC
> +    select SIFIVE_UART
> +    select SIFIVE_E_PRCI
>      select UNIMP
> -    select MCHP_PFSOC_MMUART
> +
> +config SIFIVE_U
> +    bool
> +    select CADENCE
> +    select MSI_NONBROKEN
> +    select SIFIVE_CLINT
> +    select SIFIVE_GPIO
>      select SIFIVE_PDMA
>      select SIFIVE_PLIC
> -    select CADENCE_SDHCI
> +    select SIFIVE_UART
> +    select SIFIVE_U_OTP
> +    select SIFIVE_U_PRCI
> +    select UNIMP
> +
> +config SPIKE
> +    bool
> +    select HTIF
> +    select MSI_NONBROKEN
> +    select SIFIVE_CLINT
> +    select SIFIVE_PLIC
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] hw/riscv: Clean up the directory
  2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
@ 2020-09-06 16:05   ` Alistair Francis
  2020-09-03 10:40 ` [PATCH 02/12] hw/riscv: Move sifive_u_prci " Bin Meng
                     ` (12 subsequent siblings)
  13 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-06 16:05 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, Bin Meng, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Thu, Sep 3, 2020 at 3:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Peripheral models for a specific SoC are moved to its
> corresponding hw/* subdirectories.
>
> This series should be applied after the PolarFire SoC series:
> http://patchwork.ozlabs.org/project/qemu-devel/list/?series=198727
>
>
> Bin Meng (12):
>   hw/riscv: Move sifive_e_prci model to hw/misc
>   hw/riscv: Move sifive_u_prci model to hw/misc
>   hw/riscv: Move sifive_u_otp model to hw/misc
>   hw/riscv: Move sifive_gpio model to hw/gpio
>   hw/riscv: Move sifive_clint model to hw/intc
>   hw/riscv: Move sifive_plic model to hw/intc
>   hw/riscv: Move riscv_htif model to hw/char
>   hw/riscv: Move sifive_uart model to hw/char
>   hw/riscv: Move sifive_test model to hw/misc
>   hw/riscv: Always build riscv_hart.c
>   hw/riscv: Drop CONFIG_SIFIVE
>   hw/riscv: Sort the Kconfig options in alphabetical order

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  {include/hw/riscv => hw/intc}/sifive_plic.h |  0
>  hw/riscv/trace.h                            |  1 -
>  include/hw/{riscv => char}/riscv_htif.h     |  0
>  include/hw/{riscv => char}/sifive_uart.h    |  0
>  include/hw/{riscv => gpio}/sifive_gpio.h    |  0
>  include/hw/{riscv => intc}/sifive_clint.h   |  0
>  include/hw/{riscv => misc}/sifive_e_prci.h  |  0
>  include/hw/{riscv => misc}/sifive_test.h    |  0
>  include/hw/{riscv => misc}/sifive_u_otp.h   |  0
>  include/hw/{riscv => misc}/sifive_u_prci.h  |  0
>  include/hw/riscv/sifive_e.h                 |  2 +-
>  include/hw/riscv/sifive_u.h                 |  6 +--
>  hw/{riscv => char}/riscv_htif.c             |  2 +-
>  hw/{riscv => char}/sifive_uart.c            |  2 +-
>  hw/{riscv => gpio}/sifive_gpio.c            |  2 +-
>  hw/{riscv => intc}/sifive_clint.c           |  2 +-
>  hw/{riscv => intc}/sifive_plic.c            |  2 +-
>  hw/{riscv => misc}/sifive_e_prci.c          |  2 +-
>  hw/{riscv => misc}/sifive_test.c            |  2 +-
>  hw/{riscv => misc}/sifive_u_otp.c           |  2 +-
>  hw/{riscv => misc}/sifive_u_prci.c          |  2 +-
>  hw/riscv/microchip_pfsoc.c                  |  4 +-
>  hw/riscv/sifive_e.c                         |  8 ++--
>  hw/riscv/sifive_u.c                         |  6 +--
>  hw/riscv/spike.c                            |  4 +-
>  hw/riscv/virt.c                             |  6 +--
>  hw/char/Kconfig                             |  6 +++
>  hw/char/meson.build                         |  2 +
>  hw/gpio/Kconfig                             |  3 ++
>  hw/gpio/meson.build                         |  1 +
>  hw/gpio/trace-events                        |  6 +++
>  hw/intc/Kconfig                             |  6 +++
>  hw/intc/meson.build                         |  2 +
>  hw/misc/Kconfig                             | 12 +++++
>  hw/misc/meson.build                         |  6 +++
>  hw/riscv/Kconfig                            | 74 +++++++++++++++--------------
>  hw/riscv/meson.build                        | 11 +----
>  hw/riscv/trace-events                       |  7 ---
>  meson.build                                 |  1 -
>  39 files changed, 110 insertions(+), 82 deletions(-)
>  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
>  delete mode 100644 hw/riscv/trace.h
>  rename include/hw/{riscv => char}/riscv_htif.h (100%)
>  rename include/hw/{riscv => char}/sifive_uart.h (100%)
>  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
>  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
>  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
>  rename include/hw/{riscv => misc}/sifive_test.h (100%)
>  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
>  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
>  rename hw/{riscv => char}/riscv_htif.c (99%)
>  rename hw/{riscv => char}/sifive_uart.c (99%)
>  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
>  rename hw/{riscv => intc}/sifive_clint.c (99%)
>  rename hw/{riscv => intc}/sifive_plic.c (99%)
>  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
>  rename hw/{riscv => misc}/sifive_test.c (98%)
>  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
>  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
>  delete mode 100644 hw/riscv/trace-events
>
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] hw/riscv: Clean up the directory
@ 2020-09-06 16:05   ` Alistair Francis
  0 siblings, 0 replies; 41+ messages in thread
From: Alistair Francis @ 2020-09-06 16:05 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, Bin Meng

On Thu, Sep 3, 2020 at 3:41 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This is an effort to clean up the hw/riscv directory. Ideally it
> should only contain the RISC-V SoC / machine codes plus generic
> codes. Peripheral models for a specific SoC are moved to its
> corresponding hw/* subdirectories.
>
> This series should be applied after the PolarFire SoC series:
> http://patchwork.ozlabs.org/project/qemu-devel/list/?series=198727
>
>
> Bin Meng (12):
>   hw/riscv: Move sifive_e_prci model to hw/misc
>   hw/riscv: Move sifive_u_prci model to hw/misc
>   hw/riscv: Move sifive_u_otp model to hw/misc
>   hw/riscv: Move sifive_gpio model to hw/gpio
>   hw/riscv: Move sifive_clint model to hw/intc
>   hw/riscv: Move sifive_plic model to hw/intc
>   hw/riscv: Move riscv_htif model to hw/char
>   hw/riscv: Move sifive_uart model to hw/char
>   hw/riscv: Move sifive_test model to hw/misc
>   hw/riscv: Always build riscv_hart.c
>   hw/riscv: Drop CONFIG_SIFIVE
>   hw/riscv: Sort the Kconfig options in alphabetical order

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  {include/hw/riscv => hw/intc}/sifive_plic.h |  0
>  hw/riscv/trace.h                            |  1 -
>  include/hw/{riscv => char}/riscv_htif.h     |  0
>  include/hw/{riscv => char}/sifive_uart.h    |  0
>  include/hw/{riscv => gpio}/sifive_gpio.h    |  0
>  include/hw/{riscv => intc}/sifive_clint.h   |  0
>  include/hw/{riscv => misc}/sifive_e_prci.h  |  0
>  include/hw/{riscv => misc}/sifive_test.h    |  0
>  include/hw/{riscv => misc}/sifive_u_otp.h   |  0
>  include/hw/{riscv => misc}/sifive_u_prci.h  |  0
>  include/hw/riscv/sifive_e.h                 |  2 +-
>  include/hw/riscv/sifive_u.h                 |  6 +--
>  hw/{riscv => char}/riscv_htif.c             |  2 +-
>  hw/{riscv => char}/sifive_uart.c            |  2 +-
>  hw/{riscv => gpio}/sifive_gpio.c            |  2 +-
>  hw/{riscv => intc}/sifive_clint.c           |  2 +-
>  hw/{riscv => intc}/sifive_plic.c            |  2 +-
>  hw/{riscv => misc}/sifive_e_prci.c          |  2 +-
>  hw/{riscv => misc}/sifive_test.c            |  2 +-
>  hw/{riscv => misc}/sifive_u_otp.c           |  2 +-
>  hw/{riscv => misc}/sifive_u_prci.c          |  2 +-
>  hw/riscv/microchip_pfsoc.c                  |  4 +-
>  hw/riscv/sifive_e.c                         |  8 ++--
>  hw/riscv/sifive_u.c                         |  6 +--
>  hw/riscv/spike.c                            |  4 +-
>  hw/riscv/virt.c                             |  6 +--
>  hw/char/Kconfig                             |  6 +++
>  hw/char/meson.build                         |  2 +
>  hw/gpio/Kconfig                             |  3 ++
>  hw/gpio/meson.build                         |  1 +
>  hw/gpio/trace-events                        |  6 +++
>  hw/intc/Kconfig                             |  6 +++
>  hw/intc/meson.build                         |  2 +
>  hw/misc/Kconfig                             | 12 +++++
>  hw/misc/meson.build                         |  6 +++
>  hw/riscv/Kconfig                            | 74 +++++++++++++++--------------
>  hw/riscv/meson.build                        | 11 +----
>  hw/riscv/trace-events                       |  7 ---
>  meson.build                                 |  1 -
>  39 files changed, 110 insertions(+), 82 deletions(-)
>  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
>  delete mode 100644 hw/riscv/trace.h
>  rename include/hw/{riscv => char}/riscv_htif.h (100%)
>  rename include/hw/{riscv => char}/sifive_uart.h (100%)
>  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
>  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
>  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
>  rename include/hw/{riscv => misc}/sifive_test.h (100%)
>  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
>  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
>  rename hw/{riscv => char}/riscv_htif.c (99%)
>  rename hw/{riscv => char}/sifive_uart.c (99%)
>  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
>  rename hw/{riscv => intc}/sifive_clint.c (99%)
>  rename hw/{riscv => intc}/sifive_plic.c (99%)
>  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
>  rename hw/{riscv => misc}/sifive_test.c (98%)
>  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
>  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
>  delete mode 100644 hw/riscv/trace-events
>
> --
> 2.7.4
>
>


^ permalink raw reply	[flat|nested] 41+ messages in thread
end of thread, other threads:[~2020-09-06 16:17 UTC | newest]

Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-03 10:40 [PATCH 00/12] hw/riscv: Clean up the directory Bin Meng
2020-09-03 10:40 ` [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc Bin Meng
2020-09-04 17:24   ` Alistair Francis
2020-09-04 17:24     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 02/12] hw/riscv: Move sifive_u_prci " Bin Meng
2020-09-04 17:25   ` Alistair Francis
2020-09-04 17:25     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 03/12] hw/riscv: Move sifive_u_otp " Bin Meng
2020-09-04 17:26   ` Alistair Francis
2020-09-04 17:26     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 04/12] hw/riscv: Move sifive_gpio model to hw/gpio Bin Meng
2020-09-04 17:28   ` Alistair Francis
2020-09-04 17:28     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc Bin Meng
2020-09-04 17:30   ` Alistair Francis
2020-09-04 17:30     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 06/12] hw/riscv: Move sifive_plic " Bin Meng
2020-09-04 17:34   ` Alistair Francis
2020-09-04 17:34     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char Bin Meng
2020-09-04 17:36   ` Alistair Francis
2020-09-04 17:36     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 08/12] hw/riscv: Move sifive_uart " Bin Meng
2020-09-04 17:36   ` Alistair Francis
2020-09-04 17:36     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc Bin Meng
2020-09-04 17:41   ` Alistair Francis
2020-09-04 17:41     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 10/12] hw/riscv: Always build riscv_hart.c Bin Meng
2020-09-04 17:42   ` Alistair Francis
2020-09-04 17:42     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE Bin Meng
2020-09-04 17:42   ` Alistair Francis
2020-09-04 17:42     ` Alistair Francis
2020-09-03 10:40 ` [PATCH 12/12] hw/riscv: Sort the Kconfig options in alphabetical order Bin Meng
2020-09-04 17:44   ` Alistair Francis
2020-09-04 17:44     ` Alistair Francis
2020-09-03 10:56 ` [PATCH 00/12] hw/riscv: Clean up the directory Peter Maydell
2020-09-03 10:56   ` Peter Maydell
2020-09-06 16:05 ` Alistair Francis
2020-09-06 16:05   ` Alistair Francis

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