* [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup @ 2020-09-08 23:39 Anusha Srivatsa 2020-09-09 0:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) Patchwork ` (3 more replies) 0 siblings, 4 replies; 6+ messages in thread From: Anusha Srivatsa @ 2020-09-08 23:39 UTC (permalink / raw) To: intel-gfx We currenty check for platform at multiple parts in the driver to grab the correct PLL. Let us begin to centralize it through a helper function. v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville) v3: Clean up combo_pll_disable() (Rodrigo) Suggested-by: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++-------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c9013f8f766f..441b6f52e808 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, pll->info->name, onoff(state), onoff(cur_state)); } +static +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll) +{ + + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4)) + return MG_PLL_ENABLE(0); + + return CNL_DPLL_ENABLE(pll->info->id); + + +} /** * intel_prepare_shared_dpll - call a dpll's prepare hook * @crtc_state: CRTC, and its state, which has a shared dpll @@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); - - if (IS_ELKHARTLAKE(dev_priv) && - pll->info->id == DPLL_ID_EHL_DPLL4) { - enable_reg = MG_PLL_ENABLE(0); - } + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); } @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, static void combo_pll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4) { - enable_reg = MG_PLL_ENABLE(0); /* * We need to disable DC states when this DPLL is enabled. @@ -4157,19 +4163,18 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, static void combo_pll_disable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); + + icl_pll_disable(dev_priv, pll, enable_reg); if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4) { - enable_reg = MG_PLL_ENABLE(0); - icl_pll_disable(dev_priv, pll, enable_reg); intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF, pll->wakeref); return; } - icl_pll_disable(dev_priv, pll, enable_reg); } static void tbt_pll_disable(struct drm_i915_private *dev_priv, -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) 2020-09-08 23:39 [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Anusha Srivatsa @ 2020-09-09 0:03 ` Patchwork 2020-09-09 0:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-09-09 0:03 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx == Series Details == Series: drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) URL : https://patchwork.freedesktop.org/series/81150/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3be3651c4fb7 drm/i915/pll: Centralize PLL_ENABLE register lookup -:33: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #33: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:152: +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll) -:35: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #35: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:154: +{ + -:36: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 24) #36: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:155: + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4)) + return MG_PLL_ENABLE(0); -:36: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'pll->info->id == DPLL_ID_EHL_DPLL4' #36: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:155: + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4)) -:41: CHECK:LINE_SPACING: Please don't use multiple blank lines #41: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:160: + + -:42: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #42: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:161: + +} total: 0 errors, 1 warnings, 5 checks, 65 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) 2020-09-08 23:39 [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Anusha Srivatsa 2020-09-09 0:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) Patchwork @ 2020-09-09 0:24 ` Patchwork 2020-09-09 13:06 ` [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Vivi, Rodrigo 2020-09-10 13:30 ` Jani Nikula 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2020-09-09 0:24 UTC (permalink / raw) To: Anusha Srivatsa; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 7328 bytes --] == Series Details == Series: drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) URL : https://patchwork.freedesktop.org/series/81150/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8985 -> Patchwork_18456 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18456 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18456, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18456: ### IGT changes ### #### Possible regressions #### * igt@gem_ctx_create@basic-files: - fi-tgl-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-tgl-u2/igt@gem_ctx_create@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-tgl-u2/igt@gem_ctx_create@basic-files.html Known issues ------------ Here are the changes found in Patchwork_18456 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_gttfill@basic: - fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] ([i915#2439]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-kbl-7500u/igt@gem_exec_gttfill@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-kbl-7500u/igt@gem_exec_gttfill@basic.html - fi-elk-e7500: [PASS][5] -> [INCOMPLETE][6] ([i915#2439] / [i915#66]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-elk-e7500/igt@gem_exec_gttfill@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-elk-e7500/igt@gem_exec_gttfill@basic.html - fi-ilk-650: [PASS][7] -> [INCOMPLETE][8] ([i915#2439]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-ilk-650/igt@gem_exec_gttfill@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-ilk-650/igt@gem_exec_gttfill@basic.html * igt@i915_selftest@live@gem_execbuf: - fi-gdg-551: [PASS][9] -> [INCOMPLETE][10] ([i915#172] / [i915#2440]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-gdg-551/igt@i915_selftest@live@gem_execbuf.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-gdg-551/igt@i915_selftest@live@gem_execbuf.html - fi-snb-2600: [PASS][11] -> [INCOMPLETE][12] ([i915#2440] / [i915#82]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-snb-2600/igt@i915_selftest@live@gem_execbuf.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-snb-2600/igt@i915_selftest@live@gem_execbuf.html - fi-bsw-n3050: [PASS][13] -> [INCOMPLETE][14] ([i915#2439]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-bsw-n3050/igt@i915_selftest@live@gem_execbuf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-bsw-n3050/igt@i915_selftest@live@gem_execbuf.html - fi-snb-2520m: [PASS][15] -> [INCOMPLETE][16] ([i915#2439]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-snb-2520m/igt@i915_selftest@live@gem_execbuf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-snb-2520m/igt@i915_selftest@live@gem_execbuf.html #### Possible fixes #### * igt@gem_exec_gttfill@basic: - fi-kbl-r: [INCOMPLETE][17] ([i915#2439]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-kbl-r/igt@gem_exec_gttfill@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-kbl-r/igt@gem_exec_gttfill@basic.html - fi-bdw-5557u: [INCOMPLETE][19] ([i915#2439]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-bdw-5557u/igt@gem_exec_gttfill@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-bdw-5557u/igt@gem_exec_gttfill@basic.html * igt@gem_tiled_fence_blits@basic: - fi-pnv-d510: [INCOMPLETE][21] ([i915#2439] / [i915#299]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-pnv-d510/igt@gem_tiled_fence_blits@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-pnv-d510/igt@gem_tiled_fence_blits@basic.html #### Warnings #### * igt@runner@aborted: - fi-kbl-r: [FAIL][23] ([i915#1186] / [i915#1784] / [i915#2439]) -> [FAIL][24] ([i915#2398] / [i915#2439]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-kbl-r/igt@runner@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-kbl-r/igt@runner@aborted.html - fi-kbl-7500u: [FAIL][25] ([i915#1784] / [i915#2398] / [i915#2439]) -> [FAIL][26] ([i915#1186] / [i915#1784] / [i915#2439]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-kbl-7500u/igt@runner@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-kbl-7500u/igt@runner@aborted.html - fi-kbl-guc: [FAIL][27] ([i915#1186] / [i915#1784] / [i915#2439]) -> [FAIL][28] ([i915#1186] / [i915#2439]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-kbl-guc/igt@runner@aborted.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-kbl-guc/igt@runner@aborted.html - fi-cml-s: [FAIL][29] ([i915#1186] / [i915#2439]) -> [FAIL][30] ([i915#1186] / [i915#2082] / [i915#2439]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8985/fi-cml-s/igt@runner@aborted.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/fi-cml-s/igt@runner@aborted.html [i915#1186]: https://gitlab.freedesktop.org/drm/intel/issues/1186 [i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172 [i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784 [i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082 [i915#2398]: https://gitlab.freedesktop.org/drm/intel/issues/2398 [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439 [i915#2440]: https://gitlab.freedesktop.org/drm/intel/issues/2440 [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299 [i915#66]: https://gitlab.freedesktop.org/drm/intel/issues/66 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 Participating hosts (41 -> 36) ------------------------------ Additional (1): fi-skl-6600u Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8985 -> Patchwork_18456 CI-20190529: 20190529 CI_DRM_8985: 21757387063c4f9b48141592dda7982b5eaf974d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5779: f52bf19b5f02d52fc3e201c6467ec3f511227fba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18456: 3be3651c4fb73ec965f2942da6af29ca3ba0cb31 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3be3651c4fb7 drm/i915/pll: Centralize PLL_ENABLE register lookup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18456/index.html [-- Attachment #1.2: Type: text/html, Size: 9867 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup 2020-09-08 23:39 [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Anusha Srivatsa 2020-09-09 0:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) Patchwork 2020-09-09 0:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork @ 2020-09-09 13:06 ` Vivi, Rodrigo 2020-09-10 13:30 ` Jani Nikula 3 siblings, 0 replies; 6+ messages in thread From: Vivi, Rodrigo @ 2020-09-09 13:06 UTC (permalink / raw) To: Srivatsa, Anusha; +Cc: intel-gfx > On Sep 8, 2020, at 4:39 PM, Srivatsa, Anusha <anusha.srivatsa@intel.com> wrote: > > We currenty check for platform at multiple parts in the driver > to grab the correct PLL. Let us begin to centralize it through a > helper function. > > v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville) > > v3: Clean up combo_pll_disable() (Rodrigo) > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++-------- > 1 file changed, 17 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index c9013f8f766f..441b6f52e808 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, > pll->info->name, onoff(state), onoff(cur_state)); > } > > +static > +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv, > + struct intel_shared_dpll *pll) > +{ > + > + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4)) > + return MG_PLL_ENABLE(0); > + > + return CNL_DPLL_ENABLE(pll->info->id); > + > + > +} > /** > * intel_prepare_shared_dpll - call a dpll's prepare hook > * @crtc_state: CRTC, and its state, which has a shared dpll > @@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, > struct intel_shared_dpll *pll, > struct intel_dpll_hw_state *hw_state) > { > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > - > - if (IS_ELKHARTLAKE(dev_priv) && > - pll->info->id == DPLL_ID_EHL_DPLL4) { > - enable_reg = MG_PLL_ENABLE(0); > - } > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); > } > @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, > static void combo_pll_enable(struct drm_i915_private *dev_priv, > struct intel_shared_dpll *pll) > { > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > if (IS_ELKHARTLAKE(dev_priv) && > pll->info->id == DPLL_ID_EHL_DPLL4) { > - enable_reg = MG_PLL_ENABLE(0); > > /* > * We need to disable DC states when this DPLL is enabled. > @@ -4157,19 +4163,18 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, > static void combo_pll_disable(struct drm_i915_private *dev_priv, > struct intel_shared_dpll *pll) > { > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > + > + icl_pll_disable(dev_priv, pll, enable_reg); > > if (IS_ELKHARTLAKE(dev_priv) && > pll->info->id == DPLL_ID_EHL_DPLL4) { > - enable_reg = MG_PLL_ENABLE(0); > - icl_pll_disable(dev_priv, pll, enable_reg); > > intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF, > pll->wakeref); > return; this return can also be removed > } > > - icl_pll_disable(dev_priv, pll, enable_reg); > } > > static void tbt_pll_disable(struct drm_i915_private *dev_priv, > -- > 2.25.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup 2020-09-08 23:39 [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Anusha Srivatsa ` (2 preceding siblings ...) 2020-09-09 13:06 ` [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Vivi, Rodrigo @ 2020-09-10 13:30 ` Jani Nikula 2020-09-10 17:05 ` Srivatsa, Anusha 3 siblings, 1 reply; 6+ messages in thread From: Jani Nikula @ 2020-09-10 13:30 UTC (permalink / raw) To: Anusha Srivatsa, intel-gfx On Tue, 08 Sep 2020, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > We currenty check for platform at multiple parts in the driver > to grab the correct PLL. Let us begin to centralize it through a > helper function. > > v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville) > > v3: Clean up combo_pll_disable() (Rodrigo) > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++-------- > 1 file changed, 17 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index c9013f8f766f..441b6f52e808 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, > pll->info->name, onoff(state), onoff(cur_state)); > } > > +static > +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv, Please keep the static keyword and the return type on the same line with each other. And since you're touching this, please rename dev_priv to i915 in all new code adding it. BR, Jani. > + struct intel_shared_dpll *pll) > +{ > + > + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4)) > + return MG_PLL_ENABLE(0); > + > + return CNL_DPLL_ENABLE(pll->info->id); > + > + > +} > /** > * intel_prepare_shared_dpll - call a dpll's prepare hook > * @crtc_state: CRTC, and its state, which has a shared dpll > @@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, > struct intel_shared_dpll *pll, > struct intel_dpll_hw_state *hw_state) > { > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > - > - if (IS_ELKHARTLAKE(dev_priv) && > - pll->info->id == DPLL_ID_EHL_DPLL4) { > - enable_reg = MG_PLL_ENABLE(0); > - } > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); > } > @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, > static void combo_pll_enable(struct drm_i915_private *dev_priv, > struct intel_shared_dpll *pll) > { > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > if (IS_ELKHARTLAKE(dev_priv) && > pll->info->id == DPLL_ID_EHL_DPLL4) { > - enable_reg = MG_PLL_ENABLE(0); > > /* > * We need to disable DC states when this DPLL is enabled. > @@ -4157,19 +4163,18 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, > static void combo_pll_disable(struct drm_i915_private *dev_priv, > struct intel_shared_dpll *pll) > { > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > + > + icl_pll_disable(dev_priv, pll, enable_reg); > > if (IS_ELKHARTLAKE(dev_priv) && > pll->info->id == DPLL_ID_EHL_DPLL4) { > - enable_reg = MG_PLL_ENABLE(0); > - icl_pll_disable(dev_priv, pll, enable_reg); > > intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF, > pll->wakeref); > return; > } > > - icl_pll_disable(dev_priv, pll, enable_reg); > } > > static void tbt_pll_disable(struct drm_i915_private *dev_priv, -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup 2020-09-10 13:30 ` Jani Nikula @ 2020-09-10 17:05 ` Srivatsa, Anusha 0 siblings, 0 replies; 6+ messages in thread From: Srivatsa, Anusha @ 2020-09-10 17:05 UTC (permalink / raw) To: Jani Nikula, intel-gfx > -----Original Message----- > From: Jani Nikula <jani.nikula@linux.intel.com> > Sent: Thursday, September 10, 2020 6:31 AM > To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register > lookup > > On Tue, 08 Sep 2020, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote: > > We currenty check for platform at multiple parts in the driver to grab > > the correct PLL. Let us begin to centralize it through a helper > > function. > > > > v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville) > > > > v3: Clean up combo_pll_disable() (Rodrigo) > > > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 > > +++++++++++-------- > > 1 file changed, 17 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > index c9013f8f766f..441b6f52e808 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private > *dev_priv, > > pll->info->name, onoff(state), onoff(cur_state)); } > > > > +static > > +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private > > +*dev_priv, > > Please keep the static keyword and the return type on the same line with > each other. > > And since you're touching this, please rename dev_priv to i915 in all new > code adding it. Sure. Thanks for the feedback Jani. Anusha > BR, > Jani. > > > > + struct intel_shared_dpll *pll) { > > + > > + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == > DPLL_ID_EHL_DPLL4)) > > + return MG_PLL_ENABLE(0); > > + > > + return CNL_DPLL_ENABLE(pll->info->id); > > + > > + > > +} > > /** > > * intel_prepare_shared_dpll - call a dpll's prepare hook > > * @crtc_state: CRTC, and its state, which has a shared dpll @@ > > -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct > drm_i915_private *dev_priv, > > struct intel_shared_dpll *pll, > > struct intel_dpll_hw_state *hw_state) { > > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > > - > > - if (IS_ELKHARTLAKE(dev_priv) && > > - pll->info->id == DPLL_ID_EHL_DPLL4) { > > - enable_reg = MG_PLL_ENABLE(0); > > - } > > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > > > return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); } > > @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct > > drm_i915_private *dev_priv, static void combo_pll_enable(struct > drm_i915_private *dev_priv, > > struct intel_shared_dpll *pll) { > > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > > > if (IS_ELKHARTLAKE(dev_priv) && > > pll->info->id == DPLL_ID_EHL_DPLL4) { > > - enable_reg = MG_PLL_ENABLE(0); > > > > /* > > * We need to disable DC states when this DPLL is enabled. > > @@ -4157,19 +4163,18 @@ static void icl_pll_disable(struct > > drm_i915_private *dev_priv, static void combo_pll_disable(struct > drm_i915_private *dev_priv, > > struct intel_shared_dpll *pll) { > > - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); > > + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll); > > + > > + icl_pll_disable(dev_priv, pll, enable_reg); > > > > if (IS_ELKHARTLAKE(dev_priv) && > > pll->info->id == DPLL_ID_EHL_DPLL4) { > > - enable_reg = MG_PLL_ENABLE(0); > > - icl_pll_disable(dev_priv, pll, enable_reg); > > > > intel_display_power_put(dev_priv, > POWER_DOMAIN_DPLL_DC_OFF, > > pll->wakeref); > > return; > > } > > > > - icl_pll_disable(dev_priv, pll, enable_reg); > > } > > > > static void tbt_pll_disable(struct drm_i915_private *dev_priv, > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-09-10 17:05 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-09-08 23:39 [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Anusha Srivatsa 2020-09-09 0:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev3) Patchwork 2020-09-09 0:24 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2020-09-09 13:06 ` [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup Vivi, Rodrigo 2020-09-10 13:30 ` Jani Nikula 2020-09-10 17:05 ` Srivatsa, Anusha
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