[PATCH v13 0/3] Microchip Polarfire FPGA manager

[PATCH v13 0/3] Microchip Polarfire FPGA manager

[Ivan Bornyakov]

Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Changelog:
  v1 -> v2: fix printk formating
  v2 -> v3:
   * replace "microsemi" with "microchip"
   * replace prefix "microsemi_fpga_" with "mpf_"
   * more sensible .compatible and .name strings
   * remove unused defines STATUS_SPI_VIOLATION and STATUS_SPI_ERROR
  v3 -> v4: fix unused variable warning
    Put 'mpf_of_ids' definition under conditional compilation, so it
    would not hang unused if CONFIG_OF is not enabled.
  v4 -> v5:
   * prefix defines with MPF_
   * mdelay() -> usleep_range()
   * formatting fixes
   * add DT bindings doc
   * rework fpga_manager_ops.write() to fpga_manager_ops.write_sg()
     We can't parse image header in write_init() because image header
     size is not known beforehand. Thus parsing need to be done in
     fpga_manager_ops.write() callback, but fpga_manager_ops.write()
     also need to be reenterable. On the other hand,
     fpga_manager_ops.write_sg() is called once. Thus, rework usage of
     write() callback to write_sg().
  v5 -> v6: fix patch applying
     I forgot to clean up unrelated local changes which lead to error on
     patch 0001-fpga-microchip-spi-add-Microchip-MPF-FPGA-manager.patch
     applying on vanilla kernel.
  v6 -> v7: fix binding doc to pass dt_binding_check
  v7 -> v8: another fix for dt_binding_check warning
  v8 -> v9:
   * add another patch to support bitstream offset in FPGA image buffer
   * rework fpga_manager_ops.write_sg() back to fpga_manager_ops.write()
   * move image header parsing from write() to write_init()
  v9 -> v10:
   * add parse_header() callback to fpga_manager_ops
   * adjust fpga_mgr_write_init[_buf|_sg]() for parse_header() usage
   * implement parse_header() in microchip-spi driver
  v10 -> v11: include missing unaligned.h to microchip-spi
     fix error: implicit declaration of function 'get_unaligned_le[16|32]'
  v11 -> v12:
   * microchip-spi: double read hw status, ignore first read, because it
     can be unreliable.
   * microchip-spi: remove sleep between status readings in
     poll_status_not_busy() to save a few seconds. Status is polled on
     every 16 byte writes - that is quite often, therefore
     usleep_range() accumulate to a considerable number of seconds.
  v12 -> v13:
   * fpga-mgr: separate fpga_mgr_parse_header_buf() from
     fpga_mgr_write_init_buf()
   * fpga-mgr: introduce FPGA_MGR_STATE_PARSE_HEADER and
     FPGA_MGR_STATE_PARSE_HEADER_ERR fpga_mgr_states
   * fpga-mgr: rename fpga_mgr_write_init_sg() to fpga_mgr_prepare_sg()
     and rework with respect to a new fpga_mgr_parse_header_buf()
   * fpga-mgr: rework write accounting in fpga_mgr_buf_load_sg() for
     better clarity
   * microchip-spi: rename MPF_STATUS_POLL_TIMEOUT to
     MPF_STATUS_POLL_RETRIES
   * microchip-spi: add comment about status reading quirk to
     mpf_read_status()
   * microchip-spi: rename poll_status_not_busy() to mpf_poll_status()
     and add comment.
   * microchip-spi: make if statement in mpf_poll_status() easier to
     read.

Ivan Bornyakov (3):
  fpga: fpga-mgr: support bitstream offset in image buffer
  fpga: microchip-spi: add Microchip MPF FPGA manager
  dt-bindings: fpga: add binding doc for microchip-spi fpga mgr

 .../fpga/microchip,mpf-spi-fpga-mgr.yaml      |  44 ++
 drivers/fpga/Kconfig                          |   9 +
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/fpga-mgr.c                       | 174 ++++++--
 drivers/fpga/microchip-spi.c                  | 386 ++++++++++++++++++
 include/linux/fpga/fpga-mgr.h                 |  17 +-
 6 files changed, 599 insertions(+), 32 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
 create mode 100644 drivers/fpga/microchip-spi.c

-- 
2.35.1

[PATCH v13 1/3] fpga: fpga-mgr: support bitstream offset in image buffer

[Ivan Bornyakov]

At the moment FPGA manager core loads to the device entire image
provided to fpga_mgr_load(). But it is not always whole FPGA image
buffer meant to be written to the device. In particular, .dat formatted
image for Microchip MPF contains meta info in the header that is not
meant to be written to the device. This is issue for those low level
drivers that loads data to the device with write() fpga_manager_ops
callback, since write() can be called in iterator over scatter-gather
table, not only linear image buffer. On the other hand, write_sg()
callback is provided with whole image in scatter-gather form and can
decide itself which part should be sent to the device.

Add header_size and data_size to the fpga_image_info struct and adjust
fpga_mgr_write() callers with respect to them.

  * info->header_size indicates part at the beginning of image buffer
    that is *not* meant to be written to the device. It is optional and
    can be 0.

  * info->data_size is the size of actual bitstream data that *is* meant
    to be written to the device, starting at info->header_size from the
    beginning of image buffer. It is also optional and can be 0, which
    means bitstream data is up to the end of image buffer.

Also add parse_header() callback to fpga_manager_ops, which purpose is
to set info->header_size and info->data_size. At least
initial_header_size bytes of image buffer will be passed into
parse_header() first time. If it is not enough, parse_header() should
set desired size into info->header_size and return -EAGAIN, then it will
be called again with greater part of image buffer on the input.

Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
---
 drivers/fpga/fpga-mgr.c       | 174 ++++++++++++++++++++++++++++------
 include/linux/fpga/fpga-mgr.h |  17 +++-
 2 files changed, 159 insertions(+), 32 deletions(-)

diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index a3595ecc3f79..7adca88c68a0 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -74,6 +74,15 @@ static inline int fpga_mgr_write_complete(struct fpga_manager *mgr,
 	return 0;
 }
 
+static inline int fpga_mgr_parse_header(struct fpga_manager *mgr,
+					struct fpga_image_info *info,
+					const char *buf, size_t count)
+{
+	if (mgr->mops->parse_header)
+		return mgr->mops->parse_header(mgr, info, buf, count);
+	return 0;
+}
+
 static inline int fpga_mgr_write_init(struct fpga_manager *mgr,
 				      struct fpga_image_info *info,
 				      const char *buf, size_t count)
@@ -136,44 +145,78 @@ void fpga_image_info_free(struct fpga_image_info *info)
 EXPORT_SYMBOL_GPL(fpga_image_info_free);
 
 /*
- * Call the low level driver's write_init function.  This will do the
+ * Call the low level driver's parse_header function. This will set
+ * info->header_size and info->data_size. The low level driver gets entire
+ * buffer provided. If it is not enough, driver should set desired size into
+ * info->header_size and return -EAGAIN, then parse_header() will be called
+ * again with greater part of image buffer on the input.
+ */
+static int fpga_mgr_parse_header_buf(struct fpga_manager *mgr,
+				     struct fpga_image_info *info,
+				     const char *buf, size_t count)
+{
+	int ret;
+
+	mgr->state = FPGA_MGR_STATE_PARSE_HEADER;
+	ret = fpga_mgr_parse_header(mgr, info, buf, count);
+	if (ret) {
+		if (ret != -EAGAIN)
+			dev_err(&mgr->dev,
+				"Error while parsing FPGA image header\n");
+
+		mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;
+	}
+
+	return ret;
+}
+
+/*
+ * Call the low level driver's write_init function. This will do the
  * device-specific things to get the FPGA into the state where it is ready to
- * receive an FPGA image. The low level driver only gets to see the first
- * initial_header_size bytes in the buffer.
+ * receive an FPGA image. If info->header_size is defined, the low level
+ * driver only gets to see the first info->header_size bytes in the buffer,
+ * mgr->mops->initial_header_size otherwise. If neither initial_header_size
+ * nor header_size are not set, write_init will not get any bytes of image
+ * buffer.
  */
 static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
 				   struct fpga_image_info *info,
 				   const char *buf, size_t count)
 {
+	size_t header_size;
 	int ret;
 
 	mgr->state = FPGA_MGR_STATE_WRITE_INIT;
-	if (!mgr->mops->initial_header_size) {
-		ret = fpga_mgr_write_init(mgr, info, NULL, 0);
-	} else {
-		count = min(mgr->mops->initial_header_size, count);
-		ret = fpga_mgr_write_init(mgr, info, buf, count);
-	}
+
+	header_size = mgr->mops->initial_header_size;
+	if (info->header_size)
+		header_size = info->header_size;
+
+	if (header_size > count)
+		ret = -EINVAL;
+	else
+		ret = fpga_mgr_write_init(mgr, info, header_size ? buf : NULL,
+					  header_size);
 
 	if (ret) {
 		dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
 		mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
-		return ret;
 	}
 
-	return 0;
+	return ret;
 }
 
-static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
-				  struct fpga_image_info *info,
-				  struct sg_table *sgt)
+static int fpga_mgr_prepare_sg(struct fpga_manager *mgr,
+			       struct fpga_image_info *info,
+			       struct sg_table *sgt)
 {
 	struct sg_mapping_iter miter;
-	size_t len;
+	size_t header_size, len;
 	char *buf;
 	int ret;
 
-	if (!mgr->mops->initial_header_size)
+	header_size = mgr->mops->initial_header_size;
+	if (!header_size)
 		return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
 
 	/*
@@ -182,24 +225,41 @@ static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
 	 */
 	sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
 	if (sg_miter_next(&miter) &&
-	    miter.length >= mgr->mops->initial_header_size) {
-		ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
-					      miter.length);
-		sg_miter_stop(&miter);
-		return ret;
+	    miter.length >= header_size) {
+		ret = fpga_mgr_parse_header_buf(mgr, info, miter.addr,
+						miter.length);
+		if (!ret)
+			ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
+						      miter.length);
+
+		if (ret != -EAGAIN) {
+			sg_miter_stop(&miter);
+			return ret;
+		}
 	}
 	sg_miter_stop(&miter);
 
 	/* Otherwise copy the fragments into temporary memory. */
-	buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
-	if (!buf)
-		return -ENOMEM;
+	do {
+		if (info->header_size)
+			header_size = info->header_size;
+
+		buf = kmalloc(header_size, GFP_KERNEL);
+		if (!buf)
+			return -ENOMEM;
+
+		len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf, header_size);
+		if (len != header_size) {
+			kfree(buf);
+			return -EFAULT;
+		}
 
-	len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
-				mgr->mops->initial_header_size);
-	ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
+		ret = fpga_mgr_parse_header_buf(mgr, info, buf, header_size);
+		if (!ret)
+			ret = fpga_mgr_write_init_buf(mgr, info, buf, header_size);
 
-	kfree(buf);
+		kfree(buf);
+	} while (ret == -EAGAIN);
 
 	return ret;
 }
@@ -227,7 +287,7 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
 {
 	int ret;
 
-	ret = fpga_mgr_write_init_sg(mgr, info, sgt);
+	ret = fpga_mgr_prepare_sg(mgr, info, sgt);
 	if (ret)
 		return ret;
 
@@ -237,11 +297,42 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
 		ret = fpga_mgr_write_sg(mgr, sgt);
 	} else {
 		struct sg_mapping_iter miter;
+		size_t length, data_size;
+		ssize_t count;
+		char *addr;
+
+		data_size = info->data_size;
+		count = -info->header_size;
 
 		sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
 		while (sg_miter_next(&miter)) {
-			ret = fpga_mgr_write(mgr, miter.addr, miter.length);
-			if (ret)
+			if (-count >= miter.length) {
+				count += miter.length;
+				continue;
+			}
+
+			if (count < 0) {
+				addr = miter.addr - count;
+
+				if (data_size)
+					length = min(miter.length + count,
+						     data_size);
+				else
+					length = miter.length + count;
+			} else {
+				addr = miter.addr;
+
+				if (data_size)
+					length = min(miter.length,
+						     data_size - count);
+				else
+					length = miter.length;
+			}
+
+			count += length;
+
+			ret = fpga_mgr_write(mgr, addr, length);
+			if (ret || count == data_size)
 				break;
 		}
 		sg_miter_stop(&miter);
@@ -262,10 +353,27 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
 {
 	int ret;
 
+	ret = fpga_mgr_parse_header_buf(mgr, info, buf, count);
+	if (ret)
+		return ret;
+
+	if (info->header_size + info->data_size > count) {
+		dev_err(&mgr->dev, "Bitsream data outruns FPGA image\n");
+		mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;
+		return -EINVAL;
+	}
+
 	ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
 	if (ret)
 		return ret;
 
+	if (info->data_size)
+		count = info->data_size;
+	else
+		count -= info->header_size;
+
+	buf += info->header_size;
+
 	/*
 	 * Write the FPGA image to the FPGA.
 	 */
@@ -424,6 +532,10 @@ static const char * const state_str[] = {
 	[FPGA_MGR_STATE_FIRMWARE_REQ] =		"firmware request",
 	[FPGA_MGR_STATE_FIRMWARE_REQ_ERR] =	"firmware request error",
 
+	/* Parse FPGA image header */
+	[FPGA_MGR_STATE_PARSE_HEADER] =		"parse header",
+	[FPGA_MGR_STATE_PARSE_HEADER_ERR] =	"parse header error",
+
 	/* Preparing FPGA to receive image */
 	[FPGA_MGR_STATE_WRITE_INIT] =		"write init",
 	[FPGA_MGR_STATE_WRITE_INIT_ERR] =	"write init error",
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 0f9468771bb9..cba8bb7827a5 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -22,6 +22,8 @@ struct sg_table;
  * @FPGA_MGR_STATE_RESET: FPGA in reset state
  * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
  * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
+ * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
+ * @FPGA_MGR_STATE_PARSE_HEADER_ERR: Error during PARSE_HEADER stage
  * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
  * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
  * @FPGA_MGR_STATE_WRITE: writing image to FPGA
@@ -42,6 +44,8 @@ enum fpga_mgr_states {
 	FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
 
 	/* write sequence: init, write, complete */
+	FPGA_MGR_STATE_PARSE_HEADER,
+	FPGA_MGR_STATE_PARSE_HEADER_ERR,
 	FPGA_MGR_STATE_WRITE_INIT,
 	FPGA_MGR_STATE_WRITE_INIT_ERR,
 	FPGA_MGR_STATE_WRITE,
@@ -85,6 +89,8 @@ enum fpga_mgr_states {
  * @sgt: scatter/gather table containing FPGA image
  * @buf: contiguous buffer containing FPGA image
  * @count: size of buf
+ * @header_size: offset in image buffer where bitstream data starts
+ * @data_size: size of bitstream. If 0, (count - header_size) will be used.
  * @region_id: id of target region
  * @dev: device that owns this
  * @overlay: Device Tree overlay
@@ -98,6 +104,8 @@ struct fpga_image_info {
 	struct sg_table *sgt;
 	const char *buf;
 	size_t count;
+	size_t header_size;
+	size_t data_size;
 	int region_id;
 	struct device *dev;
 #ifdef CONFIG_OF
@@ -137,9 +145,13 @@ struct fpga_manager_info {
 
 /**
  * struct fpga_manager_ops - ops for low level fpga manager drivers
- * @initial_header_size: Maximum number of bytes that should be passed into write_init
+ * @initial_header_size: minimum number of bytes that should be passed into
+ *	parse_header and write_init.
  * @state: returns an enum value of the FPGA's state
  * @status: returns status of the FPGA, including reconfiguration error code
+ * @parse_header: parse FPGA image header to set info->header_size and
+ *	info->data_size. In case the input buffer is not large enough, set
+ *	required size to info->header_size and return -EAGAIN.
  * @write_init: prepare the FPGA to receive configuration data
  * @write: write count bytes of configuration data to the FPGA
  * @write_sg: write the scatter list of configuration data to the FPGA
@@ -155,6 +167,9 @@ struct fpga_manager_ops {
 	size_t initial_header_size;
 	enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
 	u64 (*status)(struct fpga_manager *mgr);
+	int (*parse_header)(struct fpga_manager *mgr,
+			    struct fpga_image_info *info,
+			    const char *buf, size_t count);
 	int (*write_init)(struct fpga_manager *mgr,
 			  struct fpga_image_info *info,
 			  const char *buf, size_t count);
-- 
2.35.1

Re: [PATCH v13 1/3] fpga: fpga-mgr: support bitstream offset in image buffer

[Xu Yilun]

On Thu, May 26, 2022 at 09:13:42PM +0300, Ivan Bornyakov wrote:
> At the moment FPGA manager core loads to the device entire image
> provided to fpga_mgr_load(). But it is not always whole FPGA image
> buffer meant to be written to the device. In particular, .dat formatted
> image for Microchip MPF contains meta info in the header that is not
> meant to be written to the device. This is issue for those low level
> drivers that loads data to the device with write() fpga_manager_ops
> callback, since write() can be called in iterator over scatter-gather
> table, not only linear image buffer. On the other hand, write_sg()
> callback is provided with whole image in scatter-gather form and can
> decide itself which part should be sent to the device.
> 
> Add header_size and data_size to the fpga_image_info struct and adjust
> fpga_mgr_write() callers with respect to them.
> 
>   * info->header_size indicates part at the beginning of image buffer
>     that is *not* meant to be written to the device. It is optional and
>     can be 0.
> 
>   * info->data_size is the size of actual bitstream data that *is* meant
>     to be written to the device, starting at info->header_size from the
>     beginning of image buffer. It is also optional and can be 0, which
>     means bitstream data is up to the end of image buffer.
> 
> Also add parse_header() callback to fpga_manager_ops, which purpose is
> to set info->header_size and info->data_size. At least
> initial_header_size bytes of image buffer will be passed into
> parse_header() first time. If it is not enough, parse_header() should
> set desired size into info->header_size and return -EAGAIN, then it will
> be called again with greater part of image buffer on the input.
> 
> Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
> ---
>  drivers/fpga/fpga-mgr.c       | 174 ++++++++++++++++++++++++++++------
>  include/linux/fpga/fpga-mgr.h |  17 +++-
>  2 files changed, 159 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
> index a3595ecc3f79..7adca88c68a0 100644
> --- a/drivers/fpga/fpga-mgr.c
> +++ b/drivers/fpga/fpga-mgr.c
> @@ -74,6 +74,15 @@ static inline int fpga_mgr_write_complete(struct fpga_manager *mgr,
>  	return 0;
>  }
>  
> +static inline int fpga_mgr_parse_header(struct fpga_manager *mgr,
> +					struct fpga_image_info *info,
> +					const char *buf, size_t count)
> +{
> +	if (mgr->mops->parse_header)
> +		return mgr->mops->parse_header(mgr, info, buf, count);
> +	return 0;
> +}
> +
>  static inline int fpga_mgr_write_init(struct fpga_manager *mgr,
>  				      struct fpga_image_info *info,
>  				      const char *buf, size_t count)
> @@ -136,44 +145,78 @@ void fpga_image_info_free(struct fpga_image_info *info)
>  EXPORT_SYMBOL_GPL(fpga_image_info_free);
>  
>  /*
> - * Call the low level driver's write_init function.  This will do the
> + * Call the low level driver's parse_header function. This will set
> + * info->header_size and info->data_size. The low level driver gets entire
> + * buffer provided. If it is not enough, driver should set desired size into
> + * info->header_size and return -EAGAIN, then parse_header() will be called
> + * again with greater part of image buffer on the input.
> + */
> +static int fpga_mgr_parse_header_buf(struct fpga_manager *mgr,
> +				     struct fpga_image_info *info,
> +				     const char *buf, size_t count)
> +{
> +	int ret;
> +
> +	mgr->state = FPGA_MGR_STATE_PARSE_HEADER;
> +	ret = fpga_mgr_parse_header(mgr, info, buf, count);
> +	if (ret) {
> +		if (ret != -EAGAIN)
> +			dev_err(&mgr->dev,
> +				"Error while parsing FPGA image header\n");
> +
> +		mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;

If ret == EAGAIN, don't set the state to ERROR.

> +	}
> +
> +	return ret;
> +}
> +
> +/*
> + * Call the low level driver's write_init function. This will do the
>   * device-specific things to get the FPGA into the state where it is ready to
> - * receive an FPGA image. The low level driver only gets to see the first
> - * initial_header_size bytes in the buffer.
> + * receive an FPGA image. If info->header_size is defined, the low level
> + * driver only gets to see the first info->header_size bytes in the buffer,
> + * mgr->mops->initial_header_size otherwise. If neither initial_header_size
> + * nor header_size are not set, write_init will not get any bytes of image
> + * buffer.
>   */
>  static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
>  				   struct fpga_image_info *info,
>  				   const char *buf, size_t count)
>  {
> +	size_t header_size;
>  	int ret;
>  
>  	mgr->state = FPGA_MGR_STATE_WRITE_INIT;
> -	if (!mgr->mops->initial_header_size) {
> -		ret = fpga_mgr_write_init(mgr, info, NULL, 0);
> -	} else {
> -		count = min(mgr->mops->initial_header_size, count);
> -		ret = fpga_mgr_write_init(mgr, info, buf, count);
> -	}
> +
> +	header_size = mgr->mops->initial_header_size;
> +	if (info->header_size)
> +		header_size = info->header_size;

How about:

	if (info->header_size)
		header_size = info->header_size;
	else
		header_size = mgr->mops->initial_header_size;

> +
> +	if (header_size > count)
> +		ret = -EINVAL;
> +	else
> +		ret = fpga_mgr_write_init(mgr, info, header_size ? buf : NULL,

Don't abuse ternary operator, the original code style is fine.

> +					  header_size);

Maybe 'count' is better than 'header_size' here?

So how about:

	if (header_size > count)
		ret = -EINVAL;
	else if (!header_size)
		ret = fpga_mgr_write_init(mgr, info, NULL, 0);
	else
		ret = fpga_mgr_write_init(mgr, info, buf, count);

>  
>  	if (ret) {
>  		dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
>  		mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
> -		return ret;
>  	}
>  
> -	return 0;
> +	return ret;

I assume it's just code style change, not needed in this patch.

>  }
>  
> -static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
> -				  struct fpga_image_info *info,
> -				  struct sg_table *sgt)
> +static int fpga_mgr_prepare_sg(struct fpga_manager *mgr,
> +			       struct fpga_image_info *info,
> +			       struct sg_table *sgt)
>  {
>  	struct sg_mapping_iter miter;
> -	size_t len;
> +	size_t header_size, len;
>  	char *buf;
>  	int ret;
>  
> -	if (!mgr->mops->initial_header_size)
> +	header_size = mgr->mops->initial_header_size;
> +	if (!header_size)
>  		return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
>  
>  	/*
> @@ -182,24 +225,41 @@ static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
>  	 */
>  	sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
>  	if (sg_miter_next(&miter) &&
> -	    miter.length >= mgr->mops->initial_header_size) {
> -		ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
> -					      miter.length);
> -		sg_miter_stop(&miter);
> -		return ret;
> +	    miter.length >= header_size) {
> +		ret = fpga_mgr_parse_header_buf(mgr, info, miter.addr,
> +						miter.length);
> +		if (!ret)
> +			ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
> +						      miter.length);
> +
> +		if (ret != -EAGAIN) {

If fpga_mgr_write_init_buf() returns -EAGAIN, we may have trouble.

		ret = fpga_mgr_parse_header_buf(mgr, info, miter.addr,
						miter.length);
		/*
		 * If -EAGAIN, more sg buffer is needed, otherwise the
		 * flow would always endup in this branch.
		 */
		if (ret != -EAGAIN) {
			if (!ret)
				ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
							      miter.length);

			sg_miter_stop(&miter);
			return ret;
		}

> +			sg_miter_stop(&miter);
> +			return ret;
> +		}
>  	}
>  	sg_miter_stop(&miter);
>  
>  	/* Otherwise copy the fragments into temporary memory. */
> -	buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
> -	if (!buf)
> -		return -ENOMEM;
> +	do {
> +		if (info->header_size)
> +			header_size = info->header_size;
> +
> +		buf = kmalloc(header_size, GFP_KERNEL);

Does krealloc() help?

> +		if (!buf)
> +			return -ENOMEM;
> +
> +		len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf, header_size);
> +		if (len != header_size) {
> +			kfree(buf);
> +			return -EFAULT;
> +		}
>  
> -	len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
> -				mgr->mops->initial_header_size);
> -	ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
> +		ret = fpga_mgr_parse_header_buf(mgr, info, buf, header_size);
> +		if (!ret)
> +			ret = fpga_mgr_write_init_buf(mgr, info, buf, header_size);

Same issue, fpga_mgr_write_init_buf may return -EAGAIN.

Please try to move fpga_mgr_write_init_buf() out of this loop.

>  
> -	kfree(buf);
> +		kfree(buf);
> +	} while (ret == -EAGAIN);
>  
>  	return ret;
>  }
> @@ -227,7 +287,7 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
>  {
>  	int ret;
>  
> -	ret = fpga_mgr_write_init_sg(mgr, info, sgt);
> +	ret = fpga_mgr_prepare_sg(mgr, info, sgt);
>  	if (ret)
>  		return ret;
>  
> @@ -237,11 +297,42 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
>  		ret = fpga_mgr_write_sg(mgr, sgt);
>  	} else {
>  		struct sg_mapping_iter miter;
> +		size_t length, data_size;
> +		ssize_t count;
> +		char *addr;
> +
> +		data_size = info->data_size;
> +		count = -info->header_size;
>  
>  		sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
>  		while (sg_miter_next(&miter)) {
> -			ret = fpga_mgr_write(mgr, miter.addr, miter.length);
> -			if (ret)
> +			if (-count >= miter.length) {
> +				count += miter.length;
> +				continue;
> +			}
> +
> +			if (count < 0) {
> +				addr = miter.addr - count;
> +
> +				if (data_size)
> +					length = min(miter.length + count,
> +						     data_size);
> +				else
> +					length = miter.length + count;
> +			} else {
> +				addr = miter.addr;
> +
> +				if (data_size)
> +					length = min(miter.length,
> +						     data_size - count);
> +				else
> +					length = miter.length;
> +			}
> +
> +			count += length;
> +
> +			ret = fpga_mgr_write(mgr, addr, length);
> +			if (ret || count == data_size)
>  				break;
>  		}

I think a negative initial value for count could simply the code:

Some code in my mind, please help check it:

		while (sg_miter_next(&miter)) {
			count += miter.length;

			/* sg block contains no data */
			if (count < 0)
				continue;

			if (count < miter.length) {
				/* sg block contains header & data */
				addr = miter.addr + miter.length - count;
				length = count;
			} else {
				/* sg block contains pure data */
				addr = miter.addr;
				length = miter.length;
			}

			/* last block, truncate length to data_size if needed */
			if (data_size && count > data_size) {
				length -= count - data_size;
				last = true;
			}

			ret = fpga_mgr_write(mgr, addr, length);
			if (ret || last)
				break;
		}

Thanks,
Yilun

>  		sg_miter_stop(&miter);
> @@ -262,10 +353,27 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
>  {
>  	int ret;
>  
> +	ret = fpga_mgr_parse_header_buf(mgr, info, buf, count);
> +	if (ret)
> +		return ret;
> +
> +	if (info->header_size + info->data_size > count) {
> +		dev_err(&mgr->dev, "Bitsream data outruns FPGA image\n");
> +		mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;
> +		return -EINVAL;
> +	}
> +
>  	ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
>  	if (ret)
>  		return ret;
>  
> +	if (info->data_size)
> +		count = info->data_size;
> +	else
> +		count -= info->header_size;
> +
> +	buf += info->header_size;
> +
>  	/*
>  	 * Write the FPGA image to the FPGA.
>  	 */
> @@ -424,6 +532,10 @@ static const char * const state_str[] = {
>  	[FPGA_MGR_STATE_FIRMWARE_REQ] =		"firmware request",
>  	[FPGA_MGR_STATE_FIRMWARE_REQ_ERR] =	"firmware request error",
>  
> +	/* Parse FPGA image header */
> +	[FPGA_MGR_STATE_PARSE_HEADER] =		"parse header",
> +	[FPGA_MGR_STATE_PARSE_HEADER_ERR] =	"parse header error",
> +
>  	/* Preparing FPGA to receive image */
>  	[FPGA_MGR_STATE_WRITE_INIT] =		"write init",
>  	[FPGA_MGR_STATE_WRITE_INIT_ERR] =	"write init error",
> diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
> index 0f9468771bb9..cba8bb7827a5 100644
> --- a/include/linux/fpga/fpga-mgr.h
> +++ b/include/linux/fpga/fpga-mgr.h
> @@ -22,6 +22,8 @@ struct sg_table;
>   * @FPGA_MGR_STATE_RESET: FPGA in reset state
>   * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
>   * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
> + * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
> + * @FPGA_MGR_STATE_PARSE_HEADER_ERR: Error during PARSE_HEADER stage
>   * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
>   * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
>   * @FPGA_MGR_STATE_WRITE: writing image to FPGA
> @@ -42,6 +44,8 @@ enum fpga_mgr_states {
>  	FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
>  
>  	/* write sequence: init, write, complete */
> +	FPGA_MGR_STATE_PARSE_HEADER,
> +	FPGA_MGR_STATE_PARSE_HEADER_ERR,
>  	FPGA_MGR_STATE_WRITE_INIT,
>  	FPGA_MGR_STATE_WRITE_INIT_ERR,
>  	FPGA_MGR_STATE_WRITE,
> @@ -85,6 +89,8 @@ enum fpga_mgr_states {
>   * @sgt: scatter/gather table containing FPGA image
>   * @buf: contiguous buffer containing FPGA image
>   * @count: size of buf
> + * @header_size: offset in image buffer where bitstream data starts
> + * @data_size: size of bitstream. If 0, (count - header_size) will be used.
>   * @region_id: id of target region
>   * @dev: device that owns this
>   * @overlay: Device Tree overlay
> @@ -98,6 +104,8 @@ struct fpga_image_info {
>  	struct sg_table *sgt;
>  	const char *buf;
>  	size_t count;
> +	size_t header_size;
> +	size_t data_size;
>  	int region_id;
>  	struct device *dev;
>  #ifdef CONFIG_OF
> @@ -137,9 +145,13 @@ struct fpga_manager_info {
>  
>  /**
>   * struct fpga_manager_ops - ops for low level fpga manager drivers
> - * @initial_header_size: Maximum number of bytes that should be passed into write_init
> + * @initial_header_size: minimum number of bytes that should be passed into
> + *	parse_header and write_init.
>   * @state: returns an enum value of the FPGA's state
>   * @status: returns status of the FPGA, including reconfiguration error code
> + * @parse_header: parse FPGA image header to set info->header_size and
> + *	info->data_size. In case the input buffer is not large enough, set
> + *	required size to info->header_size and return -EAGAIN.
>   * @write_init: prepare the FPGA to receive configuration data
>   * @write: write count bytes of configuration data to the FPGA
>   * @write_sg: write the scatter list of configuration data to the FPGA
> @@ -155,6 +167,9 @@ struct fpga_manager_ops {
>  	size_t initial_header_size;
>  	enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
>  	u64 (*status)(struct fpga_manager *mgr);
> +	int (*parse_header)(struct fpga_manager *mgr,
> +			    struct fpga_image_info *info,
> +			    const char *buf, size_t count);
>  	int (*write_init)(struct fpga_manager *mgr,
>  			  struct fpga_image_info *info,
>  			  const char *buf, size_t count);
> -- 
> 2.35.1
> 

[PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Ivan Bornyakov]

Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
---
 drivers/fpga/Kconfig         |   9 +
 drivers/fpga/Makefile        |   1 +
 drivers/fpga/microchip-spi.c | 386 +++++++++++++++++++++++++++++++++++
 3 files changed, 396 insertions(+)
 create mode 100644 drivers/fpga/microchip-spi.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 26025dbab353..75806ef5c9ea 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -248,4 +248,13 @@ config FPGA_MGR_VERSAL_FPGA
 	  configure the programmable logic(PL).
 
 	  To compile this as a module, choose M here.
+
+config FPGA_MGR_MICROCHIP_SPI
+	tristate "Microchip Polarfire SPI FPGA manager"
+	depends on SPI
+	help
+	  FPGA manager driver support for Microchip Polarfire FPGAs
+	  programming over slave SPI interface with .dat formatted
+	  bitstream image.
+
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index e32bfa90f968..5425a15892df 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
 obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)	+= versal-fpga.o
+obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI)	+= microchip-spi.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)		+= altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)	+= altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c
new file mode 100644
index 000000000000..7579b0de119f
--- /dev/null
+++ b/drivers/fpga/microchip-spi.c
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip Polarfire FPGA programming over slave SPI interface.
+ */
+
+#include <asm/unaligned.h>
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/spi/spi.h>
+
+#define	MPF_SPI_ISC_ENABLE	0x0B
+#define	MPF_SPI_ISC_DISABLE	0x0C
+#define	MPF_SPI_READ_STATUS	0x00
+#define	MPF_SPI_READ_DATA	0x01
+#define	MPF_SPI_FRAME_INIT	0xAE
+#define	MPF_SPI_FRAME		0xEE
+#define	MPF_SPI_PRG_MODE	0x01
+#define	MPF_SPI_RELEASE		0x23
+
+#define	MPF_SPI_FRAME_SIZE	16
+
+#define	MPF_HEADER_SIZE_OFFSET	24
+#define	MPF_DATA_SIZE_OFFSET	55
+
+#define	MPF_LOOKUP_TABLE_RECORD_SIZE		9
+#define	MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET	0
+#define	MPF_LOOKUP_TABLE_BLOCK_START_OFFSET	1
+
+#define	MPF_COMPONENTS_SIZE_ID	5
+#define	MPF_BITSTREAM_ID	8
+
+#define	MPF_BITS_PER_COMPONENT_SIZE	22
+
+#define	MPF_STATUS_POLL_RETRIES		10000
+#define	MPF_STATUS_BUSY			BIT(0)
+#define	MPF_STATUS_READY		BIT(1)
+#define	MPF_STATUS_SPI_VIOLATION	BIT(2)
+#define	MPF_STATUS_SPI_ERROR		BIT(3)
+
+struct mpf_priv {
+	struct spi_device *spi;
+	bool program_mode;
+};
+
+static int mpf_read_status(struct spi_device *spi)
+{
+	u8 status = 0, status_command = MPF_SPI_READ_STATUS;
+	/*
+	 * Two identical SPI transfers are used for status reading.
+	 * The reason is that the first one can be inadequate.
+	 * We ignore it completely and use the second one.
+	 */
+	struct spi_transfer xfers[] = {
+		[0 ... 1] = {
+			.tx_buf = &status_command,
+			.rx_buf = &status,
+			.len = 1,
+			.cs_change = 1,
+		}
+	};
+	int ret = spi_sync_transfer(spi, xfers, 2);
+
+	if ((status & MPF_STATUS_SPI_VIOLATION) ||
+	    (status & MPF_STATUS_SPI_ERROR))
+		ret = -EIO;
+
+	return ret ? : status;
+}
+
+static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
+{
+	struct mpf_priv *priv = mgr->priv;
+	struct spi_device *spi;
+	bool program_mode;
+	int status;
+
+	spi = priv->spi;
+	program_mode = priv->program_mode;
+	status = mpf_read_status(spi);
+
+	if (!program_mode && !status)
+		return FPGA_MGR_STATE_OPERATING;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int mpf_ops_parse_header(struct fpga_manager *mgr,
+				struct fpga_image_info *info,
+				const char *buf, size_t count)
+{
+	size_t component_size_byte_num, component_size_byte_off,
+	       components_size_start, bitstream_start, i,
+	       block_id_offset, block_start_offset;
+	u8 header_size, blocks_num, block_id;
+	u32 block_start, component_size;
+	u16 components_num;
+
+	if (!buf) {
+		dev_err(&mgr->dev, "Image buffer is not provided\n");
+		return -EINVAL;
+	}
+
+	header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
+	if (header_size > count) {
+		info->header_size = header_size;
+		return -EAGAIN;
+	}
+
+	/*
+	 * Go through look-up table to find out where actual bitstream starts
+	 * and where sizes of components of the bitstream lies.
+	 */
+	blocks_num = *(buf + header_size - 1);
+	block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
+	block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
+
+	header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
+	if (header_size > count) {
+		info->header_size = header_size;
+		return -EAGAIN;
+	}
+
+	components_size_start = 0;
+	bitstream_start = 0;
+
+	while (blocks_num--) {
+		block_id = *(buf + block_id_offset);
+		block_start = get_unaligned_le32(buf + block_start_offset);
+
+		switch (block_id) {
+		case MPF_BITSTREAM_ID:
+			info->header_size = bitstream_start = block_start;
+			if (block_start > count)
+				return -EAGAIN;
+
+			break;
+		case MPF_COMPONENTS_SIZE_ID:
+			components_size_start = block_start;
+			break;
+		default:
+			break;
+		}
+
+		if (bitstream_start && components_size_start)
+			break;
+
+		block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
+		block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
+	}
+
+	if (!bitstream_start || !components_size_start) {
+		dev_err(&mgr->dev, "Failed to parse header look-up table\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * Parse bitstream size.
+	 * Sizes of components of the bitstream are 22-bits long placed next
+	 * to each other. Image header should be extended by now up to where
+	 * actual bitstream starts, so no need for overflow check anymore.
+	 */
+	components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
+
+	for (i = 0; i < components_num; i++) {
+		component_size_byte_num =
+			(i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
+		component_size_byte_off =
+			(i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
+
+		component_size = get_unaligned_le32(buf +
+						    components_size_start +
+						    component_size_byte_num);
+		component_size >>= component_size_byte_off;
+		component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
+
+		info->data_size += component_size * MPF_SPI_FRAME_SIZE;
+	}
+
+	return 0;
+}
+
+/* Poll HW status until busy bit is cleared and mask bits are set. */
+static int mpf_poll_status(struct spi_device *spi, u8 mask)
+{
+	int status, retries = MPF_STATUS_POLL_RETRIES;
+
+	while (retries--) {
+		status = mpf_read_status(spi);
+		if (status < 0)
+			return status;
+
+		if (status & MPF_STATUS_BUSY)
+			continue;
+
+		if (!mask || (status & mask))
+			return status;
+	}
+
+	return -EBUSY;
+}
+
+static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size)
+{
+	int status = mpf_poll_status(spi, 0);
+
+	if (status < 0)
+		return status;
+
+	return spi_write(spi, buf, buf_size);
+}
+
+static int mpf_spi_write_then_read(struct spi_device *spi,
+				   const void *txbuf, size_t txbuf_size,
+				   void *rxbuf, size_t rxbuf_size)
+{
+	const u8 read_command[] = { MPF_SPI_READ_DATA };
+	int ret;
+
+	ret = mpf_spi_write(spi, txbuf, txbuf_size);
+	if (ret)
+		return ret;
+
+	ret = mpf_poll_status(spi, MPF_STATUS_READY);
+	if (ret < 0)
+		return ret;
+
+	return spi_write_then_read(spi, read_command, sizeof(read_command),
+				   rxbuf, rxbuf_size);
+}
+
+static int mpf_ops_write_init(struct fpga_manager *mgr,
+			      struct fpga_image_info *info, const char *buf,
+			      size_t count)
+{
+	const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE };
+	const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
+	struct mpf_priv *priv = mgr->priv;
+	struct device *dev = &mgr->dev;
+	struct spi_device *spi;
+	u32 isc_ret = 0;
+	int ret;
+
+	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+		dev_err(dev, "Partial reconfiguration is not supported\n");
+		return -EOPNOTSUPP;
+	}
+
+	spi = priv->spi;
+
+	ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command),
+				      &isc_ret, sizeof(isc_ret));
+	if (ret || isc_ret) {
+		dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
+			ret, isc_ret);
+		return -EFAULT;
+	}
+
+	ret = mpf_spi_write(spi, program_mode, sizeof(program_mode));
+	if (ret) {
+		dev_err(dev, "Failed to enter program mode: %d\n", ret);
+		return ret;
+	}
+
+	priv->program_mode = true;
+
+	return 0;
+}
+
+static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
+{
+	u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
+	struct mpf_priv *priv = mgr->priv;
+	struct device *dev = &mgr->dev;
+	struct spi_device *spi;
+	int ret, i;
+
+	if (count % MPF_SPI_FRAME_SIZE) {
+		dev_err(dev, "Bitstream size is not a multiple of %d\n",
+			MPF_SPI_FRAME_SIZE);
+		return -EINVAL;
+	}
+
+	spi = priv->spi;
+
+	for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
+		memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
+		       MPF_SPI_FRAME_SIZE);
+
+		ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
+		if (ret) {
+			dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
+				i, count / MPF_SPI_FRAME_SIZE);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int mpf_ops_write_complete(struct fpga_manager *mgr,
+				  struct fpga_image_info *info)
+{
+	const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE };
+	const u8 release_command[] = { MPF_SPI_RELEASE };
+	struct mpf_priv *priv = mgr->priv;
+	struct device *dev = &mgr->dev;
+	struct spi_device *spi;
+	int ret;
+
+	spi = priv->spi;
+
+	ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command));
+	if (ret) {
+		dev_err(dev, "Failed to disable ISC: %d\n", ret);
+		return ret;
+	}
+
+	usleep_range(1000, 2000);
+
+	ret = mpf_spi_write(spi, release_command, sizeof(release_command));
+	if (ret) {
+		dev_err(dev, "Failed to exit program mode: %d\n", ret);
+		return ret;
+	}
+
+	priv->program_mode = false;
+
+	return 0;
+}
+
+static const struct fpga_manager_ops mpf_ops = {
+	.state = mpf_ops_state,
+	.initial_header_size = 71,
+	.parse_header = mpf_ops_parse_header,
+	.write_init = mpf_ops_write_init,
+	.write = mpf_ops_write,
+	.write_complete = mpf_ops_write_complete,
+};
+
+static int mpf_probe(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+	struct fpga_manager *mgr;
+	struct mpf_priv *priv;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->spi = spi;
+
+	mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager",
+				     &mpf_ops, priv);
+
+	return PTR_ERR_OR_ZERO(mgr);
+}
+
+static const struct spi_device_id mpf_spi_ids[] = {
+	{ .name = "mpf-spi-fpga-mgr", },
+	{},
+};
+MODULE_DEVICE_TABLE(spi, mpf_spi_ids);
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_device_id mpf_of_ids[] = {
+	{ .compatible = "microchip,mpf-spi-fpga-mgr" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mpf_of_ids);
+#endif /* IS_ENABLED(CONFIG_OF) */
+
+static struct spi_driver mpf_driver = {
+	.probe = mpf_probe,
+	.id_table = mpf_spi_ids,
+	.driver = {
+		.name = "microchip_mpf_spi_fpga_mgr",
+		.of_match_table = of_match_ptr(mpf_of_ids),
+	},
+};
+
+module_spi_driver(mpf_driver);
+
+MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.35.1

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Xu Yilun]

On Thu, May 26, 2022 at 09:13:43PM +0300, Ivan Bornyakov wrote:
> Add support to the FPGA manager for programming Microchip Polarfire
> FPGAs over slave SPI interface with .dat formatted bitsream image.

From previous mail thread, there are still some hardware operations yet
to be clarified, so I may need a Reviewed-by from Conor.Dooley@microchip.com.

[...]


> +static int mpf_ops_parse_header(struct fpga_manager *mgr,
> +				struct fpga_image_info *info,
> +				const char *buf, size_t count)
> +{
> +	size_t component_size_byte_num, component_size_byte_off,
> +	       components_size_start, bitstream_start, i,
> +	       block_id_offset, block_start_offset;
> +	u8 header_size, blocks_num, block_id;

I think component_size_byte_num, component_size_byte_off, i should be size_t
are all simple numbers irrelated to data size, so maybe u32 is just good.

Thanks,
Yilun

> +	u32 block_start, component_size;
> +	u16 components_num;
> +
> +	if (!buf) {
> +		dev_err(&mgr->dev, "Image buffer is not provided\n");
> +		return -EINVAL;
> +	}
> +
> +	header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
> +	if (header_size > count) {
> +		info->header_size = header_size;
> +		return -EAGAIN;
> +	}
> +
> +	/*
> +	 * Go through look-up table to find out where actual bitstream starts
> +	 * and where sizes of components of the bitstream lies.
> +	 */
> +	blocks_num = *(buf + header_size - 1);
> +	block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
> +	block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
> +
> +	header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
> +	if (header_size > count) {
> +		info->header_size = header_size;
> +		return -EAGAIN;
> +	}
> +
> +	components_size_start = 0;
> +	bitstream_start = 0;
> +
> +	while (blocks_num--) {
> +		block_id = *(buf + block_id_offset);
> +		block_start = get_unaligned_le32(buf + block_start_offset);
> +
> +		switch (block_id) {
> +		case MPF_BITSTREAM_ID:
> +			info->header_size = bitstream_start = block_start;
> +			if (block_start > count)
> +				return -EAGAIN;
> +
> +			break;
> +		case MPF_COMPONENTS_SIZE_ID:
> +			components_size_start = block_start;
> +			break;
> +		default:
> +			break;
> +		}
> +
> +		if (bitstream_start && components_size_start)
> +			break;
> +
> +		block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
> +		block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
> +	}
> +
> +	if (!bitstream_start || !components_size_start) {
> +		dev_err(&mgr->dev, "Failed to parse header look-up table\n");
> +		return -EFAULT;
> +	}
> +
> +	/*
> +	 * Parse bitstream size.
> +	 * Sizes of components of the bitstream are 22-bits long placed next
> +	 * to each other. Image header should be extended by now up to where
> +	 * actual bitstream starts, so no need for overflow check anymore.
> +	 */
> +	components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
> +
> +	for (i = 0; i < components_num; i++) {
> +		component_size_byte_num =
> +			(i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
> +		component_size_byte_off =
> +			(i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
> +
> +		component_size = get_unaligned_le32(buf +
> +						    components_size_start +
> +						    component_size_byte_num);
> +		component_size >>= component_size_byte_off;
> +		component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
> +
> +		info->data_size += component_size * MPF_SPI_FRAME_SIZE;
> +	}
> +
> +	return 0;
> +}

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Conor.Dooley]

On 29/05/2022 13:39, Xu Yilun wrote:
> On Thu, May 26, 2022 at 09:13:43PM +0300, Ivan Bornyakov wrote:
>> Add support to the FPGA manager for programming Microchip Polarfire
>> FPGAs over slave SPI interface with .dat formatted bitsream image.
> 
> From previous mail thread, there are still some hardware operations yet
> to be clarified, so I may need a Reviewed-by from Conor.Dooley@microchip.com.

Yeah, was really busy last week. Planning on giving this version a go
tomorrow. I *think* I explained the reason the status check needed to be a
sync_transfer() but it hasn't been reflected in a comment yet.

I didn't know the answers to the two other questions & passed them on to the
designers of the hardware blocks - but both are traveling so not got a
response yet. There's one bit of clarification I'd like from your:

>>> +static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
>>> +{
>>> +	u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
>>> +	struct mpf_priv *priv = mgr->priv;
>>> +	struct device *dev = &mgr->dev;
>>> +	struct spi_device *spi;
>>> +	int ret, i;
>>> +
>>> +	if (count % MPF_SPI_FRAME_SIZE) {
>>> +		dev_err(dev, "Bitstream size is not a multiple of %d\n",
>>> +			MPF_SPI_FRAME_SIZE);
>>> +		return -EINVAL;
>>> +	}
>>> +
>>> +	spi = priv->spi;
>>> +
>>> +	for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
>>> +		memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
>>> +		       MPF_SPI_FRAME_SIZE);
>>> +
>>> +		ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
>>
>> As I mentioned before, is it possible we use spi_sync_transfer to avoid
>> memcpy the whole bitstream?
>
> Unfortunately, I didn't succeed with spi_sunc_transfer here. May be
> Conor or other folks with more insight on Microchip's HW would be able
> to eliminate this memcpy...

I understood this as being a question about why it was required to check
the status of the hardware between frames of the bitstream rather than
using spi_sync_transfer() to copy each frame back to back.

Is that correct?

Thanks,
Conor.


> 
> [...]
> 
> 
>> +static int mpf_ops_parse_header(struct fpga_manager *mgr,
>> +				struct fpga_image_info *info,
>> +				const char *buf, size_t count)
>> +{
>> +	size_t component_size_byte_num, component_size_byte_off,
>> +	       components_size_start, bitstream_start, i,
>> +	       block_id_offset, block_start_offset;
>> +	u8 header_size, blocks_num, block_id;
> 
> I think component_size_byte_num, component_size_byte_off, i should be size_t
> are all simple numbers irrelated to data size, so maybe u32 is just good.
> 
> Thanks,
> Yilun
> 
>> +	u32 block_start, component_size;
>> +	u16 components_num;
>> +
>> +	if (!buf) {
>> +		dev_err(&mgr->dev, "Image buffer is not provided\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
>> +	if (header_size > count) {
>> +		info->header_size = header_size;
>> +		return -EAGAIN;
>> +	}
>> +
>> +	/*
>> +	 * Go through look-up table to find out where actual bitstream starts
>> +	 * and where sizes of components of the bitstream lies.
>> +	 */
>> +	blocks_num = *(buf + header_size - 1);
>> +	block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
>> +	block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
>> +
>> +	header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
>> +	if (header_size > count) {
>> +		info->header_size = header_size;
>> +		return -EAGAIN;
>> +	}
>> +
>> +	components_size_start = 0;
>> +	bitstream_start = 0;
>> +
>> +	while (blocks_num--) {
>> +		block_id = *(buf + block_id_offset);
>> +		block_start = get_unaligned_le32(buf + block_start_offset);
>> +
>> +		switch (block_id) {
>> +		case MPF_BITSTREAM_ID:
>> +			info->header_size = bitstream_start = block_start;
>> +			if (block_start > count)
>> +				return -EAGAIN;
>> +
>> +			break;
>> +		case MPF_COMPONENTS_SIZE_ID:
>> +			components_size_start = block_start;
>> +			break;
>> +		default:
>> +			break;
>> +		}
>> +
>> +		if (bitstream_start && components_size_start)
>> +			break;
>> +
>> +		block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
>> +		block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
>> +	}
>> +
>> +	if (!bitstream_start || !components_size_start) {
>> +		dev_err(&mgr->dev, "Failed to parse header look-up table\n");
>> +		return -EFAULT;
>> +	}
>> +
>> +	/*
>> +	 * Parse bitstream size.
>> +	 * Sizes of components of the bitstream are 22-bits long placed next
>> +	 * to each other. Image header should be extended by now up to where
>> +	 * actual bitstream starts, so no need for overflow check anymore.
>> +	 */
>> +	components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
>> +
>> +	for (i = 0; i < components_num; i++) {
>> +		component_size_byte_num =
>> +			(i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
>> +		component_size_byte_off =
>> +			(i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
>> +
>> +		component_size = get_unaligned_le32(buf +
>> +						    components_size_start +
>> +						    component_size_byte_num);
>> +		component_size >>= component_size_byte_off;
>> +		component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
>> +
>> +		info->data_size += component_size * MPF_SPI_FRAME_SIZE;
>> +	}
>> +
>> +	return 0;
>> +}

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Ivan Bornyakov]

On Sun, May 29, 2022 at 01:03:10PM +0000, Conor.Dooley@microchip.com wrote:
> On 29/05/2022 13:39, Xu Yilun wrote:
> > On Thu, May 26, 2022 at 09:13:43PM +0300, Ivan Bornyakov wrote:
> >> Add support to the FPGA manager for programming Microchip Polarfire
> >> FPGAs over slave SPI interface with .dat formatted bitsream image.
> > 
> > From previous mail thread, there are still some hardware operations yet
> > to be clarified, so I may need a Reviewed-by from Conor.Dooley@microchip.com.
> 
> Yeah, was really busy last week. Planning on giving this version a go
> tomorrow. I *think* I explained the reason the status check needed to be a
> sync_transfer() but it hasn't been reflected in a comment yet.
> 
> I didn't know the answers to the two other questions & passed them on to the
> designers of the hardware blocks - but both are traveling so not got a
> response yet. There's one bit of clarification I'd like from your:
> 
> >>> +static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
> >>> +{
> >>> +	u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
> >>> +	struct mpf_priv *priv = mgr->priv;
> >>> +	struct device *dev = &mgr->dev;
> >>> +	struct spi_device *spi;
> >>> +	int ret, i;
> >>> +
> >>> +	if (count % MPF_SPI_FRAME_SIZE) {
> >>> +		dev_err(dev, "Bitstream size is not a multiple of %d\n",
> >>> +			MPF_SPI_FRAME_SIZE);
> >>> +		return -EINVAL;
> >>> +	}
> >>> +
> >>> +	spi = priv->spi;
> >>> +
> >>> +	for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
> >>> +		memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
> >>> +		       MPF_SPI_FRAME_SIZE);
> >>> +
> >>> +		ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
> >>
> >> As I mentioned before, is it possible we use spi_sync_transfer to avoid
> >> memcpy the whole bitstream?
> >
> > Unfortunately, I didn't succeed with spi_sunc_transfer here. May be
> > Conor or other folks with more insight on Microchip's HW would be able
> > to eliminate this memcpy...
> 
> I understood this as being a question about why it was required to check
> the status of the hardware between frames of the bitstream rather than
> using spi_sync_transfer() to copy each frame back to back.
> 
> Is that correct?

No.
The issue here is memcpy() a bitstream data frame to temporary buffer
before sending it to the device.
The reason for memcpy() is that we need to send to the device 17 bytes:
1st byte 0xEE and next 16 bytes - bitstream data.
Possible solution to eliminate memcpy() is to use spi_sync_transfer()
instead of spi_write() for sending bitstream frames, like so:

diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c
index 7579b0de119f..bf62ee7fd630 100644
--- a/drivers/fpga/microchip-spi.c
+++ b/drivers/fpga/microchip-spi.c
@@ -270,7 +270,8 @@ static int mpf_ops_write_init(struct fpga_manager *mgr,

 static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
 {
-       u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
+       u8 spi_frame_command = MPF_SPI_FRAME;
+       struct spi_transfer xfers[2] = { 0 };
        struct mpf_priv *priv = mgr->priv;
        struct device *dev = &mgr->dev;
        struct spi_device *spi;
@@ -285,10 +286,15 @@ static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count
        spi = priv->spi;

        for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
-               memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
-                      MPF_SPI_FRAME_SIZE);
+               xfers[0].tx_buf = &spi_frame_command;
+               xfers[0].len = 1;
+               xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
+               xfers[1].len = MPF_SPI_FRAME_SIZE;
+
+               ret = mpf_poll_status(spi, 0);
+               if (ret >= 0)
+                       ret = spi_sync_transfer(spi, xfers, 2);

-               ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
                if (ret) {
                        dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
                                i, count / MPF_SPI_FRAME_SIZE);

Note that this is not a working solution.

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Conor.Dooley]

On 29/05/2022 19:51, Ivan Bornyakov wrote:
> On Sun, May 29, 2022 at 01:03:10PM +0000, Conor.Dooley@microchip.com wrote:
>> On 29/05/2022 13:39, Xu Yilun wrote:
>>> On Thu, May 26, 2022 at 09:13:43PM +0300, Ivan Bornyakov wrote:
>>>> Add support to the FPGA manager for programming Microchip Polarfire
>>>> FPGAs over slave SPI interface with .dat formatted bitsream image.
>>>
>>> From previous mail thread, there are still some hardware operations yet
>>> to be clarified, so I may need a Reviewed-by from Conor.Dooley@microchip.com.
>>
>> Yeah, was really busy last week. Planning on giving this version a go
>> tomorrow. I *think* I explained the reason the status check needed to be a
>> sync_transfer() but it hasn't been reflected in a comment yet.
>>
>> I didn't know the answers to the two other questions & passed them on to the
>> designers of the hardware blocks - but both are traveling so not got a
>> response yet. There's one bit of clarification I'd like from your:
>>
>>>>> +static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
>>>>> +{
>>>>> +	u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
>>>>> +	struct mpf_priv *priv = mgr->priv;
>>>>> +	struct device *dev = &mgr->dev;
>>>>> +	struct spi_device *spi;
>>>>> +	int ret, i;
>>>>> +
>>>>> +	if (count % MPF_SPI_FRAME_SIZE) {
>>>>> +		dev_err(dev, "Bitstream size is not a multiple of %d\n",
>>>>> +			MPF_SPI_FRAME_SIZE);
>>>>> +		return -EINVAL;
>>>>> +	}
>>>>> +
>>>>> +	spi = priv->spi;
>>>>> +
>>>>> +	for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
>>>>> +		memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
>>>>> +		       MPF_SPI_FRAME_SIZE);
>>>>> +
>>>>> +		ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
>>>>
>>>> As I mentioned before, is it possible we use spi_sync_transfer to avoid
>>>> memcpy the whole bitstream?
>>>
>>> Unfortunately, I didn't succeed with spi_sunc_transfer here. May be
>>> Conor or other folks with more insight on Microchip's HW would be able
>>> to eliminate this memcpy...
>>
>> I understood this as being a question about why it was required to check
>> the status of the hardware between frames of the bitstream rather than
>> using spi_sync_transfer() to copy each frame back to back.
>>
>> Is that correct?
> 
> No.
> The issue here is memcpy() a bitstream data frame to temporary buffer
> before sending it to the device.
> The reason for memcpy() is that we need to send to the device 17 bytes:
> 1st byte 0xEE and next 16 bytes - bitstream data.
> Possible solution to eliminate memcpy() is to use spi_sync_transfer()
> instead of spi_write() for sending bitstream frames, like so:
> 
> diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c
> index 7579b0de119f..bf62ee7fd630 100644
> --- a/drivers/fpga/microchip-spi.c
> +++ b/drivers/fpga/microchip-spi.c
> @@ -270,7 +270,8 @@ static int mpf_ops_write_init(struct fpga_manager *mgr,
> 
>  static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
>  {
> -       u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
> +       u8 spi_frame_command = MPF_SPI_FRAME;
> +       struct spi_transfer xfers[2] = { 0 };
>         struct mpf_priv *priv = mgr->priv;
>         struct device *dev = &mgr->dev;
>         struct spi_device *spi;
> @@ -285,10 +286,15 @@ static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count
>         spi = priv->spi;
> 
>         for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
> -               memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
> -                      MPF_SPI_FRAME_SIZE);
> +               xfers[0].tx_buf = &spi_frame_command;
> +               xfers[0].len = 1;
> +               xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
> +               xfers[1].len = MPF_SPI_FRAME_SIZE;
> +
> +               ret = mpf_poll_status(spi, 0);
> +               if (ret >= 0)
> +                       ret = spi_sync_transfer(spi, xfers, 2);
> 
> -               ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
>                 if (ret) {
>                         dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
>                                 i, count / MPF_SPI_FRAME_SIZE);
> 
> Note that this is not a working solution.

Hmm, I'll take a look again. I did quickly do something like this
last Monday when I was trying to figure out what was meant, but I
omitted the mpf_poll_status() and that was enough to screw it up.
I'll take another look w/ this snippet.
Thanks,
Conor.

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Conor.Dooley]

On 26/05/2022 19:13, Ivan Bornyakov wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add support to the FPGA manager for programming Microchip Polarfire
> FPGAs over slave SPI interface with .dat formatted bitsream image.
> 
> Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
> ---
>   drivers/fpga/Kconfig         |   9 +
>   drivers/fpga/Makefile        |   1 +
>   drivers/fpga/microchip-spi.c | 386 +++++++++++++++++++++++++++++++++++
>   3 files changed, 396 insertions(+)
>   create mode 100644 drivers/fpga/microchip-spi.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 26025dbab353..75806ef5c9ea 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -248,4 +248,13 @@ config FPGA_MGR_VERSAL_FPGA
>            configure the programmable logic(PL).
> 
>            To compile this as a module, choose M here.
> +
> +config FPGA_MGR_MICROCHIP_SPI
> +       tristate "Microchip Polarfire SPI FPGA manager"
> +       depends on SPI
> +       help
> +         FPGA manager driver support for Microchip Polarfire FPGAs
> +         programming over slave SPI interface with .dat formatted
> +         bitstream image.
> +
>   endif # FPGA
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index e32bfa90f968..5425a15892df 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_FPGA_MGR_XILINX_SPI)     += xilinx-spi.o
>   obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
>   obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
>   obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)     += versal-fpga.o
> +obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI)   += microchip-spi.o
>   obj-$(CONFIG_ALTERA_PR_IP_CORE)                += altera-pr-ip-core.o
>   obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)   += altera-pr-ip-core-plat.o
> 
> diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c
> new file mode 100644
> index 000000000000..7579b0de119f
> --- /dev/null
> +++ b/drivers/fpga/microchip-spi.c
> @@ -0,0 +1,386 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Microchip Polarfire FPGA programming over slave SPI interface.
> + */
> +
> +#include <asm/unaligned.h>
> +#include <linux/delay.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/spi/spi.h>
> +
> +#define        MPF_SPI_ISC_ENABLE      0x0B
> +#define        MPF_SPI_ISC_DISABLE     0x0C
> +#define        MPF_SPI_READ_STATUS     0x00
> +#define        MPF_SPI_READ_DATA       0x01
> +#define        MPF_SPI_FRAME_INIT      0xAE
> +#define        MPF_SPI_FRAME           0xEE
> +#define        MPF_SPI_PRG_MODE        0x01
> +#define        MPF_SPI_RELEASE         0x23
> +
> +#define        MPF_SPI_FRAME_SIZE      16
> +
> +#define        MPF_HEADER_SIZE_OFFSET  24
> +#define        MPF_DATA_SIZE_OFFSET    55
> +
> +#define        MPF_LOOKUP_TABLE_RECORD_SIZE            9
> +#define        MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET        0
> +#define        MPF_LOOKUP_TABLE_BLOCK_START_OFFSET     1
> +
> +#define        MPF_COMPONENTS_SIZE_ID  5
> +#define        MPF_BITSTREAM_ID        8
> +
> +#define        MPF_BITS_PER_COMPONENT_SIZE     22
> +
> +#define        MPF_STATUS_POLL_RETRIES         10000
> +#define        MPF_STATUS_BUSY                 BIT(0)
> +#define        MPF_STATUS_READY                BIT(1)
> +#define        MPF_STATUS_SPI_VIOLATION        BIT(2)
> +#define        MPF_STATUS_SPI_ERROR            BIT(3)
> +
> +struct mpf_priv {
> +       struct spi_device *spi;
> +       bool program_mode;
> +};
> +
> +static int mpf_read_status(struct spi_device *spi)
> +{
> +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
> +       /*
> +        * Two identical SPI transfers are used for status reading.
> +        * The reason is that the first one can be inadequate.
> +        * We ignore it completely and use the second one.
> +        */
> +       struct spi_transfer xfers[] = {
> +               [0 ... 1] = {
> +                       .tx_buf = &status_command,
> +                       .rx_buf = &status,
> +                       .len = 1,
> +                       .cs_change = 1,
> +               }
> +       };

Hmm, I don't think that this is correct, or at least it is not
correct from the polarfire /soc/ perspective. I was told that
there was nothing different other than the envm between the
programming for both devices - but this is another situation
where I start to question that.

When I run this code, ISC enable /never/ passes - failing due
to timing out. I see something like this picture here:
https://i.imgur.com/EKhd1S3.png
You can see the 0x0B ISC enable coming through & then a status
check after it.

With the current code, the value of the "status" variable will
be 0x0, given you are overwriting the first MISO value with the
second. According to the hw guys, the spi hw status *should*
only be returned on MISO in the first byte after SS goes low.

If this is not the case for a non -soc part, which, as I said
before, I don't have a board with the SPI programmer exposed
for & I have been told is not the case then my comments can
just be ignored entirely & I'll have some head scratching to
do...

Thanks,
Conor.

> +       int ret = spi_sync_transfer(spi, xfers, 2);
> +
> +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
> +           (status & MPF_STATUS_SPI_ERROR))
> +               ret = -EIO;
> +
> +       return ret ? : status;
> +}
> +
> +static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
> +{
> +       struct mpf_priv *priv = mgr->priv;
> +       struct spi_device *spi;
> +       bool program_mode;
> +       int status;
> +
> +       spi = priv->spi;
> +       program_mode = priv->program_mode;
> +       status = mpf_read_status(spi);
> +
> +       if (!program_mode && !status)
> +               return FPGA_MGR_STATE_OPERATING;
> +
> +       return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static int mpf_ops_parse_header(struct fpga_manager *mgr,
> +                               struct fpga_image_info *info,
> +                               const char *buf, size_t count)
> +{
> +       size_t component_size_byte_num, component_size_byte_off,
> +              components_size_start, bitstream_start, i,
> +              block_id_offset, block_start_offset;
> +       u8 header_size, blocks_num, block_id;
> +       u32 block_start, component_size;
> +       u16 components_num;
> +
> +       if (!buf) {
> +               dev_err(&mgr->dev, "Image buffer is not provided\n");
> +               return -EINVAL;
> +       }
> +
> +       header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
> +       if (header_size > count) {
> +               info->header_size = header_size;
> +               return -EAGAIN;
> +       }
> +
> +       /*
> +        * Go through look-up table to find out where actual bitstream starts
> +        * and where sizes of components of the bitstream lies.
> +        */
> +       blocks_num = *(buf + header_size - 1);
> +       block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
> +       block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
> +
> +       header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
> +       if (header_size > count) {
> +               info->header_size = header_size;
> +               return -EAGAIN;
> +       }
> +
> +       components_size_start = 0;
> +       bitstream_start = 0;
> +
> +       while (blocks_num--) {
> +               block_id = *(buf + block_id_offset);
> +               block_start = get_unaligned_le32(buf + block_start_offset);
> +
> +               switch (block_id) {
> +               case MPF_BITSTREAM_ID:
> +                       info->header_size = bitstream_start = block_start;
> +                       if (block_start > count)
> +                               return -EAGAIN;
> +
> +                       break;
> +               case MPF_COMPONENTS_SIZE_ID:
> +                       components_size_start = block_start;
> +                       break;
> +               default:
> +                       break;
> +               }
> +
> +               if (bitstream_start && components_size_start)
> +                       break;
> +
> +               block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
> +               block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
> +       }
> +
> +       if (!bitstream_start || !components_size_start) {
> +               dev_err(&mgr->dev, "Failed to parse header look-up table\n");
> +               return -EFAULT;
> +       }
> +
> +       /*
> +        * Parse bitstream size.
> +        * Sizes of components of the bitstream are 22-bits long placed next
> +        * to each other. Image header should be extended by now up to where
> +        * actual bitstream starts, so no need for overflow check anymore.
> +        */
> +       components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
> +
> +       for (i = 0; i < components_num; i++) {
> +               component_size_byte_num =
> +                       (i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
> +               component_size_byte_off =
> +                       (i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
> +
> +               component_size = get_unaligned_le32(buf +
> +                                                   components_size_start +
> +                                                   component_size_byte_num);
> +               component_size >>= component_size_byte_off;
> +               component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
> +
> +               info->data_size += component_size * MPF_SPI_FRAME_SIZE;
> +       }
> +
> +       return 0;
> +}
> +
> +/* Poll HW status until busy bit is cleared and mask bits are set. */
> +static int mpf_poll_status(struct spi_device *spi, u8 mask)
> +{
> +       int status, retries = MPF_STATUS_POLL_RETRIES;
> +
> +       while (retries--) {
> +               status = mpf_read_status(spi);
> +               if (status < 0)
> +                       return status;
> +
> +               if (status & MPF_STATUS_BUSY)
> +                       continue;
> +
> +               if (!mask || (status & mask))
> +                       return status;
> +       }
> +
> +       return -EBUSY;
> +}
> +
> +static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size)
> +{
> +       int status = mpf_poll_status(spi, 0);
> +
> +       if (status < 0)
> +               return status;
> +
> +       return spi_write(spi, buf, buf_size);
> +}
> +
> +static int mpf_spi_write_then_read(struct spi_device *spi,
> +                                  const void *txbuf, size_t txbuf_size,
> +                                  void *rxbuf, size_t rxbuf_size)
> +{
> +       const u8 read_command[] = { MPF_SPI_READ_DATA };
> +       int ret;
> +
> +       ret = mpf_spi_write(spi, txbuf, txbuf_size);
> +       if (ret)
> +               return ret;
> +
> +       ret = mpf_poll_status(spi, MPF_STATUS_READY);
> +       if (ret < 0)
> +               return ret;
> +
> +       return spi_write_then_read(spi, read_command, sizeof(read_command),
> +                                  rxbuf, rxbuf_size);
> +}
> +
> +static int mpf_ops_write_init(struct fpga_manager *mgr,
> +                             struct fpga_image_info *info, const char *buf,
> +                             size_t count)
> +{
> +       const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE };
> +       const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
> +       struct mpf_priv *priv = mgr->priv;
> +       struct device *dev = &mgr->dev;
> +       struct spi_device *spi;
> +       u32 isc_ret = 0;
> +       int ret;
> +
> +       if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
> +               dev_err(dev, "Partial reconfiguration is not supported\n");
> +               return -EOPNOTSUPP;
> +       }
> +
> +       spi = priv->spi;
> +
> +       ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command),
> +                                     &isc_ret, sizeof(isc_ret));
> +       if (ret || isc_ret) {
> +               dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
> +                       ret, isc_ret);
> +               return -EFAULT;
> +       }
> +
> +       ret = mpf_spi_write(spi, program_mode, sizeof(program_mode));
> +       if (ret) {
> +               dev_err(dev, "Failed to enter program mode: %d\n", ret);
> +               return ret;
> +       }
> +
> +       priv->program_mode = true;
> +
> +       return 0;
> +}
> +
> +static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
> +{
> +       u8 tmp_buf[MPF_SPI_FRAME_SIZE + 1] = { MPF_SPI_FRAME, };
> +       struct mpf_priv *priv = mgr->priv;
> +       struct device *dev = &mgr->dev;
> +       struct spi_device *spi;
> +       int ret, i;
> +
> +       if (count % MPF_SPI_FRAME_SIZE) {
> +               dev_err(dev, "Bitstream size is not a multiple of %d\n",
> +                       MPF_SPI_FRAME_SIZE);
> +               return -EINVAL;
> +       }
> +
> +       spi = priv->spi;
> +
> +       for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
> +               memcpy(tmp_buf + 1, buf + i * MPF_SPI_FRAME_SIZE,
> +                      MPF_SPI_FRAME_SIZE);
> +
> +               ret = mpf_spi_write(spi, tmp_buf, sizeof(tmp_buf));
> +               if (ret) {
> +                       dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
> +                               i, count / MPF_SPI_FRAME_SIZE);
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int mpf_ops_write_complete(struct fpga_manager *mgr,
> +                                 struct fpga_image_info *info)
> +{
> +       const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE };
> +       const u8 release_command[] = { MPF_SPI_RELEASE };
> +       struct mpf_priv *priv = mgr->priv;
> +       struct device *dev = &mgr->dev;
> +       struct spi_device *spi;
> +       int ret;
> +
> +       spi = priv->spi;
> +
> +       ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command));
> +       if (ret) {
> +               dev_err(dev, "Failed to disable ISC: %d\n", ret);
> +               return ret;
> +       }
> +
> +       usleep_range(1000, 2000);
> +
> +       ret = mpf_spi_write(spi, release_command, sizeof(release_command));
> +       if (ret) {
> +               dev_err(dev, "Failed to exit program mode: %d\n", ret);
> +               return ret;
> +       }
> +
> +       priv->program_mode = false;
> +
> +       return 0;
> +}
> +
> +static const struct fpga_manager_ops mpf_ops = {
> +       .state = mpf_ops_state,
> +       .initial_header_size = 71,
> +       .parse_header = mpf_ops_parse_header,
> +       .write_init = mpf_ops_write_init,
> +       .write = mpf_ops_write,
> +       .write_complete = mpf_ops_write_complete,
> +};
> +
> +static int mpf_probe(struct spi_device *spi)
> +{
> +       struct device *dev = &spi->dev;
> +       struct fpga_manager *mgr;
> +       struct mpf_priv *priv;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->spi = spi;
> +
> +       mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager",
> +                                    &mpf_ops, priv);
> +
> +       return PTR_ERR_OR_ZERO(mgr);
> +}
> +
> +static const struct spi_device_id mpf_spi_ids[] = {
> +       { .name = "mpf-spi-fpga-mgr", },
> +       {},
> +};
> +MODULE_DEVICE_TABLE(spi, mpf_spi_ids);
> +
> +#if IS_ENABLED(CONFIG_OF)
> +static const struct of_device_id mpf_of_ids[] = {
> +       { .compatible = "microchip,mpf-spi-fpga-mgr" },
> +       {},
> +};
> +MODULE_DEVICE_TABLE(of, mpf_of_ids);
> +#endif /* IS_ENABLED(CONFIG_OF) */
> +
> +static struct spi_driver mpf_driver = {
> +       .probe = mpf_probe,
> +       .id_table = mpf_spi_ids,
> +       .driver = {
> +               .name = "microchip_mpf_spi_fpga_mgr",
> +               .of_match_table = of_match_ptr(mpf_of_ids),
> +       },
> +};
> +
> +module_spi_driver(mpf_driver);
> +
> +MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
> +MODULE_LICENSE("GPL");
> --
> 2.35.1
> 
> 

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Ivan Bornyakov]

On Mon, May 30, 2022 at 11:22:26AM +0000, Conor.Dooley@microchip.com wrote:
> On 26/05/2022 19:13, Ivan Bornyakov wrote:
> > +static int mpf_read_status(struct spi_device *spi)
> > +{
> > +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
> > +       /*
> > +        * Two identical SPI transfers are used for status reading.
> > +        * The reason is that the first one can be inadequate.
> > +        * We ignore it completely and use the second one.
> > +        */
> > +       struct spi_transfer xfers[] = {
> > +               [0 ... 1] = {
> > +                       .tx_buf = &status_command,
> > +                       .rx_buf = &status,
> > +                       .len = 1,
> > +                       .cs_change = 1,
> > +               }
> > +       };
> 
> Hmm, I don't think that this is correct, or at least it is not
> correct from the polarfire /soc/ perspective. I was told that
> there was nothing different other than the envm between the
> programming for both devices - but this is another situation
> where I start to question that.
> 
> When I run this code, ISC enable /never/ passes - failing due
> to timing out. I see something like this picture here:
> https://i.imgur.com/EKhd1S3.png
> You can see the 0x0B ISC enable coming through & then a status
> check after it.
> 
> With the current code, the value of the "status" variable will
> be 0x0, given you are overwriting the first MISO value with the
> second. According to the hw guys, the spi hw status *should*
> only be returned on MISO in the first byte after SS goes low.
> 
> If this is not the case for a non -soc part, which, as I said
> before, I don't have a board with the SPI programmer exposed
> for & I have been told is not the case then my comments can
> just be ignored entirely & I'll have some head scratching to
> do...
> 
> Thanks,
> Conor.
> 

If I understood correctly, SS doesn't alter between two status reading
transactions despite .cs_change = 1. May be adding some .cs_change_delay
to spi_transfer struct can help with that?

> > +       int ret = spi_sync_transfer(spi, xfers, 2);
> > +
> > +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
> > +           (status & MPF_STATUS_SPI_ERROR))
> > +               ret = -EIO;
> > +
> > +       return ret ? : status;
> > +}

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Conor.Dooley]

On 30/05/2022 13:07, Ivan Bornyakov wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, May 30, 2022 at 11:22:26AM +0000, Conor.Dooley@microchip.com wrote:
>> On 26/05/2022 19:13, Ivan Bornyakov wrote:
>>> +static int mpf_read_status(struct spi_device *spi)
>>> +{
>>> +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
>>> +       /*
>>> +        * Two identical SPI transfers are used for status reading.
>>> +        * The reason is that the first one can be inadequate.
>>> +        * We ignore it completely and use the second one.
>>> +        */
>>> +       struct spi_transfer xfers[] = {
>>> +               [0 ... 1] = {
>>> +                       .tx_buf = &status_command,
>>> +                       .rx_buf = &status,
>>> +                       .len = 1,
>>> +                       .cs_change = 1,
>>> +               }
>>> +       };
>>
>> Hmm, I don't think that this is correct, or at least it is not
>> correct from the polarfire /soc/ perspective. I was told that
>> there was nothing different other than the envm between the
>> programming for both devices - but this is another situation
>> where I start to question that.
>>
>> When I run this code, ISC enable /never/ passes - failing due
>> to timing out. I see something like this picture here:
>> https://i.imgur.com/EKhd1S3.png
>> You can see the 0x0B ISC enable coming through & then a status
>> check after it.
>>
>> With the current code, the value of the "status" variable will
>> be 0x0, given you are overwriting the first MISO value with the
>> second. According to the hw guys, the spi hw status *should*
>> only be returned on MISO in the first byte after SS goes low.
>>
>> If this is not the case for a non -soc part, which, as I said
>> before, I don't have a board with the SPI programmer exposed
>> for & I have been told is not the case then my comments can
>> just be ignored entirely & I'll have some head scratching to
>> do...
>>
>> Thanks,
>> Conor.
>>
> 
> If I understood correctly, SS doesn't alter between two status reading
> transactions despite .cs_change = 1. May be adding some .cs_change_delay
> to spi_transfer struct can help with that?

D-oh - bug in the spi controller driver :)
LGTM now, successfully programmed my PolarFire SoC with v12.
I'd almost suggest adding a compatible for it too - but since
the envm programming doesn't work I don't think that would be
correct.

Tested-by: Conor Dooley <conor.dooley@microchip.com>

With a small comment about why it's using spi_sync_transfer():
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
>>> +       int ret = spi_sync_transfer(spi, xfers, 2);
>>> +
>>> +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
>>> +           (status & MPF_STATUS_SPI_ERROR))
>>> +               ret = -EIO;
>>> +
>>> +       return ret ? : status;
>>> +}
> 

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Ivan Bornyakov]

On Mon, May 30, 2022 at 02:26:18PM +0000, Conor.Dooley@microchip.com wrote:
> On 30/05/2022 13:07, Ivan Bornyakov wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On Mon, May 30, 2022 at 11:22:26AM +0000, Conor.Dooley@microchip.com wrote:
> >> On 26/05/2022 19:13, Ivan Bornyakov wrote:
> >>> +static int mpf_read_status(struct spi_device *spi)
> >>> +{
> >>> +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
> >>> +       /*
> >>> +        * Two identical SPI transfers are used for status reading.
> >>> +        * The reason is that the first one can be inadequate.
> >>> +        * We ignore it completely and use the second one.
> >>> +        */
> >>> +       struct spi_transfer xfers[] = {
> >>> +               [0 ... 1] = {
> >>> +                       .tx_buf = &status_command,
> >>> +                       .rx_buf = &status,
> >>> +                       .len = 1,
> >>> +                       .cs_change = 1,
> >>> +               }
> >>> +       };
> >>
> >> Hmm, I don't think that this is correct, or at least it is not
> >> correct from the polarfire /soc/ perspective. I was told that
> >> there was nothing different other than the envm between the
> >> programming for both devices - but this is another situation
> >> where I start to question that.
> >>
> >> When I run this code, ISC enable /never/ passes - failing due
> >> to timing out. I see something like this picture here:
> >> https://i.imgur.com/EKhd1S3.png
> >> You can see the 0x0B ISC enable coming through & then a status
> >> check after it.
> >>
> >> With the current code, the value of the "status" variable will
> >> be 0x0, given you are overwriting the first MISO value with the
> >> second. According to the hw guys, the spi hw status *should*
> >> only be returned on MISO in the first byte after SS goes low.
> >>
> >> If this is not the case for a non -soc part, which, as I said
> >> before, I don't have a board with the SPI programmer exposed
> >> for & I have been told is not the case then my comments can
> >> just be ignored entirely & I'll have some head scratching to
> >> do...
> >>
> >> Thanks,
> >> Conor.
> >>
> > 
> > If I understood correctly, SS doesn't alter between two status reading
> > transactions despite .cs_change = 1. May be adding some .cs_change_delay
> > to spi_transfer struct can help with that?
> 
> D-oh - bug in the spi controller driver :)

So, no additional delay is needed?

> LGTM now, successfully programmed my PolarFire SoC with v12.
> I'd almost suggest adding a compatible for it too - but since
> the envm programming doesn't work I don't think that would be
> correct.
> 
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> 
> With a small comment about why it's using spi_sync_transfer():
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 

Thanks for your assistance, Conor!

> > 
> >>> +       int ret = spi_sync_transfer(spi, xfers, 2);
> >>> +
> >>> +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
> >>> +           (status & MPF_STATUS_SPI_ERROR))
> >>> +               ret = -EIO;
> >>> +
> >>> +       return ret ? : status;
> >>> +}
> > 
> 

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Conor.Dooley]

On 30/05/2022 15:26, Ivan Bornyakov wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, May 30, 2022 at 02:26:18PM +0000, Conor.Dooley@microchip.com wrote:
>> On 30/05/2022 13:07, Ivan Bornyakov wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Mon, May 30, 2022 at 11:22:26AM +0000, Conor.Dooley@microchip.com wrote:
>>>> On 26/05/2022 19:13, Ivan Bornyakov wrote:
>>>>> +static int mpf_read_status(struct spi_device *spi)
>>>>> +{
>>>>> +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
>>>>> +       /*
>>>>> +        * Two identical SPI transfers are used for status reading.
>>>>> +        * The reason is that the first one can be inadequate.
>>>>> +        * We ignore it completely and use the second one.
>>>>> +        */
>>>>> +       struct spi_transfer xfers[] = {
>>>>> +               [0 ... 1] = {
>>>>> +                       .tx_buf = &status_command,
>>>>> +                       .rx_buf = &status,
>>>>> +                       .len = 1,
>>>>> +                       .cs_change = 1,
>>>>> +               }
>>>>> +       };
>>>>
>>>> Hmm, I don't think that this is correct, or at least it is not
>>>> correct from the polarfire /soc/ perspective. I was told that
>>>> there was nothing different other than the envm between the
>>>> programming for both devices - but this is another situation
>>>> where I start to question that.
>>>>
>>>> When I run this code, ISC enable /never/ passes - failing due
>>>> to timing out. I see something like this picture here:
>>>> https://i.imgur.com/EKhd1S3.png
>>>> You can see the 0x0B ISC enable coming through & then a status
>>>> check after it.
>>>>
>>>> With the current code, the value of the "status" variable will
>>>> be 0x0, given you are overwriting the first MISO value with the
>>>> second. According to the hw guys, the spi hw status *should*
>>>> only be returned on MISO in the first byte after SS goes low.
>>>>
>>>> If this is not the case for a non -soc part, which, as I said
>>>> before, I don't have a board with the SPI programmer exposed
>>>> for & I have been told is not the case then my comments can
>>>> just be ignored entirely & I'll have some head scratching to
>>>> do...
>>>>
>>>> Thanks,
>>>> Conor.
>>>>
>>>
>>> If I understood correctly, SS doesn't alter between two status reading
>>> transactions despite .cs_change = 1. May be adding some .cs_change_delay
>>> to spi_transfer struct can help with that?
>>
>> D-oh - bug in the spi controller driver :)
> 
> So, no additional delay is needed?

Correct, programmed successfully without changing the delay.

>> LGTM now, successfully programmed my PolarFire SoC with v12.

Typo, this should be v13

>> I'd almost suggest adding a compatible for it too - but since
>> the envm programming doesn't work I don't think that would be
>> correct.
>>
>> Tested-by: Conor Dooley <conor.dooley@microchip.com>
>>
>> With a small comment about why it's using spi_sync_transfer():
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>
> 
> Thanks for your assistance, Conor!
> 
>>>
>>>>> +       int ret = spi_sync_transfer(spi, xfers, 2);
>>>>> +
>>>>> +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
>>>>> +           (status & MPF_STATUS_SPI_ERROR))
>>>>> +               ret = -EIO;
>>>>> +
>>>>> +       return ret ? : status;
>>>>> +}
>>>
>>
> 

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Conor.Dooley]

One last item, sorry!

On 30/05/2022 15:24, Conor Dooley wrote:
> On 30/05/2022 13:07, Ivan Bornyakov wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Mon, May 30, 2022 at 11:22:26AM +0000, Conor.Dooley@microchip.com wrote:
>>> On 26/05/2022 19:13, Ivan Bornyakov wrote:
>>>> +static int mpf_read_status(struct spi_device *spi)
>>>> +{
>>>> +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
>>>> +       /*
>>>> +        * Two identical SPI transfers are used for status reading.
>>>> +        * The reason is that the first one can be inadequate.
>>>> +        * We ignore it completely and use the second one.
>>>> +        */
>>>> +       struct spi_transfer xfers[] = {
>>>> +               [0 ... 1] = {
>>>> +                       .tx_buf = &status_command,
>>>> +                       .rx_buf = &status,
>>>> +                       .len = 1,
>>>> +                       .cs_change = 1,

Should cs_change be set for both messages or just the first?
 From reading the documentation, it looks like we only want it
for the first one.

https://elixir.bootlin.com/linux/latest/source/include/linux/spi/spi.h#L895

Thanks,
Conor.

>>>> +               }
>>>> +       };
>>>
>>> Hmm, I don't think that this is correct, or at least it is not
>>> correct from the polarfire /soc/ perspective. I was told that
>>> there was nothing different other than the envm between the
>>> programming for both devices - but this is another situation
>>> where I start to question that.
>>>
>>> When I run this code, ISC enable /never/ passes - failing due
>>> to timing out. I see something like this picture here:
>>> https://i.imgur.com/EKhd1S3.png
>>> You can see the 0x0B ISC enable coming through & then a status
>>> check after it.
>>>
>>> With the current code, the value of the "status" variable will
>>> be 0x0, given you are overwriting the first MISO value with the
>>> second. According to the hw guys, the spi hw status *should*
>>> only be returned on MISO in the first byte after SS goes low.
>>>
>>> If this is not the case for a non -soc part, which, as I said
>>> before, I don't have a board with the SPI programmer exposed
>>> for & I have been told is not the case then my comments can
>>> just be ignored entirely & I'll have some head scratching to
>>> do...
>>>
>>> Thanks,
>>> Conor.
>>>
>>
>> If I understood correctly, SS doesn't alter between two status reading
>> transactions despite .cs_change = 1. May be adding some .cs_change_delay
>> to spi_transfer struct can help with that?
> 
> D-oh - bug in the spi controller driver :)
> LGTM now, successfully programmed my PolarFire SoC with v12.
> I'd almost suggest adding a compatible for it too - but since
> the envm programming doesn't work I don't think that would be
> correct.
> 
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> 
> With a small comment about why it's using spi_sync_transfer():
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
>>
>>>> +       int ret = spi_sync_transfer(spi, xfers, 2);
>>>> +
>>>> +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
>>>> +           (status & MPF_STATUS_SPI_ERROR))
>>>> +               ret = -EIO;
>>>> +
>>>> +       return ret ? : status;
>>>> +}
>>
> 

Re: [PATCH v13 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager

[Ivan Bornyakov]

On Tue, May 31, 2022 at 10:53:07AM +0000, Conor.Dooley@microchip.com wrote:
> One last item, sorry!
> 
> On 30/05/2022 15:24, Conor Dooley wrote:
> > On 30/05/2022 13:07, Ivan Bornyakov wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, May 30, 2022 at 11:22:26AM +0000, Conor.Dooley@microchip.com wrote:
> >>> On 26/05/2022 19:13, Ivan Bornyakov wrote:
> >>>> +static int mpf_read_status(struct spi_device *spi)
> >>>> +{
> >>>> +       u8 status = 0, status_command = MPF_SPI_READ_STATUS;
> >>>> +       /*
> >>>> +        * Two identical SPI transfers are used for status reading.
> >>>> +        * The reason is that the first one can be inadequate.
> >>>> +        * We ignore it completely and use the second one.
> >>>> +        */
> >>>> +       struct spi_transfer xfers[] = {
> >>>> +               [0 ... 1] = {
> >>>> +                       .tx_buf = &status_command,
> >>>> +                       .rx_buf = &status,
> >>>> +                       .len = 1,
> >>>> +                       .cs_change = 1,
> 
> Should cs_change be set for both messages or just the first?
>  From reading the documentation, it looks like we only want it
> for the first one.
> 
> https://elixir.bootlin.com/linux/latest/source/include/linux/spi/spi.h#L895
> 
> Thanks,
> Conor.
> 

You're right, I've overlooked that moment.

> >>>> +               }
> >>>> +       };
> >>>
> >>> Hmm, I don't think that this is correct, or at least it is not
> >>> correct from the polarfire /soc/ perspective. I was told that
> >>> there was nothing different other than the envm between the
> >>> programming for both devices - but this is another situation
> >>> where I start to question that.
> >>>
> >>> When I run this code, ISC enable /never/ passes - failing due
> >>> to timing out. I see something like this picture here:
> >>> https://i.imgur.com/EKhd1S3.png
> >>> You can see the 0x0B ISC enable coming through & then a status
> >>> check after it.
> >>>
> >>> With the current code, the value of the "status" variable will
> >>> be 0x0, given you are overwriting the first MISO value with the
> >>> second. According to the hw guys, the spi hw status *should*
> >>> only be returned on MISO in the first byte after SS goes low.
> >>>
> >>> If this is not the case for a non -soc part, which, as I said
> >>> before, I don't have a board with the SPI programmer exposed
> >>> for & I have been told is not the case then my comments can
> >>> just be ignored entirely & I'll have some head scratching to
> >>> do...
> >>>
> >>> Thanks,
> >>> Conor.
> >>>
> >>
> >> If I understood correctly, SS doesn't alter between two status reading
> >> transactions despite .cs_change = 1. May be adding some .cs_change_delay
> >> to spi_transfer struct can help with that?
> > 
> > D-oh - bug in the spi controller driver :)
> > LGTM now, successfully programmed my PolarFire SoC with v12.
> > I'd almost suggest adding a compatible for it too - but since
> > the envm programming doesn't work I don't think that would be
> > correct.
> > 
> > Tested-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > With a small comment about why it's using spi_sync_transfer():
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> >>
> >>>> +       int ret = spi_sync_transfer(spi, xfers, 2);
> >>>> +
> >>>> +       if ((status & MPF_STATUS_SPI_VIOLATION) ||
> >>>> +           (status & MPF_STATUS_SPI_ERROR))
> >>>> +               ret = -EIO;
> >>>> +
> >>>> +       return ret ? : status;
> >>>> +}
> >>
> > 
> 

[PATCH v13 3/3] dt-bindings: fpga: add binding doc for microchip-spi fpga mgr

[Ivan Bornyakov]

Add Device Tree Binding doc for Microchip Polarfire FPGA Manager using
slave SPI to load .dat formatted bitstream image.

Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../fpga/microchip,mpf-spi-fpga-mgr.yaml      | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml

diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
new file mode 100644
index 000000000000..aee45cb15592
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Polarfire FPGA manager.
+
+maintainers:
+  - Ivan Bornyakov <i.bornyakov@metrotek.ru>
+
+description:
+  Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
+  load the bitstream in .dat format.
+
+properties:
+  compatible:
+    enum:
+      - microchip,mpf-spi-fpga-mgr
+
+  reg:
+    description: SPI chip select
+    maxItems: 1
+
+  spi-max-frequency: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            fpga_mgr@0 {
+                    compatible = "microchip,mpf-spi-fpga-mgr";
+                    spi-max-frequency = <20000000>;
+                    reg = <0>;
+            };
+    };
-- 
2.35.1