From: Fenghua Yu <fenghua.yu@intel.com> To: "Thomas Gleixner" <tglx@linutronix.de>, "Borislav Petkov" <bp@alien8.de>, "Ingo Molnar" <mingo@redhat.com>, "H Peter Anvin" <hpa@zytor.com>, "Andy Lutomirski" <luto@kernel.org>, "Jean-Philippe Brucker" <jean-philippe@linaro.org>, "Christoph Hellwig" <hch@infradead.org>, "Peter Zijlstra" <peterz@infradead.org>, "David Woodhouse" <dwmw2@infradead.org>, "Lu Baolu" <baolu.lu@linux.intel.com>, "Dave Hansen" <dave.hansen@intel.com>, "Tony Luck" <tony.luck@intel.com>, "Randy Dunlap" <rdunlap@infradead.org>, "Ashok Raj" <ashok.raj@intel.com>, "Jacob Jun Pan" <jacob.jun.pan@intel.com>, "Dave Jiang" <dave.jiang@intel.com>, "Sohil Mehta" <sohil.mehta@intel.com>, "Ravi V Shankar" <ravi.v.shankar@intel.com> Cc: "linux-kernel" <linux-kernel@vger.kernel.org>, "x86" <x86@kernel.org>, iommu@lists.linux-foundation.org, Yu-cheng Yu <yu-cheng.yu@intel.com>, Fenghua Yu <fenghua.yu@intel.com> Subject: [PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Date: Tue, 15 Sep 2020 09:30:09 -0700 [thread overview] Message-ID: <1600187413-163670-6-git-send-email-fenghua.yu@intel.com> (raw) In-Reply-To: <1600187413-163670-1-git-send-email-fenghua.yu@intel.com> From: Yu-cheng Yu <yu-cheng.yu@intel.com> ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Co-developed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> --- v2: - Modify the commit message (Thomas) arch/x86/include/asm/fpu/types.h | 11 ++++++++++- arch/x86/include/asm/fpu/xstate.h | 2 +- arch/x86/kernel/fpu/xstate.c | 6 +++++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h index c87364ea6446..f5a38a5f3ae1 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -114,7 +114,7 @@ enum xfeature { XFEATURE_Hi16_ZMM, XFEATURE_PT_UNIMPLEMENTED_SO_FAR, XFEATURE_PKRU, - XFEATURE_RSRVD_COMP_10, + XFEATURE_PASID, XFEATURE_RSRVD_COMP_11, XFEATURE_RSRVD_COMP_12, XFEATURE_RSRVD_COMP_13, @@ -134,6 +134,7 @@ enum xfeature { #define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM) #define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR) #define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU) +#define XFEATURE_MASK_PASID (1 << XFEATURE_PASID) #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE) @@ -256,6 +257,14 @@ struct arch_lbr_state { struct lbr_entry entries[]; } __packed; +/* + * State component 10 is supervisor state used for context-switching the + * PASID state. + */ +struct ia32_pasid_state { + u64 pasid; +} __packed; + struct xstate_header { u64 xfeatures; u64 xcomp_bv; diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h index 14ab815132d4..47a92232d595 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -35,7 +35,7 @@ XFEATURE_MASK_BNDCSR) /* All currently supported supervisor features */ -#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (0) +#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID) /* * A supervisor state component may not always contain valuable information, diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 038e19c0019e..67f1a03b9b23 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -37,6 +37,7 @@ static const char *xfeature_names[] = "AVX-512 ZMM_Hi256" , "Processor Trace (unused)" , "Protection Keys User registers", + "PASID state", "unknown xstate feature" , }; @@ -51,6 +52,7 @@ static short xsave_cpuid_features[] __initdata = { X86_FEATURE_AVX512F, X86_FEATURE_INTEL_PT, X86_FEATURE_PKU, + X86_FEATURE_ENQCMD, }; /* @@ -318,6 +320,7 @@ static void __init print_xstate_features(void) print_xstate_feature(XFEATURE_MASK_ZMM_Hi256); print_xstate_feature(XFEATURE_MASK_Hi16_ZMM); print_xstate_feature(XFEATURE_MASK_PKRU); + print_xstate_feature(XFEATURE_MASK_PASID); } /* @@ -592,6 +595,7 @@ static void check_xstate_against_struct(int nr) XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state); XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state); XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state); + XCHECK_SZ(sz, nr, XFEATURE_PASID, struct ia32_pasid_state); /* * Make *SURE* to add any feature numbers in below if @@ -601,7 +605,7 @@ static void check_xstate_against_struct(int nr) if ((nr < XFEATURE_YMM) || (nr >= XFEATURE_MAX) || (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR) || - ((nr >= XFEATURE_RSRVD_COMP_10) && (nr <= XFEATURE_LBR))) { + ((nr >= XFEATURE_RSRVD_COMP_11) && (nr <= XFEATURE_LBR))) { WARN_ONCE(1, "no structure for xstate: %d\n", nr); XSTATE_WARN_ON(1); } -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Fenghua Yu <fenghua.yu@intel.com> To: "Thomas Gleixner" <tglx@linutronix.de>, "Borislav Petkov" <bp@alien8.de>, "Ingo Molnar" <mingo@redhat.com>, "H Peter Anvin" <hpa@zytor.com>, "Andy Lutomirski" <luto@kernel.org>, "Jean-Philippe Brucker" <jean-philippe@linaro.org>, "Christoph Hellwig" <hch@infradead.org>, "Peter Zijlstra" <peterz@infradead.org>, "David Woodhouse" <dwmw2@infradead.org>, "Lu Baolu" <baolu.lu@linux.intel.com>, "Dave Hansen" <dave.hansen@intel.com>, "Tony Luck" <tony.luck@intel.com>, "Randy Dunlap" <rdunlap@infradead.org>, "Ashok Raj" <ashok.raj@intel.com>, "Jacob Jun Pan" <jacob.jun.pan@intel.com>, "Dave Jiang" <dave.jiang@intel.com>, "Sohil Mehta" <sohil.mehta@intel.com>, "Ravi V Shankar" <ravi.v.shankar@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com>, iommu@lists.linux-foundation.org, x86 <x86@kernel.org>, Yu-cheng Yu <yu-cheng.yu@intel.com>, linux-kernel <linux-kernel@vger.kernel.org> Subject: [PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Date: Tue, 15 Sep 2020 09:30:09 -0700 [thread overview] Message-ID: <1600187413-163670-6-git-send-email-fenghua.yu@intel.com> (raw) In-Reply-To: <1600187413-163670-1-git-send-email-fenghua.yu@intel.com> From: Yu-cheng Yu <yu-cheng.yu@intel.com> ENQCMD instruction reads PASID from IA32_PASID MSR. The MSR is stored in the task's supervisor FPU PASID state and is context switched by XSAVES/XRSTORS. Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Co-developed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> --- v2: - Modify the commit message (Thomas) arch/x86/include/asm/fpu/types.h | 11 ++++++++++- arch/x86/include/asm/fpu/xstate.h | 2 +- arch/x86/kernel/fpu/xstate.c | 6 +++++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h index c87364ea6446..f5a38a5f3ae1 100644 --- a/arch/x86/include/asm/fpu/types.h +++ b/arch/x86/include/asm/fpu/types.h @@ -114,7 +114,7 @@ enum xfeature { XFEATURE_Hi16_ZMM, XFEATURE_PT_UNIMPLEMENTED_SO_FAR, XFEATURE_PKRU, - XFEATURE_RSRVD_COMP_10, + XFEATURE_PASID, XFEATURE_RSRVD_COMP_11, XFEATURE_RSRVD_COMP_12, XFEATURE_RSRVD_COMP_13, @@ -134,6 +134,7 @@ enum xfeature { #define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM) #define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR) #define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU) +#define XFEATURE_MASK_PASID (1 << XFEATURE_PASID) #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR) #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE) @@ -256,6 +257,14 @@ struct arch_lbr_state { struct lbr_entry entries[]; } __packed; +/* + * State component 10 is supervisor state used for context-switching the + * PASID state. + */ +struct ia32_pasid_state { + u64 pasid; +} __packed; + struct xstate_header { u64 xfeatures; u64 xcomp_bv; diff --git a/arch/x86/include/asm/fpu/xstate.h b/arch/x86/include/asm/fpu/xstate.h index 14ab815132d4..47a92232d595 100644 --- a/arch/x86/include/asm/fpu/xstate.h +++ b/arch/x86/include/asm/fpu/xstate.h @@ -35,7 +35,7 @@ XFEATURE_MASK_BNDCSR) /* All currently supported supervisor features */ -#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (0) +#define XFEATURE_MASK_SUPERVISOR_SUPPORTED (XFEATURE_MASK_PASID) /* * A supervisor state component may not always contain valuable information, diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 038e19c0019e..67f1a03b9b23 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -37,6 +37,7 @@ static const char *xfeature_names[] = "AVX-512 ZMM_Hi256" , "Processor Trace (unused)" , "Protection Keys User registers", + "PASID state", "unknown xstate feature" , }; @@ -51,6 +52,7 @@ static short xsave_cpuid_features[] __initdata = { X86_FEATURE_AVX512F, X86_FEATURE_INTEL_PT, X86_FEATURE_PKU, + X86_FEATURE_ENQCMD, }; /* @@ -318,6 +320,7 @@ static void __init print_xstate_features(void) print_xstate_feature(XFEATURE_MASK_ZMM_Hi256); print_xstate_feature(XFEATURE_MASK_Hi16_ZMM); print_xstate_feature(XFEATURE_MASK_PKRU); + print_xstate_feature(XFEATURE_MASK_PASID); } /* @@ -592,6 +595,7 @@ static void check_xstate_against_struct(int nr) XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state); XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state); XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state); + XCHECK_SZ(sz, nr, XFEATURE_PASID, struct ia32_pasid_state); /* * Make *SURE* to add any feature numbers in below if @@ -601,7 +605,7 @@ static void check_xstate_against_struct(int nr) if ((nr < XFEATURE_YMM) || (nr >= XFEATURE_MAX) || (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR) || - ((nr >= XFEATURE_RSRVD_COMP_10) && (nr <= XFEATURE_LBR))) { + ((nr >= XFEATURE_RSRVD_COMP_11) && (nr <= XFEATURE_LBR))) { WARN_ONCE(1, "no structure for xstate: %d\n", nr); XSTATE_WARN_ON(1); } -- 2.19.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-09-15 22:15 UTC|newest] Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-15 16:30 [PATCH v8 0/9] x86: tag application address space for devices Fenghua Yu 2020-09-15 16:30 ` [PATCH v8 1/9] drm, iommu: Change type of pasid to u32 Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu 2020-09-15 16:30 ` [PATCH v8 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu 2020-09-15 16:30 ` Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu 2020-09-15 16:30 ` [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu 2020-09-17 7:53 ` Borislav Petkov 2020-09-17 7:53 ` Borislav Petkov 2020-09-17 14:56 ` Raj, Ashok 2020-09-17 14:56 ` Raj, Ashok 2020-09-17 17:18 ` Borislav Petkov 2020-09-17 17:18 ` Borislav Petkov 2020-09-17 17:22 ` Raj, Ashok 2020-09-17 17:22 ` Raj, Ashok 2020-09-17 17:30 ` Borislav Petkov 2020-09-17 17:30 ` Borislav Petkov 2020-09-18 16:22 ` Fenghua Yu 2020-09-18 16:22 ` Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Ashok Raj 2020-09-15 16:30 ` [PATCH v8 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu 2020-09-15 16:30 ` Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu 2020-09-15 16:30 ` Fenghua Yu [this message] 2020-09-15 16:30 ` [PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] x86/fpu/xstate: Add supervisor PASID state for ENQCMD tip-bot2 for Yu-cheng Yu 2020-09-15 16:30 ` [PATCH v8 6/9] x86/msr-index: Define IA32_PASID MSR Fenghua Yu 2020-09-15 16:30 ` Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] x86/msr-index: Define an " tip-bot2 for Fenghua Yu 2020-09-15 16:30 ` [PATCH v8 7/9] mm: Define pasid in mm Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] mm: Add a pasid member to struct mm_struct tip-bot2 for Fenghua Yu 2020-09-15 16:30 ` [PATCH v8 8/9] x86/cpufeatures: Mark ENQCMD as disabled when configured out Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu 2020-09-15 16:30 ` [PATCH v8 9/9] x86/mmu: Allocate/free PASID Fenghua Yu 2020-09-15 16:30 ` Fenghua Yu 2020-09-18 7:42 ` [tip: x86/pasid] x86/mmu: Allocate/free a PASID tip-bot2 for Fenghua Yu 2021-05-29 9:17 ` [PATCH] x86/cpufeatures: Force disable X86_FEATURE_ENQCMD and remove update_pasid() Thomas Gleixner 2021-05-29 9:17 ` Thomas Gleixner 2021-05-31 8:43 ` Borislav Petkov 2021-05-31 8:43 ` Borislav Petkov 2021-05-31 10:16 ` Thomas Gleixner 2021-05-31 10:16 ` Thomas Gleixner 2021-06-02 20:37 ` Luck, Tony 2021-06-02 20:37 ` Luck, Tony 2021-06-03 17:31 ` Andy Lutomirski 2021-06-03 17:31 ` Andy Lutomirski 2021-06-09 17:32 ` Luck, Tony 2021-06-09 17:32 ` Luck, Tony 2021-06-09 23:34 ` Andy Lutomirski 2021-06-09 23:34 ` Andy Lutomirski 2021-06-25 15:46 ` Luck, Tony 2021-06-25 15:46 ` Luck, Tony 2021-06-02 10:14 ` Borislav Petkov 2021-06-02 10:14 ` Borislav Petkov 2021-06-02 10:20 ` Thomas Gleixner 2021-06-02 10:20 ` Thomas Gleixner 2021-06-03 11:20 ` Vinod Koul 2021-06-03 11:20 ` Vinod Koul 2021-06-03 11:42 ` Borislav Petkov 2021-06-03 11:42 ` Borislav Petkov 2021-06-03 12:47 ` Vinod Koul 2021-06-03 12:47 ` Vinod Koul 2021-06-03 14:33 ` Borislav Petkov 2021-06-03 14:33 ` Borislav Petkov 2021-06-02 19:49 ` [tip: x86/urgent] " tip-bot2 for Thomas Gleixner 2021-06-03 14:38 ` tip-bot2 for Thomas Gleixner 2020-09-16 8:06 ` [PATCH v8 0/9] x86: tag application address space for devices Joerg Roedel 2020-09-16 8:06 ` Joerg Roedel 2020-09-17 23:53 ` Fenghua Yu 2020-09-17 23:53 ` Fenghua Yu
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