* [PATCH V2 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy @ 2020-09-22 10:15 Piyush Mehta 2020-09-22 10:15 ` [PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller Piyush Mehta 2020-09-22 10:15 ` [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta 0 siblings, 2 replies; 6+ messages in thread From: Piyush Mehta @ 2020-09-22 10:15 UTC (permalink / raw) To: axboe, p.zabel, robh+dt Cc: linux-ide, devicetree, linux-kernel, git, sgoud, michal.simek, Piyush Mehta This patch series updates the ceva driver to add support for Xilinx GT phy. This also updates the documentation with the device tree binding required for working with Xilinx GT phy. --- Changes in V2: - Added backward compatibility with the older sequence of the CEVA controller. - Update dt-bindings document: To make phy and reset properties optional. - Remove rst_names property. --- Piyush Mehta (2): dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller ata: ahci: ceva: Update the driver to support xilinx GT phy .../devicetree/bindings/ata/ahci-ceva.txt | 6 ++++ drivers/ata/ahci_ceva.c | 39 ++++++++++++++++++++-- 2 files changed, 43 insertions(+), 2 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller 2020-09-22 10:15 [PATCH V2 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta @ 2020-09-22 10:15 ` Piyush Mehta 2020-09-29 18:09 ` Rob Herring 2020-09-22 10:15 ` [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta 1 sibling, 1 reply; 6+ messages in thread From: Piyush Mehta @ 2020-09-22 10:15 UTC (permalink / raw) To: axboe, p.zabel, robh+dt Cc: linux-ide, devicetree, linux-kernel, git, sgoud, michal.simek, Piyush Mehta This patch updates the documentation for the CEVA controller for adding the optional properties for 'phys' and 'resets'. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> --- Documentation/devicetree/bindings/ata/ahci-ceva.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt index 7561cc4..da423eb 100644 --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt @@ -38,6 +38,9 @@ Required properties: Optional properties: - ceva,broken-gen2: limit to gen1 speed instead of gen2. + - phys: phandle for the PHY device + - phy-names: Should be "sata-phy" + - resets: phandle to the reset controller for the SATA IP Examples: ahci@fd0c0000 { @@ -56,4 +59,7 @@ Examples: ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; ceva,broken-gen2; + phy-names = "sata-phy"; + phys = <&psgtr 1 PHY_TYPE_SATA 1 1>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller 2020-09-22 10:15 ` [PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller Piyush Mehta @ 2020-09-29 18:09 ` Rob Herring 0 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2020-09-29 18:09 UTC (permalink / raw) To: Piyush Mehta Cc: axboe, p.zabel, linux-ide, devicetree, linux-kernel, git, sgoud, michal.simek On Tue, Sep 22, 2020 at 03:45:12PM +0530, Piyush Mehta wrote: > This patch updates the documentation for the CEVA controller for adding > the optional properties for 'phys' and 'resets'. > > Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> > --- > Documentation/devicetree/bindings/ata/ahci-ceva.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt > index 7561cc4..da423eb 100644 > --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt > +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt > @@ -38,6 +38,9 @@ Required properties: > > Optional properties: > - ceva,broken-gen2: limit to gen1 speed instead of gen2. > + - phys: phandle for the PHY device > + - phy-names: Should be "sata-phy" Not really a useful name. There's not much point to *-names when only 1. > + - resets: phandle to the reset controller for the SATA IP > > Examples: > ahci@fd0c0000 { > @@ -56,4 +59,7 @@ Examples: > ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; > ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; > ceva,broken-gen2; > + phy-names = "sata-phy"; > + phys = <&psgtr 1 PHY_TYPE_SATA 1 1>; > + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; > }; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy 2020-09-22 10:15 [PATCH V2 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta 2020-09-22 10:15 ` [PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller Piyush Mehta @ 2020-09-22 10:15 ` Piyush Mehta 2020-09-22 12:05 ` Philipp Zabel 1 sibling, 1 reply; 6+ messages in thread From: Piyush Mehta @ 2020-09-22 10:15 UTC (permalink / raw) To: axboe, p.zabel, robh+dt Cc: linux-ide, devicetree, linux-kernel, git, sgoud, michal.simek, Piyush Mehta SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for SATA controller, the below sequence is expected. 1. Assert the SATA controller reset. 2. Configure the xilinx GT phy lane for SATA controller (phy_init). 3. De-assert the SATA controller reset. 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). The ahci_platform_enable_resources() by default does the phy_init() and phy_power_on() but the default sequence doesn't work with Xilinx platforms. Because of this reason, updated the driver to support the new sequence. Added is_rst_ctrl flag, for backward compatibility with the older sequence. If the reset controller is not available, then the SATA controller will configure with the older sequences. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> --- drivers/ata/ahci_ceva.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index b10fd4c..c704906 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c @@ -12,6 +12,7 @@ #include <linux/module.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/reset.h> #include "ahci.h" /* Vendor Specific Register Offsets */ @@ -87,6 +88,7 @@ struct ceva_ahci_priv { u32 axicc; bool is_cci_enabled; int flags; + struct reset_control *rst; }; static unsigned int ceva_ahci_read_id(struct ata_device *dev, @@ -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev) struct ahci_host_priv *hpriv; struct ceva_ahci_priv *cevapriv; enum dev_dma_attr attr; - int rc; + int rc, i, is_rst_ctrl = 1; cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); if (!cevapriv) @@ -202,14 +204,47 @@ static int ceva_ahci_probe(struct platform_device *pdev) cevapriv->ahci_pdev = pdev; + cevapriv->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(cevapriv->rst)) { + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get reset: %ld\n", + PTR_ERR(cevapriv->rst)); + is_rst_ctrl = 0; + } + hpriv = ahci_platform_get_resources(pdev, 0); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); + if (is_rst_ctrl) + rc = ahci_platform_enable_clks(hpriv); + else + rc = ahci_platform_enable_resources(hpriv); - rc = ahci_platform_enable_resources(hpriv); if (rc) return rc; + if (is_rst_ctrl) { + /* Assert the controller reset */ + reset_control_assert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_init(hpriv->phys[i]); + if (rc) + return rc; + } + + /* De-assert the controller reset */ + reset_control_deassert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_power_on(hpriv->phys[i]); + if (rc) { + phy_exit(hpriv->phys[i]); + return rc; + } + } + } + if (of_property_read_bool(np, "ceva,broken-gen2")) cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy 2020-09-22 10:15 ` [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta @ 2020-09-22 12:05 ` Philipp Zabel 2020-09-23 5:45 ` Piyush Mehta 0 siblings, 1 reply; 6+ messages in thread From: Philipp Zabel @ 2020-09-22 12:05 UTC (permalink / raw) To: Piyush Mehta, axboe, robh+dt Cc: linux-ide, devicetree, linux-kernel, git, sgoud, michal.simek On Tue, 2020-09-22 at 15:45 +0530, Piyush Mehta wrote: > SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy > which has 4 GT lanes and can used by 4 peripherals at a time. > SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure > the GT lane for SATA controller, the below sequence is expected. > > 1. Assert the SATA controller reset. > 2. Configure the xilinx GT phy lane for SATA controller (phy_init). > 3. De-assert the SATA controller reset. > 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). > > The ahci_platform_enable_resources() by default does the phy_init() > and phy_power_on() but the default sequence doesn't work with Xilinx > platforms. Because of this reason, updated the driver to support the > new sequence. > > Added is_rst_ctrl flag, for backward compatibility with the older > sequence. If the reset controller is not available, then the SATA > controller will configure with the older sequences. > > Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> > --- > drivers/ata/ahci_ceva.c | 39 +++++++++++++++++++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 2 deletions(-) > > diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c > index b10fd4c..c704906 100644 > --- a/drivers/ata/ahci_ceva.c > +++ b/drivers/ata/ahci_ceva.c > @@ -12,6 +12,7 @@ > #include <linux/module.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > +#include <linux/reset.h> > #include "ahci.h" > > /* Vendor Specific Register Offsets */ > @@ -87,6 +88,7 @@ struct ceva_ahci_priv { > u32 axicc; > bool is_cci_enabled; > int flags; > + struct reset_control *rst; > }; > > static unsigned int ceva_ahci_read_id(struct ata_device *dev, > @@ -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev) > struct ahci_host_priv *hpriv; > struct ceva_ahci_priv *cevapriv; > enum dev_dma_attr attr; > - int rc; > + int rc, i, is_rst_ctrl = 1; > > cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); > if (!cevapriv) > @@ -202,14 +204,47 @@ static int ceva_ahci_probe(struct platform_device *pdev) > > cevapriv->ahci_pdev = pdev; > > + cevapriv->rst = devm_reset_control_get(&pdev->dev, NULL); Please use devm_reset_control_get_optional_exclusive() > + if (IS_ERR(cevapriv->rst)) { > + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER) > + dev_err(&pdev->dev, "failed to get reset: %ld\n", > + PTR_ERR(cevapriv->rst)); > + is_rst_ctrl = 0; is_rst_ctrl will not be required then. > + } > + > hpriv = ahci_platform_get_resources(pdev, 0); > if (IS_ERR(hpriv)) > return PTR_ERR(hpriv); > + if (is_rst_ctrl) > + rc = ahci_platform_enable_clks(hpriv); > + else > + rc = ahci_platform_enable_resources(hpriv); > > - rc = ahci_platform_enable_resources(hpriv); > if (rc) > return rc; > > + if (is_rst_ctrl) { This can just be "if (cevapriv->rst)" > + /* Assert the controller reset */ > + reset_control_assert(cevapriv->rst); > + > + for (i = 0; i < hpriv->nports; i++) { > + rc = phy_init(hpriv->phys[i]); > + if (rc) > + return rc; > + } > + > + /* De-assert the controller reset */ > + reset_control_deassert(cevapriv->rst); > + > + for (i = 0; i < hpriv->nports; i++) { > + rc = phy_power_on(hpriv->phys[i]); > + if (rc) { > + phy_exit(hpriv->phys[i]); > + return rc; > + } > + } > + } > + > if (of_property_read_bool(np, "ceva,broken-gen2")) > cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; > regards Philipp ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy 2020-09-22 12:05 ` Philipp Zabel @ 2020-09-23 5:45 ` Piyush Mehta 0 siblings, 0 replies; 6+ messages in thread From: Piyush Mehta @ 2020-09-23 5:45 UTC (permalink / raw) To: Philipp Zabel, axboe, robh+dt Cc: linux-ide, devicetree, linux-kernel, git, Srinivas Goud, Michal Simek Hello Philipp, Thanks for review. Regards, Piyush Mehta -----Original Message----- From: Philipp Zabel <p.zabel@pengutronix.de> Sent: Tuesday, September 22, 2020 5:36 PM To: Piyush Mehta <piyushm@xilinx.com>; axboe@kernel.dk; robh+dt@kernel.org Cc: linux-ide@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; git <git@xilinx.com>; Srinivas Goud <sgoud@xilinx.com>; Michal Simek <michals@xilinx.com> Subject: Re: [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy On Tue, 2020-09-22 at 15:45 +0530, Piyush Mehta wrote: > SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy > which has 4 GT lanes and can used by 4 peripherals at a time. > SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure > the GT lane for SATA controller, the below sequence is expected. > > 1. Assert the SATA controller reset. > 2. Configure the xilinx GT phy lane for SATA controller (phy_init). > 3. De-assert the SATA controller reset. > 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). > > The ahci_platform_enable_resources() by default does the phy_init() > and phy_power_on() but the default sequence doesn't work with Xilinx > platforms. Because of this reason, updated the driver to support the > new sequence. > > Added is_rst_ctrl flag, for backward compatibility with the older > sequence. If the reset controller is not available, then the SATA > controller will configure with the older sequences. > > Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> > --- > drivers/ata/ahci_ceva.c | 39 +++++++++++++++++++++++++++++++++++++-- > 1 file changed, 37 insertions(+), 2 deletions(-) > > diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index > b10fd4c..c704906 100644 > --- a/drivers/ata/ahci_ceva.c > +++ b/drivers/ata/ahci_ceva.c > @@ -12,6 +12,7 @@ > #include <linux/module.h> > #include <linux/of_device.h> > #include <linux/platform_device.h> > +#include <linux/reset.h> > #include "ahci.h" > > /* Vendor Specific Register Offsets */ @@ -87,6 +88,7 @@ struct > ceva_ahci_priv { > u32 axicc; > bool is_cci_enabled; > int flags; > + struct reset_control *rst; > }; > > static unsigned int ceva_ahci_read_id(struct ata_device *dev, @@ > -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev) > struct ahci_host_priv *hpriv; > struct ceva_ahci_priv *cevapriv; > enum dev_dma_attr attr; > - int rc; > + int rc, i, is_rst_ctrl = 1; > > cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); > if (!cevapriv) > @@ -202,14 +204,47 @@ static int ceva_ahci_probe(struct > platform_device *pdev) > > cevapriv->ahci_pdev = pdev; > > + cevapriv->rst = devm_reset_control_get(&pdev->dev, NULL); Please use devm_reset_control_get_optional_exclusive() > + if (IS_ERR(cevapriv->rst)) { > + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER) > + dev_err(&pdev->dev, "failed to get reset: %ld\n", > + PTR_ERR(cevapriv->rst)); > + is_rst_ctrl = 0; is_rst_ctrl will not be required then. > + } > + > hpriv = ahci_platform_get_resources(pdev, 0); > if (IS_ERR(hpriv)) > return PTR_ERR(hpriv); > + if (is_rst_ctrl) > + rc = ahci_platform_enable_clks(hpriv); > + else > + rc = ahci_platform_enable_resources(hpriv); > > - rc = ahci_platform_enable_resources(hpriv); > if (rc) > return rc; > > + if (is_rst_ctrl) { This can just be "if (cevapriv->rst)" > + /* Assert the controller reset */ > + reset_control_assert(cevapriv->rst); > + > + for (i = 0; i < hpriv->nports; i++) { > + rc = phy_init(hpriv->phys[i]); > + if (rc) > + return rc; > + } > + > + /* De-assert the controller reset */ > + reset_control_deassert(cevapriv->rst); > + > + for (i = 0; i < hpriv->nports; i++) { > + rc = phy_power_on(hpriv->phys[i]); > + if (rc) { > + phy_exit(hpriv->phys[i]); > + return rc; > + } > + } > + } > + > if (of_property_read_bool(np, "ceva,broken-gen2")) > cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; > regards Philipp ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-09-29 18:09 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-09-22 10:15 [PATCH V2 0/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta 2020-09-22 10:15 ` [PATCH V2 1/2] dt-bindings: ata: ahci: ceva: Update documentation for CEVA Controller Piyush Mehta 2020-09-29 18:09 ` Rob Herring 2020-09-22 10:15 ` [PATCH V2 2/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Piyush Mehta 2020-09-22 12:05 ` Philipp Zabel 2020-09-23 5:45 ` Piyush Mehta
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