[igt-dev] [PATCH i-g-t 00/18] tests: Remove libdrm dependency

[igt-dev] [PATCH i-g-t 00/18] tests: Remove libdrm dependency

[Dominik Grzegorzek]

I decided to split previous series into smaller chunks.
(https://patchwork.freedesktop.org/series/81782/)
There are some common patches inlcuded in more than one smaller series.
This one removes libdrm usage from tests except prime_* group.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>

Dominik Grzegorzek (16):
  lib/intel_batchbuffer: add intel_bb_blit_copy wrapper
  Remove unused intel_bufmgr.h headers
  i915/gem_pwrite_snooped: Remove libdrm dependency
  i915/gem_pipe_control_store_loop.c: Remove libdrm dependency
  i915/gem_pread_after_blit.c: Remove libdrm dependency
  i915/gem_threaded_access_tiled.c: Remove libdrm dependency
  i915/gem_tiled_blits: Remove libdrm dependency
  i915/gem_unfence_active_buffers.c: Remove librdm dependency
  i915/gem_unref_active_buffers.c: Remove libdrm dependency
  i915/gem_tiled_partial_pwrite_pread: Remove libdrm dependency
  i915/gem_set_tiling_vs_blit.c: Remove libdrm dependency
  tests/kms_fence_pin_leak.c: Remove libdrm dependency
  tests/kms_flip.c: Remove libdrm dependency
  tests/kms_psr2_su.c: Get rid of unused bufmgr
  tests/i915/gem_ppgtt: make copying more readable
  HAX: don't run failing test in BAT

Zbigniew Kempczyński (2):
  lib/intel_bufops: Avoid overallocate x-tiling and linear surfaces
  lib/intel_batchbuffer: Add control over fencing in intel_bb

 benchmarks/gem_userptr_benchmark.c          |   1 -
 lib/intel_batchbuffer.c                     |  70 +++++-
 lib/intel_batchbuffer.h                     |   5 +
 lib/intel_bufops.c                          |   4 +-
 lib/media_fill.c                            |   1 -
 tests/i915/gem_create.c                     |   1 -
 tests/i915/gem_flink_race.c                 |   2 -
 tests/i915/gem_pipe_control_store_loop.c    | 142 ++++++------
 tests/i915/gem_ppgtt.c                      |  16 +-
 tests/i915/gem_pread_after_blit.c           | 135 ++++++------
 tests/i915/gem_pwrite_snooped.c             |  66 +++---
 tests/i915/gem_request_retire.c             |   1 -
 tests/i915/gem_set_tiling_vs_blt.c          | 225 ++++++++++----------
 tests/i915/gem_threaded_access_tiled.c      |  38 ++--
 tests/i915/gem_tiled_blits.c                |  75 +++----
 tests/i915/gem_tiled_partial_pwrite_pread.c | 123 ++++++-----
 tests/i915/gem_unfence_active_buffers.c     | 141 ++++++------
 tests/i915/gem_unref_active_buffers.c       |  61 +++---
 tests/i915/gem_userptr_blits.c              |   1 -
 tests/i915/i915_getparams_basic.c           |   1 -
 tests/intel-ci/fast-feedback.testlist       |   1 -
 tests/kms_fence_pin_leak.c                  |  84 ++++----
 tests/kms_flip.c                            |  22 +-
 tests/kms_psr2_su.c                         |   7 -
 tests/kms_sequence.c                        |   2 -
 tests/kms_setmode.c                         |   1 -
 tests/kms_vblank.c                          |   2 -
 27 files changed, 631 insertions(+), 597 deletions(-)

-- 
2.20.1

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[igt-dev] [PATCH i-g-t 01/18] lib/intel_bufops: Avoid overallocate x-tiling and linear surfaces

[Dominik Grzegorzek]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Height alignment was not properly set to 32 which was to big for
x-tiling and linear surfaces and leads to overallocation.
Linear surfaces currently don't require any height alignment (just 1),
for x-tiling we use 8.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_bufops.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 57aa2a40..a1e9ba55 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -712,6 +712,7 @@ static void __intel_buf_init(struct buf_ops *bops,
 	uint32_t size;
 	uint32_t devid;
 	int tile_width;
+	int align_h = 1;
 
 	igt_assert(bops);
 	igt_assert(buf);
@@ -761,6 +762,7 @@ static void __intel_buf_init(struct buf_ops *bops,
 			devid =  intel_get_drm_devid(bops->fd);
 			tile_width = get_stride(devid, tiling);
 			buf->surface[0].stride = ALIGN(width * (bpp / 8), tile_width);
+			align_h = tiling == I915_TILING_X ? 8 : 32;
 		} else {
 			buf->surface[0].stride = ALIGN(width * (bpp / 8), alignment ?: 1);
 		}
@@ -769,7 +771,7 @@ static void __intel_buf_init(struct buf_ops *bops,
 		buf->tiling = tiling;
 		buf->bpp = bpp;
 
-		size = buf->surface[0].stride * ALIGN(height, 32);
+		size = buf->surface[0].stride * ALIGN(height, align_h);
 	}
 
 	if (handle)
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 02/18] lib/intel_batchbuffer: Add control over fencing in intel_bb

[Dominik Grzegorzek]

From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

From default intel_bb uses fencing to track subsequent execs.
It is required to properly sync intel_bb. Unfortunately this
also has some drawback, when we want to use same intel_bb to
schedule some time consuming job then run something else. Fencing
as turned on from default will serialize such execs. To avoid that
add possibility to turn on / off fencing in the intel_bb.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 47 ++++++++++++++++++++++++++++++++---------
 lib/intel_batchbuffer.h |  2 ++
 2 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index be764646..079d6389 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1266,6 +1266,7 @@ __intel_bb_create(int i915, uint32_t size, bool do_relocs)
 	ibb->ptr = ibb->batch;
 	ibb->prng = (uint32_t) to_user_pointer(ibb);
 	ibb->fence = -1;
+	ibb->use_fences = true;
 
 	gtt_size = gem_aperture_size(i915);
 	if (!gem_uses_full_ppgtt(i915))
@@ -1513,6 +1514,26 @@ void intel_bb_set_debug(struct intel_bb *ibb, bool debug)
 	ibb->debug = debug;
 }
 
+/**
+ * intel_bb_set_fencing:
+ * @ibb: pointer to intel_bb
+ * @use_fences: true / false
+ *
+ * Sets using fences to true / false.
+ */
+void intel_bb_set_fencing(struct intel_bb *ibb, bool use_fences)
+{
+	if (use_fences == ibb->use_fences)
+		return;
+
+	if (use_fences == false && ibb->fence >= 0) {
+		close(ibb->fence);
+		ibb->fence = -1;
+	}
+
+	ibb->use_fences = use_fences;
+}
+
 /**
  * intel_bb_set_dump_base64:
  * @ibb: pointer to intel_bb
@@ -2058,7 +2079,11 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	execbuf.buffer_count = ibb->num_objects;
 	execbuf.batch_len = end_offset;
 	execbuf.rsvd1 = ibb->ctx = ctx;
-	execbuf.flags = flags | I915_EXEC_BATCH_FIRST | I915_EXEC_FENCE_OUT;
+	execbuf.flags = flags | I915_EXEC_BATCH_FIRST;
+
+	if (ibb->use_fences)
+		execbuf.flags |= I915_EXEC_FENCE_OUT;
+
 	if (ibb->enforce_relocs)
 		execbuf.flags &= ~I915_EXEC_NO_RELOC;
 	execbuf.rsvd2 = 0;
@@ -2077,15 +2102,17 @@ int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 	update_offsets(ibb, objects);
 
 	/* Save/merge fences */
-	fence = execbuf.rsvd2 >> 32;
-
-	if (ibb->fence < 0) {
-		ibb->fence = fence;
-	} else {
-		new_fence = sync_fence_merge(ibb->fence, fence);
-		close(ibb->fence);
-		close(fence);
-		ibb->fence = new_fence;
+	if (ibb->use_fences) {
+		fence = execbuf.rsvd2 >> 32;
+
+		if (ibb->fence < 0) {
+			ibb->fence = fence;
+		} else {
+			new_fence = sync_fence_merge(ibb->fence, fence);
+			close(ibb->fence);
+			close(fence);
+			ibb->fence = new_fence;
+		}
 	}
 
 	if (sync || ibb->debug)
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 8b9c1ed9..cbfbe25f 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -446,6 +446,7 @@ struct intel_bb {
 	uint32_t *ptr;
 	uint64_t alignment;
 	int fence;
+	bool use_fences;
 
 	uint32_t prng;
 	uint64_t gtt_size;
@@ -497,6 +498,7 @@ int intel_bb_sync(struct intel_bb *ibb);
 void intel_bb_print(struct intel_bb *ibb);
 void intel_bb_dump(struct intel_bb *ibb, const char *filename);
 void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
+void intel_bb_set_fencing(struct intel_bb *ibb, bool use_fences);
 void intel_bb_set_dump_base64(struct intel_bb *ibb, bool dump);
 
 static inline uint64_t
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 03/18] lib/intel_batchbuffer: add intel_bb_blit_copy wrapper

[Dominik Grzegorzek]

This patch adds intel_bb_copy_intel_buf to make copying a whole
intel_buf easier and more readable.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_batchbuffer.c | 23 +++++++++++++++++++++++
 lib/intel_batchbuffer.h |  3 +++
 2 files changed, 26 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 079d6389..770bfef4 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2545,6 +2545,29 @@ void intel_bb_blt_copy(struct intel_bb *ibb,
 	intel_bb_flush_blit(ibb);
 }
 
+/**
+ * intel_bb_copy_intel_buf:
+ * @batch: batchbuffer object
+ * @src: source buffer (intel_buf)
+ * @dst: destination libdrm buffer object
+ * @size: size of the copy range in bytes
+ *
+ * Emits a copy operation using blitter commands into the supplied batch.
+ * A total of @size bytes from the start of @src is copied
+ * over to @dst. Note that @size must be page-aligned.
+ */
+void intel_bb_copy_intel_buf(struct intel_bb *ibb,
+			     struct intel_buf *src, struct intel_buf *dst,
+			     long int size)
+{
+	igt_assert(size % 4096 == 0);
+
+	intel_bb_blt_copy(ibb,
+			  src, 0, 0, 4096,
+			  dst, 0, 0, 4096,
+			  4096/4, size/4096, 32);
+}
+
 /**
  * igt_get_huc_copyfunc:
  * @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index cbfbe25f..a23ba9af 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -654,6 +654,9 @@ void intel_bb_blt_copy(struct intel_bb *ibb,
 		       struct intel_buf *dst,
 		       int dst_x1, int dst_y1, int dst_pitch,
 		       int width, int height, int bpp);
+void intel_bb_copy_intel_buf(struct intel_bb *ibb,
+			     struct intel_buf *dst, struct intel_buf *src,
+			     long int size);
 
 /**
  * igt_huc_copyfunc_t:
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 04/18] Remove unused intel_bufmgr.h headers

[Dominik Grzegorzek]

Delete intel_bufmgr include where it is not necessary.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 benchmarks/gem_userptr_benchmark.c | 1 -
 lib/media_fill.c                   | 1 -
 tests/i915/gem_create.c            | 1 -
 tests/i915/gem_flink_race.c        | 2 --
 tests/i915/gem_request_retire.c    | 1 -
 tests/i915/gem_userptr_blits.c     | 1 -
 tests/i915/i915_getparams_basic.c  | 1 -
 tests/kms_sequence.c               | 2 --
 tests/kms_setmode.c                | 1 -
 tests/kms_vblank.c                 | 2 --
 10 files changed, 13 deletions(-)

diff --git a/benchmarks/gem_userptr_benchmark.c b/benchmarks/gem_userptr_benchmark.c
index eccc65be..d7a49520 100644
--- a/benchmarks/gem_userptr_benchmark.c
+++ b/benchmarks/gem_userptr_benchmark.c
@@ -48,7 +48,6 @@
 #include "i915_drm.h"
 
 #include "drmtest.h"
-#include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
 #include "ioctl_wrappers.h"
diff --git a/lib/media_fill.c b/lib/media_fill.c
index c21de54b..c4883874 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -22,7 +22,6 @@
  *
  */
 
-#include <intel_bufmgr.h>
 #include <i915_drm.h>
 
 #include "media_fill.h"
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index c7444d55..dc945ab6 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -47,7 +47,6 @@
 #include "drm.h"
 #include "drmtest.h"
 #include "ioctl_wrappers.h"
-#include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
 #include "intel_chipset.h"
diff --git a/tests/i915/gem_flink_race.c b/tests/i915/gem_flink_race.c
index c1f5d5d5..de64443d 100644
--- a/tests/i915/gem_flink_race.c
+++ b/tests/i915/gem_flink_race.c
@@ -33,8 +33,6 @@
 #include <pthread.h>
 #include <errno.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Check for flink/open vs. gem close races.");
 
 /* Testcase: check for flink/open vs. gem close races
diff --git a/tests/i915/gem_request_retire.c b/tests/i915/gem_request_retire.c
index 4a1ec115..31fb4198 100644
--- a/tests/i915/gem_request_retire.c
+++ b/tests/i915/gem_request_retire.c
@@ -48,7 +48,6 @@
 
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Collection of tests targeting request retirement code"
 		     " paths.");
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 268423dc..65272c1b 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -62,7 +62,6 @@
 
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 #include "sw_sync.h"
 
 #include "eviction_common.c"
diff --git a/tests/i915/i915_getparams_basic.c b/tests/i915/i915_getparams_basic.c
index 7cb210df..e1b4634f 100644
--- a/tests/i915/i915_getparams_basic.c
+++ b/tests/i915/i915_getparams_basic.c
@@ -30,7 +30,6 @@
 #include <errno.h>
 #include <xf86drm.h>
 #include <i915_drm.h>
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Tests the export of parameters via DRM_IOCTL_I915_GETPARAM\n");
 
diff --git a/tests/kms_sequence.c b/tests/kms_sequence.c
index a21ab55c..081bd9d7 100644
--- a/tests/kms_sequence.c
+++ b/tests/kms_sequence.c
@@ -42,8 +42,6 @@
 
 #include <drm.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Test CrtcGetSequence and CrtcQueueSequence.");
 
 typedef struct {
diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c
index 92f3ead2..00dfedd5 100644
--- a/tests/kms_setmode.c
+++ b/tests/kms_setmode.c
@@ -30,7 +30,6 @@
 #include <string.h>
 #include <sys/time.h>
 #include <math.h>
-#include "intel_bufmgr.h"
 
 #define MAX_CONNECTORS  10
 #define MAX_CRTCS       6
diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index be001312..b00ebec5 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -41,8 +41,6 @@
 
 #include <drm.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Test speed of WaitVblank.");
 
 typedef struct {
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 05/18] i915/gem_pwrite_snooped: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_pwrite_snooped.c | 66 ++++++++++++++++-----------------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/tests/i915/gem_pwrite_snooped.c b/tests/i915/gem_pwrite_snooped.c
index 4a339524..52ebaec2 100644
--- a/tests/i915/gem_pwrite_snooped.c
+++ b/tests/i915/gem_pwrite_snooped.c
@@ -42,40 +42,38 @@ IGT_TEST_DESCRIPTION(
    "pwrite to a snooped bo then make it uncached and check that the GPU sees the data.");
 
 static int fd;
-static uint32_t devid;
-static drm_intel_bufmgr *bufmgr;
+static struct buf_ops *bops;
 
-static void blit(drm_intel_bo *dst, drm_intel_bo *src,
+static void blit(struct intel_buf *dst, struct intel_buf *src,
 		 unsigned int width, unsigned int height,
 		 unsigned int dst_pitch, unsigned int src_pitch)
 {
-	struct intel_batchbuffer *batch;
+	struct intel_bb *ibb;
 
-	batch = intel_batchbuffer_alloc(bufmgr, devid);
-	igt_assert(batch);
-
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	ibb = intel_bb_create(fd, 4096);
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_add_intel_buf(ibb, src, false);
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  dst_pitch);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(height << 16 | width);
-	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(src_pitch);
-	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	if (batch->gen >= 6) {
-		BEGIN_BATCH(3, 0);
-		OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-		OUT_BATCH(0);
-		OUT_BATCH(0);
-		ADVANCE_BATCH();
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, height << 16 | width);
+	intel_bb_emit_reloc_fenced(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, dst->addr.offset);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, src_pitch);
+	intel_bb_emit_reloc_fenced(ibb, src->handle, I915_GEM_DOMAIN_RENDER,
+				   0, 0, src->addr.offset);
+
+	if (ibb->gen >= 6) {
+		intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+		intel_bb_out(ibb, 0);
+		intel_bb_out(ibb, 0);
 	}
 
-	intel_batchbuffer_flush(batch);
-	intel_batchbuffer_free(batch);
+	intel_bb_flush_blit(ibb);
+	intel_bb_destroy(ibb);
 }
 
 static void *memchr_inv(const void *s, int c, size_t n)
@@ -98,13 +96,13 @@ static void *memchr_inv(const void *s, int c, size_t n)
 static void test(int w, int h)
 {
 	int object_size = w * h * 4;
-	drm_intel_bo *src, *dst;
+	struct intel_buf *src, *dst;
 	void *buf;
 
-	src = drm_intel_bo_alloc(bufmgr, "src", object_size, 4096);
-	igt_assert(src);
-	dst = drm_intel_bo_alloc(bufmgr, "dst", object_size, 4096);
-	igt_assert(dst);
+	src = intel_buf_create(bops, w, h, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
+	dst = intel_buf_create(bops, w, h, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
 
 	buf = malloc(object_size);
 	igt_assert(buf);
@@ -125,6 +123,9 @@ static void test(int w, int h)
 	gem_read(fd, dst->handle, 0, buf, object_size);
 
 	igt_assert(memchr_inv(buf, 0xff, object_size) == NULL);
+
+	intel_buf_destroy(src);
+	intel_buf_destroy(dst);
 }
 
 igt_simple_main
@@ -133,11 +134,10 @@ igt_simple_main
 	igt_require_gem(fd);
 	gem_require_blitter(fd);
 
-	devid = intel_get_drm_devid(fd);
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+	bops = buf_ops_create(fd);
 
 	test(256, 256);
 
-	drm_intel_bufmgr_destroy(bufmgr);
+	buf_ops_destroy(bops);
 	close(fd);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 06/18] i915/gem_pipe_control_store_loop.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_pipe_control_store_loop.c | 142 +++++++++++------------
 1 file changed, 68 insertions(+), 74 deletions(-)

diff --git a/tests/i915/gem_pipe_control_store_loop.c b/tests/i915/gem_pipe_control_store_loop.c
index 863a4871..6a3344e8 100644
--- a/tests/i915/gem_pipe_control_store_loop.c
+++ b/tests/i915/gem_pipe_control_store_loop.c
@@ -43,13 +43,11 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
+static struct buf_ops *bops;
+static struct intel_bb *ibb;
 
 #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
 #define   PIPE_CONTROL_WRITE_IMMEDIATE	(1<<14)
@@ -68,96 +66,101 @@ store_pipe_control_loop(bool preuse_buffer, int timeout)
 {
 	int val = 0;
 	uint32_t *buf;
-	drm_intel_bo *target_bo;
+	struct intel_buf *target_buf;
 
 	igt_until_timeout(timeout) {
 		/* we want to check tlb consistency of the pipe_control target,
 		 * so get a new buffer every time around */
-		target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
-		igt_assert(target_bo);
+		target_buf = intel_buf_create(bops, 4096, 1, 8, 0,
+					      I915_TILING_NONE,
+					      I915_COMPRESSION_NONE);
+		intel_bb_add_intel_buf(ibb, target_buf, true);
 
 		if (preuse_buffer) {
-			COLOR_BLIT_COPY_BATCH_START(0);
-			OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
-			OUT_BATCH(0);
-			OUT_BATCH(1 << 16 | 1);
+			intel_bb_out(ibb, XY_COLOR_BLT_CMD_NOLEN |
+				     COLOR_BLT_WRITE_ALPHA |
+				     XY_COLOR_BLT_WRITE_RGB |
+				     (4 + (ibb->gen >= 8)));
+
+			intel_bb_out(ibb, (3 << 24) | (0xf0 << 16) | 64);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 1 << 16 | 1);
 
 			/*
 			 * IMPORTANT: We need to preuse the buffer in a
 			 * different domain than what the pipe control write
 			 * (and kernel wa) uses!
 			 */
-			OUT_RELOC_FENCED(target_bo,
-			     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-			     0);
-			OUT_BATCH(0xdeadbeef);
-			ADVANCE_BATCH();
+			intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
+						   I915_GEM_DOMAIN_RENDER,
+						   I915_GEM_DOMAIN_RENDER,
+						   0, target_buf->addr.offset);
+			intel_bb_out(ibb, 0xdeadbeef);
 
-			intel_batchbuffer_flush(batch);
+			intel_bb_flush_blit(ibb);
 		}
 
 		/* gem_storedw_batches_loop.c is a bit overenthusiastic with
 		 * creating new batchbuffers - with buffer reuse disabled, the
 		 * support code will do that for us. */
-		if (batch->gen >= 8) {
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
-			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-			OUT_RELOC_FENCED(target_bo,
-			     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-			     PIPE_CONTROL_GLOBAL_GTT);
-			OUT_BATCH(val); /* write data */
-			ADVANCE_BATCH();
-
-		} else if (batch->gen >= 6) {
+		if (ibb->gen >= 8) {
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL + 1);
+			intel_bb_out(ibb, PIPE_CONTROL_WRITE_IMMEDIATE);
+			intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
+						   I915_GEM_DOMAIN_INSTRUCTION,
+						   I915_GEM_DOMAIN_INSTRUCTION,
+						   PIPE_CONTROL_GLOBAL_GTT,
+						   target_buf->addr.offset);
+			intel_bb_out(ibb, val); /* write data */
+		} else if (ibb->gen >= 6) {
 			/* work-around hw issue, see intel_emit_post_sync_nonzero_flush
 			 * in mesa sources. */
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL);
-			OUT_BATCH(PIPE_CONTROL_CS_STALL |
-			     PIPE_CONTROL_STALL_AT_SCOREBOARD);
-			OUT_BATCH(0); /* address */
-			OUT_BATCH(0); /* write data */
-			ADVANCE_BATCH();
-
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL);
-			OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-			OUT_RELOC(target_bo,
-			     I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 
-			     PIPE_CONTROL_GLOBAL_GTT);
-			OUT_BATCH(val); /* write data */
-			ADVANCE_BATCH();
-		} else if (batch->gen >= 4) {
-			BEGIN_BATCH(4, 1);
-			OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
-					PIPE_CONTROL_TC_FLUSH |
-					PIPE_CONTROL_WRITE_IMMEDIATE | 2);
-			OUT_RELOC(target_bo,
-				I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
-				PIPE_CONTROL_GLOBAL_GTT);
-			OUT_BATCH(val);
-			OUT_BATCH(0xdeadbeef);
-			ADVANCE_BATCH();
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+			intel_bb_out(ibb, PIPE_CONTROL_CS_STALL |
+				     PIPE_CONTROL_STALL_AT_SCOREBOARD);
+			intel_bb_out(ibb, 0); /* address */
+			intel_bb_out(ibb, 0); /* write data */
+
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+			intel_bb_out(ibb, PIPE_CONTROL_WRITE_IMMEDIATE);
+			intel_bb_emit_reloc(ibb, target_buf->handle,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    PIPE_CONTROL_GLOBAL_GTT,
+					    target_buf->addr.offset);
+			intel_bb_out(ibb, val); /* write data */
+		} else if (ibb->gen >= 4) {
+			intel_bb_out(ibb, GFX_OP_PIPE_CONTROL |
+				     PIPE_CONTROL_WC_FLUSH |
+				     PIPE_CONTROL_TC_FLUSH |
+				     PIPE_CONTROL_WRITE_IMMEDIATE | 2);
+			intel_bb_emit_reloc(ibb, target_buf->handle,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    I915_GEM_DOMAIN_INSTRUCTION,
+					    PIPE_CONTROL_GLOBAL_GTT,
+					    target_buf->addr.offset);
+			intel_bb_out(ibb, val);
+			intel_bb_out(ibb, 0xdeadbeef);
 		}
 
-		intel_batchbuffer_flush_on_ring(batch, 0);
+		intel_bb_flush(ibb, ibb->ctx, 0);
 
-		drm_intel_bo_map(target_bo, 1);
+		intel_buf_cpu_map(target_buf, 1);
 
-		buf = target_bo->virtual;
+		buf = target_buf->ptr;
 		igt_assert(buf[0] == val);
 
-		drm_intel_bo_unmap(target_bo);
+		intel_buf_unmap(target_buf);
 		/* Make doublesure that this buffer won't get reused. */
-		drm_intel_bo_disable_reuse(target_bo);
-		drm_intel_bo_unreference(target_bo);
+		intel_bb_reset(ibb, true);
 
+		intel_buf_destroy(target_buf);
 		val++;
 	}
 }
 
 int fd;
+uint32_t devid;
 
 igt_main
 {
@@ -167,20 +170,12 @@ igt_main
 		gem_require_blitter(fd);
 
 		devid = intel_get_drm_devid(fd);
-
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		igt_assert(bufmgr);
+		bops = buf_ops_create(fd);
 
 		igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
 		igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
 
-		/* IMPORTANT: No call to
-		 * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		 * here because we wan't to have fresh buffers (to trash the tlb)
-		 * every time! */
-
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
-		igt_assert(batch);
+		ibb = intel_bb_create(fd, 4096);
 	}
 
 	igt_subtest("fresh-buffer")
@@ -190,9 +185,8 @@ igt_main
 		store_pipe_control_loop(true, 2);
 
 	igt_fixture {
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
-
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 		close(fd);
 	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 07/18] i915/gem_pread_after_blit.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_pread_after_blit.c | 135 +++++++++++++++---------------
 1 file changed, 68 insertions(+), 67 deletions(-)

diff --git a/tests/i915/gem_pread_after_blit.c b/tests/i915/gem_pread_after_blit.c
index 81454c93..2086aab0 100644
--- a/tests/i915/gem_pread_after_blit.c
+++ b/tests/i915/gem_pread_after_blit.c
@@ -50,70 +50,69 @@
 
 IGT_TEST_DESCRIPTION("Test pread behavior when getting values out of"
 		     " just-drawn-to buffers.");
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct intel_bb *ibb;
 static const int width = 512, height = 512;
 static const int size = 1024 * 1024;
 
 #define PAGE_SIZE 4096
 
-static drm_intel_bo *
-create_bo(uint32_t val)
+static struct intel_buf *
+create_bo(struct buf_ops *bops, uint32_t val)
 {
-	drm_intel_bo *bo;
+	struct intel_buf *buf;
 	uint32_t *vaddr;
 	int i;
 
-	bo = drm_intel_bo_alloc(bufmgr, "src bo", size, 4096);
+	buf = intel_buf_create(bops, width, height, 32, 0, I915_TILING_NONE,
+			       I915_COMPRESSION_NONE);
 
 	/* Fill the BO with dwords starting at start_val */
-	drm_intel_bo_map(bo, 1);
-	vaddr = bo->virtual;
+	intel_buf_cpu_map(buf, 1);
+	vaddr = buf->ptr;
 
 	for (i = 0; i < 1024 * 1024 / 4; i++)
 		vaddr[i] = val++;
 
-	drm_intel_bo_unmap(bo);
+	intel_buf_unmap(buf);
 
-	return bo;
+	return buf;
 }
 
 static void
-verify_large_read(drm_intel_bo *bo, uint32_t val)
+verify_large_read(int fd, struct intel_buf *buf, uint32_t val)
 {
-	uint32_t buf[size / 4];
+	uint32_t tmp[size / 4];
 	int i;
 
-	drm_intel_bo_get_subdata(bo, 0, size, buf);
+	gem_read(fd, buf->handle, 0, tmp, size);
 
 	for (i = 0; i < size / 4; i++) {
-		igt_assert_f(buf[i] == val,
+		igt_assert_f(tmp[i] == val,
 			     "Unexpected value 0x%08x instead of "
 			     "0x%08x at offset 0x%08x (%p)\n",
-			     buf[i], val, i * 4, buf);
+			     tmp[i], val, i * 4, tmp);
 		val++;
 	}
 }
 
 /** This reads at the size that Mesa usees for software fallbacks. */
 static void
-verify_small_read(drm_intel_bo *bo, uint32_t val)
+verify_small_read(int fd, struct intel_buf *buf, uint32_t val)
 {
-	uint32_t buf[4096 / 4];
+	uint32_t tmp[4096 / 4];
 	int offset, i;
 
 	for (i = 0; i < 4096 / 4; i++)
-		buf[i] = 0x00c0ffee;
+		tmp[i] = 0x00c0ffee;
 
 	for (offset = 0; offset < size; offset += PAGE_SIZE) {
-		drm_intel_bo_get_subdata(bo, offset, PAGE_SIZE, buf);
+		gem_read(fd, buf->handle, offset, tmp, PAGE_SIZE);
 
 		for (i = 0; i < PAGE_SIZE; i += 4) {
-			igt_assert_f(buf[i / 4] == val,
+			igt_assert_f(tmp[i / 4] == val,
 				     "Unexpected value 0x%08x instead of "
 				     "0x%08x at offset 0x%08x\n",
-				     buf[i / 4], val, i * 4);
+				     tmp[i / 4], val, i * 4);
 			val++;
 		}
 	}
@@ -128,16 +127,17 @@ static igt_hang_t no_hang(int fd)
 
 static igt_hang_t bcs_hang(int fd)
 {
-	return igt_hang_ring(fd, batch->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
+	return igt_hang_ring(fd, ibb->gen >= 6 ? I915_EXEC_BLT : I915_EXEC_DEFAULT);
 }
 
-static void do_test(int fd, int cache_level,
-		    drm_intel_bo *src[2],
+static void do_test(struct buf_ops *bops, int cache_level,
+		    struct intel_buf *src[2],
 		    const uint32_t start[2],
-		    drm_intel_bo *tmp[2],
+		    struct intel_buf *tmp[2],
 		    int loop, do_hang do_hang_func)
 {
 	igt_hang_t hang;
+	int fd = buf_ops_get_fd(bops);
 
 	if (cache_level != -1) {
 		gem_set_caching(fd, tmp[0]->handle, cache_level);
@@ -146,55 +146,52 @@ static void do_test(int fd, int cache_level,
 
 	do {
 		/* First, do a full-buffer read after blitting */
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[0], tmp[0], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[0]);
+		verify_large_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
-		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[1], tmp[0], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[1]);
+		verify_large_read(fd, tmp[0], start[1]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[0], tmp[0], size);
 		hang = do_hang_func(fd);
-		verify_small_read(tmp[0], start[0]);
+		verify_small_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
-		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[1], tmp[0], size);
 		hang = do_hang_func(fd);
-		verify_small_read(tmp[0], start[1]);
+		verify_small_read(fd, tmp[0], start[1]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[0], tmp[0], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[0]);
+		verify_large_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
-		intel_copy_bo(batch, tmp[1], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[0], tmp[0], size);
+		intel_bb_copy_intel_buf(ibb, src[1], tmp[1], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[0]);
-		verify_large_read(tmp[1], start[1]);
+		verify_large_read(fd, tmp[0], start[0]);
+		verify_large_read(fd, tmp[1], start[1]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[0], src[0], width*height*4);
-		intel_copy_bo(batch, tmp[1], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[0], tmp[0], size);
+		intel_bb_copy_intel_buf(ibb, src[1], tmp[1], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[1], start[1]);
-		verify_large_read(tmp[0], start[0]);
+		verify_large_read(fd, tmp[1], start[1]);
+		verify_large_read(fd, tmp[0], start[0]);
 		igt_post_hang_ring(fd, hang);
 
-		intel_copy_bo(batch, tmp[1], src[0], width*height*4);
-		intel_copy_bo(batch, tmp[0], src[1], width*height*4);
+		intel_bb_copy_intel_buf(ibb, src[0], tmp[1], size);
+		intel_bb_copy_intel_buf(ibb, src[1], tmp[0], size);
 		hang = do_hang_func(fd);
-		verify_large_read(tmp[0], start[1]);
-		verify_large_read(tmp[1], start[0]);
+		verify_large_read(fd, tmp[0], start[1]);
+		verify_large_read(fd, tmp[1], start[0]);
 		igt_post_hang_ring(fd, hang);
 	} while (--loop);
 }
 
-drm_intel_bo *src[2], *dst[2];
-int fd;
-
 igt_main
 {
 	const uint32_t start[2] = {0, 1024 * 1024 / 4};
@@ -208,43 +205,47 @@ igt_main
 		{ "display", 2 },
 		{ NULL, -1 },
 	}, *t;
+	struct intel_buf *src[2], *dst[2];
+	struct buf_ops *bops;
+	int fd;
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		bops = buf_ops_create(fd);
+		ibb = intel_bb_create(fd, 4096);
 
-		src[0] = create_bo(start[0]);
-		src[1] = create_bo(start[1]);
+		src[0] = create_bo(bops, start[0]);
+		src[1] = create_bo(bops, start[1]);
 
-		dst[0] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
-		dst[1] = drm_intel_bo_alloc(bufmgr, "dst bo", size, 4096);
+		dst[0] = intel_buf_create(bops, width, height, 32, 4096,
+					  I915_TILING_NONE, I915_COMPRESSION_NONE);
+		dst[1] = intel_buf_create(bops, width, height, 32, 4096,
+					  I915_TILING_NONE, I915_COMPRESSION_NONE);
 	}
 
 	for (t = tests; t->name; t++) {
 		igt_subtest_f("%s-normal", t->name)
-			do_test(fd, t->cache, src, start, dst, 1, no_hang);
+			do_test(bops, t->cache, src, start, dst, 1, no_hang);
 
 		igt_fork_signal_helper();
 		igt_subtest_f("%s-interruptible", t->name)
-			do_test(fd, t->cache, src, start, dst, 100, no_hang);
+			do_test(bops, t->cache, src, start, dst, 100, no_hang);
 		igt_stop_signal_helper();
 
 		igt_subtest_f("%s-hang", t->name)
-			do_test(fd, t->cache, src, start, dst, 1, bcs_hang);
+			do_test(bops, t->cache, src, start, dst, 1, bcs_hang);
 	}
 
 	igt_fixture {
-		drm_intel_bo_unreference(src[0]);
-		drm_intel_bo_unreference(src[1]);
-		drm_intel_bo_unreference(dst[0]);
-		drm_intel_bo_unreference(dst[1]);
+		intel_buf_destroy(src[0]);
+		intel_buf_destroy(src[1]);
+		intel_buf_destroy(dst[0]);
+		intel_buf_destroy(dst[1]);
 
-		intel_batchbuffer_free(batch);
-		drm_intel_bufmgr_destroy(bufmgr);
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 	}
 
 	igt_fixture
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 08/18] i915/gem_threaded_access_tiled.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_threaded_access_tiled.c | 38 ++++++++++++--------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/tests/i915/gem_threaded_access_tiled.c b/tests/i915/gem_threaded_access_tiled.c
index 6442d589..47b2962e 100644
--- a/tests/i915/gem_threaded_access_tiled.c
+++ b/tests/i915/gem_threaded_access_tiled.c
@@ -31,8 +31,6 @@
 #include <unistd.h>
 #include <pthread.h>
 
-#include "intel_bufmgr.h"
-
 IGT_TEST_DESCRIPTION("Check parallel access to tiled memory.");
 
 /* Testcase: check parallel access to tiled memory
@@ -45,10 +43,10 @@ IGT_TEST_DESCRIPTION("Check parallel access to tiled memory.");
 #define HEIGHT 4096
 
 struct thread_ctx {
-	drm_intel_bo *bo;
+	struct intel_buf *buf;
 };
 
-static drm_intel_bufmgr *bufmgr;
+static struct buf_ops *bops;
 static struct thread_ctx tctx[NUM_THREADS];
 
 static void *copy_fn(void *p)
@@ -60,13 +58,13 @@ static void *copy_fn(void *p)
 	if (buf == NULL)
 		return (void *)1;
 
-	memcpy(buf, c->bo->virtual, WIDTH * HEIGHT);
+	memcpy(buf, c->buf->ptr, WIDTH * HEIGHT);
 
 	free(buf);
 	return (void *)0;
 }
 
-static int copy_tile_threaded(drm_intel_bo *bo)
+static int copy_tile_threaded(struct intel_buf *buf)
 {
 	int i;
 	int r;
@@ -74,7 +72,7 @@ static int copy_tile_threaded(drm_intel_bo *bo)
 	void *status;
 
 	for (i = 0; i < NUM_THREADS; i++) {
-		tctx[i].bo = bo;
+		tctx[i].buf = buf;
 		r = pthread_create(&thr[i], NULL, copy_fn, (void *)&tctx[i]);
 		igt_assert_eq(r, 0);
 	}
@@ -90,9 +88,8 @@ static int copy_tile_threaded(drm_intel_bo *bo)
 igt_simple_main
 {
 	int fd;
-	drm_intel_bo *bo;
+	struct intel_buf *buf;
 	uint32_t tiling_mode = I915_TILING_Y;
-	unsigned long pitch = 0;
 	int r;
 
 	fd = drm_open_driver(DRIVER_INTEL);
@@ -100,24 +97,25 @@ igt_simple_main
 
 	igt_require(gem_available_fences(fd) > 0);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	igt_assert(bufmgr);
+	bops = buf_ops_create(fd);
 
-	bo = drm_intel_bo_alloc_tiled(bufmgr, "mmap bo", WIDTH, HEIGHT, 1,
-				      &tiling_mode, &pitch, 0);
-	igt_assert(bo);
+	buf = intel_buf_create(bops, WIDTH, HEIGHT, 8, 0, tiling_mode,
+			       I915_COMPRESSION_NONE);
+	igt_assert(buf);
 
-	r = drm_intel_gem_bo_map_gtt(bo);
-	igt_assert(!r);
+	buf->ptr = __gem_mmap__gtt(fd, buf->handle, buf->surface[0].size,
+				   PROT_WRITE | PROT_READ);
+	igt_assert(buf->ptr);
 
-	r = copy_tile_threaded(bo);
+	r = copy_tile_threaded(buf);
 	igt_assert(!r);
 
-	r = drm_intel_gem_bo_unmap_gtt(bo);
+	r = gem_munmap(buf->ptr, buf->surface[0].size);
+	buf->ptr = NULL;
 	igt_assert(!r);
 
-	drm_intel_bo_unreference(bo);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_buf_destroy(buf);
+	buf_ops_destroy(bops);
 
 	close(fd);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 09/18] i915/gem_tiled_blits: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_tiled_blits.c | 75 ++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 37 deletions(-)

diff --git a/tests/i915/gem_tiled_blits.c b/tests/i915/gem_tiled_blits.c
index 36e96785..2149f27f 100644
--- a/tests/i915/gem_tiled_blits.c
+++ b/tests/i915/gem_tiled_blits.c
@@ -60,49 +60,51 @@ IGT_TEST_DESCRIPTION("Test doing many tiled blits, with a working set larger"
 
 static int width = 512, height = 512;
 
-static drm_intel_bo *
-create_bo(drm_intel_bufmgr *bufmgr, struct intel_batchbuffer *batch, uint32_t x)
+static struct intel_buf *
+create_bo(struct buf_ops *bops, struct intel_bb *ibb, uint32_t x)
 {
-	drm_intel_bo *bo, *linear_bo;
+	struct intel_buf *buf, *linear_buf;
 	uint32_t *linear;
 	uint32_t tiling = I915_TILING_X;
 	int i;
 
-	bo = drm_intel_bo_alloc(bufmgr, "tiled bo", 1024 * 1024, 4096);
-	do_or_die(drm_intel_bo_set_tiling(bo, &tiling, width * 4));
-	igt_assert(tiling == I915_TILING_X);
+	buf = intel_buf_create(bops, width, height, 32, 0, tiling,
+			       I915_COMPRESSION_NONE);
 
-	linear_bo = drm_intel_bo_alloc(bufmgr, "linear src", 1024 * 1024, 4096);
+	linear_buf = intel_buf_create(bops, width, height, 32, 0,
+				      I915_TILING_NONE, I915_COMPRESSION_NONE);
 
 	/* Fill the BO with dwords starting at start_val */
-	do_or_die(drm_intel_bo_map(linear_bo, 1));
-	linear = linear_bo->virtual;
+	intel_buf_cpu_map(linear_buf, 1);
+	linear = linear_buf->ptr;
 	for (i = 0; i < 1024 * 1024 / 4; i++)
 		linear[i] = x++;
-	drm_intel_bo_unmap(linear_bo);
+	intel_buf_unmap(linear_buf);
 
-	intel_copy_bo (batch, bo, linear_bo, width*height*4);
+	intel_bb_copy_intel_buf(ibb, linear_buf, buf, width*height*4);
+	intel_bb_reset(ibb, true);
 
-	drm_intel_bo_unreference(linear_bo);
+	intel_buf_destroy(linear_buf);
 
-	return bo;
+	return buf;
 }
 
 static void
-check_bo(drm_intel_bo *bo, uint32_t val, struct intel_batchbuffer *batch)
+check_bo(struct intel_buf *buf, uint32_t val, struct intel_bb *ibb)
 {
-	drm_intel_bo *linear_bo;
+	struct intel_buf *linear_buf;
 	uint32_t *linear;
 	int num_errors;
 	int i;
 
-	linear_bo = drm_intel_bo_alloc(bo->bufmgr, "linear dst",
-				       1024 * 1024, 4096);
+	linear_buf = intel_buf_create(buf->bops, width, height, 32, 0,
+				      I915_TILING_NONE, I915_COMPRESSION_NONE);
 
-	intel_copy_bo(batch, linear_bo, bo, width*height*4);
+	intel_bb_copy_intel_buf(ibb, buf, linear_buf, width*height*4);
+	intel_bb_reset(ibb, true);
 
-	do_or_die(drm_intel_bo_map(linear_bo, 0));
-	linear = linear_bo->virtual;
+	intel_buf_cpu_map(linear_buf, 0);
+	linear = linear_buf->ptr;
 
 	num_errors = 0;
 	for (i = 0; i < 1024 * 1024 / 4; i++) {
@@ -112,31 +114,28 @@ check_bo(drm_intel_bo *bo, uint32_t val, struct intel_batchbuffer *batch)
 		val++;
 	}
 	igt_assert_eq(num_errors, 0);
-	drm_intel_bo_unmap(linear_bo);
+	intel_buf_unmap(linear_buf);
 
-	drm_intel_bo_unreference(linear_bo);
+	intel_buf_destroy(linear_buf);
 }
 
 static void run_test(int fd, int count)
 {
-	struct intel_batchbuffer *batch;
-	drm_intel_bufmgr *bufmgr;
-	drm_intel_bo **bo;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
+	struct intel_buf **bo;
 	uint32_t *bo_start_val;
 	uint32_t start = 0;
 	int i;
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create(fd, 4096);
 
-
-	bo = malloc(sizeof(drm_intel_bo *)*count);
+	bo = malloc(sizeof(struct intel_buf *)*count);
 	bo_start_val = malloc(sizeof(uint32_t)*count);
 
 	for (i = 0; i < count; i++) {
-		bo[i] = create_bo(bufmgr, batch, start);
+		bo[i] = create_bo(bops, ibb, start);
 		bo_start_val[i] = start;
 		start += 1024 * 1024 / 4;
 	}
@@ -148,20 +147,22 @@ static void run_test(int fd, int count)
 		if (src == dst)
 			continue;
 
-		intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
+		intel_bb_copy_intel_buf(ibb, bo[src], bo[dst], width*height*4);
+		intel_bb_reset(ibb, true);
+
 		bo_start_val[dst] = bo_start_val[src];
 	}
 
 	for (i = 0; i < count; i++) {
-		check_bo(bo[i], bo_start_val[i], batch);
-		drm_intel_bo_unreference(bo[i]);
+		check_bo(bo[i], bo_start_val[i], ibb);
+		intel_buf_destroy(bo[i]);
 	}
 
 	free(bo_start_val);
 	free(bo);
 
-	intel_batchbuffer_free(batch);
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 }
 
 #define MAX_32b ((1ull << 32) - 4096)
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 10/18] i915/gem_unfence_active_buffers.c: Remove librdm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.
The difference between offsets proposed from kernel using intel_bb
instead of libdrm is caused by EXEC_OBJECT_SUPPORTS_48B_ADDRESS set on
every object.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_unfence_active_buffers.c | 141 ++++++++++++------------
 1 file changed, 73 insertions(+), 68 deletions(-)

diff --git a/tests/i915/gem_unfence_active_buffers.c b/tests/i915/gem_unfence_active_buffers.c
index 1e69c70d..af01a801 100644
--- a/tests/i915/gem_unfence_active_buffers.c
+++ b/tests/i915/gem_unfence_active_buffers.c
@@ -51,24 +51,22 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
 #define TEST_SIZE (1024*1024)
 #define TEST_STRIDE (4*1024)
+#define TEST_HEIGHT (TEST_SIZE/TEST_STRIDE)
+#define TEST_WIDTH (TEST_STRIDE/4)
 
 uint32_t data[TEST_SIZE/4];
 
 igt_simple_main
 {
-	int i, ret, fd, num_fences;
-	drm_intel_bo *busy_bo, *test_bo;
-	uint32_t tiling = I915_TILING_X;
+	int i, fd, num_fences;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
+	struct intel_buf *busy_buf, *test_buf;
 
 	for (i = 0; i < 1024*256; i++)
 		data[i] = i;
@@ -77,86 +75,93 @@ igt_simple_main
 	igt_require_gem(fd);
 	gem_require_blitter(fd);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-	devid = intel_get_drm_devid(fd);
-	batch = intel_batchbuffer_alloc(bufmgr, devid);
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create_with_relocs(fd, 4 * 4096);
+	intel_bb_set_fencing(ibb, false);
 
 	igt_info("filling ring\n");
-	busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
+	busy_buf = intel_buf_create(bops, 2048, 2048, 32, 0, I915_TILING_NONE,
+				   I915_COMPRESSION_NONE);
 
 	for (i = 0; i < 250; i++) {
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
-			  (0xcc << 16) | /* copy ROP */
-			  2*1024*4);
-		OUT_BATCH(0 << 16 | 1024);
-		OUT_BATCH((2048) << 16 | (2048));
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(2*1024*4);
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-
-		if (batch->gen >= 6) {
-			BEGIN_BATCH(3, 0);
-			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-			OUT_BATCH(0);
-			OUT_BATCH(0);
-			ADVANCE_BATCH();
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
+			     (0xcc << 16) | /* copy ROP */
+			     2*1024*4);
+		intel_bb_out(ibb, 0 << 16 | 1024);
+		intel_bb_out(ibb, (2048) << 16 | (2048));
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, 2*1024*4);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
+
+		if (ibb->gen >= 6) {
+			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 0);
 		}
 	}
-	intel_batchbuffer_flush(batch);
+	intel_bb_flush_blit(ibb);
 
 	num_fences = gem_available_fences(fd);
 	igt_info("creating havoc on %i fences\n", num_fences);
 
 	for (i = 0; i < num_fences*2; i++) {
-		test_bo = drm_intel_bo_alloc(bufmgr, "test_bo",
-					     TEST_SIZE, 4096);
-		ret = drm_intel_bo_set_tiling(test_bo, &tiling, TEST_STRIDE);
-		igt_assert(ret == 0);
+		test_buf = intel_buf_create(bops, TEST_WIDTH, TEST_HEIGHT,
+					    32, 0, I915_TILING_X,
+					    I915_COMPRESSION_NONE);
+		igt_assert(TEST_STRIDE == test_buf->surface[0].stride);
 
-		drm_intel_bo_disable_reuse(test_bo);
-
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  TEST_STRIDE);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH((1) << 16 | (1));
-		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(TEST_STRIDE);
-		OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-		intel_batchbuffer_flush(batch);
-		igt_info("test bo offset: %#lx\n", test_bo->offset);
-
-		drm_intel_bo_unreference(test_bo);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, (1) << 16 | (1));
+		intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, TEST_STRIDE);
+		intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
+
+		intel_bb_flush_blit(ibb);
+		igt_info("test bo offset: %#lx\n",
+			 intel_bb_get_object_offset(ibb, test_buf->handle));
+
+		intel_buf_destroy(test_buf);
+		intel_bb_reset(ibb, true);
 	}
 
 	/* launch a few batchs to ensure the damaged slab objects get reused. */
 	for (i = 0; i < 10; i++) {
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 			  (0xcc << 16) | /* copy ROP */
 			  2*1024*4);
-		OUT_BATCH(0 << 16 | 1024);
-		OUT_BATCH((1) << 16 | (1));
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(2*1024*4);
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-
-		if (batch->gen >= 8) {
-			BEGIN_BATCH(3, 0);
-			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-			OUT_BATCH(0);
-			OUT_BATCH(0);
-			ADVANCE_BATCH();
+		intel_bb_out(ibb, 0 << 16 | 1024);
+		intel_bb_out(ibb, (1) << 16 | (1));
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, 2*1024*4);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0x0);
+
+		if (ibb->gen >= 8) {
+			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 0);
 		}
 	}
-	intel_batchbuffer_flush(batch);
+	intel_bb_flush_blit(ibb);
+
+	intel_buf_destroy(busy_buf);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 11/18] i915/gem_unref_active_buffers.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_unref_active_buffers.c | 61 +++++++++++++--------------
 1 file changed, 30 insertions(+), 31 deletions(-)

diff --git a/tests/i915/gem_unref_active_buffers.c b/tests/i915/gem_unref_active_buffers.c
index 75394794..55624aa3 100644
--- a/tests/i915/gem_unref_active_buffers.c
+++ b/tests/i915/gem_unref_active_buffers.c
@@ -29,8 +29,7 @@
  * Testcase: Unreferencing of active buffers
  *
  * Execs buffers and immediately unreferences them, hence the kernel active list
- * will be the last one to hold a reference on them. Usually libdrm bo caching
- * prevents that by keeping another reference.
+ * will be the last one to hold a reference on them.
  */
 #include <stdlib.h>
 #include <stdio.h>
@@ -44,55 +43,55 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test unreferencing of active buffers.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-static drm_intel_bo *load_bo;
-
 igt_simple_main
 {
+	struct intel_buf *load_bo;
+	struct intel_bb *ibb;
+	struct buf_ops *bops;
 	int fd, i;
 
 	fd = drm_open_driver(DRIVER_INTEL);
 	igt_require_gem(fd);
 	gem_require_blitter(fd);
 
-	bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-	igt_assert(bufmgr);
-	/* don't enable buffer reuse!! */
-	//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-
-	batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
-	igt_assert(batch);
+	bops = buf_ops_create(fd);
+	ibb = intel_bb_create_with_relocs(fd, 4096);
+	intel_bb_set_fencing(ibb, false);
 
 	/* put some load onto the gpu to keep the light buffers active for long
 	 * enough */
 	for (i = 0; i < 1000; i++) {
-		load_bo = drm_intel_bo_alloc(bufmgr, "target bo", 1024*4096, 4096);
-		igt_assert(load_bo);
+		load_bo = intel_buf_create(bops, 2048, 2048, 32, 0,
+					   I915_TILING_NONE,
+					   I915_COMPRESSION_NONE);
 
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
-			  (0xcc << 16) | /* copy ROP */
-			  4096);
-		OUT_BATCH(0); /* dst x1,y1 */
-		OUT_BATCH((1024 << 16) | 512);
-		OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH((0 << 16) | 512); /* src x1, y1 */
-		OUT_BATCH(4096);
-		OUT_RELOC_FENCED(load_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
+		intel_bb_add_intel_buf(ibb, load_bo, true);
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
+			     (0xcc << 16) | /* copy ROP */
+			     4096);
+		intel_bb_out(ibb, 0); /* dst x1,y1 */
+		intel_bb_out(ibb, (1024 << 16) | 512);
+		intel_bb_emit_reloc_fenced(ibb, load_bo->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0x0);
+		intel_bb_out(ibb, (0 << 16) | 512); /* src x1, y1 */
+		intel_bb_out(ibb, 4096);
+		intel_bb_emit_reloc_fenced(ibb, load_bo->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   0, 0, 0x0);
 
-		intel_batchbuffer_flush(batch);
+		intel_bb_flush_blit(ibb);
 
-		drm_intel_bo_disable_reuse(load_bo);
-		drm_intel_bo_unreference(load_bo);
+		intel_buf_destroy(load_bo);
+		intel_bb_reset(ibb, true);
 	}
 
-	drm_intel_bufmgr_destroy(bufmgr);
+	intel_bb_destroy(ibb);
+	buf_ops_destroy(bops);
 
 	close(fd);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 12/18] i915/gem_tiled_partial_pwrite_pread: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_tiled_partial_pwrite_pread.c | 123 ++++++++++----------
 1 file changed, 60 insertions(+), 63 deletions(-)

diff --git a/tests/i915/gem_tiled_partial_pwrite_pread.c b/tests/i915/gem_tiled_partial_pwrite_pread.c
index 7de5358b..6e7ec593 100644
--- a/tests/i915/gem_tiled_partial_pwrite_pread.c
+++ b/tests/i915/gem_tiled_partial_pwrite_pread.c
@@ -53,68 +53,69 @@ IGT_TEST_DESCRIPTION("Test pwrite/pread consistency when touching partial"
  *
  */
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
+static struct intel_bb *ibb;
 
-drm_intel_bo *scratch_bo;
-drm_intel_bo *staging_bo;
-drm_intel_bo *tiled_staging_bo;
-unsigned long scratch_pitch;
+struct intel_buf *scratch_buf;
+struct intel_buf *staging_buf;
+struct intel_buf *tiled_staging_buf;
 #define BO_SIZE (32*4096)
-uint32_t devid;
 int fd;
 
 static void
-copy_bo(drm_intel_bo *src, int src_tiled,
-	drm_intel_bo *dst, int dst_tiled)
+copy_bo(struct intel_buf *src, int src_tiled,
+	struct intel_buf *dst, int dst_tiled)
 {
-	unsigned long dst_pitch = scratch_pitch;
-	unsigned long src_pitch = scratch_pitch;
+	unsigned long dst_pitch = dst->surface[0].stride;
+	unsigned long src_pitch = src->surface[0].stride;
+	unsigned long scratch_pitch = src->surface[0].stride;
 	uint32_t cmd_bits = 0;
 
 	/* dst is tiled ... */
-	if (intel_gen(devid) >= 4 && dst_tiled) {
+	if (ibb->gen >= 4 && dst_tiled) {
 		dst_pitch /= 4;
 		cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
 	}
 
-	if (intel_gen(devid) >= 4 && dst_tiled) {
+	if (ibb->gen >= 4 && src_tiled) {
 		src_pitch /= 4;
 		cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
 	}
 
-	BLIT_COPY_BATCH_START(cmd_bits);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_blit_start(ibb, cmd_bits);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  dst_pitch);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(BO_SIZE/scratch_pitch << 16 | 1024);
-	OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(src_pitch);
-	OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-
-	intel_batchbuffer_flush(batch);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, BO_SIZE/scratch_pitch << 16 | 1024);
+	intel_bb_emit_reloc_fenced(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, dst->addr.offset);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, src_pitch);
+	intel_bb_emit_reloc_fenced(ibb, src->handle, I915_GEM_DOMAIN_RENDER, 0,
+				   0, src->addr.offset);
+
+	intel_bb_flush_blit(ibb);
 }
 
 static void
-blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, int val)
+blt_bo_fill(struct intel_buf *tmp_buf, struct intel_buf *buf, int val)
 {
 	uint8_t *gtt_ptr;
 	int i;
 
-	drm_intel_gem_bo_map_gtt(tmp_bo);
-	gtt_ptr = tmp_bo->virtual;
+	gtt_ptr = gem_mmap__gtt(fd, tmp_buf->handle, tmp_buf->surface[0].size,
+				PROT_WRITE);
 
 	for (i = 0; i < BO_SIZE; i++)
 		gtt_ptr[i] = val;
 
-	drm_intel_gem_bo_unmap_gtt(tmp_bo);
+	gem_munmap(gtt_ptr, tmp_buf->surface[0].size);
 
 	igt_drop_caches_set(fd, DROP_BOUND);
 
-	copy_bo(tmp_bo, 0, bo, 1);
+	copy_bo(tmp_buf, 0, buf, 1);
 }
 
 #define MAX_BLT_SIZE 128
@@ -130,12 +131,12 @@ static void test_partial_reads(void)
 		int start, len;
 		int val = i % 256;
 
-		blt_bo_fill(staging_bo, scratch_bo, i);
+		blt_bo_fill(staging_buf, scratch_buf, i);
 
 		start = random() % BO_SIZE;
 		len = random() % (BO_SIZE-start) + 1;
 
-		drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
+		gem_read(fd, scratch_buf->handle, start, tmp, len);
 		for (j = 0; j < len; j++) {
 			igt_assert_f(tmp[j] == val,
 				     "mismatch at %i, got: %i, expected: %i\n",
@@ -154,18 +155,17 @@ static void test_partial_writes(void)
 		int start, len;
 		int val = i % 256;
 
-		blt_bo_fill(staging_bo, scratch_bo, i);
+		blt_bo_fill(staging_buf, scratch_buf, i);
 
 		start = random() % BO_SIZE;
 		len = random() % (BO_SIZE-start) + 1;
 
 		memset(tmp, i + 63, BO_SIZE);
 
-		drm_intel_bo_subdata(scratch_bo, start, len, tmp);
+		gem_write(fd, scratch_buf->handle, start, tmp, len);
 
-		copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
-		drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
-					 compare_tmp);
+		copy_bo(scratch_buf, 1, tiled_staging_buf, 1);
+		gem_read(fd, tiled_staging_buf->handle, 0, compare_tmp, BO_SIZE);
 
 		for (j = 0; j < start; j++) {
 			igt_assert_f(compare_tmp[j] == val,
@@ -182,7 +182,6 @@ static void test_partial_writes(void)
 				     "mismatch at %i, got: %i, expected: %i\n",
 				     j, tmp[j], val);
 		}
-		drm_intel_gem_bo_unmap_gtt(staging_bo);
 
 		igt_progress("partial writes test: ", i, ROUNDS);
 	}
@@ -196,13 +195,13 @@ static void test_partial_read_writes(void)
 		int start, len;
 		int val = i % 256;
 
-		blt_bo_fill(staging_bo, scratch_bo, i);
+		blt_bo_fill(staging_buf, scratch_buf, i);
 
 		/* partial read */
 		start = random() % BO_SIZE;
 		len = random() % (BO_SIZE-start) + 1;
 
-		drm_intel_bo_get_subdata(scratch_bo, start, len, tmp);
+		gem_read(fd, scratch_buf->handle, start, tmp, len);
 		for (j = 0; j < len; j++) {
 			igt_assert_f(tmp[j] == val,
 				     "mismatch in read at %i, got: %i, expected: %i\n",
@@ -212,7 +211,7 @@ static void test_partial_read_writes(void)
 		/* Change contents through gtt to make the pread cachelines
 		 * stale. */
 		val = (i + 17) % 256;
-		blt_bo_fill(staging_bo, scratch_bo, val);
+		blt_bo_fill(staging_buf, scratch_buf, val);
 
 		/* partial write */
 		start = random() % BO_SIZE;
@@ -220,11 +219,10 @@ static void test_partial_read_writes(void)
 
 		memset(tmp, i + 63, BO_SIZE);
 
-		drm_intel_bo_subdata(scratch_bo, start, len, tmp);
+		gem_write(fd, scratch_buf->handle, start, tmp, len);
 
-		copy_bo(scratch_bo, 1, tiled_staging_bo, 1);
-		drm_intel_bo_get_subdata(tiled_staging_bo, 0, BO_SIZE,
-					 compare_tmp);
+		copy_bo(scratch_buf, 1, tiled_staging_buf, 1);
+		gem_read(fd, tiled_staging_buf->handle, 0, compare_tmp, BO_SIZE);
 
 		for (j = 0; j < start; j++) {
 			igt_assert_f(compare_tmp[j] == val,
@@ -241,7 +239,6 @@ static void test_partial_read_writes(void)
 				     "mismatch at %i, got: %i, expected: %i\n",
 				     j, tmp[j], val);
 		}
-		drm_intel_gem_bo_unmap_gtt(staging_bo);
 
 		igt_progress("partial read/writes test: ", i, ROUNDS);
 	}
@@ -261,8 +258,6 @@ static bool known_swizzling(uint32_t handle)
 
 igt_main
 {
-	uint32_t tiling_mode = I915_TILING_X;
-
 	srandom(0xdeadbeef);
 
 	igt_fixture {
@@ -271,28 +266,26 @@ igt_main
 		gem_require_mappable_ggtt(fd);
 		gem_require_blitter(fd);
 
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		devid = intel_get_drm_devid(fd);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
+		bops = buf_ops_create(fd);
+		ibb = intel_bb_create(fd, 4096);
 
 		/* overallocate the buffers we're actually using because */
-		scratch_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
-						      BO_SIZE/4096, 4,
-						      &tiling_mode, &scratch_pitch, 0);
-		igt_assert(tiling_mode == I915_TILING_X);
-		igt_assert(scratch_pitch == 4096);
+		scratch_buf = intel_buf_create(bops, 1024, BO_SIZE/4096, 32, 0,
+					       I915_TILING_X,
+					       I915_COMPRESSION_NONE);
 
 		/*
 		 * As we want to compare our template tiled pattern against
 		 * the target bo, we need consistent swizzling on both.
 		 */
-		igt_require(known_swizzling(scratch_bo->handle));
-		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
-		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
-							    BO_SIZE/4096, 4,
-							    &tiling_mode,
-							    &scratch_pitch, 0);
+		igt_require(known_swizzling(scratch_buf->handle));
+		staging_buf = intel_buf_create(bops, 1024, BO_SIZE/4096, 32,
+					       4096, I915_TILING_NONE,
+					       I915_COMPRESSION_NONE);
+
+		tiled_staging_buf = intel_buf_create(bops, 1024, BO_SIZE/4096,
+						     32, 0, I915_TILING_X,
+						     I915_COMPRESSION_NONE);
 	}
 
 	igt_subtest("reads")
@@ -305,7 +298,11 @@ igt_main
 		test_partial_read_writes();
 
 	igt_fixture {
-		drm_intel_bufmgr_destroy(bufmgr);
+		intel_buf_destroy(scratch_buf);
+		intel_buf_destroy(staging_buf);
+		intel_buf_destroy(tiled_staging_buf);
+		intel_bb_destroy(ibb);
+		buf_ops_destroy(bops);
 
 		close(fd);
 	}
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 13/18] i915/gem_set_tiling_vs_blit.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency. The tests
had depended on buffer reuse mechanism, so logic was changed a bit.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_set_tiling_vs_blt.c | 225 +++++++++++++++--------------
 1 file changed, 118 insertions(+), 107 deletions(-)

diff --git a/tests/i915/gem_set_tiling_vs_blt.c b/tests/i915/gem_set_tiling_vs_blt.c
index cb164154..df3be941 100644
--- a/tests/i915/gem_set_tiling_vs_blt.c
+++ b/tests/i915/gem_set_tiling_vs_blt.c
@@ -57,15 +57,10 @@
 #include "drm.h"
 #include "i915/gem.h"
 #include "igt.h"
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Check for proper synchronization of tiling changes vs."
 		     " tiled gpu access.");
 
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
 #define TEST_SIZE (1024*1024)
 #define TEST_STRIDE (4*1024)
 #define TEST_HEIGHT(stride)	(TEST_SIZE/(stride))
@@ -73,159 +68,174 @@ uint32_t devid;
 
 uint32_t data[TEST_SIZE/4];
 
-static void do_test(uint32_t tiling, unsigned stride,
+static void __set_tiling(struct buf_ops *bops, struct intel_buf *buf,
+			 uint32_t tiling, unsigned stride)
+{
+	int ret;
+
+	ret = __gem_set_tiling(buf_ops_get_fd(bops), buf->handle, tiling, stride);
+
+	buf->surface[0].stride = stride;
+	buf->surface[0].size = buf->surface[0].stride * TEST_HEIGHT(stride);
+	buf->tiling = tiling;
+
+	igt_assert_eq(ret, 0);
+}
+
+static void do_test(struct buf_ops *bops, uint32_t tiling, unsigned stride,
 		    uint32_t tiling_after, unsigned stride_after)
 {
-	drm_intel_bo *busy_bo, *test_bo, *target_bo;
-	int i, ret;
+	struct intel_buf *busy_buf, *test_buf, *target_buf;
+	struct intel_bb *ibb;
+	int i, fd = buf_ops_get_fd(bops);
 	uint32_t *ptr;
-	uint32_t test_bo_handle;
+	uint32_t test_buf_handle;
 	uint32_t blt_stride, blt_bits;
 	bool tiling_changed = false;
 
 	igt_info("filling ring .. ");
-	busy_bo = drm_intel_bo_alloc(bufmgr, "busy bo bo", 16*1024*1024, 4096);
-
+	busy_buf = intel_buf_create(bops, 2048, 2048, 32, 0,
+				    I915_TILING_NONE, I915_COMPRESSION_NONE);
+	ibb = intel_bb_create_with_relocs(fd, 4 * 4096);
+	intel_bb_set_fencing(ibb, false);
+	intel_bb_add_intel_buf(ibb, busy_buf, true);
 	for (i = 0; i < 250; i++) {
-		BLIT_COPY_BATCH_START(0);
-		OUT_BATCH((3 << 24) | /* 32 bits */
-			  (0xcc << 16) | /* copy ROP */
-			  2*1024*4);
-		OUT_BATCH(0 << 16 | 1024);
-		OUT_BATCH((2048) << 16 | (2048));
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-		OUT_BATCH(0 << 16 | 0);
-		OUT_BATCH(2*1024*4);
-		OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-		ADVANCE_BATCH();
-
-		if (batch->gen >= 6) {
-			BEGIN_BATCH(3, 0);
-			OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
-			OUT_BATCH(0);
-			OUT_BATCH(0);
-			ADVANCE_BATCH();
+		intel_bb_blit_start(ibb, 0);
+		intel_bb_out(ibb, (3 << 24) | /* 32 bits */
+			     (0xcc << 16) | /* copy ROP */
+			     2*1024*4);
+		intel_bb_out(ibb, 0 << 16 | 1024);
+		intel_bb_out(ibb, 2048 << 16 | 2048);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER,
+					   I915_GEM_DOMAIN_RENDER, 0, 0);
+		intel_bb_out(ibb, 0 << 16 | 0);
+		intel_bb_out(ibb, 2*1024*4);
+		intel_bb_emit_reloc_fenced(ibb, busy_buf->handle,
+					   I915_GEM_DOMAIN_RENDER, 0, 0, 0);
+
+		if (ibb->gen >= 6) {
+			intel_bb_out(ibb, XY_SETUP_CLIP_BLT_CMD);
+			intel_bb_out(ibb, 0);
+			intel_bb_out(ibb, 0);
 		}
 	}
-	intel_batchbuffer_flush(batch);
-
+	intel_bb_flush_blit(ibb);
 	igt_info("playing tricks .. ");
 	/* first allocate the target so it gets out of the way of playing funky
 	 * tricks */
-	target_bo = drm_intel_bo_alloc(bufmgr, "target bo", TEST_SIZE, 4096);
+	target_buf = intel_buf_create(bops, TEST_WIDTH(TEST_STRIDE),
+				      TEST_HEIGHT(TEST_STRIDE), 32, 0,
+				      I915_TILING_NONE, I915_COMPRESSION_NONE);
 
+	intel_bb_add_intel_buf(ibb, target_buf, true);
 	/* allocate buffer with parameters _after_ transition we want to check
 	 * and touch it, so that it's properly aligned in the gtt. */
-	test_bo = drm_intel_bo_alloc(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
-	test_bo_handle = test_bo->handle;
-	ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
-	igt_assert_eq(ret, 0);
-	drm_intel_gem_bo_map_gtt(test_bo);
-	ptr = test_bo->virtual;
-	*ptr = 0;
-	ptr = NULL;
-	drm_intel_gem_bo_unmap_gtt(test_bo);
+	test_buf = intel_buf_create(bops, TEST_WIDTH(stride_after),
+				   TEST_HEIGHT(stride_after), 32, 0,
+				   tiling_after, I915_COMPRESSION_NONE);
 
-	drm_intel_bo_unreference(test_bo);
+	intel_bb_add_intel_buf(ibb, test_buf, true);
 
-	test_bo = NULL;
+	test_buf_handle = test_buf->handle;
 
-	/* note we need a bo bigger than batches, otherwise the buffer reuse
-	 * trick will fail. */
-	test_bo = drm_intel_bo_alloc(bufmgr, "busy bo", TEST_SIZE, 4096);
-	/* double check that the reuse trick worked */
-	igt_assert(test_bo_handle == test_bo->handle);
+	ptr = gem_mmap__gtt(fd, test_buf->handle, TEST_SIZE,
+			    PROT_READ | PROT_WRITE);
+	*ptr = 0;
+	gem_munmap(ptr, TEST_SIZE);
 
-	test_bo_handle = test_bo->handle;
-	/* ensure we have the right tiling before we start. */
-	ret = drm_intel_bo_set_tiling(test_bo, &tiling, stride);
-	igt_assert_eq(ret, 0);
+	/* Reuse previously aligned in the gtt object */
+	intel_buf_init_using_handle(bops, test_buf_handle, test_buf,
+				    TEST_WIDTH(stride), TEST_HEIGHT(stride), 32,
+				    0, tiling, I915_COMPRESSION_NONE);
+	igt_assert_eq_u32(intel_buf_bo_size(test_buf), TEST_SIZE);
+	intel_buf_set_ownership(test_buf, true);
 
 	if (tiling == I915_TILING_NONE) {
-		drm_intel_bo_subdata(test_bo, 0, TEST_SIZE, data);
+		gem_write(fd, test_buf->handle, 0, data, TEST_SIZE);
 	} else {
-		drm_intel_gem_bo_map_gtt(test_bo);
-		ptr = test_bo->virtual;
+		ptr = gem_mmap__gtt(fd, test_buf->handle, TEST_SIZE,
+				    PROT_READ | PROT_WRITE);
+
 		memcpy(ptr, data, TEST_SIZE);
 		ptr = NULL;
-		drm_intel_gem_bo_unmap_gtt(test_bo);
+		gem_munmap(ptr, TEST_SIZE);
 	}
 
 	blt_stride = stride;
 	blt_bits = 0;
-	if (intel_gen(devid) >= 4 && tiling != I915_TILING_NONE) {
+	if (intel_gen(ibb->devid) >= 4 && tiling != I915_TILING_NONE) {
 		blt_stride /= 4;
 		blt_bits = XY_SRC_COPY_BLT_SRC_TILED;
 	}
 
-	BLIT_COPY_BATCH_START(blt_bits);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+	intel_bb_blit_start(ibb, blt_bits);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  stride);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH((TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
-	OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(blt_stride);
-	OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-	intel_batchbuffer_flush(batch);
-
-	drm_intel_bo_unreference(test_bo);
-
-	test_bo = drm_intel_bo_alloc_for_render(bufmgr, "tiled busy bo", TEST_SIZE, 4096);
-	/* double check that the reuse trick worked */
-	igt_assert(test_bo_handle == test_bo->handle);
-	ret = drm_intel_bo_set_tiling(test_bo, &tiling_after, stride_after);
-	igt_assert_eq(ret, 0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, (TEST_HEIGHT(stride)) << 16 | (TEST_WIDTH(stride)));
+	intel_bb_emit_reloc_fenced(ibb, target_buf->handle,
+				   I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, 0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, blt_stride);
+	intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+				   I915_GEM_DOMAIN_RENDER, 0, 0, 0);
+	intel_bb_flush_blit(ibb);
+
+	__set_tiling(bops, test_buf, tiling_after, stride_after);
 
 	/* Note: We don't care about gen4+ here because the blitter doesn't use
 	 * fences there. So not setting tiling flags on the tiled buffer is ok.
 	 */
-	BLIT_COPY_BATCH_START(0);
-	OUT_BATCH((3 << 24) | /* 32 bits */
+
+	intel_bb_blit_start(ibb, 0);
+	intel_bb_out(ibb, (3 << 24) | /* 32 bits */
 		  (0xcc << 16) | /* copy ROP */
 		  stride_after);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH((1) << 16 | (1));
-	OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(0 << 16 | 0);
-	OUT_BATCH(stride_after);
-	OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-	ADVANCE_BATCH();
-	intel_batchbuffer_flush(batch);
-
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, (1) << 16 | (1));
+	intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+				   I915_GEM_DOMAIN_RENDER,
+				   I915_GEM_DOMAIN_RENDER, 0, 0);
+	intel_bb_out(ibb, 0 << 16 | 0);
+	intel_bb_out(ibb, stride_after);
+	intel_bb_emit_reloc_fenced(ibb, test_buf->handle,
+				   I915_GEM_DOMAIN_RENDER, 0, 0, 0);
+	intel_bb_flush_blit(ibb);
 	/* Now try to trick the kernel the kernel into changing up the fencing
 	 * too early. */
-
 	igt_info("checking .. ");
 	memset(data, 0, TEST_SIZE);
-	drm_intel_bo_get_subdata(target_bo, 0, TEST_SIZE, data);
+
+	gem_read(fd, target_buf->handle, 0, data, TEST_SIZE);
 	for (i = 0; i < TEST_SIZE/4; i++)
 		igt_assert(data[i] == i);
 
-	/* check whether tiling on the test_bo actually changed. */
-	drm_intel_gem_bo_map_gtt(test_bo);
-	ptr = test_bo->virtual;
+	/* check whether tiling on the test_buf actually changed. */
+	ptr = gem_mmap__gtt(fd, test_buf->handle, TEST_SIZE,
+			    PROT_WRITE | PROT_READ);
+
 	for (i = 0; i < TEST_SIZE/4; i++)
 		if (ptr[i] != data[i])
 			tiling_changed = true;
-	ptr = NULL;
-	drm_intel_gem_bo_unmap_gtt(test_bo);
+
+	gem_munmap(ptr, TEST_SIZE);
 	igt_assert(tiling_changed);
 
-	drm_intel_bo_unreference(test_bo);
-	drm_intel_bo_unreference(target_bo);
-	drm_intel_bo_unreference(busy_bo);
+	intel_buf_destroy(test_buf);
+	intel_buf_destroy(target_buf);
+	intel_buf_destroy(busy_buf);
+
 	igt_info("done\n");
 }
 
-int fd;
-
 igt_main
 {
-	int i;
+	int fd, i;
 	uint32_t tiling, tiling_after;
+	struct buf_ops *bops;
 
 	igt_fixture {
 		for (i = 0; i < 1024*256; i++)
@@ -235,17 +245,13 @@ igt_main
 		igt_require_gem(fd);
 		gem_require_blitter(fd);
 		igt_require(gem_available_fences(fd) > 0);
-
-		bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
-		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
-		devid = intel_get_drm_devid(fd);
-		batch = intel_batchbuffer_alloc(bufmgr, devid);
+		bops = buf_ops_create(fd);
 	}
 
 	igt_subtest("untiled-to-tiled") {
 		tiling = I915_TILING_NONE;
 		tiling_after = I915_TILING_X;
-		do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
+		do_test(bops, tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
 		igt_assert(tiling == I915_TILING_NONE);
 		igt_assert(tiling_after == I915_TILING_X);
 	}
@@ -253,7 +259,7 @@ igt_main
 	igt_subtest("tiled-to-untiled") {
 		tiling = I915_TILING_X;
 		tiling_after = I915_TILING_NONE;
-		do_test(tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
+		do_test(bops, tiling, TEST_STRIDE, tiling_after, TEST_STRIDE);
 		igt_assert(tiling == I915_TILING_X);
 		igt_assert(tiling_after == I915_TILING_NONE);
 	}
@@ -261,8 +267,13 @@ igt_main
 	igt_subtest("tiled-to-tiled") {
 		tiling = I915_TILING_X;
 		tiling_after = I915_TILING_X;
-		do_test(tiling, TEST_STRIDE/2, tiling_after, TEST_STRIDE);
+		do_test(bops, tiling, TEST_STRIDE/2, tiling_after, TEST_STRIDE);
 		igt_assert(tiling == I915_TILING_X);
 		igt_assert(tiling_after == I915_TILING_X);
 	}
+
+	igt_fixture{
+		buf_ops_destroy(bops);
+		close(fd);
+	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 14/18] tests/kms_fence_pin_leak.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/kms_fence_pin_leak.c | 84 ++++++++++++++++++++------------------
 1 file changed, 45 insertions(+), 39 deletions(-)

diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c
index b59efc0a..ad4c3799 100644
--- a/tests/kms_fence_pin_leak.c
+++ b/tests/kms_fence_pin_leak.c
@@ -37,34 +37,45 @@ IGT_TEST_DESCRIPTION("Exercises full ppgtt fence pin_count leak in the "
 typedef struct {
 	int drm_fd;
 	uint32_t devid;
-	drm_intel_bufmgr *bufmgr;
+	struct buf_ops *bops;
 	igt_display_t display;
-	drm_intel_bo *bos[64]; /* >= num fence registers */
+	struct intel_buf *bos[64]; /* >= num fence registers */
 } data_t;
 
-static void exec_nop(data_t *data, uint32_t handle, drm_intel_context *context)
+static void exec_nop(data_t *data, struct igt_fb *fb, uint32_t context)
 {
-	drm_intel_bo *dst;
-	struct intel_batchbuffer *batch;
+	struct intel_buf *dst;
+	struct intel_bb *ibb;
+	uint32_t name, handle, tiling, stride, width, height, bpp, size;
 
-	dst = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, "", handle);
-	igt_assert(dst);
+	tiling = igt_fb_mod_to_tiling(fb->modifier);
+	stride = fb->strides[0];
+	bpp = fb->plane_bpp[0];
+	size = fb->size;
+	width = stride / (bpp / 8);
+	height = size / stride;
 
-	batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
-	igt_assert(batch);
+	name = gem_flink(data->drm_fd, fb->gem_handle);
+	handle = gem_open(data->drm_fd, name);
+	dst = intel_buf_create_using_handle(data->bops, handle,
+					    width, height, bpp, 0, tiling, 0);
+	intel_buf_set_ownership(dst, true);
+
+	ibb = intel_bb_create(buf_ops_get_fd(data->bops), 4096);
 
 	/* add the reloc to make sure the kernel will think we write to dst */
-	BEGIN_BATCH(4, 1);
-	OUT_BATCH(MI_BATCH_BUFFER_END);
-	OUT_BATCH(MI_NOOP);
-	OUT_RELOC(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-	OUT_BATCH(MI_NOOP);
-	ADVANCE_BATCH();
+	intel_bb_add_intel_buf(ibb, dst, true);
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_emit_reloc(ibb, dst->handle, I915_GEM_DOMAIN_RENDER,
+			    I915_GEM_DOMAIN_RENDER, 0, 0x0);
+	intel_bb_out(ibb, MI_NOOP);
+
+	intel_bb_flush_render_with_context(ibb, context);
 
-	intel_batchbuffer_flush_with_context(batch, context);
-	intel_batchbuffer_free(batch);
+	intel_bb_destroy(ibb);
 
-	drm_intel_bo_unreference(dst);
+	intel_buf_destroy(dst);
 }
 
 static void alloc_fence_objs(data_t *data)
@@ -72,13 +83,12 @@ static void alloc_fence_objs(data_t *data)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(data->bos); i++) {
-		drm_intel_bo *bo;
-
-		bo = drm_intel_bo_alloc(data->bufmgr, "fence bo", 4096, 4096);
-		igt_assert(bo);
-		gem_set_tiling(data->drm_fd, bo->handle, I915_TILING_X, 512);
+		struct intel_buf *buf;
 
-		data->bos[i] = bo;
+		buf = intel_buf_create(data->bops, 128, 8, 32, 0,
+				       I915_TILING_X, I915_COMPRESSION_NONE);
+		igt_assert(buf->surface[0].stride == 512);
+		data->bos[i] = buf;
 	}
 }
 
@@ -102,7 +112,7 @@ static void free_fence_objs(data_t *data)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(data->bos); i++)
-		drm_intel_bo_unreference(data->bos[i]);
+		intel_buf_destroy(data->bos[i]);
 }
 
 static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
@@ -133,19 +143,18 @@ static void run_single_test(data_t *data, enum pipe pipe, igt_output_t *output)
 	igt_display_commit(display);
 
 	for (i = 0; i < 64; i++) {
-		drm_intel_context *ctx;
+		uint32_t ctx;
 
 		/*
 		 * Link fb.gem_handle to the ppgtt vm of ctx so that the context
 		 * destruction will unbind the obj from the ppgtt vm in question.
 		 */
-		ctx = drm_intel_gem_context_create(data->bufmgr);
-		igt_assert(ctx);
-		exec_nop(data, fb[i&1].gem_handle, ctx);
-		drm_intel_gem_context_destroy(ctx);
+		ctx = gem_context_create(data->drm_fd);
+		exec_nop(data, &fb[i&1], ctx);
+		gem_context_destroy(data->drm_fd, ctx);
 
 		/* Force a context switch to make sure ctx gets destroyed for real. */
-		exec_nop(data, fb[i&1].gem_handle, NULL);
+		exec_nop(data, &fb[i&1], 0);
 
 		gem_sync(data->drm_fd, fb[i&1].gem_handle);
 
@@ -196,7 +205,7 @@ static void run_test(data_t *data)
 
 igt_simple_main
 {
-	drm_intel_context *ctx;
+	uint32_t ctx;
 	data_t data = {};
 
 	data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
@@ -207,15 +216,12 @@ igt_simple_main
 
 	kmstest_set_vt_graphics_mode();
 
-	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
-	igt_assert(data.bufmgr);
-	drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
+	data.bops = buf_ops_create(data.drm_fd);
 
 	igt_display_require(&data.display, data.drm_fd);
 
-	ctx = drm_intel_gem_context_create(data.bufmgr);
-	igt_require(ctx);
-	drm_intel_gem_context_destroy(ctx);
+	ctx = gem_context_create(data.drm_fd);
+	gem_context_destroy(data.drm_fd, ctx);
 
 	alloc_fence_objs(&data);
 
@@ -223,6 +229,6 @@ igt_simple_main
 
 	free_fence_objs(&data);
 
-	drm_intel_bufmgr_destroy(data.bufmgr);
+	buf_ops_destroy(data.bops);
 	igt_display_fini(&data.display);
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 15/18] tests/kms_flip.c: Remove libdrm dependency

[Dominik Grzegorzek]

Use intel_bb / intel_buf to remove libdrm dependency.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/kms_flip.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index b33cfe9c..51b9ac95 100755
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -86,8 +86,7 @@
 
 drmModeRes *resources;
 int drm_fd;
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
+static struct buf_ops *bops;
 uint32_t devid;
 int test_time = 3;
 static bool monotonic_timestamp;
@@ -211,20 +210,19 @@ static void emit_fence_stress(struct test_output *o)
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t buf[2] = { MI_BATCH_BUFFER_END, 0 };
-	drm_intel_bo **bo;
+	struct intel_buf **bo;
 	int i;
 
-	igt_require(bufmgr);
+	igt_require(bops);
 
 	igt_assert(num_fences);
 	bo = calloc(sizeof(*bo), num_fences);
 	exec = calloc(sizeof(*exec), num_fences+1);
 	for (i = 0; i < num_fences - 1; i++) {
 		uint32_t tiling = I915_TILING_X;
-		unsigned long pitch = 0;
-		bo[i] = drm_intel_bo_alloc_tiled(bufmgr,
-						 "X tiled bo", 1024, 1024, 4,
-						 &tiling, &pitch, 0);
+		bo[i] = intel_buf_create(bops, 1024, 1024, 32, 0, tiling,
+					 I915_COMPRESSION_NONE);
+
 		exec[i].handle = bo[i]->handle;
 		exec[i].flags = EXEC_OBJECT_NEEDS_FENCE;
 	}
@@ -244,7 +242,7 @@ static void emit_fence_stress(struct test_output *o)
 
 	gem_close(drm_fd, exec[i].handle);
 	for (i = 0; i < num_fences - 1; i++)
-		drm_intel_bo_unreference(bo[i]);
+		intel_buf_destroy(bo[i]);
 	free(bo);
 	free(exec);
 }
@@ -1664,11 +1662,7 @@ igt_main
 		get_timestamp_format();
 
 		if (is_i915_device(drm_fd)) {
-			bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
-			if (bufmgr) {
-				devid = intel_get_drm_devid(drm_fd);
-				batch = intel_batchbuffer_alloc(bufmgr, devid);
-			}
+			bops = buf_ops_create(drm_fd);
 		}
 	}
 
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 16/18] tests/kms_psr2_su.c: Get rid of unused bufmgr

[Dominik Grzegorzek]

Removal of bufmgr that was only set but not used.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/kms_psr2_su.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/tests/kms_psr2_su.c b/tests/kms_psr2_su.c
index d549d9a3..9215c59d 100644
--- a/tests/kms_psr2_su.c
+++ b/tests/kms_psr2_su.c
@@ -30,7 +30,6 @@
 #include <stdio.h>
 #include <string.h>
 #include <sys/timerfd.h>
-#include "intel_bufmgr.h"
 
 IGT_TEST_DESCRIPTION("Test PSR2 selective update");
 
@@ -65,7 +64,6 @@ typedef struct {
 	int drm_fd;
 	int debugfs_fd;
 	igt_display_t display;
-	drm_intel_bufmgr *bufmgr;
 	drmModeModeInfo *mode;
 	igt_output_t *output;
 	struct igt_fb fb[2];
@@ -247,10 +245,6 @@ igt_main
 					       data.debugfs_fd, PSR_MODE_2),
 			      "Sink does not support PSR2\n");
 
-		data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
-		igt_assert(data.bufmgr);
-		drm_intel_bufmgr_gem_enable_reuse(data.bufmgr);
-
 		display_init(&data);
 
 		/* Test if PSR2 can be enabled */
@@ -287,7 +281,6 @@ igt_main
 
 	igt_fixture {
 		close(data.debugfs_fd);
-		drm_intel_bufmgr_destroy(data.bufmgr);
 		display_fini(&data);
 	}
 }
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 17/18] tests/i915/gem_ppgtt: make copying more readable

[Dominik Grzegorzek]

Use intel_bb_copy_intel_buf instead of intel_bb_blit_copy
to make the code simplier.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_ppgtt.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index 949601ac..5d7239fe 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -165,12 +165,8 @@ static void fork_bcs_copy(int timeout, uint32_t final,
 			src[1] = create_bo(dst[child]->bops,
 					   i++ | child << 16);
 
-			intel_bb_blt_copy(ibb, src[1], 0, 0, 4096,
-					  src[0], 0, 0, 4096,
-					  4096/4, SIZE/4096, 32);
-			intel_bb_blt_copy(ibb, src[0], 0, 0, 4096,
-					  dst[child], 0, 0, 4096,
-					  4096/4, SIZE/4096, 32);
+			intel_bb_copy_intel_buf(ibb, src[1], src[0], SIZE);
+			intel_bb_copy_intel_buf(ibb, dst[0], src[child], SIZE);
 
 			intel_buf_destroy(src[1]);
 			intel_buf_destroy(src[0]);
@@ -180,12 +176,8 @@ static void fork_bcs_copy(int timeout, uint32_t final,
 		src[1] = create_bo(dst[child]->bops,
 				   final | child << 16);
 
-		intel_bb_blt_copy(ibb, src[1], 0, 0, 4096,
-				  src[0], 0, 0, 4096,
-				  4096/4, SIZE/4096, 32);
-		intel_bb_blt_copy(ibb, src[0], 0, 0, 4096,
-				  dst[child], 0, 0, 4096,
-				  4096/4, SIZE/4096, 32);
+		intel_bb_copy_intel_buf(ibb, src[1], src[0], SIZE);
+		intel_bb_copy_intel_buf(ibb, dst[0], src[child], SIZE);
 
 		intel_buf_destroy(src[1]);
 		intel_buf_destroy(src[0]);
-- 
2.20.1

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[igt-dev] [PATCH i-g-t 18/18] HAX: don't run failing test in BAT

[Dominik Grzegorzek]

gem_tiled_blits will fail on !llc platforms
https://gitlab.freedesktop.org/drm/intel/-/issues/2328

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
---
 tests/intel-ci/fast-feedback.testlist | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index aa2eb329..4180b5a1 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -37,7 +37,6 @@ igt@gem_render_tiled_blits@basic
 igt@gem_ringfill@basic-all
 igt@gem_sync@basic-all
 igt@gem_sync@basic-each
-igt@gem_tiled_blits@basic
 igt@gem_tiled_fence_blits@basic
 igt@gem_tiled_pread_basic
 igt@gem_wait@busy@all
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t 02/18] lib/intel_batchbuffer: Add control over fencing in intel_bb

[Chris Wilson]

Quoting Dominik Grzegorzek (2020-09-29 12:28:54)
> From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> 
> From default intel_bb uses fencing to track subsequent execs.
> It is required to properly sync intel_bb. Unfortunately this
> also has some drawback, when we want to use same intel_bb to
> schedule some time consuming job then run something else. Fencing
> as turned on from default will serialize such execs. To avoid that
> add possibility to turn on / off fencing in the intel_bb.

I'm still getting confused by this. I don't see where you are
serialising on the old fence, you are just merging the fences for later
waits. That does mean that wait does wait for all, both the short and
long jobs, but the use of the fence is not serialising the execution of
those jobs. (Providing that the intel_bb is used in such a way to allow
for parallel execution i.e. multiple timelines from using different
contexts or independent engines.)
-Chris
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[igt-dev] ✓ Fi.CI.BAT: success for tests: Remove libdrm dependency

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 6143 bytes --]

== Series Details ==

Series: tests: Remove libdrm dependency
URL   : https://patchwork.freedesktop.org/series/82203/
State : success

== Summary ==

CI Bug Log - changes from IGT_5791 -> IGTPW_5022
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/index.html

Known issues
------------

  Here are the changes found in IGTPW_5022 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@vgem_basic@unload:
    - fi-skl-guc:         [PASS][3] -> [DMESG-WARN][4] ([i915#2203])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-skl-guc/igt@vgem_basic@unload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-skl-guc/igt@vgem_basic@unload.html

  
#### Possible fixes ####

  * {igt@core_hotunplug@unbind-rebind}:
    - fi-kbl-x1275:       [DMESG-WARN][5] ([i915#62] / [i915#92]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-n3050:       [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-bsw-kefka:       [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
    - {fi-tgl-dsi}:       [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-tgl-dsi/igt@kms_busy@basic@flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-tgl-dsi/igt@kms_busy@basic@flip.html
    - fi-kbl-x1275:       [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-kbl-x1275/igt@kms_busy@basic@flip.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-kbl-x1275/igt@kms_busy@basic@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - {fi-kbl-7560u}:     [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-connector-state:
    - {fi-tgl-dsi}:       [DMESG-WARN][19] ([i915#402]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-tgl-dsi/igt@kms_force_connector_basic@force-connector-state.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-tgl-dsi/igt@kms_force_connector_basic@force-connector-state.html

  
#### Warnings ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-x1275:       [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - fi-kbl-x1275:       [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (46 -> 39)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5791 -> IGTPW_5022

  CI-20190529: 20190529
  CI_DRM_9072: cbd61a1eb61b1919ff10dd826525b4352c10da47 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5022: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/index.html
  IGT_5791: d089599869755e80accd16d3018b5f9ace139588 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/index.html

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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.IGT: failure for tests: Remove libdrm dependency

[Patchwork]

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== Series Details ==

Series: tests: Remove libdrm dependency
URL   : https://patchwork.freedesktop.org/series/82203/
State : failure

== Summary ==

CI Bug Log - changes from IGT_5791_full -> IGTPW_5022_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5022_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5022_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5022_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_pipe_control_store_loop@fresh-buffer:
    - shard-snb:          [PASS][1] -> [FAIL][2] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-snb7/igt@gem_pipe_control_store_loop@fresh-buffer.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-snb6/igt@gem_pipe_control_store_loop@fresh-buffer.html

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-kbl:          [PASS][3] -> [FAIL][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl4/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl7/igt@gem_ppgtt@blt-vs-render-ctx0.html
    - shard-glk:          [PASS][5] -> [FAIL][6] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-glk1/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-glk4/igt@gem_ppgtt@blt-vs-render-ctx0.html
    - shard-iclb:         [PASS][7] -> [FAIL][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-iclb2/igt@gem_ppgtt@blt-vs-render-ctx0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-iclb5/igt@gem_ppgtt@blt-vs-render-ctx0.html

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-tglb:         [PASS][9] -> [FAIL][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-tglb8/igt@gem_ppgtt@blt-vs-render-ctxn.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-tglb1/igt@gem_ppgtt@blt-vs-render-ctxn.html
    - shard-hsw:          [PASS][11] -> [FAIL][12] +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-hsw7/igt@gem_ppgtt@blt-vs-render-ctxn.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-hsw7/igt@gem_ppgtt@blt-vs-render-ctxn.html

  
New tests
---------

  New tests have been introduced between IGT_5791_full and IGTPW_5022_full:

### New IGT tests (1) ###

  * igt@gem_exec_parallel@userptr:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in IGTPW_5022_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-glk:          [PASS][13] -> [DMESG-WARN][14] ([i915#118] / [i915#95])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-glk5/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@gem_tiled_blits@basic:
    - shard-apl:          [PASS][15] -> [FAIL][16] ([i915#1635]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-apl6/igt@gem_tiled_blits@basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-apl8/igt@gem_tiled_blits@basic.html

  * igt@kms_3d:
    - shard-iclb:         [PASS][17] -> [DMESG-WARN][18] ([i915#1226])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-iclb6/igt@kms_3d.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-iclb3/igt@kms_3d.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([i915#1635] / [i915#1982]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-apl4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +9 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
    - shard-iclb:         [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-iclb4/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-iclb3/igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
    - shard-kbl:          [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl7/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl4/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html

  * igt@kms_vblank@pipe-a-accuracy-idle:
    - shard-tglb:         [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-tglb2/igt@kms_vblank@pipe-a-accuracy-idle.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-tglb6/igt@kms_vblank@pipe-a-accuracy-idle.html

  
#### Possible fixes ####

  * {igt@gem_ctx_persistence@heartbeat-many}:
    - shard-tglb:         [FAIL][31] ([i915#2520]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-tglb1/igt@gem_ctx_persistence@heartbeat-many.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-tglb5/igt@gem_ctx_persistence@heartbeat-many.html

  * {igt@gem_ctx_persistence@heartbeat-stop}:
    - shard-kbl:          [FAIL][33] ([i915#2520]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl2/igt@gem_ctx_persistence@heartbeat-stop.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl1/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_exec_reloc@basic-many-active@vecs0:
    - shard-glk:          [FAIL][35] ([i915#2389]) -> [PASS][36] +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-glk5/igt@gem_exec_reloc@basic-many-active@vecs0.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-glk5/igt@gem_exec_reloc@basic-many-active@vecs0.html

  * igt@i915_selftest@mock@contexts:
    - shard-apl:          [INCOMPLETE][37] ([i915#1635] / [i915#2278]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-apl3/igt@i915_selftest@mock@contexts.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-apl1/igt@i915_selftest@mock@contexts.html

  * {igt@kms_async_flips@alternate-sync-async-flip}:
    - shard-kbl:          [FAIL][39] ([i915#2521]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl3/igt@kms_async_flips@alternate-sync-async-flip.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl4/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding:
    - shard-kbl:          [FAIL][41] ([i915#54]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
    - shard-apl:          [FAIL][43] ([i915#1635] / [i915#54]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][45] ([i915#72]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-glk9/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][47] ([i915#96]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-kbl:          [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-tglb:         [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_vblank@pipe-c-accuracy-idle:
    - shard-glk:          [DMESG-WARN][55] ([i915#1982]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-glk5/igt@kms_vblank@pipe-c-accuracy-idle.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-glk2/igt@kms_vblank@pipe-c-accuracy-idle.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][57] ([i915#658]) -> [SKIP][58] ([i915#588])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          [DMESG-FAIL][59] ([fdo#108145] / [i915#1635] / [i915#1982]) -> [FAIL][60] ([fdo#108145] / [i915#1635] / [i915#265])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_psr@suspend:
    - shard-tglb:         [INCOMPLETE][61] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#456]) -> [DMESG-WARN][62] ([i915#2411])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5791/shard-tglb3/igt@kms_psr@suspend.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/shard-tglb7/igt@kms_psr@suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2519]: https://gitlab.freedesktop.org/drm/intel/issues/2519
  [i915#2520]: https://gitlab.freedesktop.org/drm/intel/issues/2520
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96


Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5791 -> IGTPW_5022

  CI-20190529: 20190529
  CI_DRM_9072: cbd61a1eb61b1919ff10dd826525b4352c10da47 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5022: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/index.html
  IGT_5791: d089599869755e80accd16d3018b5f9ace139588 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5022/index.html

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