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From: Hanks Chen <hanks.chen@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	<devicetree@vger.kernel.org>, CC Hwang <cc.hwang@mediatek.com>,
	Andy Teng <andy.teng@mediatek.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	YueHaibing <yuehaibing@huawei.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	Loda Chou <loda.chou@mediatek.com>,
	mtk01761 <wendell.lin@mediatek.com>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
Date: Sat, 3 Oct 2020 18:06:47 +0800	[thread overview]
Message-ID: <1601719607.774.1.camel@mtkswgap22> (raw)
In-Reply-To: <1599546314.24690.3.camel@mtkswgap22>

Hi Michael & Stephen,

Please kindly let me know your comments about this patch.
Thanks

Regards,
Hanks


On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote:
> Hi all,
> 
> Gentle ping on this patch.
> 
> Thanks
> 
> 
> Hanks Chen
> 
> 
> On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> > 
> > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> >  drivers/clk/mediatek/clk-mt6779.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766cccf5844..6e0d3a166729 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
> >  		    "pwm_sel", 19),
> >  	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> >  		    "pwm_sel", 21),
> > +	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > +		    "uart_sel", 22),
> >  	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> >  		    "uart_sel", 23),
> >  	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek


WARNING: multiple messages have this Message-ID (diff)
From: Hanks Chen <hanks.chen@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org, CC Hwang <cc.hwang@mediatek.com>,
	Andy Teng <andy.teng@mediatek.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	YueHaibing <yuehaibing@huawei.com>,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Loda Chou <loda.chou@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	mtk01761 <wendell.lin@mediatek.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
Date: Sat, 3 Oct 2020 18:06:47 +0800	[thread overview]
Message-ID: <1601719607.774.1.camel@mtkswgap22> (raw)
In-Reply-To: <1599546314.24690.3.camel@mtkswgap22>

Hi Michael & Stephen,

Please kindly let me know your comments about this patch.
Thanks

Regards,
Hanks


On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote:
> Hi all,
> 
> Gentle ping on this patch.
> 
> Thanks
> 
> 
> Hanks Chen
> 
> 
> On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> > 
> > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> >  drivers/clk/mediatek/clk-mt6779.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766cccf5844..6e0d3a166729 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
> >  		    "pwm_sel", 19),
> >  	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> >  		    "pwm_sel", 21),
> > +	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > +		    "uart_sel", 22),
> >  	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> >  		    "uart_sel", 23),
> >  	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Hanks Chen <hanks.chen@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org, CC Hwang <cc.hwang@mediatek.com>,
	Andy Teng <andy.teng@mediatek.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	YueHaibing <yuehaibing@huawei.com>,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Loda Chou <loda.chou@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	mtk01761 <wendell.lin@mediatek.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
Date: Sat, 3 Oct 2020 18:06:47 +0800	[thread overview]
Message-ID: <1601719607.774.1.camel@mtkswgap22> (raw)
In-Reply-To: <1599546314.24690.3.camel@mtkswgap22>

Hi Michael & Stephen,

Please kindly let me know your comments about this patch.
Thanks

Regards,
Hanks


On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote:
> Hi all,
> 
> Gentle ping on this patch.
> 
> Thanks
> 
> 
> Hanks Chen
> 
> 
> On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> > 
> > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com>
> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> >  drivers/clk/mediatek/clk-mt6779.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766cccf5844..6e0d3a166729 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
> >  		    "pwm_sel", 19),
> >  	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> >  		    "pwm_sel", 21),
> > +	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > +		    "uart_sel", 22),
> >  	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> >  		    "uart_sel", 23),
> >  	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-10-03 10:07 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-30 13:30 [PATCH v10 0/3] Add basic SoC Support for Mediatek MT6779 SoC Hanks Chen
2020-07-30 13:30 ` Hanks Chen
2020-07-30 13:30 ` Hanks Chen
2020-07-30 13:30 ` [PATCH v10 1/3] dt-bindings: pinctrl: add bindings for MediaTek " Hanks Chen
2020-07-30 13:30   ` Hanks Chen
2020-07-30 13:30   ` Hanks Chen
2020-07-31 18:26   ` Rob Herring
2020-07-31 18:26     ` Rob Herring
2020-07-31 18:26     ` Rob Herring
2020-08-03 23:31   ` Linus Walleij
2020-08-03 23:31     ` Linus Walleij
2020-08-03 23:31     ` Linus Walleij
2020-07-30 13:30 ` [PATCH v10 2/3] arm64: dts: add dts nodes for MT6779 Hanks Chen
2020-07-30 13:30   ` Hanks Chen
2020-07-30 13:30   ` Hanks Chen
2020-08-05  2:24   ` Hanks Chen
2020-08-05  2:24     ` Hanks Chen
2020-08-05  2:24     ` Hanks Chen
2020-08-27  8:20     ` Matthias Brugger
2020-08-27  8:20       ` Matthias Brugger
2020-08-27  8:20       ` Matthias Brugger
2020-10-09 12:30   ` Matthias Brugger
2020-10-09 12:30     ` Matthias Brugger
2020-10-09 12:30     ` Matthias Brugger
2020-07-30 13:30 ` [PATCH v10 3/3] clk: mediatek: add UART0 clock support Hanks Chen
2020-07-30 13:30   ` Hanks Chen
2020-07-30 13:30   ` Hanks Chen
2020-09-08  6:25   ` Hanks Chen
2020-09-08  6:25     ` Hanks Chen
2020-09-08  6:25     ` Hanks Chen
2020-10-03 10:06     ` Hanks Chen [this message]
2020-10-03 10:06       ` Hanks Chen
2020-10-03 10:06       ` Hanks Chen
2020-10-08  2:00       ` Stephen Boyd
2020-10-08  2:00         ` Stephen Boyd
2020-10-08  2:00         ` Stephen Boyd
2020-10-08  2:39         ` Hanks Chen
2020-10-08  2:39           ` Hanks Chen
2020-10-08  2:39           ` Hanks Chen
2020-10-08 21:45           ` Stephen Boyd
2020-10-08 21:45             ` Stephen Boyd
2020-10-08 21:45             ` Stephen Boyd
2020-10-08  7:25         ` Matthias Brugger
2020-10-08  7:25           ` Matthias Brugger
2020-10-08  7:25           ` Matthias Brugger
2020-10-08 21:45   ` Stephen Boyd
2020-10-08 21:45     ` Stephen Boyd
2020-10-08 21:45     ` Stephen Boyd

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