From: Kathiravan T <kathirav@codeaurora.org> To: agross@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, sivaprak@codeaurora.org, peter.ujfalusi@ti.com, boris.brezillon@collabora.com, linux-arm-msm@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: kathirav@codeaurora.org, Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Subject: [PATCH 3/3] arm64: dts: ipq6018: Add the QPIC peripheral nodes Date: Tue, 13 Oct 2020 10:45:24 +0530 [thread overview] Message-ID: <1602566124-13456-4-git-send-email-kathirav@codeaurora.org> (raw) In-Reply-To: <1602566124-13456-1-git-send-email-kathirav@codeaurora.org> Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 16 ++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 41 ++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index b31117a93995..6e68de1a0b0a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -62,3 +62,19 @@ spi_0_pins: spi-0-pins { bias-pull-down; }; }; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 1aa8d8579463..6b13e390ee29 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -173,6 +173,17 @@ serial_3_pins: serial3-pinmux { drive-strength = <8>; bias-pull-down; }; + + qpic_pins: qpic-pins { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", + "gpio15", "gpio17"; + function = "qpic_pad"; + drive-strength = <8>; + bias-disable; + }; }; gcc: gcc@1800000 { @@ -274,6 +285,36 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ status = "disabled"; }; + qpic_bam: dma@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1a000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "iface_clk", "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: nand@79b0000 { + compatible = "qcom,ipq6018-nand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: Kathiravan T <kathirav@codeaurora.org> To: agross@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, sivaprak@codeaurora.org, peter.ujfalusi@ti.com, boris.brezillon@collabora.com, linux-arm-msm@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: kathirav@codeaurora.org, Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Subject: [PATCH 3/3] arm64: dts: ipq6018: Add the QPIC peripheral nodes Date: Tue, 13 Oct 2020 10:45:24 +0530 [thread overview] Message-ID: <1602566124-13456-4-git-send-email-kathirav@codeaurora.org> (raw) In-Reply-To: <1602566124-13456-1-git-send-email-kathirav@codeaurora.org> Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Kathiravan T <kathirav@codeaurora.org> --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 16 ++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 41 ++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index b31117a93995..6e68de1a0b0a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -62,3 +62,19 @@ spi_0_pins: spi-0-pins { bias-pull-down; }; }; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 1aa8d8579463..6b13e390ee29 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -173,6 +173,17 @@ serial_3_pins: serial3-pinmux { drive-strength = <8>; bias-pull-down; }; + + qpic_pins: qpic-pins { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", + "gpio15", "gpio17"; + function = "qpic_pad"; + drive-strength = <8>; + bias-disable; + }; }; gcc: gcc@1800000 { @@ -274,6 +285,36 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ status = "disabled"; }; + qpic_bam: dma@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1a000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "iface_clk", "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: nand@79b0000 { + compatible = "qcom,ipq6018-nand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-10-13 5:15 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-13 5:15 [PATCH 0/3] Add QPIC NAND support for IPQ6018 Kathiravan T 2020-10-13 5:15 ` Kathiravan T 2020-10-13 5:15 ` [PATCH 1/3] dt-bindings: qcom_nandc: IPQ6018 QPIC NAND documentation Kathiravan T 2020-10-13 5:15 ` Kathiravan T 2020-10-13 17:23 ` Rob Herring 2020-10-13 17:23 ` Rob Herring 2020-10-30 17:27 ` Miquel Raynal 2020-10-30 17:27 ` Miquel Raynal 2020-10-13 5:15 ` [PATCH 2/3] mtd: rawnand: qcom: Support for IPQ6018 QPIC NAND controller Kathiravan T 2020-10-13 5:15 ` Kathiravan T 2020-10-30 17:27 ` Miquel Raynal 2020-10-30 17:27 ` Miquel Raynal 2020-10-13 5:15 ` Kathiravan T [this message] 2020-10-13 5:15 ` [PATCH 3/3] arm64: dts: ipq6018: Add the QPIC peripheral nodes Kathiravan T
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