[PATCH 1/4] drm/amdgpu: add s0i3 capacity check for s0i3 routine

[PATCH 1/4] drm/amdgpu: add s0i3 capacity check for s0i3 routine

[Prike Liang]

add amdgpu_acpi_is_s0ix_supported() to check the platform
whether support s0i3.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index cd91398..6bbeb04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1228,9 +1228,11 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
 
 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
 		struct amdgpu_dm_backlight_caps *caps);
+bool amdgpu_acpi_is_s0ix_supported(void);
 #else
 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
+static inline bool amdgpu_acpi_is_s0ix_supported(void) { return false; }
 #endif
 
 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 956cbbd..88740e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -27,6 +27,7 @@
 #include <linux/power_supply.h>
 #include <linux/pm_runtime.h>
 #include <acpi/video.h>
+#include <acpi/actbl.h>
 
 #include <drm/drm_crtc_helper.h>
 #include "amdgpu.h"
@@ -907,3 +908,16 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev)
 	unregister_acpi_notifier(&adev->acpi_nb);
 	kfree(adev->atif);
 }
+
+/**
+ * amdgpu_acpi_is_s0ix_supported
+ *
+ * returns true if supported, false if not.
+ */
+bool amdgpu_acpi_is_s0ix_supported()
+{
+	if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)
+		return true;
+
+	return false;
+}
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry

[Prike Liang]

The new amdgpu_gfx_state_change_set() funtion can support set GFX power
change status to D0/D3.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c           | 20 ++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h           |  7 +++++++
 drivers/gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 20 ++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |  9 +++++++++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  1 +
 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h      |  3 ++-
 7 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index d612033..e1d6c8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -789,3 +789,23 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 failed_kiq_write:
 	pr_err("failed to write reg:%x\n", reg);
 }
+
+/* amdgpu_gfx_state_change_set - Handle gfx power state change set
+ * @adev: amdgpu_device pointer
+ * @state: gfx power state(1 -eGpuChangeState_D0Entry and 2 -eGpuChangeState_D3Entry)
+ *
+ */
+
+void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
+{
+
+	mutex_lock(&adev->pm.mutex);
+
+	if (adev->powerplay.pp_funcs &&
+	    adev->powerplay.pp_funcs->gfx_state_change_set)
+			((adev)->powerplay.pp_funcs->gfx_state_change_set(
+					(adev)->powerplay.pp_handle, state));
+
+	mutex_unlock(&adev->pm.mutex);
+
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index d43c116..73942b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -47,6 +47,12 @@ enum gfx_pipe_priority {
 	AMDGPU_GFX_PIPE_PRIO_MAX
 };
 
+/* Argument for PPSMC_MSG_GpuChangeState */
+enum gfx_change_state {
+	GpuChangeState_D0Entry = 1,
+	GpuChangeState_D3Entry,
+};
+
 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
 
@@ -387,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 				  struct amdgpu_iv_entry *entry);
 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
+void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
 #endif
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index a7f92d0..e7b69dd 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -284,6 +284,7 @@ struct amd_pm_funcs {
 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
 	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 	int (*smu_i2c_bus_access)(void *handle, bool acquire);
+	int (*gfx_state_change_set)(void *handle, uint32_t state);
 /* export to DC */
 	u32 (*get_sclk)(void *handle, bool low);
 	u32 (*get_mclk)(void *handle, bool low);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 7e6dcdf..4f319be 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1321,6 +1321,25 @@ static int pp_set_powergating_by_smu(void *handle,
 	return ret;
 }
 
+static int pp_gfx_state_change_set(void *handle, uint32_t state)
+{
+	struct pp_hwmgr *hwmgr = handle;
+
+	if (!hwmgr || !hwmgr->pm_en)
+		return -EINVAL;
+
+	if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
+		pr_info_ratelimited("%s was not implemented.\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&hwmgr->smu_lock);
+	hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
+	mutex_unlock(&hwmgr->smu_lock);
+
+	return 0;
+}
+
 static int pp_notify_smu_enable_pwe(void *handle)
 {
 	struct pp_hwmgr *hwmgr = handle;
@@ -1625,6 +1644,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
 	.switch_power_profile = pp_dpm_switch_power_profile,
 	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
 	.set_powergating_by_smu = pp_set_powergating_by_smu,
+	.gfx_state_change_set = pp_gfx_state_change_set,
 	.get_power_profile_mode = pp_get_power_profile_mode,
 	.set_power_profile_mode = pp_set_power_profile_mode,
 	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index c9cfe90..3f354da 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -319,6 +319,14 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
 	return false;
 }
 
+static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
+{
+	struct amdgpu_device *adev = hwmgr->adev;
+	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
+
+	return 0;
+}
+
 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 {
 	struct amdgpu_device *adev = hwmgr->adev;
@@ -1394,6 +1402,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
 	.get_power_profile_mode = smu10_get_power_profile_mode,
 	.set_power_profile_mode = smu10_set_power_profile_mode,
 	.asic_reset = smu10_asic_reset,
+	.gfx_state_change = smu10_gfx_state_change,
 };
 
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 15ed6cb..2c9580b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -359,6 +359,7 @@ struct pp_hwmgr_func {
 	int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
 	int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
 					bool disable);
+	int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
 };
 
 struct pp_table_func {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index df4677d..4c7e08b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -83,7 +83,8 @@
 #define PPSMC_MSG_SetSoftMaxVcn                 0x34
 #define PPSMC_MSG_PowerGateMmHub                0x35
 #define PPSMC_MSG_SetRccPfcPmeRestoreRegister   0x36
-#define PPSMC_Message_Count                     0x37
+#define PPSMC_MSG_GpuChangeState                0x37
+#define PPSMC_Message_Count                     0x42
 
 typedef uint16_t PPSMC_Result;
 typedef int      PPSMC_Msg;
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/4] drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support

[Prike Liang]

- Need skip the RLC/CP/GFX disable for let GFXOFF enter during suspend period.
- For s0i3 suspend only need suspend DCE and each IP interrupt.
- Before VBIOS POSTed check and atom HW INT need set the GPU power status change
  to D0 in the resume period, otherwise the HW will be mess up and see the SDMA hang.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a027a8f..b16a7f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2432,8 +2432,10 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
 {
 	int i, r;
 
-	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
-	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+	if (!amdgpu_acpi_is_s0ix_supported()) {
+		amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
+		amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+	}
 
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 		if (!adev->ip_blocks[i].status.valid)
@@ -3459,12 +3461,15 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
 	amdgpu_fence_driver_suspend(adev);
 
-	r = amdgpu_device_ip_suspend_phase2(adev);
-
+	if (!amdgpu_acpi_is_s0ix_supported())
+		r = amdgpu_device_ip_suspend_phase2(adev);
+	else
+		amdgpu_gfx_state_change_set(adev, GpuChangeState_D3Entry);
 	/* evict remaining vram memory
 	 * This second call to evict vram is to evict the gart page table
 	 * using the CPU.
 	 */
+
 	amdgpu_bo_evict_vram(adev);
 
 	return 0;
@@ -3492,6 +3497,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
+	if (amdgpu_acpi_is_s0ix_supported())
+		amdgpu_gfx_state_change_set(adev, GpuChangeState_D0Entry);
+
 	/* post card */
 	if (amdgpu_device_need_post(adev)) {
 		r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/4] drm/amdgpu: fix reset support for s0i3 enablement

[Prike Liang]

update amdgpu device suspend sequence for gpu reset during s0i3 enable.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b16a7f7..ed44971 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2432,7 +2432,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
 {
 	int i, r;
 
-	if (!amdgpu_acpi_is_s0ix_supported()) {
+	if (!amdgpu_acpi_is_s0ix_supported() || adev->in_gpu_reset) {
 		amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
 		amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
 	}
@@ -3461,7 +3461,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
 	amdgpu_fence_driver_suspend(adev);
 
-	if (!amdgpu_acpi_is_s0ix_supported())
+	if (!amdgpu_acpi_is_s0ix_supported() || adev->in_gpu_reset)
 		r = amdgpu_device_ip_suspend_phase2(adev);
 	else
 		amdgpu_gfx_state_change_set(adev, GpuChangeState_D3Entry);
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry

[Alex Deucher]

On Fri, Oct 16, 2020 at 5:21 AM Prike Liang <Prike.Liang@amd.com> wrote:
>
> The new amdgpu_gfx_state_change_set() funtion can support set GFX power
> change status to D0/D3.
>
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> Acked-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

I presume we'll need something similar for renoir?  That can be a
follow up patch.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c           | 20 ++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h           |  7 +++++++
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 20 ++++++++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |  9 +++++++++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  1 +
>  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h      |  3 ++-
>  7 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index d612033..e1d6c8a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -789,3 +789,23 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
>  failed_kiq_write:
>         pr_err("failed to write reg:%x\n", reg);
>  }
> +
> +/* amdgpu_gfx_state_change_set - Handle gfx power state change set
> + * @adev: amdgpu_device pointer
> + * @state: gfx power state(1 -eGpuChangeState_D0Entry and 2 -eGpuChangeState_D3Entry)
> + *
> + */
> +
> +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
> +{
> +
> +       mutex_lock(&adev->pm.mutex);
> +
> +       if (adev->powerplay.pp_funcs &&
> +           adev->powerplay.pp_funcs->gfx_state_change_set)
> +                       ((adev)->powerplay.pp_funcs->gfx_state_change_set(
> +                                       (adev)->powerplay.pp_handle, state));
> +
> +       mutex_unlock(&adev->pm.mutex);
> +
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index d43c116..73942b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -47,6 +47,12 @@ enum gfx_pipe_priority {
>         AMDGPU_GFX_PIPE_PRIO_MAX
>  };
>
> +/* Argument for PPSMC_MSG_GpuChangeState */
> +enum gfx_change_state {
> +       GpuChangeState_D0Entry = 1,
> +       GpuChangeState_D3Entry,
> +};
> +
>  #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
>  #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
>
> @@ -387,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
>                                   struct amdgpu_iv_entry *entry);
>  uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
>  void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
> +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
>  #endif
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index a7f92d0..e7b69dd 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -284,6 +284,7 @@ struct amd_pm_funcs {
>         int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
>         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
>         int (*smu_i2c_bus_access)(void *handle, bool acquire);
> +       int (*gfx_state_change_set)(void *handle, uint32_t state);
>  /* export to DC */
>         u32 (*get_sclk)(void *handle, bool low);
>         u32 (*get_mclk)(void *handle, bool low);
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7e6dcdf..4f319be 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1321,6 +1321,25 @@ static int pp_set_powergating_by_smu(void *handle,
>         return ret;
>  }
>
> +static int pp_gfx_state_change_set(void *handle, uint32_t state)
> +{
> +       struct pp_hwmgr *hwmgr = handle;
> +
> +       if (!hwmgr || !hwmgr->pm_en)
> +               return -EINVAL;
> +
> +       if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
> +               pr_info_ratelimited("%s was not implemented.\n", __func__);
> +               return -EINVAL;
> +       }
> +
> +       mutex_lock(&hwmgr->smu_lock);
> +       hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
> +       mutex_unlock(&hwmgr->smu_lock);
> +
> +       return 0;
> +}
> +
>  static int pp_notify_smu_enable_pwe(void *handle)
>  {
>         struct pp_hwmgr *hwmgr = handle;
> @@ -1625,6 +1644,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
>         .switch_power_profile = pp_dpm_switch_power_profile,
>         .set_clockgating_by_smu = pp_set_clockgating_by_smu,
>         .set_powergating_by_smu = pp_set_powergating_by_smu,
> +       .gfx_state_change_set = pp_gfx_state_change_set,
>         .get_power_profile_mode = pp_get_power_profile_mode,
>         .set_power_profile_mode = pp_set_power_profile_mode,
>         .odn_edit_dpm_table = pp_odn_edit_dpm_table,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index c9cfe90..3f354da 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -319,6 +319,14 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
>         return false;
>  }
>
> +static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
> +{
> +       struct amdgpu_device *adev = hwmgr->adev;
> +       smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
> +
> +       return 0;
> +}
> +
>  static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
>  {
>         struct amdgpu_device *adev = hwmgr->adev;
> @@ -1394,6 +1402,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
>         .get_power_profile_mode = smu10_get_power_profile_mode,
>         .set_power_profile_mode = smu10_set_power_profile_mode,
>         .asic_reset = smu10_asic_reset,
> +       .gfx_state_change = smu10_gfx_state_change,
>  };
>
>  int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 15ed6cb..2c9580b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -359,6 +359,7 @@ struct pp_hwmgr_func {
>         int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
>         int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
>                                         bool disable);
> +       int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
>  };
>
>  struct pp_table_func {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> index df4677d..4c7e08b 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> @@ -83,7 +83,8 @@
>  #define PPSMC_MSG_SetSoftMaxVcn                 0x34
>  #define PPSMC_MSG_PowerGateMmHub                0x35
>  #define PPSMC_MSG_SetRccPfcPmeRestoreRegister   0x36
> -#define PPSMC_Message_Count                     0x37
> +#define PPSMC_MSG_GpuChangeState                0x37
> +#define PPSMC_Message_Count                     0x42
>
>  typedef uint16_t PPSMC_Result;
>  typedef int      PPSMC_Msg;
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry

[Liang, Prike]

[AMD Official Use Only - Internal Distribution Only]

> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Saturday, October 17, 2020 2:10 AM
> To: Liang, Prike <Prike.Liang@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Ray <Ray.Huang@amd.com>
> Subject: Re: [PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set()
> set gfx power change entry
>
> On Fri, Oct 16, 2020 at 5:21 AM Prike Liang <Prike.Liang@amd.com> wrote:
> >
> > The new amdgpu_gfx_state_change_set() funtion can support set GFX
> > power change status to D0/D3.
> >
> > Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> > Acked-by: Huang Rui <ray.huang@amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> I presume we'll need something similar for renoir?  That can be a follow up
> patch.
[Prike]  Yeah, so I have drafted the invoked function amdgpu_gfx_state_change_set() outside of the powerplay driver for common use. But until now haven't checked s0i3 on the Renoir/Cezanne yet and if needed will be implement it in the Renoir SMU driver.
>
> Alex
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c           | 20
> ++++++++++++++++++++
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h           |  7 +++++++
> >  drivers/gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
> >  drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 20
> ++++++++++++++++++++
> >  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c |  9 +++++++++
> >  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  1 +
> >  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h      |  3 ++-
> >  7 files changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index d612033..e1d6c8a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -789,3 +789,23 @@ void amdgpu_kiq_wreg(struct amdgpu_device
> *adev,
> > uint32_t reg, uint32_t v)
> >  failed_kiq_write:
> >         pr_err("failed to write reg:%x\n", reg);  }
> > +
> > +/* amdgpu_gfx_state_change_set - Handle gfx power state change set
> > + * @adev: amdgpu_device pointer
> > + * @state: gfx power state(1 -eGpuChangeState_D0Entry and 2
> > +-eGpuChangeState_D3Entry)
> > + *
> > + */
> > +
> > +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
> > +gfx_change_state state) {
> > +
> > +       mutex_lock(&adev->pm.mutex);
> > +
> > +       if (adev->powerplay.pp_funcs &&
> > +           adev->powerplay.pp_funcs->gfx_state_change_set)
> > +                       ((adev)->powerplay.pp_funcs->gfx_state_change_set(
> > +                                       (adev)->powerplay.pp_handle,
> > + state));
> > +
> > +       mutex_unlock(&adev->pm.mutex);
> > +
> > +}
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index d43c116..73942b2 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -47,6 +47,12 @@ enum gfx_pipe_priority {
> >         AMDGPU_GFX_PIPE_PRIO_MAX
> >  };
> >
> > +/* Argument for PPSMC_MSG_GpuChangeState */ enum
> gfx_change_state {
> > +       GpuChangeState_D0Entry = 1,
> > +       GpuChangeState_D3Entry,
> > +};
> > +
> >  #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0  #define
> > AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
> >
> > @@ -387,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct
> amdgpu_device *adev,
> >                                   struct amdgpu_iv_entry *entry);
> > uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> > void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg,
> > uint32_t v);
> > +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum
> > +gfx_change_state state);
> >  #endif
> > diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > index a7f92d0..e7b69dd 100644
> > --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> > @@ -284,6 +284,7 @@ struct amd_pm_funcs {
> >         int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input,
> uint32_t size);
> >         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
> >         int (*smu_i2c_bus_access)(void *handle, bool acquire);
> > +       int (*gfx_state_change_set)(void *handle, uint32_t state);
> >  /* export to DC */
> >         u32 (*get_sclk)(void *handle, bool low);
> >         u32 (*get_mclk)(void *handle, bool low); diff --git
> > a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > index 7e6dcdf..4f319be 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> > @@ -1321,6 +1321,25 @@ static int pp_set_powergating_by_smu(void
> *handle,
> >         return ret;
> >  }
> >
> > +static int pp_gfx_state_change_set(void *handle, uint32_t state) {
> > +       struct pp_hwmgr *hwmgr = handle;
> > +
> > +       if (!hwmgr || !hwmgr->pm_en)
> > +               return -EINVAL;
> > +
> > +       if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
> > +               pr_info_ratelimited("%s was not implemented.\n", __func__);
> > +               return -EINVAL;
> > +       }
> > +
> > +       mutex_lock(&hwmgr->smu_lock);
> > +       hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
> > +       mutex_unlock(&hwmgr->smu_lock);
> > +
> > +       return 0;
> > +}
> > +
> >  static int pp_notify_smu_enable_pwe(void *handle)  {
> >         struct pp_hwmgr *hwmgr = handle; @@ -1625,6 +1644,7 @@ static
> > const struct amd_pm_funcs pp_dpm_funcs = {
> >         .switch_power_profile = pp_dpm_switch_power_profile,
> >         .set_clockgating_by_smu = pp_set_clockgating_by_smu,
> >         .set_powergating_by_smu = pp_set_powergating_by_smu,
> > +       .gfx_state_change_set = pp_gfx_state_change_set,
> >         .get_power_profile_mode = pp_get_power_profile_mode,
> >         .set_power_profile_mode = pp_set_power_profile_mode,
> >         .odn_edit_dpm_table = pp_odn_edit_dpm_table, diff --git
> > a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > index c9cfe90..3f354da 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> > @@ -319,6 +319,14 @@ static bool smu10_is_gfx_on(struct pp_hwmgr
> *hwmgr)
> >         return false;
> >  }
> >
> > +static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t
> > +state) {
> > +       struct amdgpu_device *adev = hwmgr->adev;
> > +       smum_send_msg_to_smc_with_parameter(hwmgr,
> > +PPSMC_MSG_GpuChangeState, state, NULL);
> > +
> > +       return 0;
> > +}
> > +
> >  static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)  {
> >         struct amdgpu_device *adev = hwmgr->adev; @@ -1394,6 +1402,7
> > @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
> >         .get_power_profile_mode = smu10_get_power_profile_mode,
> >         .set_power_profile_mode = smu10_set_power_profile_mode,
> >         .asic_reset = smu10_asic_reset,
> > +       .gfx_state_change = smu10_gfx_state_change,
> >  };
> >
> >  int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) diff --git
> > a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > index 15ed6cb..2c9580b 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> > @@ -359,6 +359,7 @@ struct pp_hwmgr_func {
> >         int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
> >         int (*disable_power_features_for_compute_performance)(struct
> pp_hwmgr *hwmgr,
> >                                         bool disable);
> > +       int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t
> > + state);
> >  };
> >
> >  struct pp_table_func {
> > diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > index df4677d..4c7e08b 100644
> > --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > @@ -83,7 +83,8 @@
> >  #define PPSMC_MSG_SetSoftMaxVcn                 0x34
> >  #define PPSMC_MSG_PowerGateMmHub                0x35
> >  #define PPSMC_MSG_SetRccPfcPmeRestoreRegister   0x36
> > -#define PPSMC_Message_Count                     0x37
> > +#define PPSMC_MSG_GpuChangeState                0x37
> > +#define PPSMC_Message_Count                     0x42
> >
> >  typedef uint16_t PPSMC_Result;
> >  typedef int      PPSMC_Msg;
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&amp;data=04%7C01%7CPr
> >
> ike.Liang%40amd.com%7C8dc3fa74b20d4fae604708d871fec9f9%7C3dd8961f
> e4884
> >
> e608e11a82d994e183d%7C0%7C0%7C637384686409368549%7CUnknown%7
> CTWFpbGZsb
> >
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> %3D%
> >
> 7C1000&amp;sdata=sB%2FuFIiWFJ5nRsVYfRbfGZYszehIDAlhzZE5Okx4zTk%3
> D&amp;
> > reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/4] drm/amdgpu: add s0i3 capacity check for s0i3 routine

[Prike Liang]

add amdgpu_acpi_is_s0ix_supported() to check the platform
whether support s0i3.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 14 ++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 20400ec..83ac06a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1314,9 +1314,11 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
 
 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
 		struct amdgpu_dm_backlight_caps *caps);
+bool amdgpu_acpi_is_s0ix_supported(void);
 #else
 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
+static inline bool amdgpu_acpi_is_s0ix_supported(void) { return false; }
 #endif
 
 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index 165b02e..fd66ac0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -27,6 +27,7 @@
 #include <linux/power_supply.h>
 #include <linux/pm_runtime.h>
 #include <acpi/video.h>
+#include <acpi/actbl.h>
 
 #include <drm/drm_crtc_helper.h>
 #include "amdgpu.h"
@@ -894,3 +895,16 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev)
 	unregister_acpi_notifier(&adev->acpi_nb);
 	kfree(adev->atif);
 }
+
+/**
+ * amdgpu_acpi_is_s0ix_supported
+ *
+ * returns true if supported, false if not.
+ */
+bool amdgpu_acpi_is_s0ix_supported()
+{
+	if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)
+		return true;
+
+	return false;
+}
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx