[Intel-gfx] [PATCH 1/3] drm/i915: Guard debugfs against invalid access without display

[Intel-gfx] [PATCH 1/3] drm/i915: Guard debugfs against invalid access without display

[Lucas De Marchi]

Do not create the display debugfs files when we don't have display.

Based on previous patch by José Souza.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d3237b0d821d..d6e25212d5c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -671,7 +671,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
 	/* Reveal our presence to userspace */
 	if (drm_dev_register(dev, 0) == 0) {
 		i915_debugfs_register(dev_priv);
-		intel_display_debugfs_register(dev_priv);
+		if (HAS_DISPLAY(dev_priv))
+			intel_display_debugfs_register(dev_priv);
 		i915_setup_sysfs(dev_priv);
 
 		/* Depends on sysfs having been initialized */
-- 
2.29.0

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[Intel-gfx] [PATCH 2/3] drm/i915/display: remove debug message from error path

[Lucas De Marchi]

First check in the function is if swsci() is supported. All the error
paths are easy to figure out the reason, so remove the extra debug
message: it's normal not to support swsci() e.g. in dgfx.

v2: Rather than special case dgfx, just remove the debug message
    (from Ville)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index de995362f428..4f77cf849171 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1007,12 +1007,8 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
 	int ret;
 
 	ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Failed to get panel details from OpRegion (%d)\n",
-			    ret);
+	if (ret)
 		return ret;
-	}
 
 	ret = (panel_details >> 8) & 0xff;
 	if (ret > 0x10) {
-- 
2.29.0

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Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: remove debug message from error path

[Jani Nikula]

On Mon, 26 Oct 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> First check in the function is if swsci() is supported. All the error
> paths are easy to figure out the reason, so remove the extra debug
> message: it's normal not to support swsci() e.g. in dgfx.
>
> v2: Rather than special case dgfx, just remove the debug message
>     (from Ville)
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
> index de995362f428..4f77cf849171 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -1007,12 +1007,8 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
>  	int ret;
>  
>  	ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Failed to get panel details from OpRegion (%d)\n",
> -			    ret);
> +	if (ret)
>  		return ret;
> -	}
>  
>  	ret = (panel_details >> 8) & 0xff;
>  	if (ret > 0x10) {

-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Lucas De Marchi]

GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
Bridge").  Other than printing their values in debugfs we don't do
anything with them.  There's not much useful information in them. These
registers may change location in future platforms, but instead of adding
new locations, it's simpler to just remove them.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---------------
 drivers/gpu/drm/i915/i915_debugfs.c     | 17 ++---------------
 drivers/gpu/drm/i915/i915_reg.h         |  3 ---
 3 files changed, 4 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 174a24553322..8a68088c12ea 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void *unused)
 		seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(rps, rps->efficient_freq));
 	} else if (INTEL_GEN(i915) >= 6) {
-		u32 rp_state_limits;
-		u32 gt_perf_status;
 		u32 rp_state_cap;
 		u32 rpmodectl, rpinclimit, rpdeclimit;
 		u32 rpstat, cagf, reqf;
@@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void *unused)
 		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 		int max_freq;
 
-		rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
-		if (IS_GEN9_LP(i915)) {
+		if (IS_GEN9_LP(i915))
 			rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
-			gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
-		} else {
+		else
 			rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
-			gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
-		}
 
 		/* RPSTAT1 is in the GT power well */
 		intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@ -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void *unused)
 				   pm_isr, pm_iir);
 		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 			   rps->pm_intrmsk_mbz);
-		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
-		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
-		seq_printf(m, "Render p-state VID: %d\n",
-			   gt_perf_status & 0xff);
-		seq_printf(m, "Render p-state limit: %d\n",
-			   rp_state_limits & 0xff);
 		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
 		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ea469168cd44..c01f27eebf9c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(rps, rps->efficient_freq));
 	} else if (INTEL_GEN(dev_priv) >= 6) {
-		u32 rp_state_limits;
-		u32 gt_perf_status;
 		u32 rp_state_cap;
 		u32 rpmodectl, rpinclimit, rpdeclimit;
 		u32 rpstat, cagf, reqf;
@@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 		int max_freq;
 
-		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
-		if (IS_GEN9_LP(dev_priv)) {
+		if (IS_GEN9_LP(dev_priv))
 			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
-			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
-		} else {
+		else
 			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-			gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
-		}
 
 		/* RPSTAT1 is in the GT power well */
 		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
@@ -924,13 +918,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 				   pm_isr, pm_iir);
 		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 			   rps->pm_intrmsk_mbz);
-		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
-		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
-		seq_printf(m, "Render p-state VID: %d\n",
-			   gt_perf_status & 0xff);
-		seq_printf(m, "Render p-state limit: %d\n",
-			   rp_state_limits & 0xff);
 		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
 		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b021f77cb1f..6e7a0dc38bce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4044,9 +4044,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
 
-#define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
-#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
-#define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
 #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
-- 
2.29.0

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Lucas De Marchi
> Sent: Monday, October 26, 2020 9:46 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers
> from MCHBAR
> 
> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for
> Sandy Bridge").  Other than printing their values in debugfs we don't do
> anything with them.  There's not much useful information in them. These
> registers may change location in future platforms, but instead of adding
> new locations, it's simpler to just remove them.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---------------
>  drivers/gpu/drm/i915/i915_debugfs.c     | 17 ++---------------
>  drivers/gpu/drm/i915/i915_reg.h         |  3 ---
>  3 files changed, 4 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 174a24553322..8a68088c12ea 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>  		seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>  			   intel_gpu_freq(rps, rps->efficient_freq));
>  	} else if (INTEL_GEN(i915) >= 6) {
> -		u32 rp_state_limits;
> -		u32 gt_perf_status;
>  		u32 rp_state_cap;
>  		u32 rpmodectl, rpinclimit, rpdeclimit;
>  		u32 rpstat, cagf, reqf;
> @@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>  		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>  		int max_freq;
> 
> -		rp_state_limits = intel_uncore_read(uncore,
> GEN6_RP_STATE_LIMITS);
> -		if (IS_GEN9_LP(i915)) {
> +		if (IS_GEN9_LP(i915))
>  			rp_state_cap = intel_uncore_read(uncore,
> BXT_RP_STATE_CAP);
> -			gt_perf_status = intel_uncore_read(uncore,
> BXT_GT_PERF_STATUS);
> -		} else {
> +		else
>  			rp_state_cap = intel_uncore_read(uncore,
> GEN6_RP_STATE_CAP);
> -			gt_perf_status = intel_uncore_read(uncore,
> GEN6_GT_PERF_STATUS);
> -		}
> 
>  		/* RPSTAT1 is in the GT power well */
>  		intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); @@
> -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>  				   pm_isr, pm_iir);
>  		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>  			   rps->pm_intrmsk_mbz);
> -		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n",
> gt_perf_status);
> -		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 :
> 0xff00)) >> 8);
> -		seq_printf(m, "Render p-state VID: %d\n",
> -			   gt_perf_status & 0xff);
> -		seq_printf(m, "Render p-state limit: %d\n",
> -			   rp_state_limits & 0xff);
>  		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>  		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>  		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); diff --git
> a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ea469168cd44..c01f27eebf9c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m,
> void *unused)
>  			   "efficient (RPe) frequency: %d MHz\n",
>  			   intel_gpu_freq(rps, rps->efficient_freq));
>  	} else if (INTEL_GEN(dev_priv) >= 6) {
> -		u32 rp_state_limits;
> -		u32 gt_perf_status;
>  		u32 rp_state_cap;
>  		u32 rpmodectl, rpinclimit, rpdeclimit;
>  		u32 rpstat, cagf, reqf;
> @@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m,
> void *unused)
>  		u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>  		int max_freq;
> 
> -		rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> -		if (IS_GEN9_LP(dev_priv)) {
> +		if (IS_GEN9_LP(dev_priv))
>  			rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> -			gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> -		} else {
> +		else
>  			rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> -			gt_perf_status =
> I915_READ(GEN6_GT_PERF_STATUS);
> -		}
> 
>  		/* RPSTAT1 is in the GT power well */
>  		intel_uncore_forcewake_get(&dev_priv->uncore,
> FORCEWAKE_ALL); @@ -924,13 +918,6 @@ static int
> i915_frequency_info(struct seq_file *m, void *unused)
>  				   pm_isr, pm_iir);
>  		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>  			   rps->pm_intrmsk_mbz);
> -		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n",
> gt_perf_status);
> -		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ?
> 0x1ff00 : 0xff00)) >> 8);
> -		seq_printf(m, "Render p-state VID: %d\n",
> -			   gt_perf_status & 0xff);
> -		seq_printf(m, "Render p-state limit: %d\n",
> -			   rp_state_limits & 0xff);
>  		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>  		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>  		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); diff --git
> a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b021f77cb1f..6e7a0dc38bce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4044,9 +4044,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
> reg)  #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)  #define
> GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
> 
> -#define GEN6_GT_PERF_STATUS
> 	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> -#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x7070)
> -#define GEN6_RP_STATE_LIMITS
> 	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
>  #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB +
> 0x5998)
>  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
>  #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
> --
> 2.29.0
> 
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Joonas Lahtinen]

Quoting Lucas De Marchi (2020-10-27 06:46:18)
> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
> Bridge").  Other than printing their values in debugfs we don't do
> anything with them.  There's not much useful information in them. These
> registers may change location in future platforms, but instead of adding
> new locations, it's simpler to just remove them.

This code seems to have been updated for Gen9LP, so that would indicate
the debugging information is useful, right? The value is even decoded, not
simply dumped as most registers. So I would be hesitant to drop it for
not being useful.

The second question is why we have a huge block of 1-to-1 duplicated
code in there. Has there been an incorrect merge or some transition has
been left mid-way?

Regards, Joonas

> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---------------
>  drivers/gpu/drm/i915/i915_debugfs.c     | 17 ++---------------
>  drivers/gpu/drm/i915/i915_reg.h         |  3 ---
>  3 files changed, 4 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 174a24553322..8a68088c12ea 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void *unused)
>                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>                            intel_gpu_freq(rps, rps->efficient_freq));
>         } else if (INTEL_GEN(i915) >= 6) {
> -               u32 rp_state_limits;
> -               u32 gt_perf_status;
>                 u32 rp_state_cap;
>                 u32 rpmodectl, rpinclimit, rpdeclimit;
>                 u32 rpstat, cagf, reqf;
> @@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void *unused)
>                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>                 int max_freq;
>  
> -               rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
> -               if (IS_GEN9_LP(i915)) {
> +               if (IS_GEN9_LP(i915))
>                         rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
> -                       gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
> -               } else {
> +               else
>                         rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
> -                       gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
> -               }
>  
>                 /* RPSTAT1 is in the GT power well */
>                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> @@ -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void *unused)
>                                    pm_isr, pm_iir);
>                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>                            rps->pm_intrmsk_mbz);
> -               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> -               seq_printf(m, "Render p-state ratio: %d\n",
> -                          (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> -               seq_printf(m, "Render p-state VID: %d\n",
> -                          gt_perf_status & 0xff);
> -               seq_printf(m, "Render p-state limit: %d\n",
> -                          rp_state_limits & 0xff);
>                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ea469168cd44..c01f27eebf9c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>                            "efficient (RPe) frequency: %d MHz\n",
>                            intel_gpu_freq(rps, rps->efficient_freq));
>         } else if (INTEL_GEN(dev_priv) >= 6) {
> -               u32 rp_state_limits;
> -               u32 gt_perf_status;
>                 u32 rp_state_cap;
>                 u32 rpmodectl, rpinclimit, rpdeclimit;
>                 u32 rpstat, cagf, reqf;
> @@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>                 int max_freq;
>  
> -               rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> -               if (IS_GEN9_LP(dev_priv)) {
> +               if (IS_GEN9_LP(dev_priv))
>                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> -                       gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> -               } else {
> +               else
>                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> -                       gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
> -               }
>  
>                 /* RPSTAT1 is in the GT power well */
>                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> @@ -924,13 +918,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>                                    pm_isr, pm_iir);
>                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>                            rps->pm_intrmsk_mbz);
> -               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> -               seq_printf(m, "Render p-state ratio: %d\n",
> -                          (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> -               seq_printf(m, "Render p-state VID: %d\n",
> -                          gt_perf_status & 0xff);
> -               seq_printf(m, "Render p-state limit: %d\n",
> -                          rp_state_limits & 0xff);
>                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8b021f77cb1f..6e7a0dc38bce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4044,9 +4044,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
>  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>  
> -#define GEN6_GT_PERF_STATUS    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> -#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
> -#define GEN6_RP_STATE_LIMITS   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
>  #define GEN6_RP_STATE_CAP      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
>  #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
> -- 
> 2.29.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Lucas De Marchi]

On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
>Quoting Lucas De Marchi (2020-10-27 06:46:18)
>> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
>> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
>> Bridge").  Other than printing their values in debugfs we don't do
>> anything with them.  There's not much useful information in them. These
>> registers may change location in future platforms, but instead of adding
>> new locations, it's simpler to just remove them.
>
>This code seems to have been updated for Gen9LP, so that would indicate
>the debugging information is useful, right? The value is even decoded, not
>simply dumped as most registers. So I would be hesitant to drop it for
>not being useful.

but just updating the register in itself for a new gen doesn't mean it's
actually useful... the commit message where this happened is pretty
vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")

My first reaction would be to do the same if the register had moved or
if it ceased to exist in a new platform. Talking with Matt Roper some
time ago we arrived to the conclusion that just printing these values is
not giving us much benefit and it could very well be accomplished by
intel_reg.

So answering the question:  is it really useful as is? IMO, no.

>
>The second question is why we have a huge block of 1-to-1 duplicated
>code in there. Has there been an incorrect merge or some transition has
>been left mid-way?

not a bad merge, no. It seems to be to preserve the previous file
location since now it moved to be inside a gt dir. Long term I think
this is bad both because of the code duplication and because it's easy
to update one and forget the other.

Lucas De Marchi

>
>Regards, Joonas
>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---------------
>>  drivers/gpu/drm/i915/i915_debugfs.c     | 17 ++---------------
>>  drivers/gpu/drm/i915/i915_reg.h         |  3 ---
>>  3 files changed, 4 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> index 174a24553322..8a68088c12ea 100644
>> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> @@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void *unused)
>>                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>>                            intel_gpu_freq(rps, rps->efficient_freq));
>>         } else if (INTEL_GEN(i915) >= 6) {
>> -               u32 rp_state_limits;
>> -               u32 gt_perf_status;
>>                 u32 rp_state_cap;
>>                 u32 rpmodectl, rpinclimit, rpdeclimit;
>>                 u32 rpstat, cagf, reqf;
>> @@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void *unused)
>>                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>>                 int max_freq;
>>
>> -               rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
>> -               if (IS_GEN9_LP(i915)) {
>> +               if (IS_GEN9_LP(i915))
>>                         rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
>> -                       gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
>> -               } else {
>> +               else
>>                         rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
>> -                       gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
>> -               }
>>
>>                 /* RPSTAT1 is in the GT power well */
>>                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> @@ -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void *unused)
>>                                    pm_isr, pm_iir);
>>                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>>                            rps->pm_intrmsk_mbz);
>> -               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>> -               seq_printf(m, "Render p-state ratio: %d\n",
>> -                          (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> -               seq_printf(m, "Render p-state VID: %d\n",
>> -                          gt_perf_status & 0xff);
>> -               seq_printf(m, "Render p-state limit: %d\n",
>> -                          rp_state_limits & 0xff);
>>                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>>                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>>                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index ea469168cd44..c01f27eebf9c 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>                            "efficient (RPe) frequency: %d MHz\n",
>>                            intel_gpu_freq(rps, rps->efficient_freq));
>>         } else if (INTEL_GEN(dev_priv) >= 6) {
>> -               u32 rp_state_limits;
>> -               u32 gt_perf_status;
>>                 u32 rp_state_cap;
>>                 u32 rpmodectl, rpinclimit, rpdeclimit;
>>                 u32 rpstat, cagf, reqf;
>> @@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>>                 int max_freq;
>>
>> -               rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
>> -               if (IS_GEN9_LP(dev_priv)) {
>> +               if (IS_GEN9_LP(dev_priv))
>>                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
>> -                       gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
>> -               } else {
>> +               else
>>                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
>> -                       gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>> -               }
>>
>>                 /* RPSTAT1 is in the GT power well */
>>                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>> @@ -924,13 +918,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>                                    pm_isr, pm_iir);
>>                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>>                            rps->pm_intrmsk_mbz);
>> -               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>> -               seq_printf(m, "Render p-state ratio: %d\n",
>> -                          (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> -               seq_printf(m, "Render p-state VID: %d\n",
>> -                          gt_perf_status & 0xff);
>> -               seq_printf(m, "Render p-state limit: %d\n",
>> -                          rp_state_limits & 0xff);
>>                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>>                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>>                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8b021f77cb1f..6e7a0dc38bce 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4044,9 +4044,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>  #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
>>  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>>
>> -#define GEN6_GT_PERF_STATUS    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
>> -#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
>> -#define GEN6_RP_STATE_LIMITS   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
>>  #define GEN6_RP_STATE_CAP      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>>  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
>>  #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
>> --
>> 2.29.0
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Joonas Lahtinen]

Quoting Lucas De Marchi (2020-11-05 03:04:22)
> On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
> >Quoting Lucas De Marchi (2020-10-27 06:46:18)
> >> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> >> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
> >> Bridge").  Other than printing their values in debugfs we don't do
> >> anything with them.  There's not much useful information in them. These
> >> registers may change location in future platforms, but instead of adding
> >> new locations, it's simpler to just remove them.
> >
> >This code seems to have been updated for Gen9LP, so that would indicate
> >the debugging information is useful, right? The value is even decoded, not
> >simply dumped as most registers. So I would be hesitant to drop it for
> >not being useful.
> 
> but just updating the register in itself for a new gen doesn't mean it's
> actually useful... the commit message where this happened is pretty
> vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
> 
> My first reaction would be to do the same if the register had moved or
> if it ceased to exist in a new platform. Talking with Matt Roper some
> time ago we arrived to the conclusion that just printing these values is
> not giving us much benefit and it could very well be accomplished by
> intel_reg.
> 
> So answering the question:  is it really useful as is? IMO, no.

A quick discussion on #intel-gfx seems to indicate it was used for
bug triaging in the past year. So that would indicate it is still
useful to include.

So let's not remove it.

> >The second question is why we have a huge block of 1-to-1 duplicated
> >code in there. Has there been an incorrect merge or some transition has
> >been left mid-way?
> 
> not a bad merge, no. It seems to be to preserve the previous file
> location since now it moved to be inside a gt dir. Long term I think
> this is bad both because of the code duplication and because it's easy
> to update one and forget the other.

I started a discussion in the thread of the original patch which called
to move code but left the old code in place too, effectively copying it.

When this path was written and such code duplication noticed, would have
been good to highlight or address the code duplication.

Regards, Joonas

> Lucas De Marchi
> 
> >
> >Regards, Joonas
> >
> >> Cc: Matt Roper <matthew.d.roper@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---------------
> >>  drivers/gpu/drm/i915/i915_debugfs.c     | 17 ++---------------
> >>  drivers/gpu/drm/i915/i915_reg.h         |  3 ---
> >>  3 files changed, 4 insertions(+), 33 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> >> index 174a24553322..8a68088c12ea 100644
> >> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> >> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> >> @@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void *unused)
> >>                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
> >>                            intel_gpu_freq(rps, rps->efficient_freq));
> >>         } else if (INTEL_GEN(i915) >= 6) {
> >> -               u32 rp_state_limits;
> >> -               u32 gt_perf_status;
> >>                 u32 rp_state_cap;
> >>                 u32 rpmodectl, rpinclimit, rpdeclimit;
> >>                 u32 rpstat, cagf, reqf;
> >> @@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void *unused)
> >>                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> >>                 int max_freq;
> >>
> >> -               rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
> >> -               if (IS_GEN9_LP(i915)) {
> >> +               if (IS_GEN9_LP(i915))
> >>                         rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
> >> -                       gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
> >> -               } else {
> >> +               else
> >>                         rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
> >> -                       gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
> >> -               }
> >>
> >>                 /* RPSTAT1 is in the GT power well */
> >>                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> >> @@ -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void *unused)
> >>                                    pm_isr, pm_iir);
> >>                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
> >>                            rps->pm_intrmsk_mbz);
> >> -               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> >> -               seq_printf(m, "Render p-state ratio: %d\n",
> >> -                          (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> >> -               seq_printf(m, "Render p-state VID: %d\n",
> >> -                          gt_perf_status & 0xff);
> >> -               seq_printf(m, "Render p-state limit: %d\n",
> >> -                          rp_state_limits & 0xff);
> >>                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
> >>                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
> >>                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >> index ea469168cd44..c01f27eebf9c 100644
> >> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >> @@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >>                            "efficient (RPe) frequency: %d MHz\n",
> >>                            intel_gpu_freq(rps, rps->efficient_freq));
> >>         } else if (INTEL_GEN(dev_priv) >= 6) {
> >> -               u32 rp_state_limits;
> >> -               u32 gt_perf_status;
> >>                 u32 rp_state_cap;
> >>                 u32 rpmodectl, rpinclimit, rpdeclimit;
> >>                 u32 rpstat, cagf, reqf;
> >> @@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >>                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
> >>                 int max_freq;
> >>
> >> -               rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> >> -               if (IS_GEN9_LP(dev_priv)) {
> >> +               if (IS_GEN9_LP(dev_priv))
> >>                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> >> -                       gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> >> -               } else {
> >> +               else
> >>                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> >> -                       gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
> >> -               }
> >>
> >>                 /* RPSTAT1 is in the GT power well */
> >>                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> >> @@ -924,13 +918,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >>                                    pm_isr, pm_iir);
> >>                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
> >>                            rps->pm_intrmsk_mbz);
> >> -               seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> >> -               seq_printf(m, "Render p-state ratio: %d\n",
> >> -                          (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> >> -               seq_printf(m, "Render p-state VID: %d\n",
> >> -                          gt_perf_status & 0xff);
> >> -               seq_printf(m, "Render p-state limit: %d\n",
> >> -                          rp_state_limits & 0xff);
> >>                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
> >>                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
> >>                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 8b021f77cb1f..6e7a0dc38bce 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -4044,9 +4044,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >>  #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
> >>  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
> >>
> >> -#define GEN6_GT_PERF_STATUS    _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> >> -#define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
> >> -#define GEN6_RP_STATE_LIMITS   _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
> >>  #define GEN6_RP_STATE_CAP      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
> >>  #define BXT_RP_STATE_CAP        _MMIO(0x138170)
> >>  #define GEN9_RP_STATE_LIMITS   _MMIO(0x138148)
> >> --
> >> 2.29.0
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Lucas De Marchi]

On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote:
>Quoting Lucas De Marchi (2020-11-05 03:04:22)
>> On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
>> >Quoting Lucas De Marchi (2020-10-27 06:46:18)
>> >> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
>> >> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
>> >> Bridge").  Other than printing their values in debugfs we don't do
>> >> anything with them.  There's not much useful information in them. These
>> >> registers may change location in future platforms, but instead of adding
>> >> new locations, it's simpler to just remove them.
>> >
>> >This code seems to have been updated for Gen9LP, so that would indicate
>> >the debugging information is useful, right? The value is even decoded, not
>> >simply dumped as most registers. So I would be hesitant to drop it for
>> >not being useful.
>>
>> but just updating the register in itself for a new gen doesn't mean it's
>> actually useful... the commit message where this happened is pretty
>> vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
>>
>> My first reaction would be to do the same if the register had moved or
>> if it ceased to exist in a new platform. Talking with Matt Roper some
>> time ago we arrived to the conclusion that just printing these values is
>> not giving us much benefit and it could very well be accomplished by
>> intel_reg.
>>
>> So answering the question:  is it really useful as is? IMO, no.
>
>A quick discussion on #intel-gfx seems to indicate it was used for
>bug triaging in the past year. So that would indicate it is still
>useful to include.

getting back to this as we are trying to upstream XeHP-SDV that doesn't
have access to the MCHBAR. So do you think we should just make it
conditional instead of removing?

I'm still on the side that this additional code doesn't bring much value
and could be replaced by intel-reg.

>
>So let's not remove it.
>
>> >The second question is why we have a huge block of 1-to-1 duplicated
>> >code in there. Has there been an incorrect merge or some transition has
>> >been left mid-way?
>>
>> not a bad merge, no. It seems to be to preserve the previous file
>> location since now it moved to be inside a gt dir. Long term I think
>> this is bad both because of the code duplication and because it's easy
>> to update one and forget the other.
>
>I started a discussion in the thread of the original patch which called
>to move code but left the old code in place too, effectively copying it.
>
>When this path was written and such code duplication noticed, would have
>been good to highlight or address the code duplication.

yes, but it doesn't mean there will be an action regarding that, as can
be noticed since that duplication is still there today and this patch
applies cleanly :-/... and they had slightly different changes according
to

	git log -L:frequency_show:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c \
		-L:i915_frequency_info:drivers/gpu/drm/i915/i915_debugfs.c


Lucas De Marchi
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Lucas De Marchi]

On Tue, Jul 06, 2021 at 04:44:30PM -0700, Lucas De Marchi wrote:
>On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote:
>>Quoting Lucas De Marchi (2020-11-05 03:04:22)
>>>On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
>>>>Quoting Lucas De Marchi (2020-10-27 06:46:18)
>>>>> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
>>>>> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
>>>>> Bridge").  Other than printing their values in debugfs we don't do
>>>>> anything with them.  There's not much useful information in them. These
>>>>> registers may change location in future platforms, but instead of adding
>>>>> new locations, it's simpler to just remove them.
>>>>
>>>>This code seems to have been updated for Gen9LP, so that would indicate
>>>>the debugging information is useful, right? The value is even decoded, not
>>>>simply dumped as most registers. So I would be hesitant to drop it for
>>>>not being useful.
>>>
>>>but just updating the register in itself for a new gen doesn't mean it's
>>>actually useful... the commit message where this happened is pretty
>>>vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
>>>
>>>My first reaction would be to do the same if the register had moved or
>>>if it ceased to exist in a new platform. Talking with Matt Roper some
>>>time ago we arrived to the conclusion that just printing these values is
>>>not giving us much benefit and it could very well be accomplished by
>>>intel_reg.
>>>
>>>So answering the question:  is it really useful as is? IMO, no.
>>
>>A quick discussion on #intel-gfx seems to indicate it was used for
>>bug triaging in the past year. So that would indicate it is still
>>useful to include.
>
>getting back to this as we are trying to upstream XeHP-SDV that doesn't
>have access to the MCHBAR. So do you think we should just make it
>conditional instead of removing?
>
>I'm still on the side that this additional code doesn't bring much value
>and could be replaced by intel-reg.

ping?

>
>>
>>So let's not remove it.
>>
>>>>The second question is why we have a huge block of 1-to-1 duplicated
>>>>code in there. Has there been an incorrect merge or some transition has
>>>>been left mid-way?
>>>
>>>not a bad merge, no. It seems to be to preserve the previous file
>>>location since now it moved to be inside a gt dir. Long term I think
>>>this is bad both because of the code duplication and because it's easy
>>>to update one and forget the other.
>>
>>I started a discussion in the thread of the original patch which called
>>to move code but left the old code in place too, effectively copying it.
>>
>>When this path was written and such code duplication noticed, would have
>>been good to highlight or address the code duplication.
>
>yes, but it doesn't mean there will be an action regarding that, as can
>be noticed since that duplication is still there today and this patch
>applies cleanly :-/... and they had slightly different changes according
>to
>
>	git log -L:frequency_show:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c \
>		-L:i915_frequency_info:drivers/gpu/drm/i915/i915_debugfs.c

Just took a look for a potential deduplication fix there:
https://patchwork.freedesktop.org/series/94455/

Lucas De Marchi

Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Lucas De Marchi]

On Tue, Sep 07, 2021 at 02:56:21PM -0700, Lucas De Marchi wrote:
>On Tue, Jul 06, 2021 at 04:44:30PM -0700, Lucas De Marchi wrote:
>>On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote:
>>>Quoting Lucas De Marchi (2020-11-05 03:04:22)
>>>>On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
>>>>>Quoting Lucas De Marchi (2020-10-27 06:46:18)
>>>>>>GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
>>>>>>commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
>>>>>>Bridge").  Other than printing their values in debugfs we don't do
>>>>>>anything with them.  There's not much useful information in them. These
>>>>>>registers may change location in future platforms, but instead of adding
>>>>>>new locations, it's simpler to just remove them.
>>>>>
>>>>>This code seems to have been updated for Gen9LP, so that would indicate
>>>>>the debugging information is useful, right? The value is even decoded, not
>>>>>simply dumped as most registers. So I would be hesitant to drop it for
>>>>>not being useful.
>>>>
>>>>but just updating the register in itself for a new gen doesn't mean it's
>>>>actually useful... the commit message where this happened is pretty
>>>>vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
>>>>
>>>>My first reaction would be to do the same if the register had moved or
>>>>if it ceased to exist in a new platform. Talking with Matt Roper some
>>>>time ago we arrived to the conclusion that just printing these values is
>>>>not giving us much benefit and it could very well be accomplished by
>>>>intel_reg.
>>>>
>>>>So answering the question:  is it really useful as is? IMO, no.
>>>
>>>A quick discussion on #intel-gfx seems to indicate it was used for
>>>bug triaging in the past year. So that would indicate it is still
>>>useful to include.
>>
>>getting back to this as we are trying to upstream XeHP-SDV that doesn't
>>have access to the MCHBAR. So do you think we should just make it
>>conditional instead of removing?
>>
>>I'm still on the side that this additional code doesn't bring much value
>>and could be replaced by intel-reg.
>
>ping?
>
>>
>>>
>>>So let's not remove it.
>>>
>>>>>The second question is why we have a huge block of 1-to-1 duplicated
>>>>>code in there. Has there been an incorrect merge or some transition has
>>>>>been left mid-way?

the deduplication has now being merged together with fixing of the file
names: https://patchwork.freedesktop.org/series/94827/

Back to the previous question...  Does the silence here mean
there is no interest to block this anymore?

As noted by me and Matt Roper there is very little value in keeping
this. Even if it was used once in a year for bug triaging, it could very
well had used intel_reg - this is just adding to the maintenance
burden for new platforms. Who used it so I can talk to the person to
understand the gap?  Adding some more people in Cc who could possibly
know.

thanks
Lucas De Marchi

>>>>
>>>>not a bad merge, no. It seems to be to preserve the previous file
>>>>location since now it moved to be inside a gt dir. Long term I think
>>>>this is bad both because of the code duplication and because it's easy
>>>>to update one and forget the other.
>>>
>>>I started a discussion in the thread of the original patch which called
>>>to move code but left the old code in place too, effectively copying it.
>>>
>>>When this path was written and such code duplication noticed, would have
>>>been good to highlight or address the code duplication.
>>
>>yes, but it doesn't mean there will be an action regarding that, as can
>>be noticed since that duplication is still there today and this patch
>>applies cleanly :-/... and they had slightly different changes according
>>to
>>
>>	git log -L:frequency_show:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c \
>>		-L:i915_frequency_info:drivers/gpu/drm/i915/i915_debugfs.c
>
>Just took a look for a potential deduplication fix there:
>https://patchwork.freedesktop.org/series/94455/
>
>Lucas De Marchi

Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Rodrigo Vivi]

On Tue, Jul 06, 2021 at 04:44:30PM -0700, Lucas De Marchi wrote:
> On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote:
> > Quoting Lucas De Marchi (2020-11-05 03:04:22)
> > > On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
> > > >Quoting Lucas De Marchi (2020-10-27 06:46:18)
> > > >> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> > > >> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
> > > >> Bridge").  Other than printing their values in debugfs we don't do
> > > >> anything with them.  There's not much useful information in them. These
> > > >> registers may change location in future platforms, but instead of adding
> > > >> new locations, it's simpler to just remove them.
> > > >
> > > >This code seems to have been updated for Gen9LP, so that would indicate
> > > >the debugging information is useful, right? The value is even decoded, not
> > > >simply dumped as most registers. So I would be hesitant to drop it for
> > > >not being useful.
> > > 
> > > but just updating the register in itself for a new gen doesn't mean it's
> > > actually useful... the commit message where this happened is pretty
> > > vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
> > > 
> > > My first reaction would be to do the same if the register had moved or
> > > if it ceased to exist in a new platform. Talking with Matt Roper some
> > > time ago we arrived to the conclusion that just printing these values is
> > > not giving us much benefit and it could very well be accomplished by
> > > intel_reg.
> > > 
> > > So answering the question:  is it really useful as is? IMO, no.
> > 
> > A quick discussion on #intel-gfx seems to indicate it was used for
> > bug triaging in the past year. So that would indicate it is still
> > useful to include.
> 
> getting back to this as we are trying to upstream XeHP-SDV that doesn't
> have access to the MCHBAR. So do you think we should just make it
> conditional instead of removing?

Yes, please let's make this conditional.

> 
> I'm still on the side that this additional code doesn't bring much value
> and could be replaced by intel-reg.

In general I'd agree. However:

1. Sometimes it is very hard to find out what registers and bits have
some useful information.
2. If it is hard to remove sometimes it is harder to add some information
like this.
3. I was not part of the IRC chat that Joonas mentioned, but apparently
this data was useful in the past for some cases.

Thanks,
Rodrigo.

> 
> > 
> > So let's not remove it.
> > 
> > > >The second question is why we have a huge block of 1-to-1 duplicated
> > > >code in there. Has there been an incorrect merge or some transition has
> > > >been left mid-way?
> > > 
> > > not a bad merge, no. It seems to be to preserve the previous file
> > > location since now it moved to be inside a gt dir. Long term I think
> > > this is bad both because of the code duplication and because it's easy
> > > to update one and forget the other.
> > 
> > I started a discussion in the thread of the original patch which called
> > to move code but left the old code in place too, effectively copying it.
> > 
> > When this path was written and such code duplication noticed, would have
> > been good to highlight or address the code duplication.
> 
> yes, but it doesn't mean there will be an action regarding that, as can
> be noticed since that duplication is still there today and this patch
> applies cleanly :-/... and they had slightly different changes according
> to
> 
> 	git log -L:frequency_show:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c \
> 		-L:i915_frequency_info:drivers/gpu/drm/i915/i915_debugfs.c
> 
> 
> Lucas De Marchi
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Lucas De Marchi]

On Fri, Sep 24, 2021 at 04:16:24PM -0400, Rodrigo Vivi wrote:
>On Tue, Jul 06, 2021 at 04:44:30PM -0700, Lucas De Marchi wrote:
>> On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote:
>> > Quoting Lucas De Marchi (2020-11-05 03:04:22)
>> > > On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
>> > > >Quoting Lucas De Marchi (2020-10-27 06:46:18)
>> > > >> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
>> > > >> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for Sandy
>> > > >> Bridge").  Other than printing their values in debugfs we don't do
>> > > >> anything with them.  There's not much useful information in them. These
>> > > >> registers may change location in future platforms, but instead of adding
>> > > >> new locations, it's simpler to just remove them.
>> > > >
>> > > >This code seems to have been updated for Gen9LP, so that would indicate
>> > > >the debugging information is useful, right? The value is even decoded, not
>> > > >simply dumped as most registers. So I would be hesitant to drop it for
>> > > >not being useful.
>> > >
>> > > but just updating the register in itself for a new gen doesn't mean it's
>> > > actually useful... the commit message where this happened is pretty
>> > > vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
>> > >
>> > > My first reaction would be to do the same if the register had moved or
>> > > if it ceased to exist in a new platform. Talking with Matt Roper some
>> > > time ago we arrived to the conclusion that just printing these values is
>> > > not giving us much benefit and it could very well be accomplished by
>> > > intel_reg.
>> > >
>> > > So answering the question:  is it really useful as is? IMO, no.
>> >
>> > A quick discussion on #intel-gfx seems to indicate it was used for
>> > bug triaging in the past year. So that would indicate it is still
>> > useful to include.
>>
>> getting back to this as we are trying to upstream XeHP-SDV that doesn't
>> have access to the MCHBAR. So do you think we should just make it
>> conditional instead of removing?
>
>Yes, please let's make this conditional.
>
>>
>> I'm still on the side that this additional code doesn't bring much value
>> and could be replaced by intel-reg.
>
>In general I'd agree. However:
>
>1. Sometimes it is very hard to find out what registers and bits have
>some useful information.
>2. If it is hard to remove sometimes it is harder to add some information
>like this.
>3. I was not part of the IRC chat that Joonas mentioned, but apparently
>this data was useful in the past for some cases.

I will disagree and commit since 2 maintainers are against the
removal. I will send a new updated patch. Just to make my point clear:

1) This doesn't expose anything more than what is available with
intel_reg

2) we are already printing the wrong value for "recent" platforms:
one of the register wasn't updated for anything after gen9. The other
register doesn't actually seem to exist anymore after gen9.

3) It adds to the maintenance, particularly because this is an mchbar
register which is not available in bspec

4) It's still not clear how exactly this was useful

Lucas De Marchi

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Guard debugfs against invalid access without display

[Jani Nikula]

On Mon, 26 Oct 2020, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Do not create the display debugfs files when we don't have display.
>
> Based on previous patch by José Souza.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d3237b0d821d..d6e25212d5c0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -671,7 +671,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
>  	/* Reveal our presence to userspace */
>  	if (drm_dev_register(dev, 0) == 0) {
>  		i915_debugfs_register(dev_priv);
> -		intel_display_debugfs_register(dev_priv);
> +		if (HAS_DISPLAY(dev_priv))
> +			intel_display_debugfs_register(dev_priv);
>  		i915_setup_sysfs(dev_priv);
>  
>  		/* Depends on sysfs having been initialized */

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Guard debugfs against invalid access without display

[Souza, Jose]

On Mon, 2020-10-26 at 21:46 -0700, Lucas De Marchi wrote:
> Do not create the display debugfs files when we don't have display.
> 
> Based on previous patch by José Souza.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d3237b0d821d..d6e25212d5c0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -671,7 +671,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
>  	/* Reveal our presence to userspace */
>  	if (drm_dev_register(dev, 0) == 0) {
>  		i915_debugfs_register(dev_priv);
> -		intel_display_debugfs_register(dev_priv);
> +		if (HAS_DISPLAY(dev_priv))
> +			intel_display_debugfs_register(dev_priv);
>  		i915_setup_sysfs(dev_priv);
>  
> 
> 
> 
>  		/* Depends on sysfs having been initialized */

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Guard debugfs against invalid access without display

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 8259 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915: Guard debugfs against invalid access without display
URL   : https://patchwork.freedesktop.org/series/83070/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18782
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_18782 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18782, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18782:

### IGT changes ###

#### Warnings ####

  * igt@i915_module_load@reload:
    - fi-skl-lmem:        [DMESG-WARN][1] ([i915#2605]) -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-lmem/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-skl-lmem/igt@i915_module_load@reload.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9206 and Patchwork_18782:

### New CI tests (1) ###

  * boot:
    - Statuses : 41 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18782 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-apl-guc:         [PASS][3] -> [INCOMPLETE][4] ([i915#1635])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-apl-guc/igt@gem_ctx_create@basic-files.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-apl-guc/igt@gem_ctx_create@basic-files.html

  * igt@gem_mmap_gtt@basic:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@gem_mmap_gtt@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-tgl-y/igt@gem_mmap_gtt@basic.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-soraka:      [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@kms_busy@basic@flip.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-kbl-soraka/igt@kms_busy@basic@flip.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][9] -> [INCOMPLETE][10] ([i915#2606])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-tgl-y:           [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html

  * igt@kms_psr@primary_page_flip:
    - fi-cml-u2:          [PASS][13] -> [INCOMPLETE][14] ([i915#2606])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cml-u2/igt@kms_psr@primary_page_flip.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-cml-u2/igt@kms_psr@primary_page_flip.html

  * igt@vgem_basic@unload:
    - fi-skl-guc:         [PASS][15] -> [DMESG-WARN][16] ([i915#2203])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-guc/igt@vgem_basic@unload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-skl-guc/igt@vgem_basic@unload.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - {fi-kbl-7560u}:     [INCOMPLETE][17] ([i915#2417]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-byt-j1900:       [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@gem_exec_suspend@basic-s3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-byt-j1900/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_module_load@reload:
    - fi-kbl-soraka:      [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@i915_module_load@reload.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-kbl-soraka/igt@i915_module_load@reload.html
    - {fi-ehl-1}:         [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-ehl-1/igt@i915_module_load@reload.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-ehl-1/igt@i915_module_load@reload.html

  * igt@kms_busy@basic@flip:
    - {fi-tgl-dsi}:       [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-dsi/igt@kms_busy@basic@flip.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-tgl-dsi/igt@kms_busy@basic@flip.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [INCOMPLETE][27] ([i915#2606]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-tgl-y:           [DMESG-WARN][29] ([i915#1982]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html

  * igt@prime_vgem@basic-read:
    - fi-tgl-y:           [DMESG-WARN][31] ([i915#402]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@prime_vgem@basic-read.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/fi-tgl-y/igt@prime_vgem@basic-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 41)
------------------------------

  Missing    (2): fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9206 -> Patchwork_18782

  CI-20190529: 20190529
  CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18782: 3b45adb5c1be9eb28c4cbbcb34ec0676fcd62acc @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3b45adb5c1be drm/i915: remove some debug-only registers from MCHBAR
1477d756a2c8 drm/i915/display: remove debug message from error path
2007e0237e80 drm/i915: Guard debugfs against invalid access without display

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Guard debugfs against invalid access without display

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 23072 bytes --]

== Series Details ==

Series: series starting with [1/3] drm/i915: Guard debugfs against invalid access without display
URL   : https://patchwork.freedesktop.org/series/83070/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18782_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18782_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18782_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18782_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
    - shard-skl:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile}:
    - shard-skl:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9206_full and Patchwork_18782_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 175 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18782_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_read@empty-block:
    - shard-glk:          [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk2/igt@drm_read@empty-block.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk4/igt@drm_read@empty-block.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [PASS][6] -> [INCOMPLETE][7] ([i915#1635])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl2/igt@gem_softpin@noreloc-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl6/igt@gem_softpin@noreloc-s3.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
    - shard-apl:          [PASS][8] -> [DMESG-WARN][9] ([i915#1635] / [i915#1982]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl4/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#79])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
    - shard-tglb:         [PASS][12] -> [INCOMPLETE][13] ([i915#2606]) +2 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-tglb:         [PASS][14] -> [DMESG-WARN][15] ([i915#2606])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
    - shard-iclb:         [PASS][16] -> [INCOMPLETE][17] ([i915#2606])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
    - shard-skl:          [PASS][18] -> [INCOMPLETE][19] ([i915#123]) +2 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-skl:          [PASS][20] -> [INCOMPLETE][21] ([i915#123] / [i915#2606])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][22] -> [DMESG-WARN][23] ([i915#1982])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
    - shard-skl:          [PASS][24] -> [DMESG-WARN][25] ([i915#1982]) +2 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][26] -> [DMESG-FAIL][27] ([fdo#108145] / [i915#1982])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][28] -> [FAIL][29] ([i915#1635] / [i915#31])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl2/igt@kms_setmode@basic.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][30] -> [FAIL][31] ([i915#1542])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@perf@blocking.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl6/igt@perf@blocking.html

  
#### Possible fixes ####

  * igt@gem_exec_create@basic:
    - shard-snb:          [INCOMPLETE][32] ([i915#82]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-snb2/igt@gem_exec_create@basic.html

  * igt@gem_exec_gttfill@all:
    - shard-glk:          [DMESG-WARN][34] ([i915#118] / [i915#95]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk1/igt@gem_exec_gttfill@all.html

  * igt@gem_exec_whisper@basic-contexts-priority:
    - shard-iclb:         [INCOMPLETE][36] -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb3/igt@gem_exec_whisper@basic-contexts-priority.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb5/igt@gem_exec_whisper@basic-contexts-priority.html

  * {igt@kms_async_flips@async-flip-with-page-flip-events}:
    - shard-kbl:          [FAIL][38] ([i915#2521]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [INCOMPLETE][40] ([i915#1635]) -> [PASS][41] +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge:
    - shard-glk:          [DMESG-WARN][42] ([i915#1982]) -> [PASS][43] +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk3/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
    - shard-iclb:         [INCOMPLETE][44] ([i915#2606]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-tglb:         [INCOMPLETE][46] -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-skl:          [DMESG-WARN][48] ([i915#2606]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-skl:          [INCOMPLETE][50] ([i915#123] / [i915#2606]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
    - shard-skl:          [INCOMPLETE][52] ([i915#123]) -> [PASS][53] +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html

  * igt@kms_plane@plane-position-hole-dpms-pipe-a-planes:
    - shard-skl:          [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +2 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_plane@plane-position-hole-dpms-pipe-a-planes.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl1/igt@kms_plane@plane-position-hole-dpms-pipe-a-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-kbl:          [DMESG-WARN][56] ([i915#165] / [i915#78]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-kbl4/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_vblank@pipe-c-wait-forked-busy:
    - shard-apl:          [DMESG-WARN][58] ([i915#1635] / [i915#1982]) -> [PASS][59] +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl4/igt@kms_vblank@pipe-c-wait-forked-busy.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         [DMESG-WARN][60] ([i915#2606]) -> [INCOMPLETE][61] ([i915#2606])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
    - shard-tglb:         [DMESG-WARN][62] ([i915#2606]) -> [INCOMPLETE][63] ([i915#2606])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
    - shard-skl:          [DMESG-WARN][64] ([i915#1982]) -> [INCOMPLETE][65] ([i915#123])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-skl:          [DMESG-WARN][66] ([i915#1982]) -> [INCOMPLETE][67] ([i915#123] / [i915#2606])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl9/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][68], [FAIL][69]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][70] ([i915#1635] / [i915#2439])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl6/igt@runner@aborted.html
    - shard-tglb:         ([FAIL][71], [FAIL][72], [FAIL][73], [FAIL][74], [FAIL][75], [FAIL][76], [FAIL][77], [FAIL][78], [FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85], [FAIL][86], [FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120]) ([i915#1764] / [i915#1814] / [i915#456])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb3/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb3/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@runner@aborted.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb3/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb7/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb7/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb7/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9206 -> Patchwork_18782

  CI-20190529: 20190529
  CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18782: 3b45adb5c1be9eb28c4cbbcb34ec0676fcd62acc @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Guard debugfs against invalid access without display

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 03:17:45AM +0000, Patchwork wrote:
>== Series Details ==
>
>Series: series starting with [1/3] drm/i915: Guard debugfs against invalid access without display
>URL   : https://patchwork.freedesktop.org/series/83070/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18782_full
>====================================================
>
>Summary
>-------
>
>  **FAILURE**
>
>  Serious unknown changes coming with Patchwork_18782_full absolutely need to be
>  verified manually.
>
>  If you think the reported changes have nothing to do with the changes
>  introduced in Patchwork_18782_full, please notify your bug team to allow them
>  to document this new failure mode, which will reduce false positives in CI.
>
>
>
>Possible new issues
>-------------------
>
>  Here are the unknown changes that may have been introduced in Patchwork_18782_full:
>
>### IGT changes ###
>
>#### Possible regressions ####
>
>  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
>    - shard-skl:          [PASS][1] -> [DMESG-WARN][2]
>   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
>   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html

same signature as recent runs on skl, e.g.
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9202/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html#dmesg-warnings518

Lucas De Marchi

>
>
>#### Suppressed ####
>
>  The following results come from untrusted machines, tests, or statuses.
>  They do not affect the overall result.
>
>  * {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile}:
>    - shard-skl:          NOTRUN -> [FAIL][3]
>   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
>
>
>New tests
>---------
>
>  New tests have been introduced between CI_DRM_9206_full and Patchwork_18782_full:
>
>### New CI tests (1) ###
>
>  * boot:
>    - Statuses : 175 pass(s)
>    - Exec time: [0.0] s
>
>
>
>Known issues
>------------
>
>  Here are the changes found in Patchwork_18782_full that come from known issues:
>
>### IGT changes ###
>
>#### Issues hit ####
>
>  * igt@drm_read@empty-block:
>    - shard-glk:          [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
>   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk2/igt@drm_read@empty-block.html
>   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk4/igt@drm_read@empty-block.html
>
>  * igt@gem_softpin@noreloc-s3:
>    - shard-apl:          [PASS][6] -> [INCOMPLETE][7] ([i915#1635])
>   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl2/igt@gem_softpin@noreloc-s3.html
>   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl6/igt@gem_softpin@noreloc-s3.html
>
>  * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
>    - shard-apl:          [PASS][8] -> [DMESG-WARN][9] ([i915#1635] / [i915#1982]) +3 similar issues
>   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
>   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl4/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
>
>  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
>    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#79])
>   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
>   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
>
>  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
>    - shard-tglb:         [PASS][12] -> [INCOMPLETE][13] ([i915#2606]) +2 similar issues
>   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
>   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html
>
>  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
>    - shard-tglb:         [PASS][14] -> [DMESG-WARN][15] ([i915#2606])
>   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
>   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
>
>  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
>    - shard-iclb:         [PASS][16] -> [INCOMPLETE][17] ([i915#2606])
>   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
>   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear.html
>
>  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
>    - shard-skl:          [PASS][18] -> [INCOMPLETE][19] ([i915#123]) +2 similar issues
>   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
>   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
>
>  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
>    - shard-skl:          [PASS][20] -> [INCOMPLETE][21] ([i915#123] / [i915#2606])
>   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
>   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
>
>  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
>    - shard-kbl:          [PASS][22] -> [DMESG-WARN][23] ([i915#1982])
>   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
>   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
>
>  * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
>    - shard-skl:          [PASS][24] -> [DMESG-WARN][25] ([i915#1982]) +2 similar issues
>   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
>   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
>
>  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
>    - shard-skl:          [PASS][26] -> [DMESG-FAIL][27] ([fdo#108145] / [i915#1982])
>   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
>  * igt@kms_setmode@basic:
>    - shard-apl:          [PASS][28] -> [FAIL][29] ([i915#1635] / [i915#31])
>   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl3/igt@kms_setmode@basic.html
>   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl2/igt@kms_setmode@basic.html
>
>  * igt@perf@blocking:
>    - shard-skl:          [PASS][30] -> [FAIL][31] ([i915#1542])
>   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@perf@blocking.html
>   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl6/igt@perf@blocking.html
>
>
>#### Possible fixes ####
>
>  * igt@gem_exec_create@basic:
>    - shard-snb:          [INCOMPLETE][32] ([i915#82]) -> [PASS][33]
>   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@gem_exec_create@basic.html
>   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-snb2/igt@gem_exec_create@basic.html
>
>  * igt@gem_exec_gttfill@all:
>    - shard-glk:          [DMESG-WARN][34] ([i915#118] / [i915#95]) -> [PASS][35]
>   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@gem_exec_gttfill@all.html
>   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk1/igt@gem_exec_gttfill@all.html
>
>  * igt@gem_exec_whisper@basic-contexts-priority:
>    - shard-iclb:         [INCOMPLETE][36] -> [PASS][37]
>   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb3/igt@gem_exec_whisper@basic-contexts-priority.html
>   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb5/igt@gem_exec_whisper@basic-contexts-priority.html
>
>  * {igt@kms_async_flips@async-flip-with-page-flip-events}:
>    - shard-kbl:          [FAIL][38] ([i915#2521]) -> [PASS][39]
>   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_async_flips@async-flip-with-page-flip-events.html
>   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-kbl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
>
>  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
>    - shard-apl:          [INCOMPLETE][40] ([i915#1635]) -> [PASS][41] +1 similar issue
>   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
>  * igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge:
>    - shard-glk:          [DMESG-WARN][42] ([i915#1982]) -> [PASS][43] +1 similar issue
>   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk3/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
>   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-256x256-bottom-edge.html
>
>  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
>    - shard-iclb:         [INCOMPLETE][44] ([i915#2606]) -> [PASS][45]
>   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
>   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
>
>  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
>    - shard-tglb:         [INCOMPLETE][46] -> [PASS][47]
>   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
>   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
>
>  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
>    - shard-skl:          [DMESG-WARN][48] ([i915#2606]) -> [PASS][49]
>   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
>   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
>
>  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc:
>    - shard-skl:          [INCOMPLETE][50] ([i915#123] / [i915#2606]) -> [PASS][51]
>   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
>   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
>
>  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
>    - shard-skl:          [INCOMPLETE][52] ([i915#123]) -> [PASS][53] +2 similar issues
>   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
>   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html
>
>  * igt@kms_plane@plane-position-hole-dpms-pipe-a-planes:
>    - shard-skl:          [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +2 similar issues
>   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_plane@plane-position-hole-dpms-pipe-a-planes.html
>   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl1/igt@kms_plane@plane-position-hole-dpms-pipe-a-planes.html
>
>  * igt@kms_plane_lowres@pipe-a-tiling-x:
>    - shard-kbl:          [DMESG-WARN][56] ([i915#165] / [i915#78]) -> [PASS][57]
>   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_plane_lowres@pipe-a-tiling-x.html
>   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-kbl4/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
>  * igt@kms_vblank@pipe-c-wait-forked-busy:
>    - shard-apl:          [DMESG-WARN][58] ([i915#1635] / [i915#1982]) -> [PASS][59] +2 similar issues
>   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_vblank@pipe-c-wait-forked-busy.html
>   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl4/igt@kms_vblank@pipe-c-wait-forked-busy.html
>
>
>#### Warnings ####
>
>  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
>    - shard-iclb:         [DMESG-WARN][60] ([i915#2606]) -> [INCOMPLETE][61] ([i915#2606])
>   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
>   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
>
>  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
>    - shard-tglb:         [DMESG-WARN][62] ([i915#2606]) -> [INCOMPLETE][63] ([i915#2606])
>   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
>   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
>
>  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite:
>    - shard-skl:          [DMESG-WARN][64] ([i915#1982]) -> [INCOMPLETE][65] ([i915#123])
>   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
>   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite.html
>
>  * igt@kms_frontbuffer_tracking@psr-slowdraw:
>    - shard-skl:          [DMESG-WARN][66] ([i915#1982]) -> [INCOMPLETE][67] ([i915#123] / [i915#2606])
>   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl8/igt@kms_frontbuffer_tracking@psr-slowdraw.html
>   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl9/igt@kms_frontbuffer_tracking@psr-slowdraw.html
>
>  * igt@runner@aborted:
>    - shard-apl:          ([FAIL][68], [FAIL][69]) ([i915#1611] / [i915#1635] / [i915#1814]) -> [FAIL][70] ([i915#1635] / [i915#2439])
>   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl7/igt@runner@aborted.html
>   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@runner@aborted.html
>   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl6/igt@runner@aborted.html
>    - shard-tglb:         ([FAIL][71], [FAIL][72], [FAIL][73], [FAIL][74], [FAIL][75], [FAIL][76], [FAIL][77], [FAIL][78], [FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85], [FAIL][86], [FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95]) ([i915#1764] / [i915#1814] / [i915#456] / [k.org#205379]) -> ([FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120]) ([i915#1764] / [i915#1814] / [i915#456])
>   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
>   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
>   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
>   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
>   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
>   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
>   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
>   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
>   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
>   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
>   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
>   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
>   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
>   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@runner@aborted.html
>   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
>   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb3/igt@runner@aborted.html
>   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
>   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
>   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@runner@aborted.html
>   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
>   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb5/igt@runner@aborted.html
>   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
>   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb7/igt@runner@aborted.html
>   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb6/igt@runner@aborted.html
>   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb1/igt@runner@aborted.html
>   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
>   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
>   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb3/igt@runner@aborted.html
>   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
>   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
>   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
>   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
>   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb3/igt@runner@aborted.html
>   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
>   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
>   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@runner@aborted.html
>   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb3/igt@runner@aborted.html
>   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
>   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb7/igt@runner@aborted.html
>   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb6/igt@runner@aborted.html
>   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
>   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@runner@aborted.html
>   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb8/igt@runner@aborted.html
>   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb7/igt@runner@aborted.html
>   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@runner@aborted.html
>   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
>   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
>   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb7/igt@runner@aborted.html
>   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@runner@aborted.html
>   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb5/igt@runner@aborted.html
>
>
>  {name}: This element is suppressed. This means it is ignored when computing
>          the status of the difference (SUCCESS, WARNING, or FAILURE).
>
>  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
>  [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
>  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
>  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
>  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
>  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
>  [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764
>  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
>  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
>  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
>  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
>  [i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
>  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
>  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
>  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
>  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
>  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
>  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
>
>
>Participating hosts (11 -> 11)
>------------------------------
>
>  No changes in participating hosts
>
>
>Build changes
>-------------
>
>  * Linux: CI_DRM_9206 -> Patchwork_18782
>
>  CI-20190529: 20190529
>  CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
>  IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>  Patchwork_18782: 3b45adb5c1be9eb28c4cbbcb34ec0676fcd62acc @ git://anongit.freedesktop.org/gfx-ci/linux
>  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
>== Logs ==
>
>For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/index.html
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