* [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa The BLK_CTL according to HW design is basically the wrapper of the entire function specific group of IPs and holds GPRs that usually cannot be placed into one specific IP from that group. Some of these GPRs are used to control some clocks, other some resets, others some very specific function that does not fit into clocks or resets. Since the clocks are registered using the i.MX clock subsystem API, the driver is placed into the clock subsystem, but it also registers the resets. For the other functionalities that other GPRs might have, the syscon is used. Changes since v4: * added back the bus_blk_clk in the imx8mp blk_ctl driver (media_blk_ctl) * added the R-b tag from Rob to the documentation patch Abel Vesa (14): dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs dt-bindings: clock: imx8mp: Add ids for the audio shared gate dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs clk: imx8mp: Add audio shared gate Documentation: bindings: clk: Add bindings for i.MX BLK_CTL clk: imx: Add generic blk-ctl driver clk: imx: Add blk-ctl driver for i.MX8MP arm64: dts: imx8mp: Add audio_blk_ctl node arm64: dts: imx8mp: Add media_blk_ctl node arm64: dts: imx8mp: Add hdmi_blk_ctl node .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 37 +++ drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.c | 302 ++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.h | 80 ++++++ drivers/clk/imx/clk-imx8mp.c | 12 +- include/dt-bindings/clock/imx8mp-clock.h | 200 +++++++++---- include/dt-bindings/reset/imx8mp-reset.h | 45 +++ 9 files changed, 992 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c create mode 100644 drivers/clk/imx/clk-blk-ctl.c create mode 100644 drivers/clk/imx/clk-blk-ctl.h -- 2.7.4 ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel The BLK_CTL according to HW design is basically the wrapper of the entire function specific group of IPs and holds GPRs that usually cannot be placed into one specific IP from that group. Some of these GPRs are used to control some clocks, other some resets, others some very specific function that does not fit into clocks or resets. Since the clocks are registered using the i.MX clock subsystem API, the driver is placed into the clock subsystem, but it also registers the resets. For the other functionalities that other GPRs might have, the syscon is used. Changes since v4: * added back the bus_blk_clk in the imx8mp blk_ctl driver (media_blk_ctl) * added the R-b tag from Rob to the documentation patch Abel Vesa (14): dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs dt-bindings: clock: imx8mp: Add ids for the audio shared gate dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs clk: imx8mp: Add audio shared gate Documentation: bindings: clk: Add bindings for i.MX BLK_CTL clk: imx: Add generic blk-ctl driver clk: imx: Add blk-ctl driver for i.MX8MP arm64: dts: imx8mp: Add audio_blk_ctl node arm64: dts: imx8mp: Add media_blk_ctl node arm64: dts: imx8mp: Add hdmi_blk_ctl node .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 37 +++ drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.c | 302 ++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.h | 80 ++++++ drivers/clk/imx/clk-imx8mp.c | 12 +- include/dt-bindings/clock/imx8mp-clock.h | 200 +++++++++---- include/dt-bindings/reset/imx8mp-reset.h | 45 +++ 9 files changed, 992 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c create mode 100644 drivers/clk/imx/clk-blk-ctl.c create mode 100644 drivers/clk/imx/clk-blk-ctl.h -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa In the reference manual the actual name is Audio BLK_CTL. Lets make it more obvious here by renaming from audiomix to audio_blk_ctl. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fb..89c67b7 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,66 +324,66 @@ #define IMX8MP_CLK_END 313 -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG 25 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG 31 +#define IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY 38 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL 54 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL 56 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT 58 -#define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel In the reference manual the actual name is Audio BLK_CTL. Lets make it more obvious here by renaming from audiomix to audio_blk_ctl. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fb..89c67b7 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,66 +324,66 @@ #define IMX8MP_CLK_END 313 -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG 25 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG 31 +#define IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY 38 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL 54 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL 56 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT 58 -#define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:05 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:13) > In the reference manual the actual name is Audio BLK_CTL. > Lets make it more obvious here by renaming from audiomix to audio_blk_ctl. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl @ 2020-11-05 1:05 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:13) > In the reference manual the actual name is Audio BLK_CTL. > Lets make it more obvious here by renaming from audiomix to audio_blk_ctl. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/reset/imx8mp-reset.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 2e8c910..6c7f17f 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -47,4 +47,9 @@ #define IMX8MP_RESET_NUM 38 +#define IMX8MP_AUDIO_BLK_CTL_EARC_RESET 0 +#define IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET 1 + +#define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 + #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/reset/imx8mp-reset.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 2e8c910..6c7f17f 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -47,4 +47,9 @@ #define IMX8MP_RESET_NUM 38 +#define IMX8MP_AUDIO_BLK_CTL_EARC_RESET 0 +#define IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET 1 + +#define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 + #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:05 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:14) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs @ 2020-11-05 1:05 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:14) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 89c67b7..5fc2c40 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -322,7 +322,17 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 313 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 314 +#define IMX8MP_CLK_SAI1_ROOT 315 +#define IMX8MP_CLK_SAI2_ROOT 316 +#define IMX8MP_CLK_SAI3_ROOT 317 +#define IMX8MP_CLK_SAI5_ROOT 318 +#define IMX8MP_CLK_SAI6_ROOT 319 +#define IMX8MP_CLK_SAI7_ROOT 320 +#define IMX8MP_CLK_PDM_ROOT 321 + +#define IMX8MP_CLK_END 322 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 89c67b7..5fc2c40 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -322,7 +322,17 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 313 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 314 +#define IMX8MP_CLK_SAI1_ROOT 315 +#define IMX8MP_CLK_SAI2_ROOT 316 +#define IMX8MP_CLK_SAI3_ROOT 317 +#define IMX8MP_CLK_SAI5_ROOT 318 +#define IMX8MP_CLK_SAI6_ROOT 319 +#define IMX8MP_CLK_SAI7_ROOT 320 +#define IMX8MP_CLK_PDM_ROOT 321 + +#define IMX8MP_CLK_END 322 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG 0 #define IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1 1 -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:05 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:15) > All these IDs are for one single HW gate (CCGR101) that is shared > between these root clocks. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate @ 2020-11-05 1:05 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:15) > All these IDs are for one single HW gate (CCGR101) that is shared > between these root clocks. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 5fc2c40..12632fa 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -396,4 +396,32 @@ #define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK 0 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF 1 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK 2 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK 3 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL 4 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB 5 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC 6 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB 7 +#define IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK 8 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK 9 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK 10 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL 11 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB 12 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR 13 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI 14 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB 15 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR 16 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI 17 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB 18 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR 19 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI 20 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB 21 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2 22 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI 23 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI 24 + +#define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 + #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 5fc2c40..12632fa 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -396,4 +396,32 @@ #define IMX8MP_CLK_AUDIO_BLK_CTL_END 59 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK 0 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF 1 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK 2 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK 3 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL 4 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB 5 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC 6 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB 7 +#define IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK 8 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK 9 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK 10 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL 11 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB 12 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR 13 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI 14 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB 15 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR 16 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI 17 +#define IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB 18 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR 19 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI 20 +#define IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB 21 +#define IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2 22 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI 23 +#define IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI 24 + +#define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 + #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:05 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:16) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs @ 2020-11-05 1:05 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:05 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:16) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/reset/imx8mp-reset.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 6c7f17f..ba70248 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -52,4 +52,32 @@ #define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK 0 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF 1 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK 3 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL 4 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB 5 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC 6 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB 7 +#define IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK 8 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK 9 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK 10 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL 11 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB 12 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR 13 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI 14 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB 15 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR 16 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI 17 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB 18 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR 19 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI 20 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB 21 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2 22 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI 23 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI 24 + +#define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 + #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/reset/imx8mp-reset.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 6c7f17f..ba70248 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -52,4 +52,32 @@ #define IMX8MP_AUDIO_BLK_CTL_RESET_NUM 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK 0 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF 1 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK 2 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK 3 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL 4 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB 5 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC 6 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB 7 +#define IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK 8 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK 9 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK 10 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL 11 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB 12 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR 13 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI 14 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB 15 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR 16 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI 17 +#define IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB 18 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR 19 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI 20 +#define IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB 21 +#define IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2 22 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI 23 +#define IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI 24 + +#define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 + #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:06 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:06 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:17) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs @ 2020-11-05 1:06 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:06 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:17) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 12632fa..de7d522 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -424,4 +424,44 @@ #define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK 0 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK 1 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK 2 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK 3 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK 4 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK 5 +#define IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK 6 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK 7 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK 8 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK 9 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK 10 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK 11 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK 12 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK 13 +#define IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK 14 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK 15 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK 16 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK 17 +#define IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK 18 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK 19 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK 20 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK 21 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK 22 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK 23 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK 24 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK 26 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK 27 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK 28 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK 29 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK 30 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK 31 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK 32 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK 33 +#define IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL 34 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL 35 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL 36 + +#define IMX8MP_CLK_HDMI_BLK_CTL_END 37 + #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel These will be used by the imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/clock/imx8mp-clock.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 12632fa..de7d522 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -424,4 +424,44 @@ #define IMX8MP_CLK_MEDIA_BLK_CTL_END 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK 0 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK 1 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK 2 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK 3 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK 4 +#define IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK 5 +#define IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK 6 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK 7 +#define IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK 8 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK 9 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK 10 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK 11 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK 12 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK 13 +#define IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK 14 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK 15 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK 16 +#define IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK 17 +#define IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK 18 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK 19 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK 20 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK 21 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK 22 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK 23 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK 24 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK 25 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK 26 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK 27 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK 28 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK 29 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK 30 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK 31 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK 32 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK 33 +#define IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL 34 +#define IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL 35 +#define IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL 36 + +#define IMX8MP_CLK_HDMI_BLK_CTL_END 37 + #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:06 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:06 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:18) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs @ 2020-11-05 1:06 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:06 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:18) > These will be used by the imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa These will be used imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/reset/imx8mp-reset.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index ba70248..eb9ed21 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -80,4 +80,16 @@ #define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET 0 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET 1 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET 2 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PVI_RESET 3 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET 4 +#define IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET 5 +#define IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET 6 +#define IMX8MP_HDMI_BLK_CTL_LCDIF_RESET 7 + +#define IMX8MP_HDMI_BLK_CTL_RESET_NUM 8 + + #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel These will be used imx8mp for blk_ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- include/dt-bindings/reset/imx8mp-reset.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index ba70248..eb9ed21 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -80,4 +80,16 @@ #define IMX8MP_MEDIA_BLK_CTL_RESET_NUM 25 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET 0 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET 1 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET 2 +#define IMX8MP_HDMI_BLK_CTL_HDMI_PVI_RESET 3 +#define IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET 4 +#define IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET 5 +#define IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET 6 +#define IMX8MP_HDMI_BLK_CTL_LCDIF_RESET 7 + +#define IMX8MP_HDMI_BLK_CTL_RESET_NUM 8 + + #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:06 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:06 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:19) > These will be used imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs @ 2020-11-05 1:06 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:06 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:19) > These will be used imx8mp for blk_ctl driver. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 08/14] clk: imx8mp: Add audio shared gate 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- drivers/clk/imx/clk-imx8mp.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 3cb2bc4..02469f7 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -17,6 +17,7 @@ static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -725,7 +726,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 08/14] clk: imx8mp: Add audio shared gate @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- drivers/clk/imx/clk-imx8mp.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 3cb2bc4..02469f7 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -17,6 +17,7 @@ static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -725,7 +726,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 08/14] clk: imx8mp: Add audio shared gate 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:07 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:07 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:20) > According to the RM, the CCGR101 is shared for the following root clocks: > - AUDIO_AHB_CLK_ROOT > - AUDIO_AXI_CLK_ROOT > - SAI2_CLK_ROOT > - SAI3_CLK_ROOT > - SAI5_CLK_ROOT > - SAI6_CLK_ROOT > - SAI7_CLK_ROOT > - PDM_CLK_ROOT > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 08/14] clk: imx8mp: Add audio shared gate @ 2020-11-05 1:07 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:07 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:20) > According to the RM, the CCGR101 is shared for the following root clocks: > - AUDIO_AHB_CLK_ROOT > - AUDIO_AXI_CLK_ROOT > - SAI2_CLK_ROOT > - SAI3_CLK_ROOT > - SAI5_CLK_ROOT > - SAI6_CLK_ROOT > - SAI7_CLK_ROOT > - PDM_CLK_ROOT > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Document the i.MX BLK_CTL with its devicetree properties. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml new file mode 100644 index 00000000..5e9eb40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTL + +maintainers: + - Abel Vesa <abel.vesa@nxp.com> + +description: + i.MX BLK_CTL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. Because it usually contains + clocks amongst other things, it needs access to the i.MX clocks + API. All the other functionalities it provides can work just fine + from the clock subsystem tree. + +properties: + compatible: + items: + - enum: + - fsl,imx8mp-audio-blk-ctl + - fsl,imx8mp-hdmi-blk-ctl + - fsl,imx8mp-media-blk-ctl + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x10000>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Document the i.MX BLK_CTL with its devicetree properties. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml new file mode 100644 index 00000000..5e9eb40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTL + +maintainers: + - Abel Vesa <abel.vesa@nxp.com> + +description: + i.MX BLK_CTL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. Because it usually contains + clocks amongst other things, it needs access to the i.MX clocks + API. All the other functionalities it provides can work just fine + from the clock subsystem tree. + +properties: + compatible: + items: + - enum: + - fsl,imx8mp-audio-blk-ctl + - fsl,imx8mp-hdmi-blk-ctl + - fsl,imx8mp-media-blk-ctl + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x10000>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL 2020-11-03 11:18 ` Abel Vesa @ 2020-11-04 19:01 ` Rob Herring -1 siblings, 0 replies; 72+ messages in thread From: Rob Herring @ 2020-11-04 19:01 UTC (permalink / raw) To: Abel Vesa Cc: devicetree, Jacky Bai, Mike Turquette, Stephen Boyd, Anson Huang, linux-arm-kernel, NXP Linux Team, Linux Kernel Mailing List, Sascha Hauer, linux-clk, Adam Ford, Shawn Guo, Fabio Estevam, Lucas Stach, Marek Vasut, Peng Fan, Dong Aisheng On Tue, 03 Nov 2020 13:18:21 +0200, Abel Vesa wrote: > Document the i.MX BLK_CTL with its devicetree properties. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml:23:10: [warning] wrong indentation: expected 10 but found 9 (indentation) dtschema/dtc warnings/errors: See https://patchwork.ozlabs.org/patch/1392927 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL @ 2020-11-04 19:01 ` Rob Herring 0 siblings, 0 replies; 72+ messages in thread From: Rob Herring @ 2020-11-04 19:01 UTC (permalink / raw) To: Abel Vesa Cc: Dong Aisheng, devicetree, Peng Fan, Jacky Bai, Anson Huang, Stephen Boyd, Shawn Guo, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, NXP Linux Team, Sascha Hauer, Fabio Estevam, Adam Ford, linux-clk, linux-arm-kernel, Lucas Stach On Tue, 03 Nov 2020 13:18:21 +0200, Abel Vesa wrote: > Document the i.MX BLK_CTL with its devicetree properties. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml:23:10: [warning] wrong indentation: expected 10 but found 9 (indentation) dtschema/dtc warnings/errors: See https://patchwork.ozlabs.org/patch/1392927 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:08 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:08 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:21) > Document the i.MX BLK_CTL with its devicetree properties. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> > diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > new file mode 100644 > index 00000000..5e9eb40 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mp-clock.h> Is this include to make sure this file exists? > + > + audio_blk_ctl: clock-controller@30e20000 { > + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; > + reg = <0x30e20000 0x10000>; > + power-domains = <&audiomix_pd>; > + > + #clock-cells = <1>; ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL @ 2020-11-05 1:08 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:08 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:21) > Document the i.MX BLK_CTL with its devicetree properties. > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- Acked-by: Stephen Boyd <sboyd@kernel.org> > diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > new file mode 100644 > index 00000000..5e9eb40 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mp-clock.h> Is this include to make sure this file exists? > + > + audio_blk_ctl: clock-controller@30e20000 { > + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; > + reg = <0x30e20000 0x10000>; > + power-domains = <&audiomix_pd>; > + > + #clock-cells = <1>; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa The i.MX8MP platform introduces a new type of IP which is called BLK_CTL in RM and usually is comprised of some GPRs that are considered too generic to be part of any dedicated IP from that specific subsystem. In general, some of the GPRs have some clock bits, some have reset bits, so in order to be able to use the imx clock API, this needs to be in a clock driver. From there it can use the reset controller API and leave the rest to the syscon. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl.c | 302 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.h | 80 +++++++++++ 3 files changed, 383 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctl.c create mode 100644 drivers/clk/imx/clk-blk-ctl.h diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index dd6a737..3d6d9cb 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c new file mode 100644 index 00000000..9ac0ed0 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 NXP. + */ + +#include <linux/clk.h> +#include <linux/reset-controller.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "clk.h" +#include "clk-blk-ctl.h" + +struct imx_reset_hw { + u32 offset; + u32 shift; + u32 mask; + unsigned long asserted; +}; + +struct imx_pm_safekeep_info { + uint32_t *regs_values; + uint32_t *regs_offsets; + uint32_t regs_num; +}; + +struct imx_blk_ctl_drvdata { + void __iomem *base; + struct reset_controller_dev rcdev; + struct imx_reset_hw *rst_hws; + struct imx_pm_safekeep_info pm_info; + + spinlock_t lock; +}; + +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, + bool write) +{ + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; + void __iomem *base = drvdata->base; + int i; + + if (!pm_info->regs_num) + return; + + for (i = 0; i < pm_info->regs_num; i++) { + u32 offset = pm_info->regs_offsets[i]; + + if (write) + writel(pm_info->regs_values[i], base + offset); + else + pm_info->regs_values[i] = readl(base + offset); + } + +} + +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device *dev) +{ + imx_blk_ctl_read_write(dev, false); + + return 0; +} + +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device *dev) +{ + imx_blk_ctl_read_write(dev, true); + + return 0; +} + +const struct dev_pm_ops imx_blk_ctl_pm_ops = { + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, + imx_blk_ctl_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); + +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, + struct imx_blk_ctl_drvdata, rcdev); + unsigned int offset = drvdata->rst_hws[id].offset; + unsigned int shift = drvdata->rst_hws[id].shift; + unsigned int mask = drvdata->rst_hws[id].mask; + void __iomem *reg_addr = drvdata->base + offset; + unsigned long flags; + u32 reg; + + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) + return -ENODEV; + + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_get_sync(rcdev->dev); + + spin_lock_irqsave(&drvdata->lock, flags); + + reg = readl(reg_addr); + if (assert) + writel(reg & ~(mask << shift), reg_addr); + else + writel(reg | (mask << shift), reg_addr); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_put(rcdev->dev); + + return 0; +} + +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctl_reset_set(rcdev, id, true); +} + +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctl_reset_set(rcdev, id, false); +} + +static const struct reset_control_ops imx_blk_ctl_reset_ops = { + .assert = imx_blk_ctl_reset_assert, + .deassert = imx_blk_ctl_reset_deassert, +}; + +static int imx_blk_ctl_register_reset_controller(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + int max = dev_data->resets_max; + struct imx_reset_hw *hws; + int i; + + spin_lock_init(&drvdata->lock); + + drvdata->rcdev.owner = THIS_MODULE; + drvdata->rcdev.nr_resets = max; + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; + drvdata->rcdev.of_node = dev->of_node; + drvdata->rcdev.dev = dev; + + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), + GFP_KERNEL); + hws = drvdata->rst_hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; + + if (hw->type != BLK_CTL_RESET) + continue; + + hws[hw->id].offset = hw->offset; + hws[hw->id].shift = hw->shift; + hws[hw->id].mask = hw->mask; + } + + return devm_reset_controller_register(dev, &drvdata->rcdev); +} +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, + struct imx_blk_ctl_hw *hw) +{ + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + void __iomem *base = drvdata->base; + struct clk_hw *clk_hw = NULL; + + switch (hw->type) { + case BLK_CTL_CLK_MUX: + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, + base + hw->offset, + hw->shift, hw->width, + hw->parents, + hw->parents_count, + hw->flags); + break; + case BLK_CTL_CLK_GATE: + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, + base + hw->offset, hw->shift); + break; + case BLK_CTL_CLK_SHARED_GATE: + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, + hw->parents, + base + hw->offset, + hw->shift, + hw->shared_count); + break; + case BLK_CTL_CLK_PLL14XX: + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, + base + hw->offset, hw->pll_tbl); + break; + }; + + return clk_hw; +} + +static int imx_blk_ctl_register_clock_controller(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct clk_hw_onecell_data *clk_hw_data; + struct clk_hw **hws; + int i; + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + dev_data->hws_num), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = dev_data->clocks_max; + hws = clk_hw_data->hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; + + if (hw->type == BLK_CTL_RESET) + continue; + + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); + } + + imx_check_clk_hws(hws, dev_data->clocks_max); + + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_hw_data); +} + +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; + u32 regs_num = dev_data->pm_runtime_saved_regs_num; + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; + + if (!dev_data->pm_runtime_saved_regs_num) + return 0; + + pm_info->regs_values = devm_kzalloc(dev, + sizeof(u32) * regs_num, + GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_values))) + return PTR_ERR(pm_info->regs_values); + + pm_info->regs_offsets = kmemdup(regs_offsets, + regs_num * sizeof(u32), GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) + return PTR_ERR(pm_info->regs_offsets); + + pm_info->regs_num = regs_num; + + return 0; +} + +int imx_blk_ctl_register(struct platform_device *pdev) +{ + struct imx_blk_ctl_drvdata *drvdata; + struct device *dev = &pdev->dev; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (WARN_ON(!drvdata)) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(drvdata->base))) + return PTR_ERR(drvdata->base); + + dev_set_drvdata(dev, drvdata); + + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret = imx_blk_ctl_register_clock_controller(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + + ret = imx_blk_ctl_register_reset_controller(dev); + + pm_runtime_put(dev); + + return ret; +} +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h new file mode 100644 index 00000000..3f14a47 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MACH_IMX_CLK_BLK_CTL_H +#define __MACH_IMX_CLK_BLK_CTL_H + +enum imx_blk_ctl_hw_type { + BLK_CTL_CLK_MUX, + BLK_CTL_CLK_GATE, + BLK_CTL_CLK_SHARED_GATE, + BLK_CTL_CLK_PLL14XX, + BLK_CTL_RESET, +}; + +struct imx_blk_ctl_hw { + int type; + char *name; + u32 offset; + u32 shift; + u32 mask; + u32 width; + u32 flags; + u32 id; + const void *parents; + u32 parents_count; + int *shared_count; + const struct imx_pll14xx_clk *pll_tbl; +}; + +struct imx_blk_ctl_dev_data { + struct imx_blk_ctl_hw *hws; + u32 hws_num; + + u32 clocks_max; + u32 resets_max; + + u32 pm_runtime_saved_regs_num; + u32 pm_runtime_saved_regs[]; +}; + +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ + { \ + .type = _type, \ + .name = _name, \ + .id = _id, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mask = _mask, \ + .parents = _parents, \ + .parents_count = _parents_count, \ + .flags = _flags, \ + .shared_count = sh_count, \ + .pll_tbl = _pll_tbl, \ + } + +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) + +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) + +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) + +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) + +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) + +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) + +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) + +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; + +int imx_blk_ctl_register(struct platform_device *pdev); + +#endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel The i.MX8MP platform introduces a new type of IP which is called BLK_CTL in RM and usually is comprised of some GPRs that are considered too generic to be part of any dedicated IP from that specific subsystem. In general, some of the GPRs have some clock bits, some have reset bits, so in order to be able to use the imx clock API, this needs to be in a clock driver. From there it can use the reset controller API and leave the rest to the syscon. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl.c | 302 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-blk-ctl.h | 80 +++++++++++ 3 files changed, 383 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctl.c create mode 100644 drivers/clk/imx/clk-blk-ctl.h diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index dd6a737..3d6d9cb 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c new file mode 100644 index 00000000..9ac0ed0 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 NXP. + */ + +#include <linux/clk.h> +#include <linux/reset-controller.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "clk.h" +#include "clk-blk-ctl.h" + +struct imx_reset_hw { + u32 offset; + u32 shift; + u32 mask; + unsigned long asserted; +}; + +struct imx_pm_safekeep_info { + uint32_t *regs_values; + uint32_t *regs_offsets; + uint32_t regs_num; +}; + +struct imx_blk_ctl_drvdata { + void __iomem *base; + struct reset_controller_dev rcdev; + struct imx_reset_hw *rst_hws; + struct imx_pm_safekeep_info pm_info; + + spinlock_t lock; +}; + +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, + bool write) +{ + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; + void __iomem *base = drvdata->base; + int i; + + if (!pm_info->regs_num) + return; + + for (i = 0; i < pm_info->regs_num; i++) { + u32 offset = pm_info->regs_offsets[i]; + + if (write) + writel(pm_info->regs_values[i], base + offset); + else + pm_info->regs_values[i] = readl(base + offset); + } + +} + +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device *dev) +{ + imx_blk_ctl_read_write(dev, false); + + return 0; +} + +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device *dev) +{ + imx_blk_ctl_read_write(dev, true); + + return 0; +} + +const struct dev_pm_ops imx_blk_ctl_pm_ops = { + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, + imx_blk_ctl_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); + +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, + struct imx_blk_ctl_drvdata, rcdev); + unsigned int offset = drvdata->rst_hws[id].offset; + unsigned int shift = drvdata->rst_hws[id].shift; + unsigned int mask = drvdata->rst_hws[id].mask; + void __iomem *reg_addr = drvdata->base + offset; + unsigned long flags; + u32 reg; + + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) + return -ENODEV; + + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_get_sync(rcdev->dev); + + spin_lock_irqsave(&drvdata->lock, flags); + + reg = readl(reg_addr); + if (assert) + writel(reg & ~(mask << shift), reg_addr); + else + writel(reg | (mask << shift), reg_addr); + + spin_unlock_irqrestore(&drvdata->lock, flags); + + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) + pm_runtime_put(rcdev->dev); + + return 0; +} + +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctl_reset_set(rcdev, id, true); +} + +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctl_reset_set(rcdev, id, false); +} + +static const struct reset_control_ops imx_blk_ctl_reset_ops = { + .assert = imx_blk_ctl_reset_assert, + .deassert = imx_blk_ctl_reset_deassert, +}; + +static int imx_blk_ctl_register_reset_controller(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + int max = dev_data->resets_max; + struct imx_reset_hw *hws; + int i; + + spin_lock_init(&drvdata->lock); + + drvdata->rcdev.owner = THIS_MODULE; + drvdata->rcdev.nr_resets = max; + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; + drvdata->rcdev.of_node = dev->of_node; + drvdata->rcdev.dev = dev; + + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), + GFP_KERNEL); + hws = drvdata->rst_hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; + + if (hw->type != BLK_CTL_RESET) + continue; + + hws[hw->id].offset = hw->offset; + hws[hw->id].shift = hw->shift; + hws[hw->id].mask = hw->mask; + } + + return devm_reset_controller_register(dev, &drvdata->rcdev); +} +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, + struct imx_blk_ctl_hw *hw) +{ + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + void __iomem *base = drvdata->base; + struct clk_hw *clk_hw = NULL; + + switch (hw->type) { + case BLK_CTL_CLK_MUX: + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, + base + hw->offset, + hw->shift, hw->width, + hw->parents, + hw->parents_count, + hw->flags); + break; + case BLK_CTL_CLK_GATE: + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, + base + hw->offset, hw->shift); + break; + case BLK_CTL_CLK_SHARED_GATE: + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, + hw->parents, + base + hw->offset, + hw->shift, + hw->shared_count); + break; + case BLK_CTL_CLK_PLL14XX: + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, + base + hw->offset, hw->pll_tbl); + break; + }; + + return clk_hw; +} + +static int imx_blk_ctl_register_clock_controller(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct clk_hw_onecell_data *clk_hw_data; + struct clk_hw **hws; + int i; + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + dev_data->hws_num), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = dev_data->clocks_max; + hws = clk_hw_data->hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; + + if (hw->type == BLK_CTL_RESET) + continue; + + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); + } + + imx_check_clk_hws(hws, dev_data->clocks_max); + + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_hw_data); +} + +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) +{ + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; + u32 regs_num = dev_data->pm_runtime_saved_regs_num; + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; + + if (!dev_data->pm_runtime_saved_regs_num) + return 0; + + pm_info->regs_values = devm_kzalloc(dev, + sizeof(u32) * regs_num, + GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_values))) + return PTR_ERR(pm_info->regs_values); + + pm_info->regs_offsets = kmemdup(regs_offsets, + regs_num * sizeof(u32), GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) + return PTR_ERR(pm_info->regs_offsets); + + pm_info->regs_num = regs_num; + + return 0; +} + +int imx_blk_ctl_register(struct platform_device *pdev) +{ + struct imx_blk_ctl_drvdata *drvdata; + struct device *dev = &pdev->dev; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (WARN_ON(!drvdata)) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(drvdata->base))) + return PTR_ERR(drvdata->base); + + dev_set_drvdata(dev, drvdata); + + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret = imx_blk_ctl_register_clock_controller(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + + ret = imx_blk_ctl_register_reset_controller(dev); + + pm_runtime_put(dev); + + return ret; +} +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h new file mode 100644 index 00000000..3f14a47 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MACH_IMX_CLK_BLK_CTL_H +#define __MACH_IMX_CLK_BLK_CTL_H + +enum imx_blk_ctl_hw_type { + BLK_CTL_CLK_MUX, + BLK_CTL_CLK_GATE, + BLK_CTL_CLK_SHARED_GATE, + BLK_CTL_CLK_PLL14XX, + BLK_CTL_RESET, +}; + +struct imx_blk_ctl_hw { + int type; + char *name; + u32 offset; + u32 shift; + u32 mask; + u32 width; + u32 flags; + u32 id; + const void *parents; + u32 parents_count; + int *shared_count; + const struct imx_pll14xx_clk *pll_tbl; +}; + +struct imx_blk_ctl_dev_data { + struct imx_blk_ctl_hw *hws; + u32 hws_num; + + u32 clocks_max; + u32 resets_max; + + u32 pm_runtime_saved_regs_num; + u32 pm_runtime_saved_regs[]; +}; + +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ + { \ + .type = _type, \ + .name = _name, \ + .id = _id, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mask = _mask, \ + .parents = _parents, \ + .parents_count = _parents_count, \ + .flags = _flags, \ + .shared_count = sh_count, \ + .pll_tbl = _pll_tbl, \ + } + +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) + +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) + +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) + +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) + +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) + +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) + +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) + +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; + +int imx_blk_ctl_register(struct platform_device *pdev); + +#endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 0:59 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 0:59 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:22) > diff --git a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c > new file mode 100644 > index 00000000..9ac0ed0 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.c > @@ -0,0 +1,302 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright 2020 NXP. > + */ > + > +#include <linux/clk.h> > +#include <linux/reset-controller.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/slab.h> > +#include <linux/string.h> > +#include <linux/types.h> > + > +#include "clk.h" > +#include "clk-blk-ctl.h" > + > +struct imx_reset_hw { > + u32 offset; > + u32 shift; > + u32 mask; > + unsigned long asserted; > +}; > + > +struct imx_pm_safekeep_info { > + uint32_t *regs_values; > + uint32_t *regs_offsets; Please use u32, it's shorter and kernel style. > + uint32_t regs_num; > +}; > + > +struct imx_blk_ctl_drvdata { > + void __iomem *base; > + struct reset_controller_dev rcdev; > + struct imx_reset_hw *rst_hws; > + struct imx_pm_safekeep_info pm_info; > + > + spinlock_t lock; > +}; > + > +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, > + bool write) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + void __iomem *base = drvdata->base; > + int i; > + > + if (!pm_info->regs_num) > + return; > + > + for (i = 0; i < pm_info->regs_num; i++) { > + u32 offset = pm_info->regs_offsets[i]; > + > + if (write) > + writel(pm_info->regs_values[i], base + offset); > + else > + pm_info->regs_values[i] = readl(base + offset); > + } > + > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device *dev) > +{ > + imx_blk_ctl_read_write(dev, false); > + > + return 0; > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device *dev) > +{ > + imx_blk_ctl_read_write(dev, true); > + > + return 0; > +} > + > +const struct dev_pm_ops imx_blk_ctl_pm_ops = { > + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, > + imx_blk_ctl_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, > + pm_runtime_force_resume) > +}; > +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); > + > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > + struct imx_blk_ctl_drvdata, rcdev); > + unsigned int offset = drvdata->rst_hws[id].offset; > + unsigned int shift = drvdata->rst_hws[id].shift; > + unsigned int mask = drvdata->rst_hws[id].mask; > + void __iomem *reg_addr = drvdata->base + offset; > + unsigned long flags; > + u32 reg; > + > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > + return -ENODEV; > + > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) We are testing the same bit atomically, twice. At a quick glance this code looks broken. But then looking closer it's being multiplexed. Can we move these assert/!assert checks to the caller? It will make it easier to reason about. Is the atomic-ness of this code important? If not, it should use __test_bit() and __test_and_set_bit() because locking is being handled somewhere higher up. Furthermore, why are we using a per-reset bitmap to set one bit? Either combine them into one bitmap or have a simple bool please. > + pm_runtime_get_sync(rcdev->dev); > + > + spin_lock_irqsave(&drvdata->lock, flags); > + > + reg = readl(reg_addr); > + if (assert) > + writel(reg & ~(mask << shift), reg_addr); > + else > + writel(reg | (mask << shift), reg_addr); > + > + spin_unlock_irqrestore(&drvdata->lock, flags); > + > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_put(rcdev->dev); > + Same comment here. > + return 0; > +} > + > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, true); > +} > + > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, false); > +} > + > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > + .assert = imx_blk_ctl_reset_assert, > + .deassert = imx_blk_ctl_reset_deassert, > +}; > + > +static int imx_blk_ctl_register_reset_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + int max = dev_data->resets_max; > + struct imx_reset_hw *hws; > + int i; > + > + spin_lock_init(&drvdata->lock); > + > + drvdata->rcdev.owner = THIS_MODULE; > + drvdata->rcdev.nr_resets = max; > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > + drvdata->rcdev.of_node = dev->of_node; > + drvdata->rcdev.dev = dev; > + > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > + GFP_KERNEL); > + hws = drvdata->rst_hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type != BLK_CTL_RESET) > + continue; > + > + hws[hw->id].offset = hw->offset; > + hws[hw->id].shift = hw->shift; > + hws[hw->id].mask = hw->mask; > + } > + > + return devm_reset_controller_register(dev, &drvdata->rcdev); > +} Nitpick: Add a newline here please > +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > + struct imx_blk_ctl_hw *hw) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + void __iomem *base = drvdata->base; > + struct clk_hw *clk_hw = NULL; Is this necessary? Please add a default to the case if so and drop this assignment. But if all hw->type are covered in the case statement then this assignment can be dropped and nothing else. The compiler should tell us we forgot to handle a case. > + > + switch (hw->type) { > + case BLK_CTL_CLK_MUX: > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > + base + hw->offset, > + hw->shift, hw->width, > + hw->parents, > + hw->parents_count, > + hw->flags); > + break; > + case BLK_CTL_CLK_GATE: > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > + base + hw->offset, hw->shift); > + break; > + case BLK_CTL_CLK_SHARED_GATE: > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > + hw->parents, > + base + hw->offset, > + hw->shift, > + hw->shared_count); > + break; > + case BLK_CTL_CLK_PLL14XX: > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > + base + hw->offset, hw->pll_tbl); > + break; > + }; > + > + return clk_hw; > +} > + > +static int imx_blk_ctl_register_clock_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct clk_hw_onecell_data *clk_hw_data; > + struct clk_hw **hws; > + int i; > + > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > + dev_data->hws_num), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) We can drop the WARN_ON() call, slab allocations already print a stacktrace. > + return -ENOMEM; > + > + clk_hw_data->num = dev_data->clocks_max; > + hws = clk_hw_data->hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + Add a comment like /* Resets aren't a clk */ > + if (hw->type == BLK_CTL_RESET) > + continue; > + > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > + } > + > + imx_check_clk_hws(hws, dev_data->clocks_max); > + > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > + clk_hw_data); > +} > + > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > + > + if (!dev_data->pm_runtime_saved_regs_num) > + return 0; > + > + pm_info->regs_values = devm_kzalloc(dev, > + sizeof(u32) * regs_num, > + GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_values))) Please drop WARN_ON > + return PTR_ERR(pm_info->regs_values); > + > + pm_info->regs_offsets = kmemdup(regs_offsets, > + regs_num * sizeof(u32), GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) Please drop WARN_ON > + return PTR_ERR(pm_info->regs_offsets); > + > + pm_info->regs_num = regs_num; > + > + return 0; > +} > + > +int imx_blk_ctl_register(struct platform_device *pdev) > +{ > + struct imx_blk_ctl_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (WARN_ON(!drvdata)) Please drop WARN_ON > + return -ENOMEM; > + > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(drvdata->base))) Please drop WARN_ON > + return PTR_ERR(drvdata->base); > + > + dev_set_drvdata(dev, drvdata); > + > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > + if (ret) > + return ret; > + > + pm_runtime_get_noresume(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + ret = imx_blk_ctl_register_clock_controller(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + > + ret = imx_blk_ctl_register_reset_controller(dev); > + > + pm_runtime_put(dev); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h > new file mode 100644 > index 00000000..3f14a47 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > +#define __MACH_IMX_CLK_BLK_CTL_H > + > +enum imx_blk_ctl_hw_type { > + BLK_CTL_CLK_MUX, > + BLK_CTL_CLK_GATE, > + BLK_CTL_CLK_SHARED_GATE, > + BLK_CTL_CLK_PLL14XX, > + BLK_CTL_RESET, > +}; > + > +struct imx_blk_ctl_hw { > + int type; > + char *name; > + u32 offset; > + u32 shift; > + u32 mask; > + u32 width; > + u32 flags; > + u32 id; > + const void *parents; > + u32 parents_count; > + int *shared_count; > + const struct imx_pll14xx_clk *pll_tbl; Please forward declare pointer types. > +}; > + > +struct imx_blk_ctl_dev_data { > + struct imx_blk_ctl_hw *hws; Please forward declare pointer types. > + u32 hws_num; > + > + u32 clocks_max; > + u32 resets_max; > + > + u32 pm_runtime_saved_regs_num; > + u32 pm_runtime_saved_regs[]; > +}; > + > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > + { \ > + .type = _type, \ > + .name = _name, \ > + .id = _id, \ > + .offset = _offset, \ > + .shift = _shift, \ > + .width = _width, \ > + .mask = _mask, \ > + .parents = _parents, \ > + .parents_count = _parents_count, \ > + .flags = _flags, \ > + .shared_count = sh_count, \ > + .pll_tbl = _pll_tbl, \ > + } > + > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) > + > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) > + > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) > + > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > + > +int imx_blk_ctl_register(struct platform_device *pdev); Please forward declare pointer types. > + > +#endif > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2020-11-05 0:59 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 0:59 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:22) > diff --git a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c > new file mode 100644 > index 00000000..9ac0ed0 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.c > @@ -0,0 +1,302 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright 2020 NXP. > + */ > + > +#include <linux/clk.h> > +#include <linux/reset-controller.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/slab.h> > +#include <linux/string.h> > +#include <linux/types.h> > + > +#include "clk.h" > +#include "clk-blk-ctl.h" > + > +struct imx_reset_hw { > + u32 offset; > + u32 shift; > + u32 mask; > + unsigned long asserted; > +}; > + > +struct imx_pm_safekeep_info { > + uint32_t *regs_values; > + uint32_t *regs_offsets; Please use u32, it's shorter and kernel style. > + uint32_t regs_num; > +}; > + > +struct imx_blk_ctl_drvdata { > + void __iomem *base; > + struct reset_controller_dev rcdev; > + struct imx_reset_hw *rst_hws; > + struct imx_pm_safekeep_info pm_info; > + > + spinlock_t lock; > +}; > + > +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, > + bool write) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + void __iomem *base = drvdata->base; > + int i; > + > + if (!pm_info->regs_num) > + return; > + > + for (i = 0; i < pm_info->regs_num; i++) { > + u32 offset = pm_info->regs_offsets[i]; > + > + if (write) > + writel(pm_info->regs_values[i], base + offset); > + else > + pm_info->regs_values[i] = readl(base + offset); > + } > + > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device *dev) > +{ > + imx_blk_ctl_read_write(dev, false); > + > + return 0; > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device *dev) > +{ > + imx_blk_ctl_read_write(dev, true); > + > + return 0; > +} > + > +const struct dev_pm_ops imx_blk_ctl_pm_ops = { > + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, > + imx_blk_ctl_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, > + pm_runtime_force_resume) > +}; > +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); > + > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > + struct imx_blk_ctl_drvdata, rcdev); > + unsigned int offset = drvdata->rst_hws[id].offset; > + unsigned int shift = drvdata->rst_hws[id].shift; > + unsigned int mask = drvdata->rst_hws[id].mask; > + void __iomem *reg_addr = drvdata->base + offset; > + unsigned long flags; > + u32 reg; > + > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > + return -ENODEV; > + > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) We are testing the same bit atomically, twice. At a quick glance this code looks broken. But then looking closer it's being multiplexed. Can we move these assert/!assert checks to the caller? It will make it easier to reason about. Is the atomic-ness of this code important? If not, it should use __test_bit() and __test_and_set_bit() because locking is being handled somewhere higher up. Furthermore, why are we using a per-reset bitmap to set one bit? Either combine them into one bitmap or have a simple bool please. > + pm_runtime_get_sync(rcdev->dev); > + > + spin_lock_irqsave(&drvdata->lock, flags); > + > + reg = readl(reg_addr); > + if (assert) > + writel(reg & ~(mask << shift), reg_addr); > + else > + writel(reg | (mask << shift), reg_addr); > + > + spin_unlock_irqrestore(&drvdata->lock, flags); > + > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_put(rcdev->dev); > + Same comment here. > + return 0; > +} > + > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, true); > +} > + > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, false); > +} > + > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > + .assert = imx_blk_ctl_reset_assert, > + .deassert = imx_blk_ctl_reset_deassert, > +}; > + > +static int imx_blk_ctl_register_reset_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + int max = dev_data->resets_max; > + struct imx_reset_hw *hws; > + int i; > + > + spin_lock_init(&drvdata->lock); > + > + drvdata->rcdev.owner = THIS_MODULE; > + drvdata->rcdev.nr_resets = max; > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > + drvdata->rcdev.of_node = dev->of_node; > + drvdata->rcdev.dev = dev; > + > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > + GFP_KERNEL); > + hws = drvdata->rst_hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type != BLK_CTL_RESET) > + continue; > + > + hws[hw->id].offset = hw->offset; > + hws[hw->id].shift = hw->shift; > + hws[hw->id].mask = hw->mask; > + } > + > + return devm_reset_controller_register(dev, &drvdata->rcdev); > +} Nitpick: Add a newline here please > +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > + struct imx_blk_ctl_hw *hw) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + void __iomem *base = drvdata->base; > + struct clk_hw *clk_hw = NULL; Is this necessary? Please add a default to the case if so and drop this assignment. But if all hw->type are covered in the case statement then this assignment can be dropped and nothing else. The compiler should tell us we forgot to handle a case. > + > + switch (hw->type) { > + case BLK_CTL_CLK_MUX: > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > + base + hw->offset, > + hw->shift, hw->width, > + hw->parents, > + hw->parents_count, > + hw->flags); > + break; > + case BLK_CTL_CLK_GATE: > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > + base + hw->offset, hw->shift); > + break; > + case BLK_CTL_CLK_SHARED_GATE: > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > + hw->parents, > + base + hw->offset, > + hw->shift, > + hw->shared_count); > + break; > + case BLK_CTL_CLK_PLL14XX: > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > + base + hw->offset, hw->pll_tbl); > + break; > + }; > + > + return clk_hw; > +} > + > +static int imx_blk_ctl_register_clock_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct clk_hw_onecell_data *clk_hw_data; > + struct clk_hw **hws; > + int i; > + > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > + dev_data->hws_num), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) We can drop the WARN_ON() call, slab allocations already print a stacktrace. > + return -ENOMEM; > + > + clk_hw_data->num = dev_data->clocks_max; > + hws = clk_hw_data->hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + Add a comment like /* Resets aren't a clk */ > + if (hw->type == BLK_CTL_RESET) > + continue; > + > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > + } > + > + imx_check_clk_hws(hws, dev_data->clocks_max); > + > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > + clk_hw_data); > +} > + > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > + > + if (!dev_data->pm_runtime_saved_regs_num) > + return 0; > + > + pm_info->regs_values = devm_kzalloc(dev, > + sizeof(u32) * regs_num, > + GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_values))) Please drop WARN_ON > + return PTR_ERR(pm_info->regs_values); > + > + pm_info->regs_offsets = kmemdup(regs_offsets, > + regs_num * sizeof(u32), GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) Please drop WARN_ON > + return PTR_ERR(pm_info->regs_offsets); > + > + pm_info->regs_num = regs_num; > + > + return 0; > +} > + > +int imx_blk_ctl_register(struct platform_device *pdev) > +{ > + struct imx_blk_ctl_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (WARN_ON(!drvdata)) Please drop WARN_ON > + return -ENOMEM; > + > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(drvdata->base))) Please drop WARN_ON > + return PTR_ERR(drvdata->base); > + > + dev_set_drvdata(dev, drvdata); > + > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > + if (ret) > + return ret; > + > + pm_runtime_get_noresume(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + ret = imx_blk_ctl_register_clock_controller(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + > + ret = imx_blk_ctl_register_reset_controller(dev); > + > + pm_runtime_put(dev); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h > new file mode 100644 > index 00000000..3f14a47 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > +#define __MACH_IMX_CLK_BLK_CTL_H > + > +enum imx_blk_ctl_hw_type { > + BLK_CTL_CLK_MUX, > + BLK_CTL_CLK_GATE, > + BLK_CTL_CLK_SHARED_GATE, > + BLK_CTL_CLK_PLL14XX, > + BLK_CTL_RESET, > +}; > + > +struct imx_blk_ctl_hw { > + int type; > + char *name; > + u32 offset; > + u32 shift; > + u32 mask; > + u32 width; > + u32 flags; > + u32 id; > + const void *parents; > + u32 parents_count; > + int *shared_count; > + const struct imx_pll14xx_clk *pll_tbl; Please forward declare pointer types. > +}; > + > +struct imx_blk_ctl_dev_data { > + struct imx_blk_ctl_hw *hws; Please forward declare pointer types. > + u32 hws_num; > + > + u32 clocks_max; > + u32 resets_max; > + > + u32 pm_runtime_saved_regs_num; > + u32 pm_runtime_saved_regs[]; > +}; > + > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > + { \ > + .type = _type, \ > + .name = _name, \ > + .id = _id, \ > + .offset = _offset, \ > + .shift = _shift, \ > + .width = _width, \ > + .mask = _mask, \ > + .parents = _parents, \ > + .parents_count = _parents_count, \ > + .flags = _flags, \ > + .shared_count = sh_count, \ > + .pll_tbl = _pll_tbl, \ > + } > + > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) > + > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) > + > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) > + > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > + > +int imx_blk_ctl_register(struct platform_device *pdev); Please forward declare pointer types. > + > +#endif > -- > 2.7.4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2020-11-03 11:18 ` Abel Vesa @ 2020-11-09 5:45 ` Jacky Bai -1 siblings, 0 replies; 72+ messages in thread From: Jacky Bai @ 2020-11-09 5:45 UTC (permalink / raw) To: Abel Vesa, Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Peng Fan, Aisheng Dong Cc: dl-linux-imx, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa > -----Original Message----- > From: Abel Vesa [mailto:abel.vesa@nxp.com] > Sent: Tuesday, November 3, 2020 7:18 PM > To: Mike Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; Adam Ford <aford173@gmail.com>; Marek Vasut > <marek.vasut@gmail.com>; Lucas Stach <l.stach@pengutronix.de>; Rob > Herring <robh@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha > Hauer <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; > Anson Huang <anson.huang@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Peng > Fan <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com> > Cc: dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.org; > Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; Abel Vesa > <abel.vesa@nxp.com> > Subject: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver > > The i.MX8MP platform introduces a new type of IP which is called BLK_CTL in > RM and usually is comprised of some GPRs that are considered too generic to > be part of any dedicated IP from that specific subsystem. > > In general, some of the GPRs have some clock bits, some have reset bits, so in > order to be able to use the imx clock API, this needs to be in a clock driver. > From there it can use the reset controller API and leave the rest to the syscon. > From the test I did internally, this blk ctrl implementation will have system deadlock risk due to the clock prepare mutex. Please make sure it can works without deadlock. BR Jacky Bai > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/Makefile | 2 +- > drivers/clk/imx/clk-blk-ctl.c | 302 > ++++++++++++++++++++++++++++++++++++++++++ > drivers/clk/imx/clk-blk-ctl.h | 80 +++++++++++ > 3 files changed, 383 insertions(+), 1 deletion(-) create mode 100644 > drivers/clk/imx/clk-blk-ctl.c create mode 100644 > drivers/clk/imx/clk-blk-ctl.h > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index > dd6a737..3d6d9cb 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o > > obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o > obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o > -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o > +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o > obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o > > obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git > a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c new file mode > 100644 index 00000000..9ac0ed0 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.c > @@ -0,0 +1,302 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright 2020 NXP. > + */ > + > +#include <linux/clk.h> > +#include <linux/reset-controller.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/slab.h> > +#include <linux/string.h> > +#include <linux/types.h> > + > +#include "clk.h" > +#include "clk-blk-ctl.h" > + > +struct imx_reset_hw { > + u32 offset; > + u32 shift; > + u32 mask; > + unsigned long asserted; > +}; > + > +struct imx_pm_safekeep_info { > + uint32_t *regs_values; > + uint32_t *regs_offsets; > + uint32_t regs_num; > +}; > + > +struct imx_blk_ctl_drvdata { > + void __iomem *base; > + struct reset_controller_dev rcdev; > + struct imx_reset_hw *rst_hws; > + struct imx_pm_safekeep_info pm_info; > + > + spinlock_t lock; > +}; > + > +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, > + bool write) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + void __iomem *base = drvdata->base; > + int i; > + > + if (!pm_info->regs_num) > + return; > + > + for (i = 0; i < pm_info->regs_num; i++) { > + u32 offset = pm_info->regs_offsets[i]; > + > + if (write) > + writel(pm_info->regs_values[i], base + offset); > + else > + pm_info->regs_values[i] = readl(base + offset); > + } > + > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device > +*dev) { > + imx_blk_ctl_read_write(dev, false); > + > + return 0; > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device > +*dev) { > + imx_blk_ctl_read_write(dev, true); > + > + return 0; > +} > + > +const struct dev_pm_ops imx_blk_ctl_pm_ops = { > + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, > + imx_blk_ctl_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, > + pm_runtime_force_resume) > +}; > +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); > + > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > + struct imx_blk_ctl_drvdata, rcdev); > + unsigned int offset = drvdata->rst_hws[id].offset; > + unsigned int shift = drvdata->rst_hws[id].shift; > + unsigned int mask = drvdata->rst_hws[id].mask; > + void __iomem *reg_addr = drvdata->base + offset; > + unsigned long flags; > + u32 reg; > + > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > + return -ENODEV; > + > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_get_sync(rcdev->dev); > + > + spin_lock_irqsave(&drvdata->lock, flags); > + > + reg = readl(reg_addr); > + if (assert) > + writel(reg & ~(mask << shift), reg_addr); > + else > + writel(reg | (mask << shift), reg_addr); > + > + spin_unlock_irqrestore(&drvdata->lock, flags); > + > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_put(rcdev->dev); > + > + return 0; > +} > + > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, true); } > + > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, false); } > + > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > + .assert = imx_blk_ctl_reset_assert, > + .deassert = imx_blk_ctl_reset_deassert, > +}; > + > +static int imx_blk_ctl_register_reset_controller(struct device *dev) { > + const struct imx_blk_ctl_dev_data *dev_data = > of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + int max = dev_data->resets_max; > + struct imx_reset_hw *hws; > + int i; > + > + spin_lock_init(&drvdata->lock); > + > + drvdata->rcdev.owner = THIS_MODULE; > + drvdata->rcdev.nr_resets = max; > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > + drvdata->rcdev.of_node = dev->of_node; > + drvdata->rcdev.dev = dev; > + > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > + GFP_KERNEL); > + hws = drvdata->rst_hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type != BLK_CTL_RESET) > + continue; > + > + hws[hw->id].offset = hw->offset; > + hws[hw->id].shift = hw->shift; > + hws[hw->id].mask = hw->mask; > + } > + > + return devm_reset_controller_register(dev, &drvdata->rcdev); } static > +struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > + struct imx_blk_ctl_hw *hw) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + void __iomem *base = drvdata->base; > + struct clk_hw *clk_hw = NULL; > + > + switch (hw->type) { > + case BLK_CTL_CLK_MUX: > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > + base + hw->offset, > + hw->shift, hw->width, > + hw->parents, > + hw->parents_count, > + hw->flags); > + break; > + case BLK_CTL_CLK_GATE: > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > + base + hw->offset, hw->shift); > + break; > + case BLK_CTL_CLK_SHARED_GATE: > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > + hw->parents, > + base + hw->offset, > + hw->shift, > + hw->shared_count); > + break; > + case BLK_CTL_CLK_PLL14XX: > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > + base + hw->offset, hw->pll_tbl); > + break; > + }; > + > + return clk_hw; > +} > + > +static int imx_blk_ctl_register_clock_controller(struct device *dev) { > + const struct imx_blk_ctl_dev_data *dev_data = > of_device_get_match_data(dev); > + struct clk_hw_onecell_data *clk_hw_data; > + struct clk_hw **hws; > + int i; > + > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > + dev_data->hws_num), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) > + return -ENOMEM; > + > + clk_hw_data->num = dev_data->clocks_max; > + hws = clk_hw_data->hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type == BLK_CTL_RESET) > + continue; > + > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > + } > + > + imx_check_clk_hws(hws, dev_data->clocks_max); > + > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > + clk_hw_data); > +} > + > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = > of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > + > + if (!dev_data->pm_runtime_saved_regs_num) > + return 0; > + > + pm_info->regs_values = devm_kzalloc(dev, > + sizeof(u32) * regs_num, > + GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_values))) > + return PTR_ERR(pm_info->regs_values); > + > + pm_info->regs_offsets = kmemdup(regs_offsets, > + regs_num * sizeof(u32), GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) > + return PTR_ERR(pm_info->regs_offsets); > + > + pm_info->regs_num = regs_num; > + > + return 0; > +} > + > +int imx_blk_ctl_register(struct platform_device *pdev) { > + struct imx_blk_ctl_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (WARN_ON(!drvdata)) > + return -ENOMEM; > + > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(drvdata->base))) > + return PTR_ERR(drvdata->base); > + > + dev_set_drvdata(dev, drvdata); > + > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > + if (ret) > + return ret; > + > + pm_runtime_get_noresume(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + ret = imx_blk_ctl_register_clock_controller(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + > + ret = imx_blk_ctl_register_reset_controller(dev); > + > + pm_runtime_put(dev); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h new file > mode 100644 index 00000000..3f14a47 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > +#define __MACH_IMX_CLK_BLK_CTL_H > + > +enum imx_blk_ctl_hw_type { > + BLK_CTL_CLK_MUX, > + BLK_CTL_CLK_GATE, > + BLK_CTL_CLK_SHARED_GATE, > + BLK_CTL_CLK_PLL14XX, > + BLK_CTL_RESET, > +}; > + > +struct imx_blk_ctl_hw { > + int type; > + char *name; > + u32 offset; > + u32 shift; > + u32 mask; > + u32 width; > + u32 flags; > + u32 id; > + const void *parents; > + u32 parents_count; > + int *shared_count; > + const struct imx_pll14xx_clk *pll_tbl; }; > + > +struct imx_blk_ctl_dev_data { > + struct imx_blk_ctl_hw *hws; > + u32 hws_num; > + > + u32 clocks_max; > + u32 resets_max; > + > + u32 pm_runtime_saved_regs_num; > + u32 pm_runtime_saved_regs[]; > +}; > + > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, > _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > + { \ > + .type = _type, \ > + .name = _name, \ > + .id = _id, \ > + .offset = _offset, \ > + .shift = _shift, \ > + .width = _width, \ > + .mask = _mask, \ > + .parents = _parents, \ > + .parents_count = _parents_count, \ > + .flags = _flags, \ > + .shared_count = sh_count, \ > + .pll_tbl = _pll_tbl, \ > + } > + > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, > _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, > +_parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, > _parents, _flags) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, > +_parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, > +_parents, 1, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, > _parents, sh_count) \ > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, > 1, > +0, _parents, 1, 0, sh_count, NULL) > + > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) > \ > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, > +_parents, 1, 0, NULL, _pll_tbl) > + > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, > +0, NULL, NULL) > + > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, > +0, 0, NULL, NULL) > + > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > + > +int imx_blk_ctl_register(struct platform_device *pdev); > + > +#endif > -- > 2.7.4 ^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2020-11-09 5:45 ` Jacky Bai 0 siblings, 0 replies; 72+ messages in thread From: Jacky Bai @ 2020-11-09 5:45 UTC (permalink / raw) To: Abel Vesa, Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Peng Fan, Aisheng Dong Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, dl-linux-imx, linux-clk, linux-arm-kernel > -----Original Message----- > From: Abel Vesa [mailto:abel.vesa@nxp.com] > Sent: Tuesday, November 3, 2020 7:18 PM > To: Mike Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; Adam Ford <aford173@gmail.com>; Marek Vasut > <marek.vasut@gmail.com>; Lucas Stach <l.stach@pengutronix.de>; Rob > Herring <robh@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha > Hauer <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; > Anson Huang <anson.huang@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Peng > Fan <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com> > Cc: dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.org; > Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; > linux-clk@vger.kernel.org; devicetree@vger.kernel.org; Abel Vesa > <abel.vesa@nxp.com> > Subject: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver > > The i.MX8MP platform introduces a new type of IP which is called BLK_CTL in > RM and usually is comprised of some GPRs that are considered too generic to > be part of any dedicated IP from that specific subsystem. > > In general, some of the GPRs have some clock bits, some have reset bits, so in > order to be able to use the imx clock API, this needs to be in a clock driver. > From there it can use the reset controller API and leave the rest to the syscon. > From the test I did internally, this blk ctrl implementation will have system deadlock risk due to the clock prepare mutex. Please make sure it can works without deadlock. BR Jacky Bai > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/Makefile | 2 +- > drivers/clk/imx/clk-blk-ctl.c | 302 > ++++++++++++++++++++++++++++++++++++++++++ > drivers/clk/imx/clk-blk-ctl.h | 80 +++++++++++ > 3 files changed, 383 insertions(+), 1 deletion(-) create mode 100644 > drivers/clk/imx/clk-blk-ctl.c create mode 100644 > drivers/clk/imx/clk-blk-ctl.h > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index > dd6a737..3d6d9cb 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o > > obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o > obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o > -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o > +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o > obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o > > obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git > a/drivers/clk/imx/clk-blk-ctl.c b/drivers/clk/imx/clk-blk-ctl.c new file mode > 100644 index 00000000..9ac0ed0 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.c > @@ -0,0 +1,302 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright 2020 NXP. > + */ > + > +#include <linux/clk.h> > +#include <linux/reset-controller.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/slab.h> > +#include <linux/string.h> > +#include <linux/types.h> > + > +#include "clk.h" > +#include "clk-blk-ctl.h" > + > +struct imx_reset_hw { > + u32 offset; > + u32 shift; > + u32 mask; > + unsigned long asserted; > +}; > + > +struct imx_pm_safekeep_info { > + uint32_t *regs_values; > + uint32_t *regs_offsets; > + uint32_t regs_num; > +}; > + > +struct imx_blk_ctl_drvdata { > + void __iomem *base; > + struct reset_controller_dev rcdev; > + struct imx_reset_hw *rst_hws; > + struct imx_pm_safekeep_info pm_info; > + > + spinlock_t lock; > +}; > + > +static void __maybe_unused imx_blk_ctl_read_write(struct device *dev, > + bool write) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + void __iomem *base = drvdata->base; > + int i; > + > + if (!pm_info->regs_num) > + return; > + > + for (i = 0; i < pm_info->regs_num; i++) { > + u32 offset = pm_info->regs_offsets[i]; > + > + if (write) > + writel(pm_info->regs_values[i], base + offset); > + else > + pm_info->regs_values[i] = readl(base + offset); > + } > + > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_suspend(struct device > +*dev) { > + imx_blk_ctl_read_write(dev, false); > + > + return 0; > +} > + > +static int __maybe_unused imx_blk_ctl_runtime_resume(struct device > +*dev) { > + imx_blk_ctl_read_write(dev, true); > + > + return 0; > +} > + > +const struct dev_pm_ops imx_blk_ctl_pm_ops = { > + SET_RUNTIME_PM_OPS(imx_blk_ctl_runtime_suspend, > + imx_blk_ctl_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, > + pm_runtime_force_resume) > +}; > +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); > + > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > + struct imx_blk_ctl_drvdata, rcdev); > + unsigned int offset = drvdata->rst_hws[id].offset; > + unsigned int shift = drvdata->rst_hws[id].shift; > + unsigned int mask = drvdata->rst_hws[id].mask; > + void __iomem *reg_addr = drvdata->base + offset; > + unsigned long flags; > + u32 reg; > + > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > + return -ENODEV; > + > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_get_sync(rcdev->dev); > + > + spin_lock_irqsave(&drvdata->lock, flags); > + > + reg = readl(reg_addr); > + if (assert) > + writel(reg & ~(mask << shift), reg_addr); > + else > + writel(reg | (mask << shift), reg_addr); > + > + spin_unlock_irqrestore(&drvdata->lock, flags); > + > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_put(rcdev->dev); > + > + return 0; > +} > + > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, true); } > + > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, false); } > + > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > + .assert = imx_blk_ctl_reset_assert, > + .deassert = imx_blk_ctl_reset_deassert, > +}; > + > +static int imx_blk_ctl_register_reset_controller(struct device *dev) { > + const struct imx_blk_ctl_dev_data *dev_data = > of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + int max = dev_data->resets_max; > + struct imx_reset_hw *hws; > + int i; > + > + spin_lock_init(&drvdata->lock); > + > + drvdata->rcdev.owner = THIS_MODULE; > + drvdata->rcdev.nr_resets = max; > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > + drvdata->rcdev.of_node = dev->of_node; > + drvdata->rcdev.dev = dev; > + > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > + GFP_KERNEL); > + hws = drvdata->rst_hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type != BLK_CTL_RESET) > + continue; > + > + hws[hw->id].offset = hw->offset; > + hws[hw->id].shift = hw->shift; > + hws[hw->id].mask = hw->mask; > + } > + > + return devm_reset_controller_register(dev, &drvdata->rcdev); } static > +struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > + struct imx_blk_ctl_hw *hw) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + void __iomem *base = drvdata->base; > + struct clk_hw *clk_hw = NULL; > + > + switch (hw->type) { > + case BLK_CTL_CLK_MUX: > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > + base + hw->offset, > + hw->shift, hw->width, > + hw->parents, > + hw->parents_count, > + hw->flags); > + break; > + case BLK_CTL_CLK_GATE: > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > + base + hw->offset, hw->shift); > + break; > + case BLK_CTL_CLK_SHARED_GATE: > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > + hw->parents, > + base + hw->offset, > + hw->shift, > + hw->shared_count); > + break; > + case BLK_CTL_CLK_PLL14XX: > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > + base + hw->offset, hw->pll_tbl); > + break; > + }; > + > + return clk_hw; > +} > + > +static int imx_blk_ctl_register_clock_controller(struct device *dev) { > + const struct imx_blk_ctl_dev_data *dev_data = > of_device_get_match_data(dev); > + struct clk_hw_onecell_data *clk_hw_data; > + struct clk_hw **hws; > + int i; > + > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > + dev_data->hws_num), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) > + return -ENOMEM; > + > + clk_hw_data->num = dev_data->clocks_max; > + hws = clk_hw_data->hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type == BLK_CTL_RESET) > + continue; > + > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > + } > + > + imx_check_clk_hws(hws, dev_data->clocks_max); > + > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > + clk_hw_data); > +} > + > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = > of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > + > + if (!dev_data->pm_runtime_saved_regs_num) > + return 0; > + > + pm_info->regs_values = devm_kzalloc(dev, > + sizeof(u32) * regs_num, > + GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_values))) > + return PTR_ERR(pm_info->regs_values); > + > + pm_info->regs_offsets = kmemdup(regs_offsets, > + regs_num * sizeof(u32), GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) > + return PTR_ERR(pm_info->regs_offsets); > + > + pm_info->regs_num = regs_num; > + > + return 0; > +} > + > +int imx_blk_ctl_register(struct platform_device *pdev) { > + struct imx_blk_ctl_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (WARN_ON(!drvdata)) > + return -ENOMEM; > + > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(drvdata->base))) > + return PTR_ERR(drvdata->base); > + > + dev_set_drvdata(dev, drvdata); > + > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > + if (ret) > + return ret; > + > + pm_runtime_get_noresume(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + ret = imx_blk_ctl_register_clock_controller(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + > + ret = imx_blk_ctl_register_reset_controller(dev); > + > + pm_runtime_put(dev); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h new file > mode 100644 index 00000000..3f14a47 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > +#define __MACH_IMX_CLK_BLK_CTL_H > + > +enum imx_blk_ctl_hw_type { > + BLK_CTL_CLK_MUX, > + BLK_CTL_CLK_GATE, > + BLK_CTL_CLK_SHARED_GATE, > + BLK_CTL_CLK_PLL14XX, > + BLK_CTL_RESET, > +}; > + > +struct imx_blk_ctl_hw { > + int type; > + char *name; > + u32 offset; > + u32 shift; > + u32 mask; > + u32 width; > + u32 flags; > + u32 id; > + const void *parents; > + u32 parents_count; > + int *shared_count; > + const struct imx_pll14xx_clk *pll_tbl; }; > + > +struct imx_blk_ctl_dev_data { > + struct imx_blk_ctl_hw *hws; > + u32 hws_num; > + > + u32 clocks_max; > + u32 resets_max; > + > + u32 pm_runtime_saved_regs_num; > + u32 pm_runtime_saved_regs[]; > +}; > + > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, > _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > + { \ > + .type = _type, \ > + .name = _name, \ > + .id = _id, \ > + .offset = _offset, \ > + .shift = _shift, \ > + .width = _width, \ > + .mask = _mask, \ > + .parents = _parents, \ > + .parents_count = _parents_count, \ > + .flags = _flags, \ > + .shared_count = sh_count, \ > + .pll_tbl = _pll_tbl, \ > + } > + > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, > _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, > +_parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, > _parents, _flags) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, > +_parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, > +_parents, 1, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, > _parents, sh_count) \ > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, > 1, > +0, _parents, 1, 0, sh_count, NULL) > + > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) > \ > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, > +_parents, 1, 0, NULL, _pll_tbl) > + > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, > +0, NULL, NULL) > + > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, > +0, 0, NULL, NULL) > + > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > + > +int imx_blk_ctl_register(struct platform_device *pdev); > + > +#endif > -- > 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2020-11-03 11:18 ` Abel Vesa @ 2020-11-11 9:13 ` Dong Aisheng -1 siblings, 0 replies; 72+ messages in thread From: Dong Aisheng @ 2020-11-11 9:13 UTC (permalink / raw) To: Abel Vesa Cc: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, NXP Linux Team, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Linux Kernel Mailing List, linux-clk, devicetree, Philipp Zabel On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: ... > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > + struct imx_blk_ctl_drvdata, rcdev); > + unsigned int offset = drvdata->rst_hws[id].offset; > + unsigned int shift = drvdata->rst_hws[id].shift; > + unsigned int mask = drvdata->rst_hws[id].mask; > + void __iomem *reg_addr = drvdata->base + offset; > + unsigned long flags; > + u32 reg; > + > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > + return -ENODEV; What if consumers call deassert first in probe which seems common in kernel? It seems will fail. e.g. probe() { reset_control_get() reset_control_deassert() } Regards Aisheng > + > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_get_sync(rcdev->dev) > + > + spin_lock_irqsave(&drvdata->lock, flags); > + > + reg = readl(reg_addr); > + if (assert) > + writel(reg & ~(mask << shift), reg_addr); > + else > + writel(reg | (mask << shift), reg_addr); > + > + spin_unlock_irqrestore(&drvdata->lock, flags); > + > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_put(rcdev->dev) > + > + return 0; > +} > + > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, true); > +} > + > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, false); > +} > + > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > + .assert = imx_blk_ctl_reset_assert, > + .deassert = imx_blk_ctl_reset_deassert, > +}; > + > +static int imx_blk_ctl_register_reset_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + int max = dev_data->resets_max; > + struct imx_reset_hw *hws; > + int i; > + > + spin_lock_init(&drvdata->lock); > + > + drvdata->rcdev.owner = THIS_MODULE; > + drvdata->rcdev.nr_resets = max; > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > + drvdata->rcdev.of_node = dev->of_node; > + drvdata->rcdev.dev = dev; > + > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > + GFP_KERNEL); > + hws = drvdata->rst_hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type != BLK_CTL_RESET) > + continue; > + > + hws[hw->id].offset = hw->offset; > + hws[hw->id].shift = hw->shift; > + hws[hw->id].mask = hw->mask; > + } > + > + return devm_reset_controller_register(dev, &drvdata->rcdev); > +} > +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > + struct imx_blk_ctl_hw *hw) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + void __iomem *base = drvdata->base; > + struct clk_hw *clk_hw = NULL; > + > + switch (hw->type) { > + case BLK_CTL_CLK_MUX: > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > + base + hw->offset, > + hw->shift, hw->width, > + hw->parents, > + hw->parents_count, > + hw->flags); > + break; > + case BLK_CTL_CLK_GATE: > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > + base + hw->offset, hw->shift); > + break; > + case BLK_CTL_CLK_SHARED_GATE: > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > + hw->parents, > + base + hw->offset, > + hw->shift, > + hw->shared_count); > + break; > + case BLK_CTL_CLK_PLL14XX: > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > + base + hw->offset, hw->pll_tbl); > + break; > + }; > + > + return clk_hw; > +} > + > +static int imx_blk_ctl_register_clock_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct clk_hw_onecell_data *clk_hw_data; > + struct clk_hw **hws; > + int i; > + > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > + dev_data->hws_num), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) > + return -ENOMEM; > + > + clk_hw_data->num = dev_data->clocks_max; > + hws = clk_hw_data->hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type == BLK_CTL_RESET) > + continue; > + > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > + } > + > + imx_check_clk_hws(hws, dev_data->clocks_max); > + > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > + clk_hw_data); > +} > + > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > + > + if (!dev_data->pm_runtime_saved_regs_num) > + return 0; > + > + pm_info->regs_values = devm_kzalloc(dev, > + sizeof(u32) * regs_num, > + GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_values))) > + return PTR_ERR(pm_info->regs_values); > + > + pm_info->regs_offsets = kmemdup(regs_offsets, > + regs_num * sizeof(u32), GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) > + return PTR_ERR(pm_info->regs_offsets); > + > + pm_info->regs_num = regs_num; > + > + return 0; > +} > + > +int imx_blk_ctl_register(struct platform_device *pdev) > +{ > + struct imx_blk_ctl_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (WARN_ON(!drvdata)) > + return -ENOMEM; > + > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(drvdata->base))) > + return PTR_ERR(drvdata->base); > + > + dev_set_drvdata(dev, drvdata); > + > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > + if (ret) > + return ret; > + > + pm_runtime_get_noresume(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + ret = imx_blk_ctl_register_clock_controller(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + > + ret = imx_blk_ctl_register_reset_controller(dev); > + > + pm_runtime_put(dev); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h > new file mode 100644 > index 00000000..3f14a47 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > +#define __MACH_IMX_CLK_BLK_CTL_H > + > +enum imx_blk_ctl_hw_type { > + BLK_CTL_CLK_MUX, > + BLK_CTL_CLK_GATE, > + BLK_CTL_CLK_SHARED_GATE, > + BLK_CTL_CLK_PLL14XX, > + BLK_CTL_RESET, > +}; > + > +struct imx_blk_ctl_hw { > + int type; > + char *name; > + u32 offset; > + u32 shift; > + u32 mask; > + u32 width; > + u32 flags; > + u32 id; > + const void *parents; > + u32 parents_count; > + int *shared_count; > + const struct imx_pll14xx_clk *pll_tbl; > +}; > + > +struct imx_blk_ctl_dev_data { > + struct imx_blk_ctl_hw *hws; > + u32 hws_num; > + > + u32 clocks_max; > + u32 resets_max; > + > + u32 pm_runtime_saved_regs_num; > + u32 pm_runtime_saved_regs[]; > +}; > + > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > + { \ > + .type = _type, \ > + .name = _name, \ > + .id = _id, \ > + .offset = _offset, \ > + .shift = _shift, \ > + .width = _width, \ > + .mask = _mask, \ > + .parents = _parents, \ > + .parents_count = _parents_count, \ > + .flags = _flags, \ > + .shared_count = sh_count, \ > + .pll_tbl = _pll_tbl, \ > + } > + > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) > + > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) > + > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) > + > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > + > +int imx_blk_ctl_register(struct platform_device *pdev); > + > +#endif > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2020-11-11 9:13 ` Dong Aisheng 0 siblings, 0 replies; 72+ messages in thread From: Dong Aisheng @ 2020-11-11 9:13 UTC (permalink / raw) To: Abel Vesa Cc: Dong Aisheng, Rob Herring, Peng Fan, Jacky Bai, Anson Huang, devicetree, Stephen Boyd, Shawn Guo, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, NXP Linux Team, Sascha Hauer, Fabio Estevam, Philipp Zabel, Adam Ford, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: ... > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > + unsigned long id, bool assert) > +{ > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > + struct imx_blk_ctl_drvdata, rcdev); > + unsigned int offset = drvdata->rst_hws[id].offset; > + unsigned int shift = drvdata->rst_hws[id].shift; > + unsigned int mask = drvdata->rst_hws[id].mask; > + void __iomem *reg_addr = drvdata->base + offset; > + unsigned long flags; > + u32 reg; > + > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > + return -ENODEV; What if consumers call deassert first in probe which seems common in kernel? It seems will fail. e.g. probe() { reset_control_get() reset_control_deassert() } Regards Aisheng > + > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_get_sync(rcdev->dev) > + > + spin_lock_irqsave(&drvdata->lock, flags); > + > + reg = readl(reg_addr); > + if (assert) > + writel(reg & ~(mask << shift), reg_addr); > + else > + writel(reg | (mask << shift), reg_addr); > + > + spin_unlock_irqrestore(&drvdata->lock, flags); > + > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > + pm_runtime_put(rcdev->dev) > + > + return 0; > +} > + > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, true); > +} > + > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + return imx_blk_ctl_reset_set(rcdev, id, false); > +} > + > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > + .assert = imx_blk_ctl_reset_assert, > + .deassert = imx_blk_ctl_reset_deassert, > +}; > + > +static int imx_blk_ctl_register_reset_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + int max = dev_data->resets_max; > + struct imx_reset_hw *hws; > + int i; > + > + spin_lock_init(&drvdata->lock); > + > + drvdata->rcdev.owner = THIS_MODULE; > + drvdata->rcdev.nr_resets = max; > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > + drvdata->rcdev.of_node = dev->of_node; > + drvdata->rcdev.dev = dev; > + > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > + GFP_KERNEL); > + hws = drvdata->rst_hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type != BLK_CTL_RESET) > + continue; > + > + hws[hw->id].offset = hw->offset; > + hws[hw->id].shift = hw->shift; > + hws[hw->id].mask = hw->mask; > + } > + > + return devm_reset_controller_register(dev, &drvdata->rcdev); > +} > +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > + struct imx_blk_ctl_hw *hw) > +{ > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + void __iomem *base = drvdata->base; > + struct clk_hw *clk_hw = NULL; > + > + switch (hw->type) { > + case BLK_CTL_CLK_MUX: > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > + base + hw->offset, > + hw->shift, hw->width, > + hw->parents, > + hw->parents_count, > + hw->flags); > + break; > + case BLK_CTL_CLK_GATE: > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > + base + hw->offset, hw->shift); > + break; > + case BLK_CTL_CLK_SHARED_GATE: > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > + hw->parents, > + base + hw->offset, > + hw->shift, > + hw->shared_count); > + break; > + case BLK_CTL_CLK_PLL14XX: > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > + base + hw->offset, hw->pll_tbl); > + break; > + }; > + > + return clk_hw; > +} > + > +static int imx_blk_ctl_register_clock_controller(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct clk_hw_onecell_data *clk_hw_data; > + struct clk_hw **hws; > + int i; > + > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > + dev_data->hws_num), GFP_KERNEL); > + if (WARN_ON(!clk_hw_data)) > + return -ENOMEM; > + > + clk_hw_data->num = dev_data->clocks_max; > + hws = clk_hw_data->hws; > + > + for (i = 0; i < dev_data->hws_num; i++) { > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > + > + if (hw->type == BLK_CTL_RESET) > + continue; > + > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > + } > + > + imx_check_clk_hws(hws, dev_data->clocks_max); > + > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > + clk_hw_data); > +} > + > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > +{ > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > + > + if (!dev_data->pm_runtime_saved_regs_num) > + return 0; > + > + pm_info->regs_values = devm_kzalloc(dev, > + sizeof(u32) * regs_num, > + GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_values))) > + return PTR_ERR(pm_info->regs_values); > + > + pm_info->regs_offsets = kmemdup(regs_offsets, > + regs_num * sizeof(u32), GFP_KERNEL); > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) > + return PTR_ERR(pm_info->regs_offsets); > + > + pm_info->regs_num = regs_num; > + > + return 0; > +} > + > +int imx_blk_ctl_register(struct platform_device *pdev) > +{ > + struct imx_blk_ctl_drvdata *drvdata; > + struct device *dev = &pdev->dev; > + int ret; > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (WARN_ON(!drvdata)) > + return -ENOMEM; > + > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > + if (WARN_ON(IS_ERR(drvdata->base))) > + return PTR_ERR(drvdata->base); > + > + dev_set_drvdata(dev, drvdata); > + > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > + if (ret) > + return ret; > + > + pm_runtime_get_noresume(dev); > + pm_runtime_set_active(dev); > + pm_runtime_enable(dev); > + > + ret = imx_blk_ctl_register_clock_controller(dev); > + if (ret) { > + pm_runtime_put(dev); > + return ret; > + } > + > + ret = imx_blk_ctl_register_reset_controller(dev); > + > + pm_runtime_put(dev); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h > new file mode 100644 > index 00000000..3f14a47 > --- /dev/null > +++ b/drivers/clk/imx/clk-blk-ctl.h > @@ -0,0 +1,80 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > +#define __MACH_IMX_CLK_BLK_CTL_H > + > +enum imx_blk_ctl_hw_type { > + BLK_CTL_CLK_MUX, > + BLK_CTL_CLK_GATE, > + BLK_CTL_CLK_SHARED_GATE, > + BLK_CTL_CLK_PLL14XX, > + BLK_CTL_RESET, > +}; > + > +struct imx_blk_ctl_hw { > + int type; > + char *name; > + u32 offset; > + u32 shift; > + u32 mask; > + u32 width; > + u32 flags; > + u32 id; > + const void *parents; > + u32 parents_count; > + int *shared_count; > + const struct imx_pll14xx_clk *pll_tbl; > +}; > + > +struct imx_blk_ctl_dev_data { > + struct imx_blk_ctl_hw *hws; > + u32 hws_num; > + > + u32 clocks_max; > + u32 resets_max; > + > + u32 pm_runtime_saved_regs_num; > + u32 pm_runtime_saved_regs[]; > +}; > + > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > + { \ > + .type = _type, \ > + .name = _name, \ > + .id = _id, \ > + .offset = _offset, \ > + .shift = _shift, \ > + .width = _width, \ > + .mask = _mask, \ > + .parents = _parents, \ > + .parents_count = _parents_count, \ > + .flags = _flags, \ > + .shared_count = sh_count, \ > + .pll_tbl = _pll_tbl, \ > + } > + > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) > + > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) > + > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) > + > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) > + > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > + > +int imx_blk_ctl_register(struct platform_device *pdev); > + > +#endif > -- > 2.7.4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2020-11-11 9:13 ` Dong Aisheng @ 2020-11-17 14:48 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-17 14:48 UTC (permalink / raw) To: Dong Aisheng Cc: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, NXP Linux Team, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Linux Kernel Mailing List, linux-clk, devicetree, Philipp Zabel On 20-11-11 17:13:25, Dong Aisheng wrote: > On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: > ... > > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > > + unsigned long id, bool assert) > > +{ > > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > > + struct imx_blk_ctl_drvdata, rcdev); > > + unsigned int offset = drvdata->rst_hws[id].offset; > > + unsigned int shift = drvdata->rst_hws[id].shift; > > + unsigned int mask = drvdata->rst_hws[id].mask; > > + void __iomem *reg_addr = drvdata->base + offset; > > + unsigned long flags; > > + u32 reg; > > + > > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > > + return -ENODEV; > > What if consumers call deassert first in probe which seems common in kernel? > It seems will fail. > e.g. > probe() { > reset_control_get() > reset_control_deassert() > } > > Regards > Aisheng > OK, I'm trying to explain here how I know the resets are supposed to be working and how the BLK_CTL IP is working. First of, the BLK_CTL bits (resets and clocks) all have the HW init (default) values as 0. Basically, after the blk_ctl PD is powered on, the resets are deasserted and clocks are gated by default. Since the blk_ctl is not the parent of any of the consumers in devicetree (the reg maps are entirely different anyway), there is no way of ordering the runtime callbacks between the consumer and the blk_ctl. So we might end up having the runtime resume callback after the one from EARC (consumer), for example, which will basically overwrite the value written by EARC driver with whatever was saved on suspend. Now, about the usage of the reset bits. AFAICT, it would make more sense to assert the reset, then enable the clock, then deassert. This way, you're keeping the EARC (consumer) in reset (with the clocks on) until you eventually release it out of reset by deasserting. This is how the runtime resume should deal with the reset and the clock. As for the runtime suspend, the reset can be entirely ignored as long as you're disabling the clock. This last part will allow the blk_ctl to make the following assumption: if all the clocks are disabled and none of the reset bits are asserted, I can power off. Now, I know there are drivers outthere that do assert on suspend, but as long as the clocks are disabled, the assert will have no impact. But maybe in their case the reset controller cannot power down itself. As for the safekeeping of the register, I'll just drop it due to the following arguments: 1. all the clocks are gated by default 2. all resets are deasserted by default 3. when blk_ctl goes down, all the consumers go down. (all have the same PD) From 1 and 2 results the IP will not be running and from 3 results the HW state of every IP becomes HW init state. > > + > > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) > > + pm_runtime_get_sync(rcdev->dev) > > + > > + spin_lock_irqsave(&drvdata->lock, flags); > > + > > + reg = readl(reg_addr); > > + if (assert) > > + writel(reg & ~(mask << shift), reg_addr); > > + else > > + writel(reg | (mask << shift), reg_addr); > > + > > + spin_unlock_irqrestore(&drvdata->lock, flags); > > + > > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > > + pm_runtime_put(rcdev->dev) > > + > > + return 0; > > +} > > + > > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + return imx_blk_ctl_reset_set(rcdev, id, true); > > +} > > + > > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + return imx_blk_ctl_reset_set(rcdev, id, false); > > +} > > + > > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > > + .assert = imx_blk_ctl_reset_assert, > > + .deassert = imx_blk_ctl_reset_deassert, > > +}; > > + > > +static int imx_blk_ctl_register_reset_controller(struct device *dev) > > +{ > > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > > + int max = dev_data->resets_max; > > + struct imx_reset_hw *hws; > > + int i; > > + > > + spin_lock_init(&drvdata->lock); > > + > > + drvdata->rcdev.owner = THIS_MODULE; > > + drvdata->rcdev.nr_resets = max; > > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > > + drvdata->rcdev.of_node = dev->of_node; > > + drvdata->rcdev.dev = dev; > > + > > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > > + GFP_KERNEL); > > + hws = drvdata->rst_hws; > > + > > + for (i = 0; i < dev_data->hws_num; i++) { > > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > > + > > + if (hw->type != BLK_CTL_RESET) > > + continue; > > + > > + hws[hw->id].offset = hw->offset; > > + hws[hw->id].shift = hw->shift; > > + hws[hw->id].mask = hw->mask; > > + } > > + > > + return devm_reset_controller_register(dev, &drvdata->rcdev); > > +} > > +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > > + struct imx_blk_ctl_hw *hw) > > +{ > > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > > + void __iomem *base = drvdata->base; > > + struct clk_hw *clk_hw = NULL; > > + > > + switch (hw->type) { > > + case BLK_CTL_CLK_MUX: > > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > > + base + hw->offset, > > + hw->shift, hw->width, > > + hw->parents, > > + hw->parents_count, > > + hw->flags); > > + break; > > + case BLK_CTL_CLK_GATE: > > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > > + base + hw->offset, hw->shift); > > + break; > > + case BLK_CTL_CLK_SHARED_GATE: > > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > > + hw->parents, > > + base + hw->offset, > > + hw->shift, > > + hw->shared_count); > > + break; > > + case BLK_CTL_CLK_PLL14XX: > > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > > + base + hw->offset, hw->pll_tbl); > > + break; > > + }; > > + > > + return clk_hw; > > +} > > + > > +static int imx_blk_ctl_register_clock_controller(struct device *dev) > > +{ > > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > > + struct clk_hw_onecell_data *clk_hw_data; > > + struct clk_hw **hws; > > + int i; > > + > > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > > + dev_data->hws_num), GFP_KERNEL); > > + if (WARN_ON(!clk_hw_data)) > > + return -ENOMEM; > > + > > + clk_hw_data->num = dev_data->clocks_max; > > + hws = clk_hw_data->hws; > > + > > + for (i = 0; i < dev_data->hws_num; i++) { > > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > > + > > + if (hw->type == BLK_CTL_RESET) > > + continue; > > + > > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > > + } > > + > > + imx_check_clk_hws(hws, dev_data->clocks_max); > > + > > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > > + clk_hw_data); > > +} > > + > > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > > +{ > > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > > + > > + if (!dev_data->pm_runtime_saved_regs_num) > > + return 0; > > + > > + pm_info->regs_values = devm_kzalloc(dev, > > + sizeof(u32) * regs_num, > > + GFP_KERNEL); > > + if (WARN_ON(IS_ERR(pm_info->regs_values))) > > + return PTR_ERR(pm_info->regs_values); > > + > > + pm_info->regs_offsets = kmemdup(regs_offsets, > > + regs_num * sizeof(u32), GFP_KERNEL); > > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) > > + return PTR_ERR(pm_info->regs_offsets); > > + > > + pm_info->regs_num = regs_num; > > + > > + return 0; > > +} > > + > > +int imx_blk_ctl_register(struct platform_device *pdev) > > +{ > > + struct imx_blk_ctl_drvdata *drvdata; > > + struct device *dev = &pdev->dev; > > + int ret; > > + > > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > > + if (WARN_ON(!drvdata)) > > + return -ENOMEM; > > + > > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > > + if (WARN_ON(IS_ERR(drvdata->base))) > > + return PTR_ERR(drvdata->base); > > + > > + dev_set_drvdata(dev, drvdata); > > + > > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > > + if (ret) > > + return ret; > > + > > + pm_runtime_get_noresume(dev); > > + pm_runtime_set_active(dev); > > + pm_runtime_enable(dev); > > + > > + ret = imx_blk_ctl_register_clock_controller(dev); > > + if (ret) { > > + pm_runtime_put(dev); > > + return ret; > > + } > > + > > + ret = imx_blk_ctl_register_reset_controller(dev); > > + > > + pm_runtime_put(dev); > > + > > + return ret; > > +} > > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h > > new file mode 100644 > > index 00000000..3f14a47 > > --- /dev/null > > +++ b/drivers/clk/imx/clk-blk-ctl.h > > @@ -0,0 +1,80 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > > +#define __MACH_IMX_CLK_BLK_CTL_H > > + > > +enum imx_blk_ctl_hw_type { > > + BLK_CTL_CLK_MUX, > > + BLK_CTL_CLK_GATE, > > + BLK_CTL_CLK_SHARED_GATE, > > + BLK_CTL_CLK_PLL14XX, > > + BLK_CTL_RESET, > > +}; > > + > > +struct imx_blk_ctl_hw { > > + int type; > > + char *name; > > + u32 offset; > > + u32 shift; > > + u32 mask; > > + u32 width; > > + u32 flags; > > + u32 id; > > + const void *parents; > > + u32 parents_count; > > + int *shared_count; > > + const struct imx_pll14xx_clk *pll_tbl; > > +}; > > + > > +struct imx_blk_ctl_dev_data { > > + struct imx_blk_ctl_hw *hws; > > + u32 hws_num; > > + > > + u32 clocks_max; > > + u32 resets_max; > > + > > + u32 pm_runtime_saved_regs_num; > > + u32 pm_runtime_saved_regs[]; > > +}; > > + > > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > > + { \ > > + .type = _type, \ > > + .name = _name, \ > > + .id = _id, \ > > + .offset = _offset, \ > > + .shift = _shift, \ > > + .width = _width, \ > > + .mask = _mask, \ > > + .parents = _parents, \ > > + .parents_count = _parents_count, \ > > + .flags = _flags, \ > > + .shared_count = sh_count, \ > > + .pll_tbl = _pll_tbl, \ > > + } > > + > > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > > + > > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > > + > > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) > > + > > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) > > + > > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) > > + > > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) > > + > > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) > > + > > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > > + > > +int imx_blk_ctl_register(struct platform_device *pdev); > > + > > +#endif > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2020-11-17 14:48 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-17 14:48 UTC (permalink / raw) To: Dong Aisheng Cc: Dong Aisheng, Rob Herring, Peng Fan, Jacky Bai, Anson Huang, devicetree, Stephen Boyd, Shawn Guo, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, NXP Linux Team, Sascha Hauer, Fabio Estevam, Philipp Zabel, Adam Ford, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach On 20-11-11 17:13:25, Dong Aisheng wrote: > On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: > ... > > +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > > + unsigned long id, bool assert) > > +{ > > + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > > + struct imx_blk_ctl_drvdata, rcdev); > > + unsigned int offset = drvdata->rst_hws[id].offset; > > + unsigned int shift = drvdata->rst_hws[id].shift; > > + unsigned int mask = drvdata->rst_hws[id].mask; > > + void __iomem *reg_addr = drvdata->base + offset; > > + unsigned long flags; > > + u32 reg; > > + > > + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > > + return -ENODEV; > > What if consumers call deassert first in probe which seems common in kernel? > It seems will fail. > e.g. > probe() { > reset_control_get() > reset_control_deassert() > } > > Regards > Aisheng > OK, I'm trying to explain here how I know the resets are supposed to be working and how the BLK_CTL IP is working. First of, the BLK_CTL bits (resets and clocks) all have the HW init (default) values as 0. Basically, after the blk_ctl PD is powered on, the resets are deasserted and clocks are gated by default. Since the blk_ctl is not the parent of any of the consumers in devicetree (the reg maps are entirely different anyway), there is no way of ordering the runtime callbacks between the consumer and the blk_ctl. So we might end up having the runtime resume callback after the one from EARC (consumer), for example, which will basically overwrite the value written by EARC driver with whatever was saved on suspend. Now, about the usage of the reset bits. AFAICT, it would make more sense to assert the reset, then enable the clock, then deassert. This way, you're keeping the EARC (consumer) in reset (with the clocks on) until you eventually release it out of reset by deasserting. This is how the runtime resume should deal with the reset and the clock. As for the runtime suspend, the reset can be entirely ignored as long as you're disabling the clock. This last part will allow the blk_ctl to make the following assumption: if all the clocks are disabled and none of the reset bits are asserted, I can power off. Now, I know there are drivers outthere that do assert on suspend, but as long as the clocks are disabled, the assert will have no impact. But maybe in their case the reset controller cannot power down itself. As for the safekeeping of the register, I'll just drop it due to the following arguments: 1. all the clocks are gated by default 2. all resets are deasserted by default 3. when blk_ctl goes down, all the consumers go down. (all have the same PD) From 1 and 2 results the IP will not be running and from 3 results the HW state of every IP becomes HW init state. > > + > > + if (assert && !test_and_set_bit(1, &drvdata->rst_hws[id].asserted)) > > + pm_runtime_get_sync(rcdev->dev) > > + > > + spin_lock_irqsave(&drvdata->lock, flags); > > + > > + reg = readl(reg_addr); > > + if (assert) > > + writel(reg & ~(mask << shift), reg_addr); > > + else > > + writel(reg | (mask << shift), reg_addr); > > + > > + spin_unlock_irqrestore(&drvdata->lock, flags); > > + > > + if (!assert && test_and_clear_bit(1, &drvdata->rst_hws[id].asserted)) > > + pm_runtime_put(rcdev->dev) > > + > > + return 0; > > +} > > + > > +static int imx_blk_ctl_reset_assert(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + return imx_blk_ctl_reset_set(rcdev, id, true); > > +} > > + > > +static int imx_blk_ctl_reset_deassert(struct reset_controller_dev *rcdev, > > + unsigned long id) > > +{ > > + return imx_blk_ctl_reset_set(rcdev, id, false); > > +} > > + > > +static const struct reset_control_ops imx_blk_ctl_reset_ops = { > > + .assert = imx_blk_ctl_reset_assert, > > + .deassert = imx_blk_ctl_reset_deassert, > > +}; > > + > > +static int imx_blk_ctl_register_reset_controller(struct device *dev) > > +{ > > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > > + int max = dev_data->resets_max; > > + struct imx_reset_hw *hws; > > + int i; > > + > > + spin_lock_init(&drvdata->lock); > > + > > + drvdata->rcdev.owner = THIS_MODULE; > > + drvdata->rcdev.nr_resets = max; > > + drvdata->rcdev.ops = &imx_blk_ctl_reset_ops; > > + drvdata->rcdev.of_node = dev->of_node; > > + drvdata->rcdev.dev = dev; > > + > > + drvdata->rst_hws = devm_kcalloc(dev, max, sizeof(struct imx_reset_hw), > > + GFP_KERNEL); > > + hws = drvdata->rst_hws; > > + > > + for (i = 0; i < dev_data->hws_num; i++) { > > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > > + > > + if (hw->type != BLK_CTL_RESET) > > + continue; > > + > > + hws[hw->id].offset = hw->offset; > > + hws[hw->id].shift = hw->shift; > > + hws[hw->id].mask = hw->mask; > > + } > > + > > + return devm_reset_controller_register(dev, &drvdata->rcdev); > > +} > > +static struct clk_hw *imx_blk_ctl_register_one_clock(struct device *dev, > > + struct imx_blk_ctl_hw *hw) > > +{ > > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > > + void __iomem *base = drvdata->base; > > + struct clk_hw *clk_hw = NULL; > > + > > + switch (hw->type) { > > + case BLK_CTL_CLK_MUX: > > + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, > > + base + hw->offset, > > + hw->shift, hw->width, > > + hw->parents, > > + hw->parents_count, > > + hw->flags); > > + break; > > + case BLK_CTL_CLK_GATE: > > + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, > > + base + hw->offset, hw->shift); > > + break; > > + case BLK_CTL_CLK_SHARED_GATE: > > + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, > > + hw->parents, > > + base + hw->offset, > > + hw->shift, > > + hw->shared_count); > > + break; > > + case BLK_CTL_CLK_PLL14XX: > > + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, > > + base + hw->offset, hw->pll_tbl); > > + break; > > + }; > > + > > + return clk_hw; > > +} > > + > > +static int imx_blk_ctl_register_clock_controller(struct device *dev) > > +{ > > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > > + struct clk_hw_onecell_data *clk_hw_data; > > + struct clk_hw **hws; > > + int i; > > + > > + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, > > + dev_data->hws_num), GFP_KERNEL); > > + if (WARN_ON(!clk_hw_data)) > > + return -ENOMEM; > > + > > + clk_hw_data->num = dev_data->clocks_max; > > + hws = clk_hw_data->hws; > > + > > + for (i = 0; i < dev_data->hws_num; i++) { > > + struct imx_blk_ctl_hw *hw = &dev_data->hws[i]; > > + > > + if (hw->type == BLK_CTL_RESET) > > + continue; > > + > > + hws[hw->id] = imx_blk_ctl_register_one_clock(dev, hw); > > + } > > + > > + imx_check_clk_hws(hws, dev_data->clocks_max); > > + > > + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, > > + clk_hw_data); > > +} > > + > > +static int imx_blk_ctl_init_runtime_pm_safekeeping(struct device *dev) > > +{ > > + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); > > + struct imx_blk_ctl_drvdata *drvdata = dev_get_drvdata(dev); > > + struct imx_pm_safekeep_info *pm_info = &drvdata->pm_info; > > + u32 regs_num = dev_data->pm_runtime_saved_regs_num; > > + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; > > + > > + if (!dev_data->pm_runtime_saved_regs_num) > > + return 0; > > + > > + pm_info->regs_values = devm_kzalloc(dev, > > + sizeof(u32) * regs_num, > > + GFP_KERNEL); > > + if (WARN_ON(IS_ERR(pm_info->regs_values))) > > + return PTR_ERR(pm_info->regs_values); > > + > > + pm_info->regs_offsets = kmemdup(regs_offsets, > > + regs_num * sizeof(u32), GFP_KERNEL); > > + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) > > + return PTR_ERR(pm_info->regs_offsets); > > + > > + pm_info->regs_num = regs_num; > > + > > + return 0; > > +} > > + > > +int imx_blk_ctl_register(struct platform_device *pdev) > > +{ > > + struct imx_blk_ctl_drvdata *drvdata; > > + struct device *dev = &pdev->dev; > > + int ret; > > + > > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > > + if (WARN_ON(!drvdata)) > > + return -ENOMEM; > > + > > + drvdata->base = devm_platform_ioremap_resource(pdev, 0); > > + if (WARN_ON(IS_ERR(drvdata->base))) > > + return PTR_ERR(drvdata->base); > > + > > + dev_set_drvdata(dev, drvdata); > > + > > + ret = imx_blk_ctl_init_runtime_pm_safekeeping(dev); > > + if (ret) > > + return ret; > > + > > + pm_runtime_get_noresume(dev); > > + pm_runtime_set_active(dev); > > + pm_runtime_enable(dev); > > + > > + ret = imx_blk_ctl_register_clock_controller(dev); > > + if (ret) { > > + pm_runtime_put(dev); > > + return ret; > > + } > > + > > + ret = imx_blk_ctl_register_reset_controller(dev); > > + > > + pm_runtime_put(dev); > > + > > + return ret; > > +} > > +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); > > diff --git a/drivers/clk/imx/clk-blk-ctl.h b/drivers/clk/imx/clk-blk-ctl.h > > new file mode 100644 > > index 00000000..3f14a47 > > --- /dev/null > > +++ b/drivers/clk/imx/clk-blk-ctl.h > > @@ -0,0 +1,80 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef __MACH_IMX_CLK_BLK_CTL_H > > +#define __MACH_IMX_CLK_BLK_CTL_H > > + > > +enum imx_blk_ctl_hw_type { > > + BLK_CTL_CLK_MUX, > > + BLK_CTL_CLK_GATE, > > + BLK_CTL_CLK_SHARED_GATE, > > + BLK_CTL_CLK_PLL14XX, > > + BLK_CTL_RESET, > > +}; > > + > > +struct imx_blk_ctl_hw { > > + int type; > > + char *name; > > + u32 offset; > > + u32 shift; > > + u32 mask; > > + u32 width; > > + u32 flags; > > + u32 id; > > + const void *parents; > > + u32 parents_count; > > + int *shared_count; > > + const struct imx_pll14xx_clk *pll_tbl; > > +}; > > + > > +struct imx_blk_ctl_dev_data { > > + struct imx_blk_ctl_hw *hws; > > + u32 hws_num; > > + > > + u32 clocks_max; > > + u32 resets_max; > > + > > + u32 pm_runtime_saved_regs_num; > > + u32 pm_runtime_saved_regs[]; > > +}; > > + > > +#define IMX_BLK_CTL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ > > + { \ > > + .type = _type, \ > > + .name = _name, \ > > + .id = _id, \ > > + .offset = _offset, \ > > + .shift = _shift, \ > > + .width = _width, \ > > + .mask = _mask, \ > > + .parents = _parents, \ > > + .parents_count = _parents_count, \ > > + .flags = _flags, \ > > + .shared_count = sh_count, \ > > + .pll_tbl = _pll_tbl, \ > > + } > > + > > +#define IMX_BLK_CTL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) > > + > > +#define IMX_BLK_CTL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) > > + > > +#define IMX_BLK_CTL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) > > + > > +#define IMX_BLK_CTL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) > > + > > +#define IMX_BLK_CTL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ > > + IMX_BLK_CTL(BLK_CTL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) > > + > > +#define IMX_BLK_CTL_RESET(_id, _offset, _shift) \ > > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) > > + > > +#define IMX_BLK_CTL_RESET_MASK(_id, _offset, _shift, mask) \ > > + IMX_BLK_CTL(BLK_CTL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) > > + > > +extern const struct dev_pm_ops imx_blk_ctl_pm_ops; > > + > > +int imx_blk_ctl_register(struct platform_device *pdev); > > + > > +#endif > > -- > > 2.7.4 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2020-11-17 14:48 ` Abel Vesa @ 2021-02-25 8:23 ` Frieder Schrempf -1 siblings, 0 replies; 72+ messages in thread From: Frieder Schrempf @ 2021-02-25 8:23 UTC (permalink / raw) To: Abel Vesa, Dong Aisheng Cc: Dong Aisheng, Rob Herring, Peng Fan, Jacky Bai, Anson Huang, devicetree, Stephen Boyd, Shawn Guo, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, NXP Linux Team, Sascha Hauer, Fabio Estevam, Philipp Zabel, Adam Ford, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach Hi Abel, On 17.11.20 15:48, Abel Vesa wrote: > On 20-11-11 17:13:25, Dong Aisheng wrote: >> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: >> ... >>> +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, >>> + unsigned long id, bool assert) >>> +{ >>> + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, >>> + struct imx_blk_ctl_drvdata, rcdev); >>> + unsigned int offset = drvdata->rst_hws[id].offset; >>> + unsigned int shift = drvdata->rst_hws[id].shift; >>> + unsigned int mask = drvdata->rst_hws[id].mask; >>> + void __iomem *reg_addr = drvdata->base + offset; >>> + unsigned long flags; >>> + u32 reg; >>> + >>> + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) >>> + return -ENODEV; >> >> What if consumers call deassert first in probe which seems common in kernel? >> It seems will fail. >> e.g. >> probe() { >> reset_control_get() >> reset_control_deassert() >> } >> >> Regards >> Aisheng >> > > OK, I'm trying to explain here how I know the resets are supposed to be working > and how the BLK_CTL IP is working. > > > First of, the BLK_CTL bits (resets and clocks) all have the HW init (default) values > as 0. Basically, after the blk_ctl PD is powered on, the resets are deasserted and > clocks are gated by default. Since the blk_ctl is not the parent of any of the > consumers in devicetree (the reg maps are entirely different anyway), there is no > way of ordering the runtime callbacks between the consumer and the blk_ctl. So we > might end up having the runtime resume callback after the one from EARC (consumer), > for example, which will basically overwrite the value written by EARC driver with > whatever was saved on suspend. > > Now, about the usage of the reset bits. AFAICT, it would make more sense to assert > the reset, then enable the clock, then deassert. This way, you're keeping the > EARC (consumer) in reset (with the clocks on) until you eventually release it out of > reset by deasserting. This is how the runtime resume should deal with the reset > and the clock. As for the runtime suspend, the reset can be entirely ignored as long > as you're disabling the clock. > > This last part will allow the blk_ctl to make the following assumption: > if all the clocks are disabled and none of the reset bits are asserted, I can power off. > > Now, I know there are drivers outthere that do assert on suspend, but as long as the > clocks are disabled, the assert will have no impact. But maybe in their case the reset > controller cannot power down itself. > > As for the safekeeping of the register, I'll just drop it due to the following arguments: > 1. all the clocks are gated by default > 2. all resets are deasserted by default > 3. when blk_ctl goes down, all the consumers go down. (all have the same PD) > > From 1 and 2 results the IP will not be running and from 3 results the HW state > of every IP becomes HW init state. Are there any plans to continue this work? As BLK-CTL it is not only relevant for the i.MX8MP, but also for i.MX8MM and i.MX8MN, it would be nice to get this ready in order to prepare for proper graphics/display support. Thanks Frieder ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2021-02-25 8:23 ` Frieder Schrempf 0 siblings, 0 replies; 72+ messages in thread From: Frieder Schrempf @ 2021-02-25 8:23 UTC (permalink / raw) To: Abel Vesa, Dong Aisheng Cc: Dong Aisheng, Rob Herring, Peng Fan, Jacky Bai, Anson Huang, devicetree, Stephen Boyd, Adam Ford, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, NXP Linux Team, Sascha Hauer, Fabio Estevam, Philipp Zabel, Shawn Guo, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach Hi Abel, On 17.11.20 15:48, Abel Vesa wrote: > On 20-11-11 17:13:25, Dong Aisheng wrote: >> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: >> ... >>> +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, >>> + unsigned long id, bool assert) >>> +{ >>> + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, >>> + struct imx_blk_ctl_drvdata, rcdev); >>> + unsigned int offset = drvdata->rst_hws[id].offset; >>> + unsigned int shift = drvdata->rst_hws[id].shift; >>> + unsigned int mask = drvdata->rst_hws[id].mask; >>> + void __iomem *reg_addr = drvdata->base + offset; >>> + unsigned long flags; >>> + u32 reg; >>> + >>> + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) >>> + return -ENODEV; >> >> What if consumers call deassert first in probe which seems common in kernel? >> It seems will fail. >> e.g. >> probe() { >> reset_control_get() >> reset_control_deassert() >> } >> >> Regards >> Aisheng >> > > OK, I'm trying to explain here how I know the resets are supposed to be working > and how the BLK_CTL IP is working. > > > First of, the BLK_CTL bits (resets and clocks) all have the HW init (default) values > as 0. Basically, after the blk_ctl PD is powered on, the resets are deasserted and > clocks are gated by default. Since the blk_ctl is not the parent of any of the > consumers in devicetree (the reg maps are entirely different anyway), there is no > way of ordering the runtime callbacks between the consumer and the blk_ctl. So we > might end up having the runtime resume callback after the one from EARC (consumer), > for example, which will basically overwrite the value written by EARC driver with > whatever was saved on suspend. > > Now, about the usage of the reset bits. AFAICT, it would make more sense to assert > the reset, then enable the clock, then deassert. This way, you're keeping the > EARC (consumer) in reset (with the clocks on) until you eventually release it out of > reset by deasserting. This is how the runtime resume should deal with the reset > and the clock. As for the runtime suspend, the reset can be entirely ignored as long > as you're disabling the clock. > > This last part will allow the blk_ctl to make the following assumption: > if all the clocks are disabled and none of the reset bits are asserted, I can power off. > > Now, I know there are drivers outthere that do assert on suspend, but as long as the > clocks are disabled, the assert will have no impact. But maybe in their case the reset > controller cannot power down itself. > > As for the safekeeping of the register, I'll just drop it due to the following arguments: > 1. all the clocks are gated by default > 2. all resets are deasserted by default > 3. when blk_ctl goes down, all the consumers go down. (all have the same PD) > > From 1 and 2 results the IP will not be running and from 3 results the HW state > of every IP becomes HW init state. Are there any plans to continue this work? As BLK-CTL it is not only relevant for the i.MX8MP, but also for i.MX8MM and i.MX8MN, it would be nice to get this ready in order to prepare for proper graphics/display support. Thanks Frieder _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2021-02-25 8:23 ` Frieder Schrempf @ 2021-02-25 8:27 ` Jacky Bai -1 siblings, 0 replies; 72+ messages in thread From: Jacky Bai @ 2021-02-25 8:27 UTC (permalink / raw) To: Frieder Schrempf, Abel Vesa, Dong Aisheng Cc: Aisheng Dong, Rob Herring, Peng Fan, Anson Huang, devicetree, Stephen Boyd, Shawn Guo, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, dl-linux-imx, Sascha Hauer, Fabio Estevam, Philipp Zabel, Adam Ford, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach > -----Original Message----- > From: Frieder Schrempf [mailto:frieder.schrempf@kontron.de] > Sent: Thursday, February 25, 2021 4:23 PM > To: Abel Vesa <abel.vesa@nxp.com>; Dong Aisheng <dongas86@gmail.com> > Cc: Aisheng Dong <aisheng.dong@nxp.com>; Rob Herring <robh@kernel.org>; > Peng Fan <peng.fan@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Anson Huang > <anson.huang@nxp.com>; devicetree <devicetree@vger.kernel.org>; > Stephen Boyd <sboyd@kernel.org>; Shawn Guo <shawnguo@kernel.org>; > Mike Turquette <mturquette@baylibre.com>; Linux Kernel Mailing List > <linux-kernel@vger.kernel.org>; Marek Vasut <marek.vasut@gmail.com>; > dl-linux-imx <linux-imx@nxp.com>; Sascha Hauer <kernel@pengutronix.de>; > Fabio Estevam <fabio.estevam@nxp.com>; Philipp Zabel > <p.zabel@pengutronix.de>; Adam Ford <aford173@gmail.com>; linux-clk > <linux-clk@vger.kernel.org>; moderated list:ARM/FREESCALE IMX / MXC > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Lucas Stach > <l.stach@pengutronix.de> > Subject: Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver > > Hi Abel, > > On 17.11.20 15:48, Abel Vesa wrote: > > On 20-11-11 17:13:25, Dong Aisheng wrote: > >> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: > >> ... > >>> +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > >>> + unsigned long id, bool assert) { > >>> + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > >>> + struct imx_blk_ctl_drvdata, rcdev); > >>> + unsigned int offset = drvdata->rst_hws[id].offset; > >>> + unsigned int shift = drvdata->rst_hws[id].shift; > >>> + unsigned int mask = drvdata->rst_hws[id].mask; > >>> + void __iomem *reg_addr = drvdata->base + offset; > >>> + unsigned long flags; > >>> + u32 reg; > >>> + > >>> + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > >>> + return -ENODEV; > >> > >> What if consumers call deassert first in probe which seems common in > kernel? > >> It seems will fail. > >> e.g. > >> probe() { > >> reset_control_get() > >> reset_control_deassert() > >> } > >> > >> Regards > >> Aisheng > >> > > > > OK, I'm trying to explain here how I know the resets are supposed to > > be working and how the BLK_CTL IP is working. > > > > > > First of, the BLK_CTL bits (resets and clocks) all have the HW init > > (default) values as 0. Basically, after the blk_ctl PD is powered on, > > the resets are deasserted and clocks are gated by default. Since the > > blk_ctl is not the parent of any of the consumers in devicetree (the > > reg maps are entirely different anyway), there is no way of ordering > > the runtime callbacks between the consumer and the blk_ctl. So we > > might end up having the runtime resume callback after the one from > > EARC (consumer), for example, which will basically overwrite the value > written by EARC driver with whatever was saved on suspend. > > > > Now, about the usage of the reset bits. AFAICT, it would make more > > sense to assert the reset, then enable the clock, then deassert. This > > way, you're keeping the EARC (consumer) in reset (with the clocks on) > > until you eventually release it out of reset by deasserting. This is > > how the runtime resume should deal with the reset and the clock. As > > for the runtime suspend, the reset can be entirely ignored as long as you're > disabling the clock. > > > > This last part will allow the blk_ctl to make the following assumption: > > if all the clocks are disabled and none of the reset bits are asserted, I can > power off. > > > > Now, I know there are drivers outthere that do assert on suspend, but > > as long as the clocks are disabled, the assert will have no impact. > > But maybe in their case the reset controller cannot power down itself. > > > > As for the safekeeping of the register, I'll just drop it due to the following > arguments: > > 1. all the clocks are gated by default 2. all resets are deasserted by > > default 3. when blk_ctl goes down, all the consumers go down. (all > > have the same PD) > > > > From 1 and 2 results the IP will not be running and from 3 results > > the HW state of every IP becomes HW init state. > > Are there any plans to continue this work? As BLK-CTL it is not only relevant > for the i.MX8MP, but also for i.MX8MM and i.MX8MN, it would be nice to get > this ready in order to prepare for proper graphics/display support. > Before continuing this work, we need to find out a way to resolve the cycling dependency issue between power domain and blk-ctrl. it is indeed introduced some troubles in NXP latest internal release when the blk-ctrl driver is added. BR Jacky Bai > Thanks > Frieder ^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2021-02-25 8:27 ` Jacky Bai 0 siblings, 0 replies; 72+ messages in thread From: Jacky Bai @ 2021-02-25 8:27 UTC (permalink / raw) To: Frieder Schrempf, Abel Vesa, Dong Aisheng Cc: Aisheng Dong, Rob Herring, Peng Fan, Philipp Zabel, Anson Huang, devicetree, Stephen Boyd, Adam Ford, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, dl-linux-imx, Sascha Hauer, Fabio Estevam, Shawn Guo, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach > -----Original Message----- > From: Frieder Schrempf [mailto:frieder.schrempf@kontron.de] > Sent: Thursday, February 25, 2021 4:23 PM > To: Abel Vesa <abel.vesa@nxp.com>; Dong Aisheng <dongas86@gmail.com> > Cc: Aisheng Dong <aisheng.dong@nxp.com>; Rob Herring <robh@kernel.org>; > Peng Fan <peng.fan@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Anson Huang > <anson.huang@nxp.com>; devicetree <devicetree@vger.kernel.org>; > Stephen Boyd <sboyd@kernel.org>; Shawn Guo <shawnguo@kernel.org>; > Mike Turquette <mturquette@baylibre.com>; Linux Kernel Mailing List > <linux-kernel@vger.kernel.org>; Marek Vasut <marek.vasut@gmail.com>; > dl-linux-imx <linux-imx@nxp.com>; Sascha Hauer <kernel@pengutronix.de>; > Fabio Estevam <fabio.estevam@nxp.com>; Philipp Zabel > <p.zabel@pengutronix.de>; Adam Ford <aford173@gmail.com>; linux-clk > <linux-clk@vger.kernel.org>; moderated list:ARM/FREESCALE IMX / MXC > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Lucas Stach > <l.stach@pengutronix.de> > Subject: Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver > > Hi Abel, > > On 17.11.20 15:48, Abel Vesa wrote: > > On 20-11-11 17:13:25, Dong Aisheng wrote: > >> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: > >> ... > >>> +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > >>> + unsigned long id, bool assert) { > >>> + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > >>> + struct imx_blk_ctl_drvdata, rcdev); > >>> + unsigned int offset = drvdata->rst_hws[id].offset; > >>> + unsigned int shift = drvdata->rst_hws[id].shift; > >>> + unsigned int mask = drvdata->rst_hws[id].mask; > >>> + void __iomem *reg_addr = drvdata->base + offset; > >>> + unsigned long flags; > >>> + u32 reg; > >>> + > >>> + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > >>> + return -ENODEV; > >> > >> What if consumers call deassert first in probe which seems common in > kernel? > >> It seems will fail. > >> e.g. > >> probe() { > >> reset_control_get() > >> reset_control_deassert() > >> } > >> > >> Regards > >> Aisheng > >> > > > > OK, I'm trying to explain here how I know the resets are supposed to > > be working and how the BLK_CTL IP is working. > > > > > > First of, the BLK_CTL bits (resets and clocks) all have the HW init > > (default) values as 0. Basically, after the blk_ctl PD is powered on, > > the resets are deasserted and clocks are gated by default. Since the > > blk_ctl is not the parent of any of the consumers in devicetree (the > > reg maps are entirely different anyway), there is no way of ordering > > the runtime callbacks between the consumer and the blk_ctl. So we > > might end up having the runtime resume callback after the one from > > EARC (consumer), for example, which will basically overwrite the value > written by EARC driver with whatever was saved on suspend. > > > > Now, about the usage of the reset bits. AFAICT, it would make more > > sense to assert the reset, then enable the clock, then deassert. This > > way, you're keeping the EARC (consumer) in reset (with the clocks on) > > until you eventually release it out of reset by deasserting. This is > > how the runtime resume should deal with the reset and the clock. As > > for the runtime suspend, the reset can be entirely ignored as long as you're > disabling the clock. > > > > This last part will allow the blk_ctl to make the following assumption: > > if all the clocks are disabled and none of the reset bits are asserted, I can > power off. > > > > Now, I know there are drivers outthere that do assert on suspend, but > > as long as the clocks are disabled, the assert will have no impact. > > But maybe in their case the reset controller cannot power down itself. > > > > As for the safekeeping of the register, I'll just drop it due to the following > arguments: > > 1. all the clocks are gated by default 2. all resets are deasserted by > > default 3. when blk_ctl goes down, all the consumers go down. (all > > have the same PD) > > > > From 1 and 2 results the IP will not be running and from 3 results > > the HW state of every IP becomes HW init state. > > Are there any plans to continue this work? As BLK-CTL it is not only relevant > for the i.MX8MP, but also for i.MX8MM and i.MX8MN, it would be nice to get > this ready in order to prepare for proper graphics/display support. > Before continuing this work, we need to find out a way to resolve the cycling dependency issue between power domain and blk-ctrl. it is indeed introduced some troubles in NXP latest internal release when the blk-ctrl driver is added. BR Jacky Bai > Thanks > Frieder _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver 2021-02-25 8:27 ` Jacky Bai @ 2021-03-18 19:58 ` Tim Harvey -1 siblings, 0 replies; 72+ messages in thread From: Tim Harvey @ 2021-03-18 19:58 UTC (permalink / raw) To: Jacky Bai Cc: Frieder Schrempf, Abel Vesa, Dong Aisheng, Aisheng Dong, Rob Herring, Peng Fan, Philipp Zabel, Anson Huang, devicetree, Stephen Boyd, Adam Ford, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, dl-linux-imx, Sascha Hauer, Fabio Estevam, Shawn Guo, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach On Thu, Feb 25, 2021 at 12:28 AM Jacky Bai <ping.bai@nxp.com> wrote: > > > > > -----Original Message----- > > From: Frieder Schrempf [mailto:frieder.schrempf@kontron.de] > > Sent: Thursday, February 25, 2021 4:23 PM > > To: Abel Vesa <abel.vesa@nxp.com>; Dong Aisheng <dongas86@gmail.com> > > Cc: Aisheng Dong <aisheng.dong@nxp.com>; Rob Herring <robh@kernel.org>; > > Peng Fan <peng.fan@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Anson Huang > > <anson.huang@nxp.com>; devicetree <devicetree@vger.kernel.org>; > > Stephen Boyd <sboyd@kernel.org>; Shawn Guo <shawnguo@kernel.org>; > > Mike Turquette <mturquette@baylibre.com>; Linux Kernel Mailing List > > <linux-kernel@vger.kernel.org>; Marek Vasut <marek.vasut@gmail.com>; > > dl-linux-imx <linux-imx@nxp.com>; Sascha Hauer <kernel@pengutronix.de>; > > Fabio Estevam <fabio.estevam@nxp.com>; Philipp Zabel > > <p.zabel@pengutronix.de>; Adam Ford <aford173@gmail.com>; linux-clk > > <linux-clk@vger.kernel.org>; moderated list:ARM/FREESCALE IMX / MXC > > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Lucas Stach > > <l.stach@pengutronix.de> > > Subject: Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver > > > > Hi Abel, > > > > On 17.11.20 15:48, Abel Vesa wrote: > > > On 20-11-11 17:13:25, Dong Aisheng wrote: > > >> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: > > >> ... > > >>> +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > > >>> + unsigned long id, bool assert) { > > >>> + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > > >>> + struct imx_blk_ctl_drvdata, rcdev); > > >>> + unsigned int offset = drvdata->rst_hws[id].offset; > > >>> + unsigned int shift = drvdata->rst_hws[id].shift; > > >>> + unsigned int mask = drvdata->rst_hws[id].mask; > > >>> + void __iomem *reg_addr = drvdata->base + offset; > > >>> + unsigned long flags; > > >>> + u32 reg; > > >>> + > > >>> + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > > >>> + return -ENODEV; > > >> > > >> What if consumers call deassert first in probe which seems common in > > kernel? > > >> It seems will fail. > > >> e.g. > > >> probe() { > > >> reset_control_get() > > >> reset_control_deassert() > > >> } > > >> > > >> Regards > > >> Aisheng > > >> > > > > > > OK, I'm trying to explain here how I know the resets are supposed to > > > be working and how the BLK_CTL IP is working. > > > > > > > > > First of, the BLK_CTL bits (resets and clocks) all have the HW init > > > (default) values as 0. Basically, after the blk_ctl PD is powered on, > > > the resets are deasserted and clocks are gated by default. Since the > > > blk_ctl is not the parent of any of the consumers in devicetree (the > > > reg maps are entirely different anyway), there is no way of ordering > > > the runtime callbacks between the consumer and the blk_ctl. So we > > > might end up having the runtime resume callback after the one from > > > EARC (consumer), for example, which will basically overwrite the value > > written by EARC driver with whatever was saved on suspend. > > > > > > Now, about the usage of the reset bits. AFAICT, it would make more > > > sense to assert the reset, then enable the clock, then deassert. This > > > way, you're keeping the EARC (consumer) in reset (with the clocks on) > > > until you eventually release it out of reset by deasserting. This is > > > how the runtime resume should deal with the reset and the clock. As > > > for the runtime suspend, the reset can be entirely ignored as long as you're > > disabling the clock. > > > > > > This last part will allow the blk_ctl to make the following assumption: > > > if all the clocks are disabled and none of the reset bits are asserted, I can > > power off. > > > > > > Now, I know there are drivers outthere that do assert on suspend, but > > > as long as the clocks are disabled, the assert will have no impact. > > > But maybe in their case the reset controller cannot power down itself. > > > > > > As for the safekeeping of the register, I'll just drop it due to the following > > arguments: > > > 1. all the clocks are gated by default 2. all resets are deasserted by > > > default 3. when blk_ctl goes down, all the consumers go down. (all > > > have the same PD) > > > > > > From 1 and 2 results the IP will not be running and from 3 results > > > the HW state of every IP becomes HW init state. > > > > Are there any plans to continue this work? As BLK-CTL it is not only relevant > > for the i.MX8MP, but also for i.MX8MM and i.MX8MN, it would be nice to get > > this ready in order to prepare for proper graphics/display support. > > > > Before continuing this work, we need to find out a way to resolve the cycling dependency issue between power domain and blk-ctrl. > it is indeed introduced some troubles in NXP latest internal release when the blk-ctrl driver is added. > Jacky, Any update on this? This is still blocking several drivers and major functionality of the i.MX8 SoC's in mainline and I would hope this would be a top priority for NXP. Best regards, Tim ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver @ 2021-03-18 19:58 ` Tim Harvey 0 siblings, 0 replies; 72+ messages in thread From: Tim Harvey @ 2021-03-18 19:58 UTC (permalink / raw) To: Jacky Bai Cc: Frieder Schrempf, Abel Vesa, Dong Aisheng, Aisheng Dong, Rob Herring, Peng Fan, Philipp Zabel, Anson Huang, devicetree, Stephen Boyd, Adam Ford, Mike Turquette, Linux Kernel Mailing List, Marek Vasut, dl-linux-imx, Sascha Hauer, Fabio Estevam, Shawn Guo, linux-clk, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Lucas Stach On Thu, Feb 25, 2021 at 12:28 AM Jacky Bai <ping.bai@nxp.com> wrote: > > > > > -----Original Message----- > > From: Frieder Schrempf [mailto:frieder.schrempf@kontron.de] > > Sent: Thursday, February 25, 2021 4:23 PM > > To: Abel Vesa <abel.vesa@nxp.com>; Dong Aisheng <dongas86@gmail.com> > > Cc: Aisheng Dong <aisheng.dong@nxp.com>; Rob Herring <robh@kernel.org>; > > Peng Fan <peng.fan@nxp.com>; Jacky Bai <ping.bai@nxp.com>; Anson Huang > > <anson.huang@nxp.com>; devicetree <devicetree@vger.kernel.org>; > > Stephen Boyd <sboyd@kernel.org>; Shawn Guo <shawnguo@kernel.org>; > > Mike Turquette <mturquette@baylibre.com>; Linux Kernel Mailing List > > <linux-kernel@vger.kernel.org>; Marek Vasut <marek.vasut@gmail.com>; > > dl-linux-imx <linux-imx@nxp.com>; Sascha Hauer <kernel@pengutronix.de>; > > Fabio Estevam <fabio.estevam@nxp.com>; Philipp Zabel > > <p.zabel@pengutronix.de>; Adam Ford <aford173@gmail.com>; linux-clk > > <linux-clk@vger.kernel.org>; moderated list:ARM/FREESCALE IMX / MXC > > ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Lucas Stach > > <l.stach@pengutronix.de> > > Subject: Re: [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver > > > > Hi Abel, > > > > On 17.11.20 15:48, Abel Vesa wrote: > > > On 20-11-11 17:13:25, Dong Aisheng wrote: > > >> On Tue, Nov 3, 2020 at 7:22 PM Abel Vesa <abel.vesa@nxp.com> wrote: > > >> ... > > >>> +static int imx_blk_ctl_reset_set(struct reset_controller_dev *rcdev, > > >>> + unsigned long id, bool assert) { > > >>> + struct imx_blk_ctl_drvdata *drvdata = container_of(rcdev, > > >>> + struct imx_blk_ctl_drvdata, rcdev); > > >>> + unsigned int offset = drvdata->rst_hws[id].offset; > > >>> + unsigned int shift = drvdata->rst_hws[id].shift; > > >>> + unsigned int mask = drvdata->rst_hws[id].mask; > > >>> + void __iomem *reg_addr = drvdata->base + offset; > > >>> + unsigned long flags; > > >>> + u32 reg; > > >>> + > > >>> + if (!assert && !test_bit(1, &drvdata->rst_hws[id].asserted)) > > >>> + return -ENODEV; > > >> > > >> What if consumers call deassert first in probe which seems common in > > kernel? > > >> It seems will fail. > > >> e.g. > > >> probe() { > > >> reset_control_get() > > >> reset_control_deassert() > > >> } > > >> > > >> Regards > > >> Aisheng > > >> > > > > > > OK, I'm trying to explain here how I know the resets are supposed to > > > be working and how the BLK_CTL IP is working. > > > > > > > > > First of, the BLK_CTL bits (resets and clocks) all have the HW init > > > (default) values as 0. Basically, after the blk_ctl PD is powered on, > > > the resets are deasserted and clocks are gated by default. Since the > > > blk_ctl is not the parent of any of the consumers in devicetree (the > > > reg maps are entirely different anyway), there is no way of ordering > > > the runtime callbacks between the consumer and the blk_ctl. So we > > > might end up having the runtime resume callback after the one from > > > EARC (consumer), for example, which will basically overwrite the value > > written by EARC driver with whatever was saved on suspend. > > > > > > Now, about the usage of the reset bits. AFAICT, it would make more > > > sense to assert the reset, then enable the clock, then deassert. This > > > way, you're keeping the EARC (consumer) in reset (with the clocks on) > > > until you eventually release it out of reset by deasserting. This is > > > how the runtime resume should deal with the reset and the clock. As > > > for the runtime suspend, the reset can be entirely ignored as long as you're > > disabling the clock. > > > > > > This last part will allow the blk_ctl to make the following assumption: > > > if all the clocks are disabled and none of the reset bits are asserted, I can > > power off. > > > > > > Now, I know there are drivers outthere that do assert on suspend, but > > > as long as the clocks are disabled, the assert will have no impact. > > > But maybe in their case the reset controller cannot power down itself. > > > > > > As for the safekeeping of the register, I'll just drop it due to the following > > arguments: > > > 1. all the clocks are gated by default 2. all resets are deasserted by > > > default 3. when blk_ctl goes down, all the consumers go down. (all > > > have the same PD) > > > > > > From 1 and 2 results the IP will not be running and from 3 results > > > the HW state of every IP becomes HW init state. > > > > Are there any plans to continue this work? As BLK-CTL it is not only relevant > > for the i.MX8MP, but also for i.MX8MM and i.MX8MN, it would be nice to get > > this ready in order to prepare for proper graphics/display support. > > > > Before continuing this work, we need to find out a way to resolve the cycling dependency issue between power domain and blk-ctrl. > it is indeed introduced some troubles in NXP latest internal release when the blk-ctrl driver is added. > Jacky, Any update on this? This is still blocking several drivers and major functionality of the i.MX8 SoC's in mainline and I would hope this would be a top priority for NXP. Best regards, Tim _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 11/14] clk: imx: Add blk-ctl driver for i.MX8MP 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa This driver is intended to work with the following BLK_CTL IPs found in i.MX8MP: - Audio - Media - HDMI Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++++++++++++++++++++++++++++++++++ 2 files changed, 318 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 3d6d9cb..6c9b595 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o clk-blk-ctl-imx8mp.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git a/drivers/clk/imx/clk-blk-ctl-imx8mp.c b/drivers/clk/imx/clk-blk-ctl-imx8mp.c new file mode 100644 index 00000000..76bbe67 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl-imx8mp.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/reset/imx8mp-reset.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/types.h> + +#include "clk.h" +#include "clk-blk-ctl.h" + +#define IMX_AUDIO_BLK_CTL_CLKEN0 0x0 +#define IMX_AUDIO_BLK_CTL_CLKEN1 0x4 +#define IMX_AUDIO_BLK_CTL_EARC 0x200 +#define IMX_AUDIO_BLK_CTL_SAI1_MCLK_SEL 0x300 +#define IMX_AUDIO_BLK_CTL_SAI2_MCLK_SEL 0x304 +#define IMX_AUDIO_BLK_CTL_SAI3_MCLK_SEL 0x308 +#define IMX_AUDIO_BLK_CTL_SAI5_MCLK_SEL 0x30C +#define IMX_AUDIO_BLK_CTL_SAI6_MCLK_SEL 0x310 +#define IMX_AUDIO_BLK_CTL_SAI7_MCLK_SEL 0x314 +#define IMX_AUDIO_BLK_CTL_PDM_CLK 0x318 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_GNRL_CTL 0x400 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL0 0x404 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL1 0x408 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_SSCG_CTL 0x40C +#define IMX_AUDIO_BLK_CTL_SAI_PLL_MNIT_CTL 0x410 +#define IMX_AUDIO_BLK_CTL_IPG_LP_CTRL 0x504 + +#define IMX_MEDIA_BLK_CTL_SFT_RSTN 0x0 +#define IMX_MEDIA_BLK_CTL_CLK_EN 0x4 + +static int shared_count_pdm; + +static const struct imx_pll14xx_rate_table imx_blk_ctl_sai_pll_tbl[] = { + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +}; + +static const struct imx_pll14xx_clk imx_blk_ctl_sai_pll = { + .type = PLL_1443X, + .rate_table = imx_blk_ctl_sai_pll_tbl, +}; + +static const char * const imx_sai_mclk2_sels[] = {"sai1_root", "sai2_root", "sai3_root", "dummy", + "sai5_root", "sai6_root", "sai7_root", "sai1_mclk", + "sai2_mclk", "sai3_mclk", "dummy", + "sai5_mclk", "sai6_mclk", "sai7_mclk", "spdif1_ext_clk"}; +static const char * const imx_sai1_mclk1_sels[] = {"sai1_root", "sai1_mclk", }; +static const char * const imx_sai2_mclk1_sels[] = {"sai2_root", "sai2_mclk", }; +static const char * const imx_sai3_mclk1_sels[] = {"sai3_root", "sai3_mclk", }; +static const char * const imx_sai5_mclk1_sels[] = {"sai5_root", "sai5_mclk", }; +static const char * const imx_sai6_mclk1_sels[] = {"sai6_root", "sai6_mclk", }; +static const char * const imx_sai7_mclk1_sels[] = {"sai7_root", "sai7_mclk", }; +static const char * const imx_pdm_sels[] = {"pdm_root", "sai_pll_div2", "dummy", "dummy" }; +static const char * const imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; +static const char * const imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; + +static const char * const imx_hdmi_phy_clks_sels[] = {"hdmi_glb_24m", "dummy", }; +static const char * const imx_lcdif_clks_sels[] = {"dummy", "hdmi_glb_pix", }; +static const char * const imx_hdmi_pipe_clks_sels[] = {"dummy", "hdmi_glb_pix", }; + +static struct imx_blk_ctl_hw imx8mp_hdmi_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_GATE("hdmi_glb_apb", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK, 0x40, 0, "hdmi_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_b", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK, 0x40, 1, "hdmi_axi"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_ref_266m", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK, 0x40, 2, "hdmi_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_24m", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK, 0x40, 4, "hdmi_24m"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_32k", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK, 0x40, 5, "osc_32k"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_pix", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK, 0x40, 7, "hdmi_phy"), + IMX_BLK_CTL_CLK_GATE("hdmi_irq_steer", IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK, 0x40, 9, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_noc", IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK, 0x40, 10, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdcp_noc", IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK, 0x40, 11, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_apb", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK, 0x40, 16, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_b", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK, 0x40, 17, "hdmi_glb_b"), + IMX_BLK_CTL_CLK_GATE("lcdif3_pdi", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK, 0x40, 18, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_pxl", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK, 0x40, 19, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("lcdif3_spu", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK, 0x40, 20, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_fdcc_ref", IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK, 0x50, 2, "hdmi_fdcc_tst"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_apb", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK, 0x50, 3, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_b", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK, 0x50, 4, "hdmi_glb_axi"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_cea", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK, 0x50, 5, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("vsfd_cea", IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK, 0x50, 6, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_hpi", IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK, 0x50, 13, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK, 0x50, 14, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_cec", IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK, 0x50, 15, "hdmi_glb_32k"), + IMX_BLK_CTL_CLK_GATE("hdmi_esm", IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK, 0x50, 16, "hdmi_glb_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_gpa", IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK, 0x50, 17, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_pix", IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK, 0x50, 18, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_sfr", IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK, 0x50, 19, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_skp", IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK, 0x50, 20, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_prep", IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK, 0x50, 21, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_phy_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK, 0x50, 22, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_phy_int", IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK, 0x50, 24, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_sec_mem", IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK, 0x50, 25, "hdmi_glb_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_trng_skp", IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK, 0x50, 27, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_vid_pix", IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK, 0x50, 28, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("hdmi_trng_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK, 0x50, 30, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_MUX("hdmi_phy_sel", IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL, 0x50, 10, 1, imx_hdmi_phy_clks_sels), + IMX_BLK_CTL_CLK_MUX("lcdif_clk_sel", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL, 0x50, 11, 1, imx_lcdif_clks_sels), + IMX_BLK_CTL_CLK_MUX("hdmi_pipe_sel", IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL, 0x50, 12, 1, imx_hdmi_pipe_clks_sels), + + /* resets */ + IMX_BLK_CTL_RESET_MASK(IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET, 0x20, 6, 0x33), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET, 0x20, 12), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET, 0x20, 18), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET, 0x20, 22), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET, 0x20, 20), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET, 0x20, 16), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET, 0x20, 13), + IMX_BLK_CTL_RESET_MASK(IMX8MP_HDMI_BLK_CTL_LCDIF_RESET, 0x20, 4, 0x3), +}; + +static struct imx_blk_ctl_hw imx8mp_media_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_GATE("mipi_dsi_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK, 0x4, 0, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_dsi_clkref", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF, 0x4, 1, "media_mipi_phy1_ref"), + IMX_BLK_CTL_CLK_GATE("mipi_csi_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK, 0x4, 2, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi_aclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK, 0x4, 3, "media_cam1_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL, 0x4, 4, "media_disp1_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB, 0x4, 5, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isi_proc_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC, 0x4, 6, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isi_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB, 0x4, 7, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("bus_blk_clk", IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK, 0x4, 8, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi2_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK, 0x4, 9, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi2_aclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK, 0x4, 10, "media_cam2_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL, 0x4, 11, "media_disp2_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB, 0x4, 12, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR, 0x4, 13, "media_isp_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI, 0x4, 14, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB, 0x4, 15, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR, 0x4, 16, "media_isp_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI, 0x4, 17, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB, 0x4, 18, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR, 0x4, 19, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI, 0x4, 20, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB, 0x4, 21, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_dsi2_clk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2, 0x4, 22, "media_mipi_phy1_ref"), + IMX_BLK_CTL_CLK_GATE("lcdif_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI, 0x4, 23, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI, 0x4, 24, "media_axi_root_clk"), + + /* resets */ + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK, 0, 0), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF, 0, 1), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK, 0, 2), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK, 0, 3), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL, 0, 4), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB, 0, 5), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC, 0, 6), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB, 0, 7), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK, 0, 8), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK, 0, 9), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK, 0, 10), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL, 0, 11), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB, 0, 12), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR, 0, 13), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI, 0, 14), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB, 0, 15), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR, 0, 16), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI, 0, 17), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB, 0, 18), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR, 0, 19), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI, 0, 20), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB, 0, 21), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2, 0, 22), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI, 0, 23), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI, 0, 24) +}; + +static struct imx_blk_ctl_hw imx8mp_audio_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), + IMX_BLK_CTL_CLK_PLL14XX("sai_pll", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL, 0x400, "sai_pll_ref_sel", &imx_blk_ctl_sai_pll), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai_pll_bypass", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS, 0x400, 4, 1, imx_sai_pll_bypass_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_GATE("sai_pll_out", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT, 0x400, 13, "sai_pll_bypass"), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai1_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL, 0x300, 0, 1, imx_sai1_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai1_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL, 0x300, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai2_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL, 0x304, 0, 1, imx_sai2_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai2_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL, 0x304, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai3_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL, 0x308, 0, 1, imx_sai3_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai3_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL, 0x308, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai5_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL, 0x30C, 0, 1, imx_sai5_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai5_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL, 0x30C, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai6_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL, 0x310, 0, 1, imx_sai6_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai6_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL, 0x310, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai7_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL, 0x314, 0, 1, imx_sai7_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai7_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL, 0x314, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("pdm_sel", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL, 0x318, 0, 2, imx_pdm_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_GATE("sai1_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG, 0, 0, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1, 0, 1, "sai1_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2, 0, 2, "sai1_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3, 0, 3, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai2_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG, 0, 4, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1, 0, 5, "sai2_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2, 0, 6, "sai2_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3, 0, 7, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai3_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG, 0, 8, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1, 0, 9, "sai3_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2, 0, 10, "sai3_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3, 0, 11, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai5_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG, 0, 12, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1, 0, 13, "sai5_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2, 0, 14, "sai5_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3, 0, 15, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai6_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG, 0, 16, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1, 0, 17, "sai6_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2, 0, 18, "sai6_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3, 0, 19, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai7_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG, 0, 20, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1, 0, 21, "sai7_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2, 0, 22, "sai7_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3, 0, 23, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("asrc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG, 0, 24, "audio_ahb_root"), + IMX_BLK_CTL_CLK_SHARED_GATE("pdm_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG, 0, 25, "audio_ahb_root", &shared_count_pdm), + IMX_BLK_CTL_CLK_SHARED_GATE("pdm_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT, 0, 25, "pdm_sel", &shared_count_pdm), + IMX_BLK_CTL_CLK_GATE("sdma3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT, 0, 27, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("spba2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT, 0, 28, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("dsp_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT, 0, 29, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("dsp_dbg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT, 0, 30, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("earc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG, 0, 31, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("ocram_a_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG, 4, 0, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("aud2htx_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG, 4, 1, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("edma_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT, 4, 2, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("aud_pll_clk", IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT, 4, 3, "osc_24m"), + IMX_BLK_CTL_CLK_GATE("mu2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT, 4, 4, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("mu3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT, 4, 5, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("earc_phy_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY, 4, 6, "sai_pll_out"), + + /* resets */ + IMX_BLK_CTL_RESET(IMX8MP_AUDIO_BLK_CTL_EARC_RESET, 0x200, 0), + IMX_BLK_CTL_RESET(IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET, 0x200, 1), +}; + +const struct imx_blk_ctl_dev_data imx8mp_hdmi_blk_ctl_dev_data __initconst = { + .hws = imx8mp_hdmi_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_hdmi_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_HDMI_BLK_CTL_END, + .resets_max = IMX8MP_HDMI_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 0 +}; + +const struct imx_blk_ctl_dev_data imx8mp_media_blk_ctl_dev_data __initconst = { + .hws = imx8mp_media_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_media_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_MEDIA_BLK_CTL_END, + .resets_max = IMX8MP_MEDIA_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 2, + .pm_runtime_saved_regs = { + IMX_MEDIA_BLK_CTL_SFT_RSTN, + IMX_MEDIA_BLK_CTL_CLK_EN, + }, +}; + +const struct imx_blk_ctl_dev_data imx8mp_audio_blk_ctl_dev_data __initconst = { + .hws = imx8mp_audio_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_AUDIO_BLK_CTL_END, + .resets_max = IMX8MP_AUDIO_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 16, + .pm_runtime_saved_regs = { + IMX_AUDIO_BLK_CTL_CLKEN0, + IMX_AUDIO_BLK_CTL_CLKEN1, + IMX_AUDIO_BLK_CTL_EARC, + IMX_AUDIO_BLK_CTL_SAI1_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI2_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI3_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI5_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI6_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI7_MCLK_SEL, + IMX_AUDIO_BLK_CTL_PDM_CLK, + IMX_AUDIO_BLK_CTL_SAI_PLL_GNRL_CTL, + IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL0, + IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL1, + IMX_AUDIO_BLK_CTL_SAI_PLL_SSCG_CTL, + IMX_AUDIO_BLK_CTL_SAI_PLL_MNIT_CTL, + IMX_AUDIO_BLK_CTL_IPG_LP_CTRL + }, +}; + +static const struct of_device_id imx8mp_blk_ctl_of_match[] = { + { + .compatible = "fsl,imx8mp-audio-blk-ctl", + .data = &imx8mp_audio_blk_ctl_dev_data + }, + { + .compatible = "fsl,imx8mp-media-blk-ctl", + .data = &imx8mp_media_blk_ctl_dev_data + }, + { + .compatible = "fsl,imx8mp-hdmi-blk-ctl", + .data = &imx8mp_hdmi_blk_ctl_dev_data + }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8mp_blk_ctl_of_match); + +static int imx8mp_blk_ctl_probe(struct platform_device *pdev) +{ + return imx_blk_ctl_register(pdev); +} + +static struct platform_driver imx8mp_blk_ctl_driver = { + .probe = imx8mp_blk_ctl_probe, + .driver = { + .name = "imx8mp-blk-ctl", + .of_match_table = of_match_ptr(imx8mp_blk_ctl_of_match), + .pm = &imx_blk_ctl_pm_ops, + }, +}; +module_platform_driver(imx8mp_blk_ctl_driver); -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 11/14] clk: imx: Add blk-ctl driver for i.MX8MP @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel This driver is intended to work with the following BLK_CTL IPs found in i.MX8MP: - Audio - Media - HDMI Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++++++++++++++++++++++++++++++++++ 2 files changed, 318 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 3d6d9cb..6c9b595 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctl.o clk-blk-ctl-imx8mp.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o diff --git a/drivers/clk/imx/clk-blk-ctl-imx8mp.c b/drivers/clk/imx/clk-blk-ctl-imx8mp.c new file mode 100644 index 00000000..76bbe67 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctl-imx8mp.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/reset/imx8mp-reset.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/types.h> + +#include "clk.h" +#include "clk-blk-ctl.h" + +#define IMX_AUDIO_BLK_CTL_CLKEN0 0x0 +#define IMX_AUDIO_BLK_CTL_CLKEN1 0x4 +#define IMX_AUDIO_BLK_CTL_EARC 0x200 +#define IMX_AUDIO_BLK_CTL_SAI1_MCLK_SEL 0x300 +#define IMX_AUDIO_BLK_CTL_SAI2_MCLK_SEL 0x304 +#define IMX_AUDIO_BLK_CTL_SAI3_MCLK_SEL 0x308 +#define IMX_AUDIO_BLK_CTL_SAI5_MCLK_SEL 0x30C +#define IMX_AUDIO_BLK_CTL_SAI6_MCLK_SEL 0x310 +#define IMX_AUDIO_BLK_CTL_SAI7_MCLK_SEL 0x314 +#define IMX_AUDIO_BLK_CTL_PDM_CLK 0x318 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_GNRL_CTL 0x400 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL0 0x404 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL1 0x408 +#define IMX_AUDIO_BLK_CTL_SAI_PLL_SSCG_CTL 0x40C +#define IMX_AUDIO_BLK_CTL_SAI_PLL_MNIT_CTL 0x410 +#define IMX_AUDIO_BLK_CTL_IPG_LP_CTRL 0x504 + +#define IMX_MEDIA_BLK_CTL_SFT_RSTN 0x0 +#define IMX_MEDIA_BLK_CTL_CLK_EN 0x4 + +static int shared_count_pdm; + +static const struct imx_pll14xx_rate_table imx_blk_ctl_sai_pll_tbl[] = { + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +}; + +static const struct imx_pll14xx_clk imx_blk_ctl_sai_pll = { + .type = PLL_1443X, + .rate_table = imx_blk_ctl_sai_pll_tbl, +}; + +static const char * const imx_sai_mclk2_sels[] = {"sai1_root", "sai2_root", "sai3_root", "dummy", + "sai5_root", "sai6_root", "sai7_root", "sai1_mclk", + "sai2_mclk", "sai3_mclk", "dummy", + "sai5_mclk", "sai6_mclk", "sai7_mclk", "spdif1_ext_clk"}; +static const char * const imx_sai1_mclk1_sels[] = {"sai1_root", "sai1_mclk", }; +static const char * const imx_sai2_mclk1_sels[] = {"sai2_root", "sai2_mclk", }; +static const char * const imx_sai3_mclk1_sels[] = {"sai3_root", "sai3_mclk", }; +static const char * const imx_sai5_mclk1_sels[] = {"sai5_root", "sai5_mclk", }; +static const char * const imx_sai6_mclk1_sels[] = {"sai6_root", "sai6_mclk", }; +static const char * const imx_sai7_mclk1_sels[] = {"sai7_root", "sai7_mclk", }; +static const char * const imx_pdm_sels[] = {"pdm_root", "sai_pll_div2", "dummy", "dummy" }; +static const char * const imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; +static const char * const imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; + +static const char * const imx_hdmi_phy_clks_sels[] = {"hdmi_glb_24m", "dummy", }; +static const char * const imx_lcdif_clks_sels[] = {"dummy", "hdmi_glb_pix", }; +static const char * const imx_hdmi_pipe_clks_sels[] = {"dummy", "hdmi_glb_pix", }; + +static struct imx_blk_ctl_hw imx8mp_hdmi_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_GATE("hdmi_glb_apb", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_APB_CLK, 0x40, 0, "hdmi_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_b", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_B_CLK, 0x40, 1, "hdmi_axi"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_ref_266m", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_REF266M_CLK, 0x40, 2, "hdmi_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_24m", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL24M_CLK, 0x40, 4, "hdmi_24m"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_32k", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_XTAL32K_CLK, 0x40, 5, "osc_32k"), + IMX_BLK_CTL_CLK_GATE("hdmi_glb_pix", IMX8MP_CLK_HDMI_BLK_CTL_GLOBAL_TX_PIX_CLK, 0x40, 7, "hdmi_phy"), + IMX_BLK_CTL_CLK_GATE("hdmi_irq_steer", IMX8MP_CLK_HDMI_BLK_CTL_IRQS_STEER_CLK, 0x40, 9, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_noc", IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDMI_CLK, 0x40, 10, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdcp_noc", IMX8MP_CLK_HDMI_BLK_CTL_NOC_HDCP_CLK, 0x40, 11, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_apb", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_APB_CLK, 0x40, 16, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_b", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_B_CLK, 0x40, 17, "hdmi_glb_b"), + IMX_BLK_CTL_CLK_GATE("lcdif3_pdi", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PDI_CLK, 0x40, 18, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("lcdif3_pxl", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_PIX_CLK, 0x40, 19, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("lcdif3_spu", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_SPU_CLK, 0x40, 20, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_fdcc_ref", IMX8MP_CLK_HDMI_BLK_CTL_FDCC_REF_CLK, 0x50, 2, "hdmi_fdcc_tst"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_apb", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_APB_CLK, 0x50, 3, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_b", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_B_CLK, 0x50, 4, "hdmi_glb_axi"), + IMX_BLK_CTL_CLK_GATE("hrv_mwr_cea", IMX8MP_CLK_HDMI_BLK_CTL_HRV_MWR_CEA_CLK, 0x50, 5, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("vsfd_cea", IMX8MP_CLK_HDMI_BLK_CTL_VSFD_CEA_CLK, 0x50, 6, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_hpi", IMX8MP_CLK_HDMI_BLK_CTL_TX_HPI_CLK, 0x50, 13, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_APB_CLK, 0x50, 14, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_cec", IMX8MP_CLK_HDMI_BLK_CTL_TX_CEC_CLK, 0x50, 15, "hdmi_glb_32k"), + IMX_BLK_CTL_CLK_GATE("hdmi_esm", IMX8MP_CLK_HDMI_BLK_CTL_TX_ESM_CLK, 0x50, 16, "hdmi_glb_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_gpa", IMX8MP_CLK_HDMI_BLK_CTL_TX_GPA_CLK, 0x50, 17, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_pix", IMX8MP_CLK_HDMI_BLK_CTL_TX_PIXEL_CLK, 0x50, 18, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_sfr", IMX8MP_CLK_HDMI_BLK_CTL_TX_SFR_CLK, 0x50, 19, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_skp", IMX8MP_CLK_HDMI_BLK_CTL_TX_SKP_CLK, 0x50, 20, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_tx_prep", IMX8MP_CLK_HDMI_BLK_CTL_TX_PREP_CLK, 0x50, 21, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_phy_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_APB_CLK, 0x50, 22, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_phy_int", IMX8MP_CLK_HDMI_BLK_CTL_TX_PHY_INT_CLK, 0x50, 24, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_sec_mem", IMX8MP_CLK_HDMI_BLK_CTL_TX_SEC_MEM_CLK, 0x50, 25, "hdmi_glb_ref_266m"), + IMX_BLK_CTL_CLK_GATE("hdmi_trng_skp", IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_SKP_CLK, 0x50, 27, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_GATE("hdmi_vid_pix", IMX8MP_CLK_HDMI_BLK_CTL_TX_VID_LINK_PIX_CLK, 0x50, 28, "hdmi_glb_pix"), + IMX_BLK_CTL_CLK_GATE("hdmi_trng_apb", IMX8MP_CLK_HDMI_BLK_CTL_TX_TRNG_APB_CLK, 0x50, 30, "hdmi_glb_apb"), + IMX_BLK_CTL_CLK_MUX("hdmi_phy_sel", IMX8MP_CLK_HDMI_BLK_CTL_HTXPHY_CLK_SEL, 0x50, 10, 1, imx_hdmi_phy_clks_sels), + IMX_BLK_CTL_CLK_MUX("lcdif_clk_sel", IMX8MP_CLK_HDMI_BLK_CTL_LCDIF_CLK_SEL, 0x50, 11, 1, imx_lcdif_clks_sels), + IMX_BLK_CTL_CLK_MUX("hdmi_pipe_sel", IMX8MP_CLK_HDMI_BLK_CTL_TX_PIPE_CLK_SEL, 0x50, 12, 1, imx_hdmi_pipe_clks_sels), + + /* resets */ + IMX_BLK_CTL_RESET_MASK(IMX8MP_HDMI_BLK_CTL_HDMI_TX_RESET, 0x20, 6, 0x33), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PHY_RESET, 0x20, 12), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET, 0x20, 18), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_PAI_RESET, 0x20, 22), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_TRNG_RESET, 0x20, 20), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_IRQ_STEER_RESET, 0x20, 16), + IMX_BLK_CTL_RESET(IMX8MP_HDMI_BLK_CTL_HDMI_HDCP_RESET, 0x20, 13), + IMX_BLK_CTL_RESET_MASK(IMX8MP_HDMI_BLK_CTL_LCDIF_RESET, 0x20, 4, 0x3), +}; + +static struct imx_blk_ctl_hw imx8mp_media_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_GATE("mipi_dsi_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_PCLK, 0x4, 0, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_dsi_clkref", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI_CLKREF, 0x4, 1, "media_mipi_phy1_ref"), + IMX_BLK_CTL_CLK_GATE("mipi_csi_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_PCLK, 0x4, 2, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi_aclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI_ACLK, 0x4, 3, "media_cam1_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_PIXEL, 0x4, 4, "media_disp1_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_APB, 0x4, 5, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isi_proc_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISI_PROC, 0x4, 6, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isi_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISI_APB, 0x4, 7, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("bus_blk_clk", IMX8MP_CLK_MEDIA_BLK_CTL_BUS_BLK, 0x4, 8, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi2_pclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_PCLK, 0x4, 9, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_csi2_aclk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_CSI2_ACLK, 0x4, 10, "media_cam2_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_PIXEL, 0x4, 11, "media_disp2_pix_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_APB, 0x4, 12, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_COR, 0x4, 13, "media_isp_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AXI, 0x4, 14, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp1_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP1_AHB, 0x4, 15, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_COR, 0x4, 16, "media_isp_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AXI, 0x4, 17, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("isp0_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_ISP0_AHB, 0x4, 18, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_COR, 0x4, 19, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AXI, 0x4, 20, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("dwe_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTL_DWE_AHB, 0x4, 21, "media_apb_root_clk"), + IMX_BLK_CTL_CLK_GATE("mipi_dsi2_clk", IMX8MP_CLK_MEDIA_BLK_CTL_MIPI_DSI2, 0x4, 22, "media_mipi_phy1_ref"), + IMX_BLK_CTL_CLK_GATE("lcdif_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF_AXI, 0x4, 23, "media_axi_root_clk"), + IMX_BLK_CTL_CLK_GATE("lcdif2_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTL_LCDIF2_AXI, 0x4, 24, "media_axi_root_clk"), + + /* resets */ + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_PCLK, 0, 0), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI_CLKREF, 0, 1), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_PCLK, 0, 2), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI_ACLK, 0, 3), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_PIXEL, 0, 4), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_APB, 0, 5), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISI_PROC, 0, 6), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISI_APB, 0, 7), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_BUS_BLK, 0, 8), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_PCLK, 0, 9), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_CSI2_ACLK, 0, 10), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_PIXEL, 0, 11), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_APB, 0, 12), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_COR, 0, 13), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AXI, 0, 14), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP1_AHB, 0, 15), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_COR, 0, 16), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AXI, 0, 17), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_ISP0_AHB, 0, 18), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_COR, 0, 19), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AXI, 0, 20), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_DWE_AHB, 0, 21), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_MIPI_DSI2, 0, 22), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF_AXI, 0, 23), + IMX_BLK_CTL_RESET(IMX8MP_MEDIA_BLK_CTL_RESET_LCDIF2_AXI, 0, 24) +}; + +static struct imx_blk_ctl_hw imx8mp_audio_blk_ctl_hws[] = { + /* clocks */ + IMX_BLK_CTL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), + IMX_BLK_CTL_CLK_PLL14XX("sai_pll", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL, 0x400, "sai_pll_ref_sel", &imx_blk_ctl_sai_pll), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai_pll_bypass", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_BYPASS, 0x400, 4, 1, imx_sai_pll_bypass_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_GATE("sai_pll_out", IMX8MP_CLK_AUDIO_BLK_CTL_SAI_PLL_OUT, 0x400, 13, "sai_pll_bypass"), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai1_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1_SEL, 0x300, 0, 1, imx_sai1_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai1_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2_SEL, 0x300, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai2_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1_SEL, 0x304, 0, 1, imx_sai2_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai2_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2_SEL, 0x304, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("sai3_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1_SEL, 0x308, 0, 1, imx_sai3_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_MUX("sai3_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2_SEL, 0x308, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai5_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1_SEL, 0x30C, 0, 1, imx_sai5_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai5_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2_SEL, 0x30C, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai6_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1_SEL, 0x310, 0, 1, imx_sai6_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai6_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2_SEL, 0x310, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX("sai7_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1_SEL, 0x314, 0, 1, imx_sai7_mclk1_sels), + IMX_BLK_CTL_CLK_MUX("sai7_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2_SEL, 0x314, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTL_CLK_MUX_FLAGS("pdm_sel", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_SEL, 0x318, 0, 2, imx_pdm_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTL_CLK_GATE("sai1_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_IPG, 0, 0, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK1, 0, 1, "sai1_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK2, 0, 2, "sai1_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai1_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI1_MCLK3, 0, 3, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai2_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_IPG, 0, 4, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK1, 0, 5, "sai2_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK2, 0, 6, "sai2_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai2_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI2_MCLK3, 0, 7, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai3_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_IPG, 0, 8, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK1, 0, 9, "sai3_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK2, 0, 10, "sai3_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai3_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI3_MCLK3, 0, 11, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai5_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_IPG, 0, 12, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK1, 0, 13, "sai5_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK2, 0, 14, "sai5_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai5_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI5_MCLK3, 0, 15, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai6_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_IPG, 0, 16, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK1, 0, 17, "sai6_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK2, 0, 18, "sai6_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai6_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI6_MCLK3, 0, 19, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("sai7_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_IPG, 0, 20, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK1, 0, 21, "sai7_mclk1_sel"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK2, 0, 22, "sai7_mclk2_sel"), + IMX_BLK_CTL_CLK_GATE("sai7_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SAI7_MCLK3, 0, 23, "sai_pll_out"), + IMX_BLK_CTL_CLK_GATE("asrc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_ASRC_IPG, 0, 24, "audio_ahb_root"), + IMX_BLK_CTL_CLK_SHARED_GATE("pdm_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_IPG, 0, 25, "audio_ahb_root", &shared_count_pdm), + IMX_BLK_CTL_CLK_SHARED_GATE("pdm_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_PDM_ROOT, 0, 25, "pdm_sel", &shared_count_pdm), + IMX_BLK_CTL_CLK_GATE("sdma3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SDMA3_ROOT, 0, 27, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("spba2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_SPBA2_ROOT, 0, 28, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("dsp_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_DSP_ROOT, 0, 29, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("dsp_dbg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_DSPDBG_ROOT, 0, 30, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("earc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EARC_IPG, 0, 31, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("ocram_a_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_OCRAMA_IPG, 4, 0, "audio_axi_root"), + IMX_BLK_CTL_CLK_GATE("aud2htx_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTL_AUD2HTX_IPG, 4, 1, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("edma_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EDMA_ROOT, 4, 2, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("aud_pll_clk", IMX8MP_CLK_AUDIO_BLK_CTL_AUDPLL_ROOT, 4, 3, "osc_24m"), + IMX_BLK_CTL_CLK_GATE("mu2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_MU2_ROOT, 4, 4, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("mu3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTL_MU3_ROOT, 4, 5, "audio_ahb_root"), + IMX_BLK_CTL_CLK_GATE("earc_phy_clk", IMX8MP_CLK_AUDIO_BLK_CTL_EARC_PHY, 4, 6, "sai_pll_out"), + + /* resets */ + IMX_BLK_CTL_RESET(IMX8MP_AUDIO_BLK_CTL_EARC_RESET, 0x200, 0), + IMX_BLK_CTL_RESET(IMX8MP_AUDIO_BLK_CTL_EARC_PHY_RESET, 0x200, 1), +}; + +const struct imx_blk_ctl_dev_data imx8mp_hdmi_blk_ctl_dev_data __initconst = { + .hws = imx8mp_hdmi_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_hdmi_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_HDMI_BLK_CTL_END, + .resets_max = IMX8MP_HDMI_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 0 +}; + +const struct imx_blk_ctl_dev_data imx8mp_media_blk_ctl_dev_data __initconst = { + .hws = imx8mp_media_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_media_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_MEDIA_BLK_CTL_END, + .resets_max = IMX8MP_MEDIA_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 2, + .pm_runtime_saved_regs = { + IMX_MEDIA_BLK_CTL_SFT_RSTN, + IMX_MEDIA_BLK_CTL_CLK_EN, + }, +}; + +const struct imx_blk_ctl_dev_data imx8mp_audio_blk_ctl_dev_data __initconst = { + .hws = imx8mp_audio_blk_ctl_hws, + .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctl_hws), + .clocks_max = IMX8MP_CLK_AUDIO_BLK_CTL_END, + .resets_max = IMX8MP_AUDIO_BLK_CTL_RESET_NUM, + .pm_runtime_saved_regs_num = 16, + .pm_runtime_saved_regs = { + IMX_AUDIO_BLK_CTL_CLKEN0, + IMX_AUDIO_BLK_CTL_CLKEN1, + IMX_AUDIO_BLK_CTL_EARC, + IMX_AUDIO_BLK_CTL_SAI1_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI2_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI3_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI5_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI6_MCLK_SEL, + IMX_AUDIO_BLK_CTL_SAI7_MCLK_SEL, + IMX_AUDIO_BLK_CTL_PDM_CLK, + IMX_AUDIO_BLK_CTL_SAI_PLL_GNRL_CTL, + IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL0, + IMX_AUDIO_BLK_CTL_SAI_PLL_FDIVL_CTL1, + IMX_AUDIO_BLK_CTL_SAI_PLL_SSCG_CTL, + IMX_AUDIO_BLK_CTL_SAI_PLL_MNIT_CTL, + IMX_AUDIO_BLK_CTL_IPG_LP_CTRL + }, +}; + +static const struct of_device_id imx8mp_blk_ctl_of_match[] = { + { + .compatible = "fsl,imx8mp-audio-blk-ctl", + .data = &imx8mp_audio_blk_ctl_dev_data + }, + { + .compatible = "fsl,imx8mp-media-blk-ctl", + .data = &imx8mp_media_blk_ctl_dev_data + }, + { + .compatible = "fsl,imx8mp-hdmi-blk-ctl", + .data = &imx8mp_hdmi_blk_ctl_dev_data + }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8mp_blk_ctl_of_match); + +static int imx8mp_blk_ctl_probe(struct platform_device *pdev) +{ + return imx_blk_ctl_register(pdev); +} + +static struct platform_driver imx8mp_blk_ctl_driver = { + .probe = imx8mp_blk_ctl_probe, + .driver = { + .name = "imx8mp-blk-ctl", + .of_match_table = of_match_ptr(imx8mp_blk_ctl_of_match), + .pm = &imx_blk_ctl_pm_ops, + }, +}; +module_platform_driver(imx8mp_blk_ctl_driver); -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 11/14] clk: imx: Add blk-ctl driver for i.MX8MP 2020-11-03 11:18 ` Abel Vesa @ 2020-11-05 1:09 ` Stephen Boyd -1 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:09 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Quoting Abel Vesa (2020-11-03 03:18:23) > This driver is intended to work with the following BLK_CTL IPs found in > i.MX8MP: > - Audio > - Media > - HDMI > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org> ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 11/14] clk: imx: Add blk-ctl driver for i.MX8MP @ 2020-11-05 1:09 ` Stephen Boyd 0 siblings, 0 replies; 72+ messages in thread From: Stephen Boyd @ 2020-11-05 1:09 UTC (permalink / raw) To: Abel Vesa, Adam Ford, Anson Huang, Dong Aisheng, Fabio Estevam, Jacky Bai, Lucas Stach, Marek Vasut, Mike Turquette, Peng Fan, Rob Herring, Sascha Hauer, Shawn Guo Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Quoting Abel Vesa (2020-11-03 03:18:23) > This driver is intended to work with the following BLK_CTL IPs found in > i.MX8MP: > - Audio > - Media > - HDMI > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- Reviewed-by: Stephen Boyd <sboyd@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 12/14] arm64: dts: imx8mp: Add audio_blk_ctl node 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Some of the features of the audio_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 4793122..3716119 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -743,6 +743,21 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x50c>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 12/14] arm64: dts: imx8mp: Add audio_blk_ctl node @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Some of the features of the audio_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 4793122..3716119 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -743,6 +743,21 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + audio_blk_ctl: clock-controller@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctl", "syscon"; + reg = <0x30e20000 0x50c>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 13/14] arm64: dts: imx8mp: Add media_blk_ctl node 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Some of the features of the media_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3716119..8e1a01f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -743,6 +743,21 @@ }; }; + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + media_blk_ctl: clock-controller@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctl", "syscon"; + reg = <0x32ec0000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + aips5: bus@30c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30c00000 0x400000>; -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 13/14] arm64: dts: imx8mp: Add media_blk_ctl node @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Some of the features of the media_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3716119..8e1a01f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -743,6 +743,21 @@ }; }; + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + media_blk_ctl: clock-controller@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctl", "syscon"; + reg = <0x32ec0000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + aips5: bus@30c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30c00000 0x400000>; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 14/14] arm64: dts: imx8mp: Add hdmi_blk_ctl node 2020-11-03 11:18 ` Abel Vesa @ 2020-11-03 11:18 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, Abel Vesa Some of the features of the hdmi_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 8e1a01f..f1c5a07d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -756,6 +756,13 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + hdmi_blk_ctl: clock-controller@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctl", "syscon"; + reg = <0x32fc0000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; aips5: bus@30c00000 { -- 2.7.4 ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v5 14/14] arm64: dts: imx8mp: Add hdmi_blk_ctl node @ 2020-11-03 11:18 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2020-11-03 11:18 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng Cc: devicetree, Abel Vesa, Linux Kernel Mailing List, NXP Linux Team, linux-clk, linux-arm-kernel Some of the features of the hdmi_ctl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctl driver. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 8e1a01f..f1c5a07d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -756,6 +756,13 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + hdmi_blk_ctl: clock-controller@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctl", "syscon"; + reg = <0x32fc0000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; aips5: bus@30c00000 { -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP 2020-11-03 11:18 ` Abel Vesa @ 2021-03-03 10:47 ` Abel Vesa -1 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2021-03-03 10:47 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, pete.zhang, marex Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, linux-pm On 20-11-03 13:18:12, Abel Vesa wrote: > The BLK_CTL according to HW design is basically the wrapper of the entire > function specific group of IPs and holds GPRs that usually cannot be placed > into one specific IP from that group. Some of these GPRs are used to control > some clocks, other some resets, others some very specific function that does > not fit into clocks or resets. Since the clocks are registered using the i.MX > clock subsystem API, the driver is placed into the clock subsystem, but it > also registers the resets. For the other functionalities that other GPRs might > have, the syscon is used. > This approach seems to be introducing a possible ABBA deadlock due to the core clock and genpd locking. Here is a backtrace I got from Pete Zhang (he reported the issue on the internal mailing list): [ 11.667711][ T108] -> #1 (&genpd->mlock){+.+.}-{3:3}: [ 11.675041][ T108] __lock_acquire+0xae4/0xef8 [ 11.680093][ T108] lock_acquire+0xfc/0x2f8 [ 11.684888][ T108] __mutex_lock+0x90/0x870 [ 11.689685][ T108] mutex_lock_nested+0x44/0x50 [ 11.694826][ T108] genpd_lock_mtx+0x18/0x24 [ 11.699706][ T108] genpd_runtime_resume+0x90/0x214 (hold genpd->mlock) [ 11.705194][ T108] __rpm_callback+0x80/0x2c0 [ 11.710160][ T108] rpm_resume+0x468/0x650 [ 11.714866][ T108] __pm_runtime_resume+0x60/0x88 [ 11.720180][ T108] clk_pm_runtime_get+0x28/0x9c [ 11.725410][ T108] clk_disable_unused_subtree+0x8c/0x144 [ 11.731420][ T108] clk_disable_unused_subtree+0x124/0x144 [ 11.737518][ T108] clk_disable_unused+0xa4/0x11c (hold prepare_lock) [ 11.742833][ T108] do_one_initcall+0x98/0x178 [ 11.747888][ T108] do_initcall_level+0x9c/0xb8 [ 11.753028][ T108] do_initcalls+0x54/0x94 [ 11.757736][ T108] do_basic_setup+0x24/0x30 [ 11.762614][ T108] kernel_init_freeable+0x70/0xa4 [ 11.768014][ T108] kernel_init+0x14/0x18c [ 11.772722][ T108] ret_from_fork+0x10/0x18 [ 11.777512][ T108] -> #0 (prepare_lock){+.+.}-{3:3}: [ 11.784749][ T108] check_noncircular+0x134/0x13c [ 11.790064][ T108] validate_chain+0x590/0x2a04 [ 11.795204][ T108] __lock_acquire+0xae4/0xef8 [ 11.800258][ T108] lock_acquire+0xfc/0x2f8 [ 11.805050][ T108] __mutex_lock+0x90/0x870 [ 11.809841][ T108] mutex_lock_nested+0x44/0x50 [ 11.814983][ T108] clk_unprepare+0x5c/0x100 ((hold prepare_lock)) [ 11.819864][ T108] imx8m_pd_power_off+0xac/0x110 [ 11.825179][ T108] genpd_power_off+0x1b4/0x2dc [ 11.830318][ T108] genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock) [ 11.835981][ T108] process_one_work+0x270/0x444 [ 11.841208][ T108] worker_thread+0x280/0x4e4 [ 11.846176][ T108] kthread+0x13c/0x14 [ 11.850621][ T108] ret_from_fork+0x10/0x18 Now, this has been reproduced only on the NXP internal tree, but I think it is pretty obvious this could happen in upstream too, with this patchset applied. First, my thought was to change the prepare_lock/enable_lock in clock core, from a global approach to a per clock basis. But that doesn't actually fix the issue. The usecase seen above is due to clk_disable_unused, but the same could happen when a clock consumer calls prepare/unprepare on a clock. I guess the conclusion is that the current state of the clock core and genpd implementation does not support a usecase where a clock controller has a PD which in turn uses another clock (from another clock controller). Jacky, Pete, did I miss anything here ? > Changes since v4: > * added back the bus_blk_clk in the imx8mp blk_ctl driver (media_blk_ctl) > * added the R-b tag from Rob to the documentation patch > > Abel Vesa (14): > dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to > audio_blk_ctl > dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs > dt-bindings: clock: imx8mp: Add ids for the audio shared gate > dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs > dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs > dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs > dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs > clk: imx8mp: Add audio shared gate > Documentation: bindings: clk: Add bindings for i.MX BLK_CTL > clk: imx: Add generic blk-ctl driver > clk: imx: Add blk-ctl driver for i.MX8MP > arm64: dts: imx8mp: Add audio_blk_ctl node > arm64: dts: imx8mp: Add media_blk_ctl node > arm64: dts: imx8mp: Add hdmi_blk_ctl node > > .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++ > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 37 +++ > drivers/clk/imx/Makefile | 2 +- > drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++++++++++++++++++++ > drivers/clk/imx/clk-blk-ctl.c | 302 ++++++++++++++++++++ > drivers/clk/imx/clk-blk-ctl.h | 80 ++++++ > drivers/clk/imx/clk-imx8mp.c | 12 +- > include/dt-bindings/clock/imx8mp-clock.h | 200 +++++++++---- > include/dt-bindings/reset/imx8mp-reset.h | 45 +++ > 9 files changed, 992 insertions(+), 63 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c > create mode 100644 drivers/clk/imx/clk-blk-ctl.c > create mode 100644 drivers/clk/imx/clk-blk-ctl.h > > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP @ 2021-03-03 10:47 ` Abel Vesa 0 siblings, 0 replies; 72+ messages in thread From: Abel Vesa @ 2021-03-03 10:47 UTC (permalink / raw) To: Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, pete.zhang, marex Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, linux-pm On 20-11-03 13:18:12, Abel Vesa wrote: > The BLK_CTL according to HW design is basically the wrapper of the entire > function specific group of IPs and holds GPRs that usually cannot be placed > into one specific IP from that group. Some of these GPRs are used to control > some clocks, other some resets, others some very specific function that does > not fit into clocks or resets. Since the clocks are registered using the i.MX > clock subsystem API, the driver is placed into the clock subsystem, but it > also registers the resets. For the other functionalities that other GPRs might > have, the syscon is used. > This approach seems to be introducing a possible ABBA deadlock due to the core clock and genpd locking. Here is a backtrace I got from Pete Zhang (he reported the issue on the internal mailing list): [ 11.667711][ T108] -> #1 (&genpd->mlock){+.+.}-{3:3}: [ 11.675041][ T108] __lock_acquire+0xae4/0xef8 [ 11.680093][ T108] lock_acquire+0xfc/0x2f8 [ 11.684888][ T108] __mutex_lock+0x90/0x870 [ 11.689685][ T108] mutex_lock_nested+0x44/0x50 [ 11.694826][ T108] genpd_lock_mtx+0x18/0x24 [ 11.699706][ T108] genpd_runtime_resume+0x90/0x214 (hold genpd->mlock) [ 11.705194][ T108] __rpm_callback+0x80/0x2c0 [ 11.710160][ T108] rpm_resume+0x468/0x650 [ 11.714866][ T108] __pm_runtime_resume+0x60/0x88 [ 11.720180][ T108] clk_pm_runtime_get+0x28/0x9c [ 11.725410][ T108] clk_disable_unused_subtree+0x8c/0x144 [ 11.731420][ T108] clk_disable_unused_subtree+0x124/0x144 [ 11.737518][ T108] clk_disable_unused+0xa4/0x11c (hold prepare_lock) [ 11.742833][ T108] do_one_initcall+0x98/0x178 [ 11.747888][ T108] do_initcall_level+0x9c/0xb8 [ 11.753028][ T108] do_initcalls+0x54/0x94 [ 11.757736][ T108] do_basic_setup+0x24/0x30 [ 11.762614][ T108] kernel_init_freeable+0x70/0xa4 [ 11.768014][ T108] kernel_init+0x14/0x18c [ 11.772722][ T108] ret_from_fork+0x10/0x18 [ 11.777512][ T108] -> #0 (prepare_lock){+.+.}-{3:3}: [ 11.784749][ T108] check_noncircular+0x134/0x13c [ 11.790064][ T108] validate_chain+0x590/0x2a04 [ 11.795204][ T108] __lock_acquire+0xae4/0xef8 [ 11.800258][ T108] lock_acquire+0xfc/0x2f8 [ 11.805050][ T108] __mutex_lock+0x90/0x870 [ 11.809841][ T108] mutex_lock_nested+0x44/0x50 [ 11.814983][ T108] clk_unprepare+0x5c/0x100 ((hold prepare_lock)) [ 11.819864][ T108] imx8m_pd_power_off+0xac/0x110 [ 11.825179][ T108] genpd_power_off+0x1b4/0x2dc [ 11.830318][ T108] genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock) [ 11.835981][ T108] process_one_work+0x270/0x444 [ 11.841208][ T108] worker_thread+0x280/0x4e4 [ 11.846176][ T108] kthread+0x13c/0x14 [ 11.850621][ T108] ret_from_fork+0x10/0x18 Now, this has been reproduced only on the NXP internal tree, but I think it is pretty obvious this could happen in upstream too, with this patchset applied. First, my thought was to change the prepare_lock/enable_lock in clock core, from a global approach to a per clock basis. But that doesn't actually fix the issue. The usecase seen above is due to clk_disable_unused, but the same could happen when a clock consumer calls prepare/unprepare on a clock. I guess the conclusion is that the current state of the clock core and genpd implementation does not support a usecase where a clock controller has a PD which in turn uses another clock (from another clock controller). Jacky, Pete, did I miss anything here ? > Changes since v4: > * added back the bus_blk_clk in the imx8mp blk_ctl driver (media_blk_ctl) > * added the R-b tag from Rob to the documentation patch > > Abel Vesa (14): > dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to > audio_blk_ctl > dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs > dt-bindings: clock: imx8mp: Add ids for the audio shared gate > dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs > dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs > dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs > dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs > clk: imx8mp: Add audio shared gate > Documentation: bindings: clk: Add bindings for i.MX BLK_CTL > clk: imx: Add generic blk-ctl driver > clk: imx: Add blk-ctl driver for i.MX8MP > arm64: dts: imx8mp: Add audio_blk_ctl node > arm64: dts: imx8mp: Add media_blk_ctl node > arm64: dts: imx8mp: Add hdmi_blk_ctl node > > .../devicetree/bindings/clock/fsl,imx-blk-ctl.yaml | 60 ++++ > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 37 +++ > drivers/clk/imx/Makefile | 2 +- > drivers/clk/imx/clk-blk-ctl-imx8mp.c | 317 +++++++++++++++++++++ > drivers/clk/imx/clk-blk-ctl.c | 302 ++++++++++++++++++++ > drivers/clk/imx/clk-blk-ctl.h | 80 ++++++ > drivers/clk/imx/clk-imx8mp.c | 12 +- > include/dt-bindings/clock/imx8mp-clock.h | 200 +++++++++---- > include/dt-bindings/reset/imx8mp-reset.h | 45 +++ > 9 files changed, 992 insertions(+), 63 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctl.yaml > create mode 100644 drivers/clk/imx/clk-blk-ctl-imx8mp.c > create mode 100644 drivers/clk/imx/clk-blk-ctl.c > create mode 100644 drivers/clk/imx/clk-blk-ctl.h > > -- > 2.7.4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP 2021-03-03 10:47 ` Abel Vesa @ 2021-03-03 10:54 ` Marek Vasut -1 siblings, 0 replies; 72+ messages in thread From: Marek Vasut @ 2021-03-03 10:54 UTC (permalink / raw) To: Abel Vesa Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, linux-pm, Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, pete.zhang, Claudius Heine On 3/3/21 11:47 AM, Abel Vesa wrote: > On 20-11-03 13:18:12, Abel Vesa wrote: >> The BLK_CTL according to HW design is basically the wrapper of the entire >> function specific group of IPs and holds GPRs that usually cannot be placed >> into one specific IP from that group. Some of these GPRs are used to control >> some clocks, other some resets, others some very specific function that does >> not fit into clocks or resets. Since the clocks are registered using the i.MX >> clock subsystem API, the driver is placed into the clock subsystem, but it >> also registers the resets. For the other functionalities that other GPRs might >> have, the syscon is used. >> > > This approach seems to be introducing a possible ABBA deadlock due to > the core clock and genpd locking. Here is a backtrace I got from Pete > Zhang (he reported the issue on the internal mailing list): > > [ 11.667711][ T108] -> #1 (&genpd->mlock){+.+.}-{3:3}: > [ 11.675041][ T108] __lock_acquire+0xae4/0xef8 > [ 11.680093][ T108] lock_acquire+0xfc/0x2f8 > [ 11.684888][ T108] __mutex_lock+0x90/0x870 > [ 11.689685][ T108] mutex_lock_nested+0x44/0x50 > [ 11.694826][ T108] genpd_lock_mtx+0x18/0x24 > [ 11.699706][ T108] genpd_runtime_resume+0x90/0x214 (hold genpd->mlock) > [ 11.705194][ T108] __rpm_callback+0x80/0x2c0 > [ 11.710160][ T108] rpm_resume+0x468/0x650 > [ 11.714866][ T108] __pm_runtime_resume+0x60/0x88 > [ 11.720180][ T108] clk_pm_runtime_get+0x28/0x9c > [ 11.725410][ T108] clk_disable_unused_subtree+0x8c/0x144 > [ 11.731420][ T108] clk_disable_unused_subtree+0x124/0x144 > [ 11.737518][ T108] clk_disable_unused+0xa4/0x11c (hold prepare_lock) > [ 11.742833][ T108] do_one_initcall+0x98/0x178 > [ 11.747888][ T108] do_initcall_level+0x9c/0xb8 > [ 11.753028][ T108] do_initcalls+0x54/0x94 > [ 11.757736][ T108] do_basic_setup+0x24/0x30 > [ 11.762614][ T108] kernel_init_freeable+0x70/0xa4 > [ 11.768014][ T108] kernel_init+0x14/0x18c > [ 11.772722][ T108] ret_from_fork+0x10/0x18 > > [ 11.777512][ T108] -> #0 (prepare_lock){+.+.}-{3:3}: > [ 11.784749][ T108] check_noncircular+0x134/0x13c > [ 11.790064][ T108] validate_chain+0x590/0x2a04 > [ 11.795204][ T108] __lock_acquire+0xae4/0xef8 > [ 11.800258][ T108] lock_acquire+0xfc/0x2f8 > [ 11.805050][ T108] __mutex_lock+0x90/0x870 > [ 11.809841][ T108] mutex_lock_nested+0x44/0x50 > [ 11.814983][ T108] clk_unprepare+0x5c/0x100 ((hold prepare_lock)) > [ 11.819864][ T108] imx8m_pd_power_off+0xac/0x110 > [ 11.825179][ T108] genpd_power_off+0x1b4/0x2dc > [ 11.830318][ T108] genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock) > [ 11.835981][ T108] process_one_work+0x270/0x444 > [ 11.841208][ T108] worker_thread+0x280/0x4e4 > [ 11.846176][ T108] kthread+0x13c/0x14 > [ 11.850621][ T108] ret_from_fork+0x10/0x18 > > Now, this has been reproduced only on the NXP internal tree, but I think > it is pretty obvious this could happen in upstream too, with this > patchset applied. > > First, my thought was to change the prepare_lock/enable_lock in clock > core, from a global approach to a per clock basis. But that doesn't > actually fix the issue. > > The usecase seen above is due to clk_disable_unused, but the same could > happen when a clock consumer calls prepare/unprepare on a clock. > > I guess the conclusion is that the current state of the clock core and > genpd implementation does not support a usecase where a clock controller > has a PD which in turn uses another clock (from another clock controller). > > Jacky, Pete, did I miss anything here ? Just for completeness, I have a feeling I already managed to trigger this and discussed this with Lucas before, so this concern is certainly valid. ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP @ 2021-03-03 10:54 ` Marek Vasut 0 siblings, 0 replies; 72+ messages in thread From: Marek Vasut @ 2021-03-03 10:54 UTC (permalink / raw) To: Abel Vesa Cc: NXP Linux Team, linux-arm-kernel, Linux Kernel Mailing List, linux-clk, devicetree, linux-pm, Mike Turquette, Stephen Boyd, Adam Ford, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, pete.zhang, Claudius Heine On 3/3/21 11:47 AM, Abel Vesa wrote: > On 20-11-03 13:18:12, Abel Vesa wrote: >> The BLK_CTL according to HW design is basically the wrapper of the entire >> function specific group of IPs and holds GPRs that usually cannot be placed >> into one specific IP from that group. Some of these GPRs are used to control >> some clocks, other some resets, others some very specific function that does >> not fit into clocks or resets. Since the clocks are registered using the i.MX >> clock subsystem API, the driver is placed into the clock subsystem, but it >> also registers the resets. For the other functionalities that other GPRs might >> have, the syscon is used. >> > > This approach seems to be introducing a possible ABBA deadlock due to > the core clock and genpd locking. Here is a backtrace I got from Pete > Zhang (he reported the issue on the internal mailing list): > > [ 11.667711][ T108] -> #1 (&genpd->mlock){+.+.}-{3:3}: > [ 11.675041][ T108] __lock_acquire+0xae4/0xef8 > [ 11.680093][ T108] lock_acquire+0xfc/0x2f8 > [ 11.684888][ T108] __mutex_lock+0x90/0x870 > [ 11.689685][ T108] mutex_lock_nested+0x44/0x50 > [ 11.694826][ T108] genpd_lock_mtx+0x18/0x24 > [ 11.699706][ T108] genpd_runtime_resume+0x90/0x214 (hold genpd->mlock) > [ 11.705194][ T108] __rpm_callback+0x80/0x2c0 > [ 11.710160][ T108] rpm_resume+0x468/0x650 > [ 11.714866][ T108] __pm_runtime_resume+0x60/0x88 > [ 11.720180][ T108] clk_pm_runtime_get+0x28/0x9c > [ 11.725410][ T108] clk_disable_unused_subtree+0x8c/0x144 > [ 11.731420][ T108] clk_disable_unused_subtree+0x124/0x144 > [ 11.737518][ T108] clk_disable_unused+0xa4/0x11c (hold prepare_lock) > [ 11.742833][ T108] do_one_initcall+0x98/0x178 > [ 11.747888][ T108] do_initcall_level+0x9c/0xb8 > [ 11.753028][ T108] do_initcalls+0x54/0x94 > [ 11.757736][ T108] do_basic_setup+0x24/0x30 > [ 11.762614][ T108] kernel_init_freeable+0x70/0xa4 > [ 11.768014][ T108] kernel_init+0x14/0x18c > [ 11.772722][ T108] ret_from_fork+0x10/0x18 > > [ 11.777512][ T108] -> #0 (prepare_lock){+.+.}-{3:3}: > [ 11.784749][ T108] check_noncircular+0x134/0x13c > [ 11.790064][ T108] validate_chain+0x590/0x2a04 > [ 11.795204][ T108] __lock_acquire+0xae4/0xef8 > [ 11.800258][ T108] lock_acquire+0xfc/0x2f8 > [ 11.805050][ T108] __mutex_lock+0x90/0x870 > [ 11.809841][ T108] mutex_lock_nested+0x44/0x50 > [ 11.814983][ T108] clk_unprepare+0x5c/0x100 ((hold prepare_lock)) > [ 11.819864][ T108] imx8m_pd_power_off+0xac/0x110 > [ 11.825179][ T108] genpd_power_off+0x1b4/0x2dc > [ 11.830318][ T108] genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock) > [ 11.835981][ T108] process_one_work+0x270/0x444 > [ 11.841208][ T108] worker_thread+0x280/0x4e4 > [ 11.846176][ T108] kthread+0x13c/0x14 > [ 11.850621][ T108] ret_from_fork+0x10/0x18 > > Now, this has been reproduced only on the NXP internal tree, but I think > it is pretty obvious this could happen in upstream too, with this > patchset applied. > > First, my thought was to change the prepare_lock/enable_lock in clock > core, from a global approach to a per clock basis. But that doesn't > actually fix the issue. > > The usecase seen above is due to clk_disable_unused, but the same could > happen when a clock consumer calls prepare/unprepare on a clock. > > I guess the conclusion is that the current state of the clock core and > genpd implementation does not support a usecase where a clock controller > has a PD which in turn uses another clock (from another clock controller). > > Jacky, Pete, did I miss anything here ? Just for completeness, I have a feeling I already managed to trigger this and discussed this with Lucas before, so this concern is certainly valid. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP 2021-03-03 10:54 ` Marek Vasut @ 2021-03-22 23:49 ` Adam Ford -1 siblings, 0 replies; 72+ messages in thread From: Adam Ford @ 2021-03-22 23:49 UTC (permalink / raw) To: Marek Vasut Cc: Abel Vesa, NXP Linux Team, arm-soc, Linux Kernel Mailing List, linux-clk, devicetree, linux-pm, Mike Turquette, Stephen Boyd, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, pete.zhang, Claudius Heine On Wed, Mar 3, 2021 at 4:54 AM Marek Vasut <marex@denx.de> wrote: > > On 3/3/21 11:47 AM, Abel Vesa wrote: > > On 20-11-03 13:18:12, Abel Vesa wrote: > >> The BLK_CTL according to HW design is basically the wrapper of the entire > >> function specific group of IPs and holds GPRs that usually cannot be placed > >> into one specific IP from that group. Some of these GPRs are used to control > >> some clocks, other some resets, others some very specific function that does > >> not fit into clocks or resets. Since the clocks are registered using the i.MX > >> clock subsystem API, the driver is placed into the clock subsystem, but it > >> also registers the resets. For the other functionalities that other GPRs might > >> have, the syscon is used. > >> > > > > This approach seems to be introducing a possible ABBA deadlock due to > > the core clock and genpd locking. Here is a backtrace I got from Pete > > Zhang (he reported the issue on the internal mailing list): > > > > [ 11.667711][ T108] -> #1 (&genpd->mlock){+.+.}-{3:3}: > > [ 11.675041][ T108] __lock_acquire+0xae4/0xef8 > > [ 11.680093][ T108] lock_acquire+0xfc/0x2f8 > > [ 11.684888][ T108] __mutex_lock+0x90/0x870 > > [ 11.689685][ T108] mutex_lock_nested+0x44/0x50 > > [ 11.694826][ T108] genpd_lock_mtx+0x18/0x24 > > [ 11.699706][ T108] genpd_runtime_resume+0x90/0x214 (hold genpd->mlock) > > [ 11.705194][ T108] __rpm_callback+0x80/0x2c0 > > [ 11.710160][ T108] rpm_resume+0x468/0x650 > > [ 11.714866][ T108] __pm_runtime_resume+0x60/0x88 > > [ 11.720180][ T108] clk_pm_runtime_get+0x28/0x9c > > [ 11.725410][ T108] clk_disable_unused_subtree+0x8c/0x144 > > [ 11.731420][ T108] clk_disable_unused_subtree+0x124/0x144 > > [ 11.737518][ T108] clk_disable_unused+0xa4/0x11c (hold prepare_lock) > > [ 11.742833][ T108] do_one_initcall+0x98/0x178 > > [ 11.747888][ T108] do_initcall_level+0x9c/0xb8 > > [ 11.753028][ T108] do_initcalls+0x54/0x94 > > [ 11.757736][ T108] do_basic_setup+0x24/0x30 > > [ 11.762614][ T108] kernel_init_freeable+0x70/0xa4 > > [ 11.768014][ T108] kernel_init+0x14/0x18c > > [ 11.772722][ T108] ret_from_fork+0x10/0x18 > > > > [ 11.777512][ T108] -> #0 (prepare_lock){+.+.}-{3:3}: > > [ 11.784749][ T108] check_noncircular+0x134/0x13c > > [ 11.790064][ T108] validate_chain+0x590/0x2a04 > > [ 11.795204][ T108] __lock_acquire+0xae4/0xef8 > > [ 11.800258][ T108] lock_acquire+0xfc/0x2f8 > > [ 11.805050][ T108] __mutex_lock+0x90/0x870 > > [ 11.809841][ T108] mutex_lock_nested+0x44/0x50 > > [ 11.814983][ T108] clk_unprepare+0x5c/0x100 ((hold prepare_lock)) > > [ 11.819864][ T108] imx8m_pd_power_off+0xac/0x110 > > [ 11.825179][ T108] genpd_power_off+0x1b4/0x2dc > > [ 11.830318][ T108] genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock) > > [ 11.835981][ T108] process_one_work+0x270/0x444 > > [ 11.841208][ T108] worker_thread+0x280/0x4e4 > > [ 11.846176][ T108] kthread+0x13c/0x14 > > [ 11.850621][ T108] ret_from_fork+0x10/0x18 > > > > Now, this has been reproduced only on the NXP internal tree, but I think > > it is pretty obvious this could happen in upstream too, with this > > patchset applied. > > > > First, my thought was to change the prepare_lock/enable_lock in clock > > core, from a global approach to a per clock basis. But that doesn't > > actually fix the issue. > > > > The usecase seen above is due to clk_disable_unused, but the same could > > happen when a clock consumer calls prepare/unprepare on a clock. > > > > I guess the conclusion is that the current state of the clock core and > > genpd implementation does not support a usecase where a clock controller > > has a PD which in turn uses another clock (from another clock controller). > > > > Jacky, Pete, did I miss anything here ? > > Just for completeness, I have a feeling I already managed to trigger > this and discussed this with Lucas before, so this concern is certainly > valid. I know it may not be ideal, someone tied a soft-reset and soft-enable to the driver of the Hantro VPU on the IMXMQ [1], and I wonder if something similar could be done for the drivers who are consumers of the clocks. For example: lcdif could request the power domain. The power domain soft-resets and enables bus clock (vis syscon) After successful enabling of power-domain, the LCDIF requests the soft reset and respective clock bits (also via syscon) similar to how [1] and [2] do it for the Hantro VPU. The syscon node could be a common node similar to what was done in [2], and multiple consumers could control when each soft-reset and clock-enable get activated. I know it's probably more of an abuse of the syscon system, but having the individual drivers control the order of operations might be safer than trying to create a one-size-fits-all driver. adam [1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210318082046.51546-4-benjamin.gaignard@collabora.com/ [2] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210318082046.51546-14-benjamin.gaignard@collabora.com/ ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP @ 2021-03-22 23:49 ` Adam Ford 0 siblings, 0 replies; 72+ messages in thread From: Adam Ford @ 2021-03-22 23:49 UTC (permalink / raw) To: Marek Vasut Cc: Abel Vesa, NXP Linux Team, arm-soc, Linux Kernel Mailing List, linux-clk, devicetree, linux-pm, Mike Turquette, Stephen Boyd, Marek Vasut, Lucas Stach, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Anson Huang, Jacky Bai, Peng Fan, Dong Aisheng, pete.zhang, Claudius Heine On Wed, Mar 3, 2021 at 4:54 AM Marek Vasut <marex@denx.de> wrote: > > On 3/3/21 11:47 AM, Abel Vesa wrote: > > On 20-11-03 13:18:12, Abel Vesa wrote: > >> The BLK_CTL according to HW design is basically the wrapper of the entire > >> function specific group of IPs and holds GPRs that usually cannot be placed > >> into one specific IP from that group. Some of these GPRs are used to control > >> some clocks, other some resets, others some very specific function that does > >> not fit into clocks or resets. Since the clocks are registered using the i.MX > >> clock subsystem API, the driver is placed into the clock subsystem, but it > >> also registers the resets. For the other functionalities that other GPRs might > >> have, the syscon is used. > >> > > > > This approach seems to be introducing a possible ABBA deadlock due to > > the core clock and genpd locking. Here is a backtrace I got from Pete > > Zhang (he reported the issue on the internal mailing list): > > > > [ 11.667711][ T108] -> #1 (&genpd->mlock){+.+.}-{3:3}: > > [ 11.675041][ T108] __lock_acquire+0xae4/0xef8 > > [ 11.680093][ T108] lock_acquire+0xfc/0x2f8 > > [ 11.684888][ T108] __mutex_lock+0x90/0x870 > > [ 11.689685][ T108] mutex_lock_nested+0x44/0x50 > > [ 11.694826][ T108] genpd_lock_mtx+0x18/0x24 > > [ 11.699706][ T108] genpd_runtime_resume+0x90/0x214 (hold genpd->mlock) > > [ 11.705194][ T108] __rpm_callback+0x80/0x2c0 > > [ 11.710160][ T108] rpm_resume+0x468/0x650 > > [ 11.714866][ T108] __pm_runtime_resume+0x60/0x88 > > [ 11.720180][ T108] clk_pm_runtime_get+0x28/0x9c > > [ 11.725410][ T108] clk_disable_unused_subtree+0x8c/0x144 > > [ 11.731420][ T108] clk_disable_unused_subtree+0x124/0x144 > > [ 11.737518][ T108] clk_disable_unused+0xa4/0x11c (hold prepare_lock) > > [ 11.742833][ T108] do_one_initcall+0x98/0x178 > > [ 11.747888][ T108] do_initcall_level+0x9c/0xb8 > > [ 11.753028][ T108] do_initcalls+0x54/0x94 > > [ 11.757736][ T108] do_basic_setup+0x24/0x30 > > [ 11.762614][ T108] kernel_init_freeable+0x70/0xa4 > > [ 11.768014][ T108] kernel_init+0x14/0x18c > > [ 11.772722][ T108] ret_from_fork+0x10/0x18 > > > > [ 11.777512][ T108] -> #0 (prepare_lock){+.+.}-{3:3}: > > [ 11.784749][ T108] check_noncircular+0x134/0x13c > > [ 11.790064][ T108] validate_chain+0x590/0x2a04 > > [ 11.795204][ T108] __lock_acquire+0xae4/0xef8 > > [ 11.800258][ T108] lock_acquire+0xfc/0x2f8 > > [ 11.805050][ T108] __mutex_lock+0x90/0x870 > > [ 11.809841][ T108] mutex_lock_nested+0x44/0x50 > > [ 11.814983][ T108] clk_unprepare+0x5c/0x100 ((hold prepare_lock)) > > [ 11.819864][ T108] imx8m_pd_power_off+0xac/0x110 > > [ 11.825179][ T108] genpd_power_off+0x1b4/0x2dc > > [ 11.830318][ T108] genpd_power_off_work_fn+0x38/0x58 (hold genpd->mlock) > > [ 11.835981][ T108] process_one_work+0x270/0x444 > > [ 11.841208][ T108] worker_thread+0x280/0x4e4 > > [ 11.846176][ T108] kthread+0x13c/0x14 > > [ 11.850621][ T108] ret_from_fork+0x10/0x18 > > > > Now, this has been reproduced only on the NXP internal tree, but I think > > it is pretty obvious this could happen in upstream too, with this > > patchset applied. > > > > First, my thought was to change the prepare_lock/enable_lock in clock > > core, from a global approach to a per clock basis. But that doesn't > > actually fix the issue. > > > > The usecase seen above is due to clk_disable_unused, but the same could > > happen when a clock consumer calls prepare/unprepare on a clock. > > > > I guess the conclusion is that the current state of the clock core and > > genpd implementation does not support a usecase where a clock controller > > has a PD which in turn uses another clock (from another clock controller). > > > > Jacky, Pete, did I miss anything here ? > > Just for completeness, I have a feeling I already managed to trigger > this and discussed this with Lucas before, so this concern is certainly > valid. I know it may not be ideal, someone tied a soft-reset and soft-enable to the driver of the Hantro VPU on the IMXMQ [1], and I wonder if something similar could be done for the drivers who are consumers of the clocks. For example: lcdif could request the power domain. The power domain soft-resets and enables bus clock (vis syscon) After successful enabling of power-domain, the LCDIF requests the soft reset and respective clock bits (also via syscon) similar to how [1] and [2] do it for the Hantro VPU. The syscon node could be a common node similar to what was done in [2], and multiple consumers could control when each soft-reset and clock-enable get activated. I know it's probably more of an abuse of the syscon system, but having the individual drivers control the order of operations might be safer than trying to create a one-size-fits-all driver. adam [1] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210318082046.51546-4-benjamin.gaignard@collabora.com/ [2] - https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210318082046.51546-14-benjamin.gaignard@collabora.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
end of thread, other threads:[~2021-03-22 23:51 UTC | newest] Thread overview: 72+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-11-03 11:18 [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-03 11:18 ` [PATCH v5 01/14] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctl Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:05 ` Stephen Boyd 2020-11-05 1:05 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 02/14] dt-bindings: reset: imx8mp: Add audio blk_ctl reset IDs Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:05 ` Stephen Boyd 2020-11-05 1:05 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 03/14] dt-bindings: clock: imx8mp: Add ids for the audio shared gate Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:05 ` Stephen Boyd 2020-11-05 1:05 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 04/14] dt-bindings: clock: imx8mp: Add media blk_ctl clock IDs Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:05 ` Stephen Boyd 2020-11-05 1:05 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 05/14] dt-bindings: reset: imx8mp: Add media blk_ctl reset IDs Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:06 ` Stephen Boyd 2020-11-05 1:06 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 06/14] dt-bindings: clock: imx8mp: Add hdmi blk_ctl clock IDs Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:06 ` Stephen Boyd 2020-11-05 1:06 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 07/14] dt-bindings: reset: imx8mp: Add hdmi blk_ctl reset IDs Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:06 ` Stephen Boyd 2020-11-05 1:06 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 08/14] clk: imx8mp: Add audio shared gate Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:07 ` Stephen Boyd 2020-11-05 1:07 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 09/14] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-04 19:01 ` Rob Herring 2020-11-04 19:01 ` Rob Herring 2020-11-05 1:08 ` Stephen Boyd 2020-11-05 1:08 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 10/14] clk: imx: Add generic blk-ctl driver Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 0:59 ` Stephen Boyd 2020-11-05 0:59 ` Stephen Boyd 2020-11-09 5:45 ` Jacky Bai 2020-11-09 5:45 ` Jacky Bai 2020-11-11 9:13 ` Dong Aisheng 2020-11-11 9:13 ` Dong Aisheng 2020-11-17 14:48 ` Abel Vesa 2020-11-17 14:48 ` Abel Vesa 2021-02-25 8:23 ` Frieder Schrempf 2021-02-25 8:23 ` Frieder Schrempf 2021-02-25 8:27 ` Jacky Bai 2021-02-25 8:27 ` Jacky Bai 2021-03-18 19:58 ` Tim Harvey 2021-03-18 19:58 ` Tim Harvey 2020-11-03 11:18 ` [PATCH v5 11/14] clk: imx: Add blk-ctl driver for i.MX8MP Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-05 1:09 ` Stephen Boyd 2020-11-05 1:09 ` Stephen Boyd 2020-11-03 11:18 ` [PATCH v5 12/14] arm64: dts: imx8mp: Add audio_blk_ctl node Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-03 11:18 ` [PATCH v5 13/14] arm64: dts: imx8mp: Add media_blk_ctl node Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2020-11-03 11:18 ` [PATCH v5 14/14] arm64: dts: imx8mp: Add hdmi_blk_ctl node Abel Vesa 2020-11-03 11:18 ` Abel Vesa 2021-03-03 10:47 ` [PATCH v5 00/14] Add BLK_CTL support for i.MX8MP Abel Vesa 2021-03-03 10:47 ` Abel Vesa 2021-03-03 10:54 ` Marek Vasut 2021-03-03 10:54 ` Marek Vasut 2021-03-22 23:49 ` Adam Ford 2021-03-22 23:49 ` Adam Ford
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