* [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
@ 2020-11-02 22:10 Chris Wilson
2020-11-02 22:10 ` [Intel-gfx] " Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Chris Wilson @ 2020-11-02 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Add another lower level to emit_ggtt_write so that the GGTT nature of
the write is not hardcoded into the emitter.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 55 ++++++++++++++++----------
1 file changed, 35 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 7c3a1012e702..760fefdfe392 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -245,22 +245,14 @@ static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u
}
static inline u32 *
-__gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
+__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
{
- /* We're using qword write, offset should be aligned to 8 bytes. */
- GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
-
- /* w/a for post sync ops following a GPGPU operation we
- * need a prior CS_STALL, which is emitted by the flush
- * following the batch.
- */
*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
- *cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
- *cs++ = gtt_offset;
+ *cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
+ *cs++ = offset;
*cs++ = 0;
*cs++ = value;
- /* We're thrashing one dword of HWS. */
- *cs++ = 0;
+ *cs++ = 0; /* We're thrashing one extra dword. */
return cs;
}
@@ -268,13 +260,38 @@ __gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 f
static inline u32*
gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
{
- return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
+ /* We're using qword write, offset should be aligned to 8 bytes. */
+ GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
+
+ return __gen8_emit_write_rcs(cs,
+ value,
+ gtt_offset,
+ 0,
+ flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
}
static inline u32*
gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
{
- return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, flags0, flags1);
+ /* We're using qword write, offset should be aligned to 8 bytes. */
+ GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
+
+ return __gen8_emit_write_rcs(cs,
+ value,
+ gtt_offset,
+ flags0,
+ flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
+}
+
+static inline u32 *
+__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+{
+ *cs++ = (MI_FLUSH_DW + 1) | flags;
+ *cs++ = gtt_offset;
+ *cs++ = 0;
+ *cs++ = value;
+
+ return cs;
}
static inline u32 *
@@ -285,12 +302,10 @@ gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
- *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
- *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
- *cs++ = 0;
- *cs++ = value;
-
- return cs;
+ return __gen8_emit_flush_dw(cs,
+ value,
+ gtt_offset | MI_FLUSH_DW_USE_GTT,
+ flags | MI_FLUSH_DW_OP_STOREDW);
}
static inline void __intel_engine_reset(struct intel_engine_cs *engine,
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
2020-11-02 22:10 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Chris Wilson
@ 2020-11-02 22:10 ` Chris Wilson
2020-11-02 23:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-11-02 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Mika Kuoppala, stable
In a simple test case that writes to scratch and then busy-waits for the
batch to be signaled, we observe that the signal is before the write is
posted. That is bad news.
Splitting the flush + write_dword into two separate flush_dw prevents
the issue from being reproduced, we can presume the post-sync op is not
so post-sync.
Testcase: igt/gem_exec_fence/parallel
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d0be98b67138..a437140a987d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5047,7 +5047,8 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
{
- return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
+ cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
+ return gen12_emit_fini_breadcrumb_tail(rq, cs);
}
static u32 *
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
@ 2020-11-02 22:10 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-11-02 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: stable, Chris Wilson
In a simple test case that writes to scratch and then busy-waits for the
batch to be signaled, we observe that the signal is before the write is
posted. That is bad news.
Splitting the flush + write_dword into two separate flush_dw prevents
the issue from being reproduced, we can presume the post-sync op is not
so post-sync.
Testcase: igt/gem_exec_fence/parallel
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d0be98b67138..a437140a987d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -5047,7 +5047,8 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
{
- return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
+ cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
+ return gen12_emit_fini_breadcrumb_tail(rq, cs);
}
static u32 *
--
2.20.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
2020-11-02 22:10 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Chris Wilson
2020-11-02 22:10 ` [Intel-gfx] " Chris Wilson
@ 2020-11-02 23:01 ` Patchwork
2020-11-02 23:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-11-02 23:01 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
URL : https://patchwork.freedesktop.org/series/83376/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
2020-11-02 22:10 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Chris Wilson
2020-11-02 22:10 ` [Intel-gfx] " Chris Wilson
2020-11-02 23:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Patchwork
@ 2020-11-02 23:25 ` Patchwork
2020-11-03 7:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-11-03 10:12 ` [Intel-gfx] [PATCH 1/2] " Mika Kuoppala
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-11-02 23:25 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 6465 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
URL : https://patchwork.freedesktop.org/series/83376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247 -> Patchwork_18832
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/index.html
New tests
---------
New tests have been introduced between CI_DRM_9247 and Patchwork_18832:
### New CI tests (1) ###
* boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18832 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@active:
- fi-cml-u2: [PASS][3] -> [DMESG-FAIL][4] ([i915#666])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-cml-u2/igt@i915_selftest@live@active.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-cml-u2/igt@i915_selftest@live@active.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][7] ([i915#1635] / [i915#1982]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-apl-guc/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-apl-guc/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-bsw-n3050/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][11] ([i915#2601]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [INCOMPLETE][13] ([i915#1635]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-tgl-dsi/igt@kms_busy@basic@flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-tgl-dsi/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
#### Warnings ####
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-gdg-551: [INCOMPLETE][23] ([i915#172]) -> [SKIP][24] ([fdo#109271])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/fi-gdg-551/igt@amdgpu/amd_prime@i915-to-amd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/fi-gdg-551/igt@amdgpu/amd_prime@i915-to-amd.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
Participating hosts (43 -> 39)
------------------------------
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9247 -> Patchwork_18832
CI-20190529: 20190529
CI_DRM_9247: 009a99e9be393d32ed57bcac34d6b1fb37c28cdf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18832: 33e74dd124ade0e803e61b0e3c111758c5b7023e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
33e74dd124ad drm/i915/gt: Flush xcs before tgl breadcrumbs
84a21f6284b4 drm/i915/gt: Expose more parameters for emitting writes into the ring
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
2020-11-02 22:10 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Chris Wilson
` (2 preceding siblings ...)
2020-11-02 23:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-11-03 7:16 ` Patchwork
2020-11-03 10:12 ` [Intel-gfx] [PATCH 1/2] " Mika Kuoppala
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2020-11-03 7:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
URL : https://patchwork.freedesktop.org/series/83376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9247_full -> Patchwork_18832_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_18832_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18832_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18832_full:
### IGT changes ###
#### Warnings ####
* igt@kms_flip@flip-vs-suspend-interruptible@d-edp1:
- shard-tglb: [DMESG-WARN][1] ([i915#2411]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
New tests
---------
New tests have been introduced between CI_DRM_9247_full and Patchwork_18832_full:
### New CI tests (1) ###
* boot:
- Statuses : 174 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18832_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_create@forked:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk2/igt@gem_exec_create@forked.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-glk5/igt@gem_exec_create@forked.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl6/igt@gem_workarounds@suspend-resume.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-kbl2/igt@gem_workarounds@suspend-resume.html
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
- shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-snb6/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-snb2/igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl7/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-kbl1/igt@kms_big_fb@y-tiled-32bpp-rotate-270.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / [i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-apl7/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-apl4/igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#1635] / [i915#79])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#79])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +7 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-skl: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@core_hotunplug@unbind-rebind.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl4/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_schedule@deep@vecs0:
- shard-skl: [INCOMPLETE][27] -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl3/igt@gem_exec_schedule@deep@vecs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl9/igt@gem_exec_schedule@deep@vecs0.html
* igt@gem_pipe_control_store_loop@fresh-buffer:
- shard-tglb: [INCOMPLETE][29] -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb1/igt@gem_pipe_control_store_loop@fresh-buffer.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-tglb3/igt@gem_pipe_control_store_loop@fresh-buffer.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-tglb: [FAIL][31] ([i915#2521]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb1/igt@kms_async_flips@async-flip-with-page-flip-events.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-tglb5/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@hdmi-a-1-pipe-a:
- shard-glk: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk5/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@hdmi-a-1-pipe-a.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-glk5/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@hdmi-a-1-pipe-a.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
- shard-skl: [FAIL][35] ([i915#54]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
- shard-apl: [DMESG-WARN][37] ([i915#1635] / [i915#1982]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-apl4/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-apl7/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][39] ([i915#2346]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: [FAIL][41] ([i915#52] / [i915#54]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][43] ([i915#2122]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@dpms-vs-vblank-race@b-dp1:
- shard-kbl: [INCOMPLETE][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl6/igt@kms_flip@dpms-vs-vblank-race@b-dp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-kbl2/igt@kms_flip@dpms-vs-vblank-race@b-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][47] ([i915#79]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_tiling@flip-to-yf-tiled:
- shard-kbl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-kbl4/igt@kms_flip_tiling@flip-to-yf-tiled.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-kbl3/igt@kms_flip_tiling@flip-to-yf-tiled.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-iclb3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-iclb: [INCOMPLETE][53] ([i915#1185] / [i915#250]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][55] ([fdo#109642] / [fdo#111068]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_sequence@queue-idle:
- shard-skl: [FAIL][59] ([i915#2441]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl3/igt@kms_sequence@queue-idle.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl9/igt@kms_sequence@queue-idle.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: [FAIL][61] ([i915#1731]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl2/igt@sysfs_heartbeat_interval@mixed@bcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl7/igt@sysfs_heartbeat_interval@mixed@bcs0.html
#### Warnings ####
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-snb: [FAIL][63] -> [INCOMPLETE][64] ([i915#82])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-snb7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-snb6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [DMESG-FAIL][65] ([i915#1982]) -> [DMESG-WARN][66] ([i915#1982])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl8/igt@kms_color@pipe-a-ctm-red-to-blue.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl2/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-tglb: [DMESG-WARN][67] ([i915#2411]) -> [DMESG-WARN][68] ([i915#1436] / [i915#2411])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [DMESG-WARN][69] ([i915#1982]) -> [DMESG-FAIL][70] ([i915#1982])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-skl: [DMESG-FAIL][71] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][72] ([i915#1982])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-skl8/igt@kms_flip_tiling@flip-x-tiled.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-skl2/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: [DMESG-FAIL][73] ([fdo#108145] / [i915#1635] / [i915#1982]) -> [FAIL][74] ([fdo#108145] / [i915#1635] / [i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@runner@aborted:
- shard-tglb: ([FAIL][75], [FAIL][76]) ([i915#2439]) -> ([FAIL][77], [FAIL][78]) ([i915#2248] / [i915#2439])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb1/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9247/shard-tglb2/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-tglb5/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/shard-tglb2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2248]: https://gitlab.freedesktop.org/drm/intel/issues/2248
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2441]: https://gitlab.freedesktop.org/drm/intel/issues/2441
[i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9247 -> Patchwork_18832
CI-20190529: 20190529
CI_DRM_9247: 009a99e9be393d32ed57bcac34d6b1fb37c28cdf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18832: 33e74dd124ade0e803e61b0e3c111758c5b7023e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18832/index.html
[-- Attachment #1.2: Type: text/html, Size: 22249 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring
2020-11-02 22:10 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Chris Wilson
` (3 preceding siblings ...)
2020-11-03 7:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-11-03 10:12 ` Mika Kuoppala
4 siblings, 0 replies; 11+ messages in thread
From: Mika Kuoppala @ 2020-11-03 10:12 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Add another lower level to emit_ggtt_write so that the GGTT nature of
> the write is not hardcoded into the emitter.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 55 ++++++++++++++++----------
> 1 file changed, 35 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 7c3a1012e702..760fefdfe392 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -245,22 +245,14 @@ static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u
> }
>
> static inline u32 *
> -__gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
> +__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
Opportunity to swap the offset/value to be in line with the actual qw
write. Just an observation rather than a value add proposal.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> {
> - /* We're using qword write, offset should be aligned to 8 bytes. */
> - GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> -
> - /* w/a for post sync ops following a GPGPU operation we
> - * need a prior CS_STALL, which is emitted by the flush
> - * following the batch.
> - */
> *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
> - *cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
> - *cs++ = gtt_offset;
> + *cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
> + *cs++ = offset;
> *cs++ = 0;
> *cs++ = value;
> - /* We're thrashing one dword of HWS. */
> - *cs++ = 0;
> + *cs++ = 0; /* We're thrashing one extra dword. */
>
> return cs;
> }
> @@ -268,13 +260,38 @@ __gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 f
> static inline u32*
> gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> {
> - return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
> + /* We're using qword write, offset should be aligned to 8 bytes. */
> + GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> +
> + return __gen8_emit_write_rcs(cs,
> + value,
> + gtt_offset,
> + 0,
> + flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
> }
>
> static inline u32*
> gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
> {
> - return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, flags0, flags1);
> + /* We're using qword write, offset should be aligned to 8 bytes. */
> + GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
> +
> + return __gen8_emit_write_rcs(cs,
> + value,
> + gtt_offset,
> + flags0,
> + flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
> +}
> +
> +static inline u32 *
> +__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> +{
> + *cs++ = (MI_FLUSH_DW + 1) | flags;
> + *cs++ = gtt_offset;
> + *cs++ = 0;
> + *cs++ = value;
> +
> + return cs;
> }
>
> static inline u32 *
> @@ -285,12 +302,10 @@ gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
> /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
> GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
>
> - *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
> - *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
> - *cs++ = 0;
> - *cs++ = value;
> -
> - return cs;
> + return __gen8_emit_flush_dw(cs,
> + value,
> + gtt_offset | MI_FLUSH_DW_USE_GTT,
> + flags | MI_FLUSH_DW_OP_STOREDW);
> }
>
> static inline void __intel_engine_reset(struct intel_engine_cs *engine,
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
2020-11-02 22:10 ` [Intel-gfx] " Chris Wilson
@ 2020-11-03 12:44 ` Mika Kuoppala
-1 siblings, 0 replies; 11+ messages in thread
From: Mika Kuoppala @ 2020-11-03 12:44 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Chris Wilson, stable
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In a simple test case that writes to scratch and then busy-waits for the
> batch to be signaled, we observe that the signal is before the write is
> posted. That is bad news.
>
> Splitting the flush + write_dword into two separate flush_dw prevents
> the issue from being reproduced, we can presume the post-sync op is not
> so post-sync.
>
Only thing that is mildly surpricing is that first one doesnt
need postop write.
> Testcase: igt/gem_exec_fence/parallel
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: stable@vger.kernel.org
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index d0be98b67138..a437140a987d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -5047,7 +5047,8 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
>
> static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
> + cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
> + return gen12_emit_fini_breadcrumb_tail(rq, cs);
> }
>
> static u32 *
> --
> 2.20.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
@ 2020-11-03 12:44 ` Mika Kuoppala
0 siblings, 0 replies; 11+ messages in thread
From: Mika Kuoppala @ 2020-11-03 12:44 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: stable, Chris Wilson
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In a simple test case that writes to scratch and then busy-waits for the
> batch to be signaled, we observe that the signal is before the write is
> posted. That is bad news.
>
> Splitting the flush + write_dword into two separate flush_dw prevents
> the issue from being reproduced, we can presume the post-sync op is not
> so post-sync.
>
Only thing that is mildly surpricing is that first one doesnt
need postop write.
> Testcase: igt/gem_exec_fence/parallel
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: stable@vger.kernel.org
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index d0be98b67138..a437140a987d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -5047,7 +5047,8 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
>
> static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
> {
> - return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
> + cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
> + return gen12_emit_fini_breadcrumb_tail(rq, cs);
> }
>
> static u32 *
> --
> 2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
2020-11-03 12:44 ` [Intel-gfx] " Mika Kuoppala
@ 2020-11-03 14:16 ` Chris Wilson
-1 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-11-03 14:16 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: stable
Quoting Mika Kuoppala (2020-11-03 12:44:53)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > In a simple test case that writes to scratch and then busy-waits for the
> > batch to be signaled, we observe that the signal is before the write is
> > posted. That is bad news.
> >
> > Splitting the flush + write_dword into two separate flush_dw prevents
> > the issue from being reproduced, we can presume the post-sync op is not
> > so post-sync.
> >
>
> Only thing that is mildly surpricing is that first one doesnt
> need postop write.
The MI_FLUSH_DW is stalling, so the second will^W should wait for the
first to complete. (And we don't want to do the write from the first as
we observe that write is too early.)
-Chris
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs
@ 2020-11-03 14:16 ` Chris Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Chris Wilson @ 2020-11-03 14:16 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: stable
Quoting Mika Kuoppala (2020-11-03 12:44:53)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > In a simple test case that writes to scratch and then busy-waits for the
> > batch to be signaled, we observe that the signal is before the write is
> > posted. That is bad news.
> >
> > Splitting the flush + write_dword into two separate flush_dw prevents
> > the issue from being reproduced, we can presume the post-sync op is not
> > so post-sync.
> >
>
> Only thing that is mildly surpricing is that first one doesnt
> need postop write.
The MI_FLUSH_DW is stalling, so the second will^W should wait for the
first to complete. (And we don't want to do the write from the first as
we observe that write is too early.)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-11-03 14:16 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-02 22:10 [Intel-gfx] [PATCH 1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Chris Wilson
2020-11-02 22:10 ` [PATCH 2/2] drm/i915/gt: Flush xcs before tgl breadcrumbs Chris Wilson
2020-11-02 22:10 ` [Intel-gfx] " Chris Wilson
2020-11-03 12:44 ` Mika Kuoppala
2020-11-03 12:44 ` [Intel-gfx] " Mika Kuoppala
2020-11-03 14:16 ` Chris Wilson
2020-11-03 14:16 ` [Intel-gfx] " Chris Wilson
2020-11-02 23:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/gt: Expose more parameters for emitting writes into the ring Patchwork
2020-11-02 23:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-03 7:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-11-03 10:12 ` [Intel-gfx] [PATCH 1/2] " Mika Kuoppala
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