[Intel-gfx] [PATCH 0/6] drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code

[Intel-gfx] [PATCH 0/6] drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of intel_atomic_crtc_state_for_each_plane_state() from the
skl+ wm code so that we don't have to bother messing with it for
bigjoiner support.

Ville Syrjälä (6):
  drm/i915: Pass intel_atomic_state around
  drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from
    skl+ wm code
  drm/i915: Pimp the watermark documentation a bit
  drm/i915: Precompute can_sagv for each wm level
  drm/i915: Store plane relative data rate in crtc_state
  drm/i915: Remove skl_adjusted_plane_pixel_rate()

 .../drm/i915/display/intel_display_types.h    |  53 +++--
 drivers/gpu/drm/i915/intel_pm.c               | 196 +++++++++---------
 2 files changed, 125 insertions(+), 124 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH 1/6] drm/i915: Pass intel_atomic_state around

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pass the whole intel_atomic_state to skl_build_pipe_wm()
and skl_allocate_pipe_ddb() so we can start to iterate
stuff containerd in the commit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..e9ac6f1a5d28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4791,9 +4791,11 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
 }
 
 static int
-skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
+skl_allocate_pipe_ddb(struct intel_atomic_state *state,
+		      struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
 	u16 alloc_size, start = 0;
@@ -5583,9 +5585,12 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
+static int skl_build_pipe_wm(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
 	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
@@ -5794,7 +5799,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
-		ret = skl_allocate_pipe_ddb(new_crtc_state);
+		ret = skl_allocate_pipe_ddb(state, crtc);
 		if (ret)
 			return ret;
 
@@ -6092,7 +6097,6 @@ skl_compute_wm(struct intel_atomic_state *state)
 {
 	struct intel_crtc *crtc;
 	struct intel_crtc_state *new_crtc_state;
-	struct intel_crtc_state *old_crtc_state;
 	int ret, i;
 
 	ret = skl_ddb_add_affected_pipes(state);
@@ -6104,9 +6108,8 @@ skl_compute_wm(struct intel_atomic_state *state)
 	 * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
 	 * weren't otherwise being modified if pipe allocations had to change.
 	 */
-	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
-					    new_crtc_state, i) {
-		ret = skl_build_pipe_wm(new_crtc_state);
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		ret = skl_build_pipe_wm(state, crtc);
 		if (ret)
 			return ret;
 	}
@@ -6124,8 +6127,7 @@ skl_compute_wm(struct intel_atomic_state *state)
 	 * based on how much ddb is available. Now we can actually
 	 * check if the final watermarks changed.
 	 */
-	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
-					    new_crtc_state, i) {
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		ret = skl_wm_add_affected_planes(state, crtc);
 		if (ret)
 			return ret;
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Pass intel_atomic_state around

[Navare, Manasi]

On Fri, Nov 06, 2020 at 07:30:37PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pass the whole intel_atomic_state to skl_build_pipe_wm()
> and skl_allocate_pipe_ddb() so we can start to iterate
> stuff containerd in the commit.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This looks good to me,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++-----------
>  1 file changed, 13 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f54375b11964..e9ac6f1a5d28 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4791,9 +4791,11 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
>  }
>  
>  static int
> -skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> +skl_allocate_pipe_ddb(struct intel_atomic_state *state,
> +		      struct intel_crtc *crtc)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
>  	u16 alloc_size, start = 0;
> @@ -5583,9 +5585,12 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>  	return 0;
>  }
>  
> -static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> +static int skl_build_pipe_wm(struct intel_atomic_state *state,
> +			     struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
>  	struct intel_plane *plane;
>  	const struct intel_plane_state *plane_state;
> @@ -5794,7 +5799,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
> -		ret = skl_allocate_pipe_ddb(new_crtc_state);
> +		ret = skl_allocate_pipe_ddb(state, crtc);
>  		if (ret)
>  			return ret;
>  
> @@ -6092,7 +6097,6 @@ skl_compute_wm(struct intel_atomic_state *state)
>  {
>  	struct intel_crtc *crtc;
>  	struct intel_crtc_state *new_crtc_state;
> -	struct intel_crtc_state *old_crtc_state;
>  	int ret, i;
>  
>  	ret = skl_ddb_add_affected_pipes(state);
> @@ -6104,9 +6108,8 @@ skl_compute_wm(struct intel_atomic_state *state)
>  	 * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
>  	 * weren't otherwise being modified if pipe allocations had to change.
>  	 */
> -	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> -					    new_crtc_state, i) {
> -		ret = skl_build_pipe_wm(new_crtc_state);
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		ret = skl_build_pipe_wm(state, crtc);
>  		if (ret)
>  			return ret;
>  	}
> @@ -6124,8 +6127,7 @@ skl_compute_wm(struct intel_atomic_state *state)
>  	 * based on how much ddb is available. Now we can actually
>  	 * check if the final watermarks changed.
>  	 */
> -	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> -					    new_crtc_state, i) {
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>  		ret = skl_wm_add_affected_planes(state, crtc);
>  		if (ret)
>  			return ret;
> -- 
> 2.26.2
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 2/6] drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_atomic_crtc_state_for_each_plane_state() peeks at the
plane's current state without holding the plane's mutex, trusting
that the crtc's mutex will protect it. In practice that does work
since our planes can't move between pipes, but it sets a bad
example. intel_atomic_crtc_state_for_each_plane_state() also
relies on crtc_state.uapi.plane_mask which may be full of lies
when it comes to the bigjoiner stuff, so soon we can't use it as
is anyway. So best to just get rid of it entirely. Which we can
easily do by switching to the g4x/vlv "raw" watermark approach.

Later on we should even be able to move the "raw" watermark
computation into the normal .plane_check() code, leaving only
the merging/clamping of the final watermarks to the later
stages. But that will require adjusting the ilk+ wm code
similarly as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/intel_pm.c               | 41 +++++++++++--------
 2 files changed, 27 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..6b249969c394 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -755,6 +755,8 @@ struct intel_crtc_wm_state {
 		} ilk;
 
 		struct {
+			/* "raw" watermarks */
+			struct skl_pipe_wm raw;
 			/* gen9+ only needs 1-step wm programming */
 			struct skl_pipe_wm optimal;
 			struct skl_ddb_entry ddb;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e9ac6f1a5d28..85b4bfb02e2e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5480,7 +5480,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
 	struct skl_wm_params wm_params;
 	int ret;
 
@@ -5503,7 +5503,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 				 const struct intel_plane_state *plane_state,
 				 enum plane_id plane_id)
 {
-	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
 	struct skl_wm_params wm_params;
 	int ret;
 
@@ -5524,10 +5524,13 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	enum plane_id plane_id = plane->id;
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int ret;
 
+	memset(wm, 0, sizeof(*wm));
+
 	if (!intel_wm_plane_visible(crtc_state, plane_state))
 		return 0;
 
@@ -5549,10 +5552,14 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 			      const struct intel_plane_state *plane_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum plane_id plane_id = plane->id;
+	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
 	int ret;
 
+	memset(wm, 0, sizeof(*wm));
+
 	/* Watermarks calculated in master */
 	if (plane_state->planar_slave)
 		return 0;
@@ -5591,19 +5598,18 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
-	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
-	int ret;
+	struct intel_plane *plane;
+	int ret, i;
 
-	/*
-	 * We'll only calculate watermarks for planes that are actually
-	 * enabled, so make sure all other planes are set as disabled.
-	 */
-	memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
-
-	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
-						     crtc_state) {
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		/*
+		 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
+		 * instead but we don't populate that correctly for NV12 Y
+		 * planes so for now hack this.
+		 */
+		if (plane->pipe != crtc->pipe)
+			continue;
 
 		if (INTEL_GEN(dev_priv) >= 11)
 			ret = icl_build_plane_wm(crtc_state, plane_state);
@@ -5613,6 +5619,8 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
 			return ret;
 	}
 
+	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
+
 	return 0;
 }
 
@@ -6273,6 +6281,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		crtc_state = to_intel_crtc_state(crtc->base.state);
 
 		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
+		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
 	}
 
 	if (dev_priv->active_pipes) {
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code

[Lisovskiy, Stanislav]

On Fri, Nov 06, 2020 at 07:30:38PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_atomic_crtc_state_for_each_plane_state() peeks at the
> plane's current state without holding the plane's mutex, trusting
> that the crtc's mutex will protect it. In practice that does work
> since our planes can't move between pipes, but it sets a bad
> example. intel_atomic_crtc_state_for_each_plane_state() also
> relies on crtc_state.uapi.plane_mask which may be full of lies
> when it comes to the bigjoiner stuff, so soon we can't use it as
> is anyway. So best to just get rid of it entirely. Which we can
> easily do by switching to the g4x/vlv "raw" watermark approach.
> 
> Later on we should even be able to move the "raw" watermark
> computation into the normal .plane_check() code, leaving only
> the merging/clamping of the final watermarks to the later
> stages. But that will require adjusting the ilk+ wm code
> similarly as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> ---
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  drivers/gpu/drm/i915/intel_pm.c               | 41 +++++++++++--------
>  2 files changed, 27 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..6b249969c394 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -755,6 +755,8 @@ struct intel_crtc_wm_state {
>  		} ilk;
>  
>  		struct {
> +			/* "raw" watermarks */
> +			struct skl_pipe_wm raw;
>  			/* gen9+ only needs 1-step wm programming */
>  			struct skl_pipe_wm optimal;
>  			struct skl_ddb_entry ddb;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e9ac6f1a5d28..85b4bfb02e2e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5480,7 +5480,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> +	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
>  	struct skl_wm_params wm_params;
>  	int ret;
>  
> @@ -5503,7 +5503,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  				 const struct intel_plane_state *plane_state,
>  				 enum plane_id plane_id)
>  {
> -	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
> +	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
>  	struct skl_wm_params wm_params;
>  	int ret;
>  
> @@ -5524,10 +5524,13 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
>  			      const struct intel_plane_state *plane_state)
>  {
>  	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> -	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	enum plane_id plane_id = plane->id;
> +	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	int ret;
>  
> +	memset(wm, 0, sizeof(*wm));
> +
>  	if (!intel_wm_plane_visible(crtc_state, plane_state))
>  		return 0;
>  
> @@ -5549,10 +5552,14 @@ static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
>  static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
>  			      const struct intel_plane_state *plane_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
> +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +	enum plane_id plane_id = plane->id;
> +	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
>  	int ret;
>  
> +	memset(wm, 0, sizeof(*wm));
> +
>  	/* Watermarks calculated in master */
>  	if (plane_state->planar_slave)
>  		return 0;
> @@ -5591,19 +5598,18 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> -	struct intel_plane *plane;
>  	const struct intel_plane_state *plane_state;
> -	int ret;
> +	struct intel_plane *plane;
> +	int ret, i;
>  
> -	/*
> -	 * We'll only calculate watermarks for planes that are actually
> -	 * enabled, so make sure all other planes are set as disabled.
> -	 */
> -	memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
> -
> -	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
> -						     crtc_state) {
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		/*
> +		 * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
> +		 * instead but we don't populate that correctly for NV12 Y
> +		 * planes so for now hack this.
> +		 */
> +		if (plane->pipe != crtc->pipe)
> +			continue;
>  
>  		if (INTEL_GEN(dev_priv) >= 11)
>  			ret = icl_build_plane_wm(crtc_state, plane_state);
> @@ -5613,6 +5619,8 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state,
>  			return ret;
>  	}
>  
> +	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
> +
>  	return 0;
>  }
>  
> @@ -6273,6 +6281,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		crtc_state = to_intel_crtc_state(crtc->base.state);
>  
>  		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
> +		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
>  	}
>  
>  	if (dev_priv->active_pipes) {
> -- 
> 2.26.2
> 
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[Intel-gfx] [PATCH 3/6] drm/i915: Pimp the watermark documentation a bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Document what each of the "raw" vs. "optimal" vs. "intermediate"
watermarks do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    | 48 ++++++++++---------
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6b249969c394..b977e70e34d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -737,25 +737,34 @@ struct g4x_wm_state {
 
 struct intel_crtc_wm_state {
 	union {
+		/*
+		 * raw:
+		 * The "raw" watermark values produced by the formula
+		 * given the plane's current state. They do not consider
+		 * how much FIFO is actually allocated for each plane.
+		 *
+		 * optimal:
+		 * The "optimal" watermark values given the current
+		 * state of the planes and the amount of FIFO
+		 * allocated to each, ignoring any previous state
+		 * of the planes.
+		 *
+		 * intermediate:
+		 * The "intermediate" watermark values when transitioning
+		 * between the old and new "optimal" values. Used when
+		 * the watermark registers are single buffered and hence
+		 * their state changes asynchronously with regards to the
+		 * actual plane registers. These are essentially the
+		 * worst case combination of the old and new "optimal"
+		 * watermarks, which are therefore safe to use when the
+		 * plane is in either its old or new state.
+		 */
 		struct {
-			/*
-			 * Intermediate watermarks; these can be
-			 * programmed immediately since they satisfy
-			 * both the current configuration we're
-			 * switching away from and the new
-			 * configuration we're switching to.
-			 */
 			struct intel_pipe_wm intermediate;
-
-			/*
-			 * Optimal watermarks, programmed post-vblank
-			 * when this state is committed.
-			 */
 			struct intel_pipe_wm optimal;
 		} ilk;
 
 		struct {
-			/* "raw" watermarks */
 			struct skl_pipe_wm raw;
 			/* gen9+ only needs 1-step wm programming */
 			struct skl_pipe_wm optimal;
@@ -765,22 +774,15 @@ struct intel_crtc_wm_state {
 		} skl;
 
 		struct {
-			/* "raw" watermarks (not inverted) */
-			struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
-			/* intermediate watermarks (inverted) */
-			struct vlv_wm_state intermediate;
-			/* optimal watermarks (inverted) */
-			struct vlv_wm_state optimal;
-			/* display FIFO split */
+			struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
+			struct vlv_wm_state intermediate; /* inverted */
+			struct vlv_wm_state optimal; /* inverted */
 			struct vlv_fifo_state fifo_state;
 		} vlv;
 
 		struct {
-			/* "raw" watermarks */
 			struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
-			/* intermediate watermarks */
 			struct g4x_wm_state intermediate;
-			/* optimal watermarks */
 			struct g4x_wm_state optimal;
 		} g4x;
 	};
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Pimp the watermark documentation a bit

[Navare, Manasi]

On Fri, Nov 06, 2020 at 07:30:39PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Document what each of the "raw" vs. "optimal" vs. "intermediate"
> watermarks do.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks good to me

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  .../drm/i915/display/intel_display_types.h    | 48 ++++++++++---------
>  1 file changed, 25 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6b249969c394..b977e70e34d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -737,25 +737,34 @@ struct g4x_wm_state {
>  
>  struct intel_crtc_wm_state {
>  	union {
> +		/*
> +		 * raw:
> +		 * The "raw" watermark values produced by the formula
> +		 * given the plane's current state. They do not consider
> +		 * how much FIFO is actually allocated for each plane.
> +		 *
> +		 * optimal:
> +		 * The "optimal" watermark values given the current
> +		 * state of the planes and the amount of FIFO
> +		 * allocated to each, ignoring any previous state
> +		 * of the planes.
> +		 *
> +		 * intermediate:
> +		 * The "intermediate" watermark values when transitioning
> +		 * between the old and new "optimal" values. Used when
> +		 * the watermark registers are single buffered and hence
> +		 * their state changes asynchronously with regards to the
> +		 * actual plane registers. These are essentially the
> +		 * worst case combination of the old and new "optimal"
> +		 * watermarks, which are therefore safe to use when the
> +		 * plane is in either its old or new state.
> +		 */
>  		struct {
> -			/*
> -			 * Intermediate watermarks; these can be
> -			 * programmed immediately since they satisfy
> -			 * both the current configuration we're
> -			 * switching away from and the new
> -			 * configuration we're switching to.
> -			 */
>  			struct intel_pipe_wm intermediate;
> -
> -			/*
> -			 * Optimal watermarks, programmed post-vblank
> -			 * when this state is committed.
> -			 */
>  			struct intel_pipe_wm optimal;
>  		} ilk;
>  
>  		struct {
> -			/* "raw" watermarks */
>  			struct skl_pipe_wm raw;
>  			/* gen9+ only needs 1-step wm programming */
>  			struct skl_pipe_wm optimal;
> @@ -765,22 +774,15 @@ struct intel_crtc_wm_state {
>  		} skl;
>  
>  		struct {
> -			/* "raw" watermarks (not inverted) */
> -			struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
> -			/* intermediate watermarks (inverted) */
> -			struct vlv_wm_state intermediate;
> -			/* optimal watermarks (inverted) */
> -			struct vlv_wm_state optimal;
> -			/* display FIFO split */
> +			struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
> +			struct vlv_wm_state intermediate; /* inverted */
> +			struct vlv_wm_state optimal; /* inverted */
>  			struct vlv_fifo_state fifo_state;
>  		} vlv;
>  
>  		struct {
> -			/* "raw" watermarks */
>  			struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
> -			/* intermediate watermarks */
>  			struct g4x_wm_state intermediate;
> -			/* optimal watermarks */
>  			struct g4x_wm_state optimal;
>  		} g4x;
>  	};
> -- 
> 2.26.2
> 
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[Intel-gfx] [PATCH 4/6] drm/i915: Precompute can_sagv for each wm level

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In order to remove intel_atomic_crtc_state_for_each_plane_state()
from skl_crtc_can_enable_sagv() we can simply precompute whether
each wm level can tolerate the SAGV block time latency or not.

This has the nice side benefit that we remove the duplicated
wm level latency calculation. In fact the copy of that code
we had in skl_crtc_can_enable_sagv() didn't even handle
WaIncreaseLatencyIPCEnabled/Display WA #1141 whereas the copy
in skl_compute_plane_wm() did. So now we just have the one
copy which handles all the w/as.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/intel_pm.c               | 21 +++++++------------
 2 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b977e70e34d7..8a0276044832 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -686,6 +686,7 @@ struct skl_wm_level {
 	u8 plane_res_l;
 	bool plane_en;
 	bool ignore_lines;
+	bool can_sagv;
 };
 
 struct skl_plane_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 85b4bfb02e2e..b789ad78319b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3873,9 +3873,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_plane *plane;
-	const struct intel_plane_state *plane_state;
-	int level, latency;
+	enum plane_id plane_id;
 
 	if (!intel_has_sagv(dev_priv))
 		return false;
@@ -3886,9 +3884,10 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
 		return false;
 
-	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
+	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane->id];
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+		int level;
 
 		/* Skip this plane if it's not enabled */
 		if (!wm->wm[0].plane_en)
@@ -3899,19 +3898,12 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 		     !wm->wm[level].plane_en; --level)
 		     { }
 
-		latency = dev_priv->wm.skl_latency[level];
-
-		if (skl_needs_memory_bw_wa(dev_priv) &&
-		    plane_state->uapi.fb->modifier ==
-		    I915_FORMAT_MOD_X_TILED)
-			latency += 15;
-
 		/*
 		 * If any of the planes on this pipe don't enable wm levels that
 		 * incur memory latencies higher than sagv_block_time_us we
 		 * can't enable SAGV.
 		 */
-		if (latency < dev_priv->sagv_block_time_us)
+		if (!wm->wm[level].can_sagv)
 			return false;
 	}
 
@@ -5375,6 +5367,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 	/* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
 	result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
 	result->plane_en = true;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		result->can_sagv = latency >= dev_priv->sagv_block_time_us;
 }
 
 static void
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Precompute can_sagv for each wm level

[Lisovskiy, Stanislav]

On Fri, Nov 06, 2020 at 07:30:40PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> In order to remove intel_atomic_crtc_state_for_each_plane_state()
> from skl_crtc_can_enable_sagv() we can simply precompute whether
> each wm level can tolerate the SAGV block time latency or not.
> 
> This has the nice side benefit that we remove the duplicated
> wm level latency calculation. In fact the copy of that code
> we had in skl_crtc_can_enable_sagv() didn't even handle
> WaIncreaseLatencyIPCEnabled/Display WA #1141 whereas the copy
> in skl_compute_plane_wm() did. So now we just have the one
> copy which handles all the w/as.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/intel_pm.c               | 21 +++++++------------
>  2 files changed, 9 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b977e70e34d7..8a0276044832 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -686,6 +686,7 @@ struct skl_wm_level {
>  	u8 plane_res_l;
>  	bool plane_en;
>  	bool ignore_lines;
> +	bool can_sagv;
>  };
>  
>  struct skl_plane_wm {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 85b4bfb02e2e..b789ad78319b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3873,9 +3873,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct intel_plane *plane;
> -	const struct intel_plane_state *plane_state;
> -	int level, latency;
> +	enum plane_id plane_id;
>  
>  	if (!intel_has_sagv(dev_priv))
>  		return false;
> @@ -3886,9 +3884,10 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
>  		return false;
>  
> -	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_plane_wm *wm =
> -			&crtc_state->wm.skl.optimal.planes[plane->id];
> +			&crtc_state->wm.skl.optimal.planes[plane_id];
> +		int level;
>  
>  		/* Skip this plane if it's not enabled */
>  		if (!wm->wm[0].plane_en)
> @@ -3899,19 +3898,12 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
>  		     !wm->wm[level].plane_en; --level)
>  		     { }
>  
> -		latency = dev_priv->wm.skl_latency[level];
> -
> -		if (skl_needs_memory_bw_wa(dev_priv) &&
> -		    plane_state->uapi.fb->modifier ==
> -		    I915_FORMAT_MOD_X_TILED)
> -			latency += 15;
> -
>  		/*
>  		 * If any of the planes on this pipe don't enable wm levels that
>  		 * incur memory latencies higher than sagv_block_time_us we
>  		 * can't enable SAGV.
>  		 */
> -		if (latency < dev_priv->sagv_block_time_us)
> +		if (!wm->wm[level].can_sagv)
>  			return false;
>  	}

Ah yet again that "thing". I wonder tbh, do we even need this per level,
as we anyway do "to SAGV or not to SAGV" decision, based on all wm levels.

Also I remember we even discussed that we wanted some clarification here,
as for Gen12+ we actually checking only if we can fit wm0 + block time to ddb.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>


>  
> @@ -5375,6 +5367,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  	/* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
>  	result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
>  	result->plane_en = true;
> +
> +	if (INTEL_GEN(dev_priv) < 12)
> +		result->can_sagv = latency >= dev_priv->sagv_block_time_us;
>  }
>  
>  static void
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Precompute can_sagv for each wm level

[Ville Syrjälä]

On Thu, Nov 12, 2020 at 03:59:40PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Nov 06, 2020 at 07:30:40PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > In order to remove intel_atomic_crtc_state_for_each_plane_state()
> > from skl_crtc_can_enable_sagv() we can simply precompute whether
> > each wm level can tolerate the SAGV block time latency or not.
> > 
> > This has the nice side benefit that we remove the duplicated
> > wm level latency calculation. In fact the copy of that code
> > we had in skl_crtc_can_enable_sagv() didn't even handle
> > WaIncreaseLatencyIPCEnabled/Display WA #1141 whereas the copy
> > in skl_compute_plane_wm() did. So now we just have the one
> > copy which handles all the w/as.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c               | 21 +++++++------------
> >  2 files changed, 9 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index b977e70e34d7..8a0276044832 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -686,6 +686,7 @@ struct skl_wm_level {
> >  	u8 plane_res_l;
> >  	bool plane_en;
> >  	bool ignore_lines;
> > +	bool can_sagv;
> >  };
> >  
> >  struct skl_plane_wm {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 85b4bfb02e2e..b789ad78319b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3873,9 +3873,7 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	struct intel_plane *plane;
> > -	const struct intel_plane_state *plane_state;
> > -	int level, latency;
> > +	enum plane_id plane_id;
> >  
> >  	if (!intel_has_sagv(dev_priv))
> >  		return false;
> > @@ -3886,9 +3884,10 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> >  	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> >  		return false;
> >  
> > -	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > +	for_each_plane_id_on_crtc(crtc, plane_id) {
> >  		const struct skl_plane_wm *wm =
> > -			&crtc_state->wm.skl.optimal.planes[plane->id];
> > +			&crtc_state->wm.skl.optimal.planes[plane_id];
> > +		int level;
> >  
> >  		/* Skip this plane if it's not enabled */
> >  		if (!wm->wm[0].plane_en)
> > @@ -3899,19 +3898,12 @@ static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> >  		     !wm->wm[level].plane_en; --level)
> >  		     { }
> >  
> > -		latency = dev_priv->wm.skl_latency[level];
> > -
> > -		if (skl_needs_memory_bw_wa(dev_priv) &&
> > -		    plane_state->uapi.fb->modifier ==
> > -		    I915_FORMAT_MOD_X_TILED)
> > -			latency += 15;
> > -
> >  		/*
> >  		 * If any of the planes on this pipe don't enable wm levels that
> >  		 * incur memory latencies higher than sagv_block_time_us we
> >  		 * can't enable SAGV.
> >  		 */
> > -		if (latency < dev_priv->sagv_block_time_us)
> > +		if (!wm->wm[level].can_sagv)
> >  			return false;
> >  	}
> 
> Ah yet again that "thing". I wonder tbh, do we even need this per level,
> as we anyway do "to SAGV or not to SAGV" decision, based on all wm levels.

We need it because we don't know which levels will actually be enabled
until later when we've done the ddb allocation.

> 
> Also I remember we even discussed that we wanted some clarification here,
> as for Gen12+ we actually checking only if we can fit wm0 + block time to ddb.

Yeah, it's quite unclear still.

Also atm we enable sagv if all planes have enabled at least one
level with latency>=sagv_block_time, but atm there is no guarantee that
said level is the same for all the planes (since the w/as can
change the latencies in ways that make two planes use different
latencies for the same level). That to me feels a bit broken. I suspect
we should be looking to make sure the highest common level for all the
planes can tolerate sagv, because I think that's the highest level that
can actually be used by the hw.

So eg. we could have
plane A wm0/en=yes,sagv=no, wm1/en=yes,sagv=no,  wm2/en=yes,sagv=yes
plane B wm0/en=yes,sagv=no, wm1/en=yes,sagv=yes, wm2/en=no

and the hardware will never actully use wm2 (I think) which
would be required for sagv to be safe with plane A. But I
think I need to double check the hardware behaviour to be sure
I'm thinking this correctly.

> 
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> 
> >  
> > @@ -5375,6 +5367,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> >  	/* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
> >  	result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
> >  	result->plane_en = true;
> > +
> > +	if (INTEL_GEN(dev_priv) < 12)
> > +		result->can_sagv = latency >= dev_priv->sagv_block_time_us;
> >  }
> >  
> >  static void
> > -- 
> > 2.26.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH 5/6] drm/i915: Store plane relative data rate in crtc_state

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Store the relative data rate for planes in the crtc state
so that we don't have to use
intel_atomic_crtc_state_for_each_plane_state() to compute
it even for the planes that are no part of the current state.

Should probably just nuke this stuff entirely an use the normal
plane data rate instead. The two are slightly different since this
relative data rate doesn't factor in the actual pixel clock, so
it's a bit odd thing to even call a "data rate". And since the
watermarks are computed based on the actual data rate anyway
I don't really see what the point of this relative data rate
is. But that's for the future...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  4 +
 drivers/gpu/drm/i915/intel_pm.c               | 83 ++++++++++---------
 2 files changed, 50 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8a0276044832..768bd3dc77dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1024,6 +1024,10 @@ struct intel_crtc_state {
 
 	u32 data_rate[I915_MAX_PLANES];
 
+	/* FIXME unify with data_rate[] */
+	u64 plane_data_rate[I915_MAX_PLANES];
+	u64 uv_plane_data_rate[I915_MAX_PLANES];
+
 	/* Gamma mode programmed on the pipe */
 	u32 gamma_mode;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b789ad78319b..8865f37d6297 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4696,50 +4696,63 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 }
 
 static u64
-skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
-				 u64 *plane_data_rate,
-				 u64 *uv_plane_data_rate)
+skl_get_total_relative_data_rate(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc)
 {
-	struct intel_plane *plane;
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_plane_state *plane_state;
+	struct intel_plane *plane;
 	u64 total_data_rate = 0;
+	enum plane_id plane_id;
+	int i;
 
 	/* Calculate and cache data rate for each plane */
-	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
-		enum plane_id plane_id = plane->id;
-		u64 rate;
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		if (plane->pipe != crtc->pipe)
+			continue;
+
+		plane_id = plane->id;
 
 		/* packed/y */
-		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-		plane_data_rate[plane_id] = rate;
-		total_data_rate += rate;
+		crtc_state->plane_data_rate[plane_id] =
+			skl_plane_relative_data_rate(crtc_state, plane_state, 0);
 
 		/* uv-plane */
-		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
-		uv_plane_data_rate[plane_id] = rate;
-		total_data_rate += rate;
+		crtc_state->uv_plane_data_rate[plane_id] =
+			skl_plane_relative_data_rate(crtc_state, plane_state, 1);
+	}
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		total_data_rate += crtc_state->plane_data_rate[plane_id];
+		total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
 	}
 
 	return total_data_rate;
 }
 
 static u64
-icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
-				 u64 *plane_data_rate)
+icl_get_total_relative_data_rate(struct intel_atomic_state *state,
+				 struct intel_crtc *crtc)
 {
-	struct intel_plane *plane;
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_plane_state *plane_state;
+	struct intel_plane *plane;
 	u64 total_data_rate = 0;
+	enum plane_id plane_id;
+	int i;
 
 	/* Calculate and cache data rate for each plane */
-	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
-		enum plane_id plane_id = plane->id;
-		u64 rate;
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		if (plane->pipe != crtc->pipe)
+			continue;
+
+		plane_id = plane->id;
 
 		if (!plane_state->planar_linked_plane) {
-			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
-			plane_data_rate[plane_id] = rate;
-			total_data_rate += rate;
+			crtc_state->plane_data_rate[plane_id] =
+				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
 		} else {
 			enum plane_id y_plane_id;
 
@@ -4754,17 +4767,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 				continue;
 
 			/* Y plane rate is calculated on the slave */
-			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
 			y_plane_id = plane_state->planar_linked_plane->id;
-			plane_data_rate[y_plane_id] = rate;
-			total_data_rate += rate;
+			crtc_state->plane_data_rate[y_plane_id] =
+				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
 
-			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
-			plane_data_rate[plane_id] = rate;
-			total_data_rate += rate;
+			crtc_state->plane_data_rate[plane_id] =
+				skl_plane_relative_data_rate(crtc_state, plane_state, 1);
 		}
 	}
 
+	for_each_plane_id_on_crtc(crtc, plane_id)
+		total_data_rate += crtc_state->plane_data_rate[plane_id];
+
 	return total_data_rate;
 }
 
@@ -4796,8 +4810,6 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 	u64 total_data_rate;
 	enum plane_id plane_id;
 	int num_active;
-	u64 plane_data_rate[I915_MAX_PLANES] = {};
-	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
 	u32 blocks;
 	int level;
 	int ret;
@@ -4837,13 +4849,10 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		total_data_rate =
-			icl_get_total_relative_data_rate(crtc_state,
-							 plane_data_rate);
+			icl_get_total_relative_data_rate(state, crtc);
 	else
 		total_data_rate =
-			skl_get_total_relative_data_rate(crtc_state,
-							 plane_data_rate,
-							 uv_plane_data_rate);
+			skl_get_total_relative_data_rate(state, crtc);
 
 	ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
 						 total_data_rate,
@@ -4924,7 +4933,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 		if (total_data_rate == 0)
 			break;
 
-		rate = plane_data_rate[plane_id];
+		rate = crtc_state->plane_data_rate[plane_id];
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
@@ -4935,7 +4944,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
 		if (total_data_rate == 0)
 			break;
 
-		rate = uv_plane_data_rate[plane_id];
+		rate = crtc_state->uv_plane_data_rate[plane_id];
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Store plane relative data rate in crtc_state

[Lisovskiy, Stanislav]

On Fri, Nov 06, 2020 at 07:30:41PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Store the relative data rate for planes in the crtc state
> so that we don't have to use
> intel_atomic_crtc_state_for_each_plane_state() to compute
> it even for the planes that are no part of the current state.
> 
> Should probably just nuke this stuff entirely an use the normal
> plane data rate instead. The two are slightly different since this
> relative data rate doesn't factor in the actual pixel clock, so
> it's a bit odd thing to even call a "data rate". And since the
> watermarks are computed based on the actual data rate anyway
> I don't really see what the point of this relative data rate
> is. But that's for the future...
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>


> ---
>  .../drm/i915/display/intel_display_types.h    |  4 +
>  drivers/gpu/drm/i915/intel_pm.c               | 83 ++++++++++---------
>  2 files changed, 50 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8a0276044832..768bd3dc77dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1024,6 +1024,10 @@ struct intel_crtc_state {
>  
>  	u32 data_rate[I915_MAX_PLANES];
>  
> +	/* FIXME unify with data_rate[] */
> +	u64 plane_data_rate[I915_MAX_PLANES];
> +	u64 uv_plane_data_rate[I915_MAX_PLANES];
> +
>  	/* Gamma mode programmed on the pipe */
>  	u32 gamma_mode;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b789ad78319b..8865f37d6297 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4696,50 +4696,63 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>  }
>  
>  static u64
> -skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> -				 u64 *plane_data_rate,
> -				 u64 *uv_plane_data_rate)
> +skl_get_total_relative_data_rate(struct intel_atomic_state *state,
> +				 struct intel_crtc *crtc)
>  {
> -	struct intel_plane *plane;
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct intel_plane_state *plane_state;
> +	struct intel_plane *plane;
>  	u64 total_data_rate = 0;
> +	enum plane_id plane_id;
> +	int i;
>  
>  	/* Calculate and cache data rate for each plane */
> -	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> -		enum plane_id plane_id = plane->id;
> -		u64 rate;
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		if (plane->pipe != crtc->pipe)
> +			continue;
> +
> +		plane_id = plane->id;
>  
>  		/* packed/y */
> -		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> -		plane_data_rate[plane_id] = rate;
> -		total_data_rate += rate;
> +		crtc_state->plane_data_rate[plane_id] =
> +			skl_plane_relative_data_rate(crtc_state, plane_state, 0);
>  
>  		/* uv-plane */
> -		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> -		uv_plane_data_rate[plane_id] = rate;
> -		total_data_rate += rate;
> +		crtc_state->uv_plane_data_rate[plane_id] =
> +			skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> +	}
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		total_data_rate += crtc_state->plane_data_rate[plane_id];
> +		total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
>  	}
>  
>  	return total_data_rate;
>  }
>  
>  static u64
> -icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> -				 u64 *plane_data_rate)
> +icl_get_total_relative_data_rate(struct intel_atomic_state *state,
> +				 struct intel_crtc *crtc)
>  {
> -	struct intel_plane *plane;
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct intel_plane_state *plane_state;
> +	struct intel_plane *plane;
>  	u64 total_data_rate = 0;
> +	enum plane_id plane_id;
> +	int i;
>  
>  	/* Calculate and cache data rate for each plane */
> -	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> -		enum plane_id plane_id = plane->id;
> -		u64 rate;
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		if (plane->pipe != crtc->pipe)
> +			continue;
> +
> +		plane_id = plane->id;
>  
>  		if (!plane_state->planar_linked_plane) {
> -			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> -			plane_data_rate[plane_id] = rate;
> -			total_data_rate += rate;
> +			crtc_state->plane_data_rate[plane_id] =
> +				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
>  		} else {
>  			enum plane_id y_plane_id;
>  
> @@ -4754,17 +4767,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
>  				continue;
>  
>  			/* Y plane rate is calculated on the slave */
> -			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
>  			y_plane_id = plane_state->planar_linked_plane->id;
> -			plane_data_rate[y_plane_id] = rate;
> -			total_data_rate += rate;
> +			crtc_state->plane_data_rate[y_plane_id] =
> +				skl_plane_relative_data_rate(crtc_state, plane_state, 0);
>  
> -			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> -			plane_data_rate[plane_id] = rate;
> -			total_data_rate += rate;
> +			crtc_state->plane_data_rate[plane_id] =
> +				skl_plane_relative_data_rate(crtc_state, plane_state, 1);
>  		}
>  	}
>  
> +	for_each_plane_id_on_crtc(crtc, plane_id)
> +		total_data_rate += crtc_state->plane_data_rate[plane_id];
> +
>  	return total_data_rate;
>  }
>  
> @@ -4796,8 +4810,6 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
>  	u64 total_data_rate;
>  	enum plane_id plane_id;
>  	int num_active;
> -	u64 plane_data_rate[I915_MAX_PLANES] = {};
> -	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
>  	u32 blocks;
>  	int level;
>  	int ret;
> @@ -4837,13 +4849,10 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
>  		total_data_rate =
> -			icl_get_total_relative_data_rate(crtc_state,
> -							 plane_data_rate);
> +			icl_get_total_relative_data_rate(state, crtc);
>  	else
>  		total_data_rate =
> -			skl_get_total_relative_data_rate(crtc_state,
> -							 plane_data_rate,
> -							 uv_plane_data_rate);
> +			skl_get_total_relative_data_rate(state, crtc);
>  
>  	ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
>  						 total_data_rate,
> @@ -4924,7 +4933,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
>  		if (total_data_rate == 0)
>  			break;
>  
> -		rate = plane_data_rate[plane_id];
> +		rate = crtc_state->plane_data_rate[plane_id];
>  		extra = min_t(u16, alloc_size,
>  			      DIV64_U64_ROUND_UP(alloc_size * rate,
>  						 total_data_rate));
> @@ -4935,7 +4944,7 @@ skl_allocate_pipe_ddb(struct intel_atomic_state *state,
>  		if (total_data_rate == 0)
>  			break;
>  
> -		rate = uv_plane_data_rate[plane_id];
> +		rate = crtc_state->uv_plane_data_rate[plane_id];
>  		extra = min_t(u16, alloc_size,
>  			      DIV64_U64_ROUND_UP(alloc_size * rate,
>  						 total_data_rate));
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 6/6] drm/i915: Remove skl_adjusted_plane_pixel_rate()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace skl_adjusted_plane_pixel_rate() with the generic
intel_plane_pixel_rate(). The two should produce identical
results.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 27 ++-------------------------
 1 file changed, 2 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8865f37d6297..bc59dc8f44e0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -33,6 +33,7 @@
 #include <drm/drm_plane_helper.h>
 
 #include "display/intel_atomic.h"
+#include "display/intel_atomic_plane.h"
 #include "display/intel_bw.h"
 #include "display/intel_display_types.h"
 #include "display/intel_fbc.h"
@@ -5102,30 +5103,6 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 	return linetime_us;
 }
 
-static u32
-skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
-			      const struct intel_plane_state *plane_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	u64 adjusted_pixel_rate;
-	uint_fixed_16_16_t downscale_amount;
-
-	/* Shouldn't reach here on disabled planes... */
-	if (drm_WARN_ON(&dev_priv->drm,
-			!intel_wm_plane_visible(crtc_state, plane_state)))
-		return 0;
-
-	/*
-	 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
-	 * with additional adjustments for plane-specific scaling.
-	 */
-	adjusted_pixel_rate = crtc_state->pixel_rate;
-	downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
-
-	return mul_round_up_u32_fixed16(adjusted_pixel_rate,
-					    downscale_amount);
-}
-
 static int
 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 		      int width, const struct drm_format_info *format,
@@ -5238,7 +5215,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
 	return skl_compute_wm_params(crtc_state, width,
 				     fb->format, fb->modifier,
 				     plane_state->hw.rotation,
-				     skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
+				     intel_plane_pixel_rate(crtc_state, plane_state),
 				     wp, color_plane);
 }
 
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 6/6] drm/i915: Remove skl_adjusted_plane_pixel_rate()

[Lisovskiy, Stanislav]

On Fri, Nov 06, 2020 at 07:30:42PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace skl_adjusted_plane_pixel_rate() with the generic
> intel_plane_pixel_rate(). The two should produce identical
> results.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 27 ++-------------------------
>  1 file changed, 2 insertions(+), 25 deletions(-)

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8865f37d6297..bc59dc8f44e0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -33,6 +33,7 @@
>  #include <drm/drm_plane_helper.h>
>  
>  #include "display/intel_atomic.h"
> +#include "display/intel_atomic_plane.h"
>  #include "display/intel_bw.h"
>  #include "display/intel_display_types.h"
>  #include "display/intel_fbc.h"
> @@ -5102,30 +5103,6 @@ intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
>  	return linetime_us;
>  }
>  
> -static u32
> -skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
> -			      const struct intel_plane_state *plane_state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	u64 adjusted_pixel_rate;
> -	uint_fixed_16_16_t downscale_amount;
> -
> -	/* Shouldn't reach here on disabled planes... */
> -	if (drm_WARN_ON(&dev_priv->drm,
> -			!intel_wm_plane_visible(crtc_state, plane_state)))
> -		return 0;
> -
> -	/*
> -	 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> -	 * with additional adjustments for plane-specific scaling.
> -	 */
> -	adjusted_pixel_rate = crtc_state->pixel_rate;
> -	downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
> -
> -	return mul_round_up_u32_fixed16(adjusted_pixel_rate,
> -					    downscale_amount);
> -}
> -
>  static int
>  skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
>  		      int width, const struct drm_format_info *format,
> @@ -5238,7 +5215,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
>  	return skl_compute_wm_params(crtc_state, width,
>  				     fb->format, fb->modifier,
>  				     plane_state->hw.rotation,
> -				     skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
> +				     intel_plane_pixel_rate(crtc_state, plane_state),
>  				     wp, color_plane);
>  }
>  
> -- 
> 2.26.2
> 
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code

[Patchwork]

== Series Details ==

Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code
URL   : https://patchwork.freedesktop.org/series/83589/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7648 bytes --]

== Series Details ==

Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code
URL   : https://patchwork.freedesktop.org/series/83589/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9283 -> Patchwork_18868
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18868 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18868, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18868:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_lrc:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9283 and Patchwork_18868:

### New CI tests (1) ###

  * boot:
    - Statuses : 40 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18868 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-icl-u2:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [PASS][5] -> [DMESG-WARN][6] ([i915#2605])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-bsw-kefka:       [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@vgem_basic@setversion:
    - fi-tgl-y:           [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-tgl-y/igt@vgem_basic@setversion.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-tgl-y/igt@vgem_basic@setversion.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-icl-y:           [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-icl-y/igt@i915_module_load@reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-icl-y/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
    - fi-tgl-y:           [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-tgl-y/igt@kms_busy@basic@flip.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-tgl-y/igt@kms_busy@basic@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - {fi-kbl-7560u}:     [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-kbl-soraka:      [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-kbl-soraka/igt@kms_frontbuffer_tracking@basic.html

  * igt@prime_vgem@basic-gtt:
    - fi-tgl-y:           [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-tgl-y/igt@prime_vgem@basic-gtt.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-tgl-y/igt@prime_vgem@basic-gtt.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-y:           [DMESG-WARN][23] ([i915#2411]) -> [DMESG-WARN][24] ([i915#2411] / [i915#402])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-tgl-y:           [DMESG-WARN][25] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][26] ([i915#2411])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-tgl-y/igt@i915_pm_rpm@basic-rte.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-tgl-y/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - fi-tgl-y:           [DMESG-WARN][27] ([i915#2411]) -> [DMESG-WARN][28] ([i915#1982] / [i915#2411])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9283/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/fi-tgl-y/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 40)
------------------------------

  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9283 -> Patchwork_18868

  CI-20190529: 20190529
  CI_DRM_9283: fa5964fce9d6f7ab77c6073254ed2a148de82029 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5836: 4c2ec0ad123b82f42f9fe2297e1a41fec73c9229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18868: bfc29a699776d9791edc9907e59b13be67cac9c0 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bfc29a699776 drm/i915: Remove skl_adjusted_plane_pixel_rate()
4149eae8202e drm/i915: Store plane relative data rate in crtc_state
96bd6550d33f drm/i915: Precompute can_sagv for each wm level
44603c86d826 drm/i915: Pimp the watermark documentation a bit
e8f0c29568f2 drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code
48f2f19d916c drm/i915: Pass intel_atomic_state around

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18868/index.html

[-- Attachment #1.2: Type: text/html, Size: 9683 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)
URL   : https://patchwork.freedesktop.org/series/83589/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7739 bytes --]

== Series Details ==

Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)
URL   : https://patchwork.freedesktop.org/series/83589/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9326 -> Patchwork_18900
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18900:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_pm:
    - {fi-tgl-dsi}:       [DMESG-FAIL][1] ([i915#1759]) -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9326 and Patchwork_18900:

### New CI tests (1) ###

  * boot:
    - Statuses : 41 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18900 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-bsw-nick:        [PASS][3] -> [INCOMPLETE][4] ([i915#1250] / [i915#1436])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-bsw-nick/igt@debugfs_test@read_all_entries.html

  * igt@gem_sync@basic-all:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@gem_sync@basic-all.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-y/igt@gem_sync@basic-all.html

  * igt@i915_module_load@reload:
    - fi-icl-u2:          [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@i915_module_load@reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-icl-u2/igt@i915_module_load@reload.html
    - fi-byt-j1900:       [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@i915_module_load@reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-byt-j1900/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-soraka:      [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-kbl-soraka/igt@kms_busy@basic@flip.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-kbl-soraka/igt@kms_busy@basic@flip.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-tgl-y:           [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
#### Possible fixes ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-cml-u2:          [FAIL][17] ([i915#1161] / [i915#262]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - {fi-kbl-7560u}:     [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
    - fi-tgl-y:           [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html

  * igt@prime_vgem@basic-read:
    - fi-tgl-y:           [DMESG-WARN][27] ([i915#402]) -> [PASS][28] +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/fi-tgl-y/igt@prime_vgem@basic-read.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/fi-tgl-y/igt@prime_vgem@basic-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (46 -> 41)
------------------------------

  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9326 -> Patchwork_18900

  CI-20190529: 20190529
  CI_DRM_9326: 3048c2a1dcf02422e89930148ffad9e91d690499 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5850: 9748a4a0f93d108955d374a866e60cb962da9b5d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18900: bd8a2bc2ea0fd0f4495abc2eea16ac09377b25cf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

bd8a2bc2ea0f drm/i915: Remove skl_adjusted_plane_pixel_rate()
306dbc2be210 drm/i915: Store plane relative data rate in crtc_state
3c1c83dff45a drm/i915: Precompute can_sagv for each wm level
0b9dde127a47 drm/i915: Pimp the watermark documentation a bit
fdf6d6f4eff3 drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code
227192af4f8c drm/i915: Pass intel_atomic_state around

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/index.html

[-- Attachment #1.2: Type: text/html, Size: 9281 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 18305 bytes --]

== Series Details ==

Series: drm/i915: Eliminate intel_atomic_crtc_state_for_each_plane_state() from skl+ wm code (rev2)
URL   : https://patchwork.freedesktop.org/series/83589/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9326_full -> Patchwork_18900_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_18900_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18900_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18900_full:

### IGT changes ###

#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][1] ([i915#1515]) -> [WARN][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html

  

### Piglit changes ###

#### Possible regressions ####

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-abs-neg-ivec2-int (NEW):
    - {pig-icl-1065g7}:   NOTRUN -> [INCOMPLETE][3] +7 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/pig-icl-1065g7/spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-abs-neg-ivec2-int.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9326_full and Patchwork_18900_full:

### New CI tests (1) ###

  * boot:
    - Statuses : 199 pass(s)
    - Exec time: [0.0] s

  


### New Piglit tests (8) ###

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-clamp-uvec2-uint-uint:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitand-ivec2-int:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-assign-bitxor-uvec2-uint:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-bitand-abs-neg-ivec2-int:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-div-int-int:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-lshift-uint-uint:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-op-selection-bool-ivec2-ivec2:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@arb_tessellation_shader@execution@built-in-functions@tcs-trunc-float:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_18900_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_reloc@basic-many-active@rcs0:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#2389])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk7/igt@gem_exec_reloc@basic-many-active@rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk4/igt@gem_exec_reloc@basic-many-active@rcs0.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-skl:          [PASS][6] -> [INCOMPLETE][7] ([i915#198])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl7/igt@gem_workarounds@suspend-resume-fd.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl9/igt@gem_workarounds@suspend-resume-fd.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
    - shard-skl:          [PASS][8] -> [FAIL][9] ([i915#54]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html

  * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
    - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-kbl3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-kbl3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled:
    - shard-skl:          [PASS][12] -> [FAIL][13] ([i915#177] / [i915#52] / [i915#54])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl10/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [PASS][14] -> [FAIL][15] ([i915#79])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
    - shard-skl:          [PASS][16] -> [FAIL][17] ([i915#2122])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-tglb:         [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-badstride:
    - shard-iclb:         [PASS][20] -> [DMESG-WARN][21] ([i915#1982])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-badstride.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#49])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-skl:          [PASS][24] -> [INCOMPLETE][25] ([i915#123])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl3/igt@kms_frontbuffer_tracking@psr-suspend.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl5/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane_cursor@pipe-a-overlay-size-256:
    - shard-skl:          [PASS][26] -> [DMESG-WARN][27] ([i915#1982]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl9/igt@kms_plane_cursor@pipe-a-overlay-size-256.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl4/igt@kms_plane_cursor@pipe-a-overlay-size-256.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb2/igt@kms_psr@psr2_basic.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb5/igt@kms_psr@psr2_basic.html

  * igt@kms_vblank@pipe-c-wait-forked-busy:
    - shard-apl:          [PASS][30] -> [DMESG-WARN][31] ([i915#1635] / [i915#1982]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-apl3/igt@kms_vblank@pipe-c-wait-forked-busy.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-apl3/igt@kms_vblank@pipe-c-wait-forked-busy.html

  * igt@perf@polling-parameterized:
    - shard-apl:          [PASS][32] -> [FAIL][33] ([i915#1542] / [i915#1635])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-apl3/igt@perf@polling-parameterized.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-apl3/igt@perf@polling-parameterized.html

  * igt@perf_pmu@module-unload:
    - shard-hsw:          [PASS][34] -> [DMESG-WARN][35] ([i915#1982]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw4/igt@perf_pmu@module-unload.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-hsw1/igt@perf_pmu@module-unload.html

  
#### Possible fixes ####

  * igt@gem_exec_whisper@basic-queues-priority:
    - shard-glk:          [DMESG-WARN][36] ([i915#118] / [i915#95]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk1/igt@gem_exec_whisper@basic-queues-priority.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk2/igt@gem_exec_whisper@basic-queues-priority.html

  * igt@i915_module_load@reload:
    - shard-iclb:         [DMESG-WARN][38] ([i915#1982]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb2/igt@i915_module_load@reload.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb7/igt@i915_module_load@reload.html

  * igt@i915_pm_rpm@i2c:
    - shard-glk:          [DMESG-WARN][40] ([i915#1982]) -> [PASS][41] +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk9/igt@i915_pm_rpm@i2c.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk6/igt@i915_pm_rpm@i2c.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x64-random:
    - shard-skl:          [FAIL][42] ([i915#54]) -> [PASS][43] +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][44] ([i915#96]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
    - shard-apl:          [DMESG-WARN][46] ([i915#1635] / [i915#1982]) -> [PASS][47] +4 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-apl6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-apl4/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [INCOMPLETE][48] ([i915#198]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_fbcon_fbt@psr-suspend.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl5/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          [FAIL][50] ([i915#79]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][52] ([fdo#108145] / [i915#265]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_cursor@pipe-a-viewport-size-128:
    - shard-skl:          [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +7 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-skl2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-skl2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][56] ([fdo#109441]) -> [PASS][57] +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@perf@polling-parameterized:
    - shard-hsw:          [FAIL][58] ([i915#1542]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw6/igt@perf@polling-parameterized.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-hsw4/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [DMESG-WARN][60] ([i915#1226]) -> [SKIP][61] ([fdo#109349])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@runner@aborted:
    - shard-hsw:          ([FAIL][62], [FAIL][63]) ([fdo#109271] / [i915#2295] / [i915#2439]) -> ([FAIL][64], [FAIL][65]) ([fdo#109271] / [i915#2295] / [i915#2439] / [i915#483])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw5/igt@runner@aborted.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-hsw2/igt@runner@aborted.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-hsw1/igt@runner@aborted.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-hsw6/igt@runner@aborted.html
    - shard-glk:          ([FAIL][66], [FAIL][67], [FAIL][68]) ([i915#1611] / [i915#1814] / [i915#2295] / [i915#2439] / [i915#86] / [k.org#202321]) -> ([FAIL][69], [FAIL][70], [FAIL][71]) ([i915#1611] / [i915#1814] / [i915#2295] / [i915#2439] / [i915#483] / [i915#86] / [k.org#202321])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk1/igt@runner@aborted.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk8/igt@runner@aborted.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9326/shard-glk8/igt@runner@aborted.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk3/igt@runner@aborted.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk5/igt@runner@aborted.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/shard-glk5/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
  [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#86]: https://gitlab.freedesktop.org/drm/intel/issues/86
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9326 -> Patchwork_18900

  CI-20190529: 20190529
  CI_DRM_9326: 3048c2a1dcf02422e89930148ffad9e91d690499 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5850: 9748a4a0f93d108955d374a866e60cb962da9b5d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18900: bd8a2bc2ea0fd0f4495abc2eea16ac09377b25cf @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18900/index.html

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