From: Timothy McDaniel <timothy.mcdaniel@intel.com>
Cc: dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,
harry.van.haaren@intel.com, jerinj@marvell.com,
thomas@monjalon.net, david.marchand@redhat.com
Subject: [dpdk-dev] [PATCH] event/dlb: remove duplicate/unused PCI code and constants
Date: Wed, 11 Nov 2020 14:27:02 -0600 [thread overview]
Message-ID: <1605126422-522-4-git-send-email-timothy.mcdaniel@intel.com> (raw)
In-Reply-To: <1605126422-522-1-git-send-email-timothy.mcdaniel@intel.com>
Use rte_pci_find_ext_capability instead of private version,
Remove unused PCI offsets and values
Use PCI definitions from rte_pci.h, where available.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
drivers/event/dlb/pf/dlb_main.c | 50 +++++++----------------------------------
1 file changed, 8 insertions(+), 42 deletions(-)
diff --git a/drivers/event/dlb/pf/dlb_main.c b/drivers/event/dlb/pf/dlb_main.c
index 17e671e..264350e 100644
--- a/drivers/event/dlb/pf/dlb_main.c
+++ b/drivers/event/dlb/pf/dlb_main.c
@@ -23,17 +23,12 @@
unsigned int dlb_unregister_timeout_s = DLB_DEFAULT_UNREGISTER_TIMEOUT_S;
-#define DLB_PCI_CFG_SPACE_SIZE 256
#define DLB_PCI_CAP_POINTER 0x34
#define DLB_PCI_CAP_NEXT(hdr) (((hdr) >> 8) & 0xFC)
#define DLB_PCI_CAP_ID(hdr) ((hdr) & 0xFF)
-#define DLB_PCI_EXT_CAP_NEXT(hdr) (((hdr) >> 20) & 0xFFC)
-#define DLB_PCI_EXT_CAP_ID(hdr) ((hdr) & 0xFFFF)
-#define DLB_PCI_EXT_CAP_ID_ERR 1
#define DLB_PCI_ERR_UNCOR_MASK 8
#define DLB_PCI_ERR_UNC_UNSUP 0x00100000
-#define DLB_PCI_EXP_DEVCTL 8
#define DLB_PCI_LNKCTL 16
#define DLB_PCI_SLTCTL 24
#define DLB_PCI_RTCTL 28
@@ -41,22 +36,15 @@ unsigned int dlb_unregister_timeout_s = DLB_DEFAULT_UNREGISTER_TIMEOUT_S;
#define DLB_PCI_LNKCTL2 48
#define DLB_PCI_SLTCTL2 56
#define DLB_PCI_CMD 4
-#define DLB_PCI_X_CMD 2
#define DLB_PCI_EXP_DEVSTA 10
#define DLB_PCI_EXP_DEVSTA_TRPND 0x20
#define DLB_PCI_EXP_DEVCTL_BCR_FLR 0x8000
-#define DLB_PCI_PASID_CTRL 6
-#define DLB_PCI_PASID_CAP 4
#define DLB_PCI_CAP_ID_EXP 0x10
#define DLB_PCI_CAP_ID_MSIX 0x11
-#define DLB_PCI_EXT_CAP_ID_PAS 0x1B
#define DLB_PCI_EXT_CAP_ID_PRI 0x13
#define DLB_PCI_EXT_CAP_ID_ACS 0xD
-#define DLB_PCI_PASID_CAP_EXEC 0x2
-#define DLB_PCI_PASID_CAP_PRIV 0x4
-#define DLB_PCI_PASID_CTRL_ENABLE 0x1
#define DLB_PCI_PRI_CTRL_ENABLE 0x1
#define DLB_PCI_PRI_ALLOC_REQ 0xC
#define DLB_PCI_PRI_CTRL 0x4
@@ -75,28 +63,6 @@ unsigned int dlb_unregister_timeout_s = DLB_DEFAULT_UNREGISTER_TIMEOUT_S;
#define DLB_PCI_ACS_UF 0x10
#define DLB_PCI_ACS_EC 0x20
-static int dlb_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id)
-{
- uint32_t hdr;
- size_t sz;
- int pos;
-
- pos = DLB_PCI_CFG_SPACE_SIZE;
- sz = sizeof(hdr);
-
- while (pos > 0xFF) {
- if (rte_pci_read_config(pdev, &hdr, sz, pos) != (int)sz)
- return -1;
-
- if (DLB_PCI_EXT_CAP_ID(hdr) == id)
- return pos;
-
- pos = DLB_PCI_EXT_CAP_NEXT(hdr);
- }
-
- return -1;
-}
-
static int dlb_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)
{
uint8_t pos;
@@ -130,7 +96,7 @@ static int dlb_mask_ur_err(struct rte_pci_device *pdev)
{
uint32_t mask;
size_t sz = sizeof(mask);
- int pos = dlb_pci_find_ext_capability(pdev, DLB_PCI_EXT_CAP_ID_ERR);
+ int pos = rte_pci_find_ext_capability(pdev, RTE_PCI_EXT_CAP_ID_ERR);
if (pos < 0) {
DLB_LOG_ERR("[%s()] failed to find the aer capability\n",
@@ -274,7 +240,7 @@ dlb_pf_reset(struct dlb_dev *dlb_dev)
return pcie_cap_offset;
}
- off = pcie_cap_offset + DLB_PCI_EXP_DEVCTL;
+ off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL;
if (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2)
dev_ctl_word = 0;
@@ -302,7 +268,7 @@ dlb_pf_reset(struct dlb_dev *dlb_dev)
if (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2)
slt_word2 = 0;
- pri_cap_offset = dlb_pci_find_ext_capability(pdev,
+ pri_cap_offset = rte_pci_find_ext_capability(pdev,
DLB_PCI_EXT_CAP_ID_PRI);
if (pri_cap_offset >= 0) {
off = pri_cap_offset + DLB_PCI_PRI_ALLOC_REQ;
@@ -345,7 +311,7 @@ dlb_pf_reset(struct dlb_dev *dlb_dev)
return -1;
}
- off = pcie_cap_offset + DLB_PCI_EXP_DEVCTL;
+ off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL;
ret = rte_pci_read_config(pdev, &devctl_word, 2, off);
if (ret != 2) {
DLB_LOG_ERR("[%s()] failed to read the pcie device control\n",
@@ -366,7 +332,7 @@ dlb_pf_reset(struct dlb_dev *dlb_dev)
/* Restore PCI config state */
if (pcie_cap_offset >= 0) {
- off = pcie_cap_offset + DLB_PCI_EXP_DEVCTL;
+ off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL;
if (rte_pci_write_config(pdev, &dev_ctl_word, 2, off) != 2) {
DLB_LOG_ERR("[%s()] failed to write the pcie device control at offset %d\n",
__func__, (int)off);
@@ -434,8 +400,8 @@ dlb_pf_reset(struct dlb_dev *dlb_dev)
}
}
- err_cap_offset = dlb_pci_find_ext_capability(pdev,
- DLB_PCI_EXT_CAP_ID_ERR);
+ err_cap_offset = rte_pci_find_ext_capability(pdev,
+ RTE_PCI_EXT_CAP_ID_ERR);
if (err_cap_offset >= 0) {
uint32_t tmp;
@@ -513,7 +479,7 @@ dlb_pf_reset(struct dlb_dev *dlb_dev)
}
}
- acs_cap_offset = dlb_pci_find_ext_capability(pdev,
+ acs_cap_offset = rte_pci_find_ext_capability(pdev,
DLB_PCI_EXT_CAP_ID_ACS);
if (acs_cap_offset >= 0) {
uint16_t acs_cap, acs_ctrl, acs_mask;
--
2.6.4
next prev parent reply other threads:[~2020-11-11 20:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 20:26 [dpdk-dev] [PATCH] event/dlb2: add missing delayed token pop logic Timothy McDaniel
2020-11-11 20:27 ` [dpdk-dev] [PATCH] event/dlb2: remove duplicate/unused PCI code and constants Timothy McDaniel
2020-11-11 20:27 ` [dpdk-dev] [PATCH] event/dlb: do not free memzone if port create succeeds Timothy McDaniel
2020-11-11 21:04 ` Chen, Mike Ximing
2020-11-11 20:27 ` Timothy McDaniel [this message]
2020-11-11 21:12 ` [dpdk-dev] [PATCH] event/dlb2: add missing delayed token pop logic Chen, Mike Ximing
2020-11-13 9:53 ` Jerin Jacob
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