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From: Catalin Marinas <catalin.marinas@arm.com>
To: Kostya Serebryany <kcc@google.com>,
	Peter Collingbourne <pcc@google.com>,
	Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Dave Martin <Dave.Martin@arm.com>,
	Evgenii Stepanov <eugenis@google.com>,
	Will Deacon <will@kernel.org>
Cc: linux-api@vger.kernel.org,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Andrey Konovalov <andreyknvl@google.com>
Subject: Re: [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled
Date: Wed, 25 Nov 2020 18:54:52 +0000	[thread overview]
Message-ID: <160633041769.14178.5621643710037826918.b4-ty@arm.com> (raw)
In-Reply-To: <20f64e26fc8a1309caa446fffcb1b4e2fe9e229f.1605952129.git.pcc@google.com>

On Sat, 21 Nov 2020 01:59:02 -0800, Peter Collingbourne wrote:
> On hardware supporting pointer authentication, we previously ended up
> enabling TBI on instruction accesses when tag-based ASAN was enabled,
> but this was costing us 8 bits of PAC entropy, which was unnecessary
> since tag-based ASAN does not require TBI on instruction accesses. Get
> them back by setting TCR_EL1.TBID1.

Applied to arm64 (for-next/misc), thanks!

[1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled
      https://git.kernel.org/arm64/c/49b3cf035edc

This patch looks safe. Patch 2/2 needs more discussions.

-- 
Catalin


WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Kostya Serebryany <kcc@google.com>,
	Peter Collingbourne <pcc@google.com>,
	Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Dave Martin <Dave.Martin@arm.com>,
	Evgenii Stepanov <eugenis@google.com>,
	Will Deacon <will@kernel.org>
Cc: linux-api@vger.kernel.org,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Andrey Konovalov <andreyknvl@google.com>
Subject: Re: [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled
Date: Wed, 25 Nov 2020 18:54:52 +0000	[thread overview]
Message-ID: <160633041769.14178.5621643710037826918.b4-ty@arm.com> (raw)
In-Reply-To: <20f64e26fc8a1309caa446fffcb1b4e2fe9e229f.1605952129.git.pcc@google.com>

On Sat, 21 Nov 2020 01:59:02 -0800, Peter Collingbourne wrote:
> On hardware supporting pointer authentication, we previously ended up
> enabling TBI on instruction accesses when tag-based ASAN was enabled,
> but this was costing us 8 bits of PAC entropy, which was unnecessary
> since tag-based ASAN does not require TBI on instruction accesses. Get
> them back by setting TCR_EL1.TBID1.

Applied to arm64 (for-next/misc), thanks!

[1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled
      https://git.kernel.org/arm64/c/49b3cf035edc

This patch looks safe. Patch 2/2 needs more discussions.

-- 
Catalin


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  parent reply	other threads:[~2020-11-25 18:54 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-21  9:59 [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled Peter Collingbourne
2020-11-21  9:59 ` Peter Collingbourne
2020-11-21  9:59 ` [PATCH 2/2] arm64: allow TCR_EL1.TBID0 to be configured Peter Collingbourne
2020-11-21  9:59   ` Peter Collingbourne
2020-11-24 18:47   ` Catalin Marinas
2020-11-24 18:47     ` Catalin Marinas
2020-11-24 19:18     ` Peter Collingbourne
2020-11-24 19:18       ` Peter Collingbourne
2020-11-25 14:37       ` Szabolcs Nagy
2020-11-25 14:37         ` Szabolcs Nagy
2021-06-15 23:41         ` Peter Collingbourne
2021-06-15 23:41           ` Peter Collingbourne
2021-06-16 12:55           ` Szabolcs Nagy
2021-06-16 12:55             ` Szabolcs Nagy
2021-06-22  5:13             ` Peter Collingbourne
2021-06-22  5:13               ` Peter Collingbourne
2020-11-23 18:20 ` [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled Andrey Konovalov
2020-11-23 18:20   ` Andrey Konovalov
2020-11-25 18:54 ` Catalin Marinas [this message]
2020-11-25 18:54   ` Catalin Marinas

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