* [Intel-gfx] [PATCH v3 2/5] drm/i915/display/psr: Calculate Trancoder's SU rect and plane's SF rect
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
@ 2020-11-27 10:50 ` Gwan-gyeong Mun
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() Gwan-gyeong Mun
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Gwan-gyeong Mun @ 2020-11-27 10:50 UTC (permalink / raw)
To: intel-gfx
It implements calculating of Selective Update area for transcoder.
SU follows crtc geometry.
the logic handles the following cases.
1. plane has moved
2. plane's alpha value has changed
3. plane's visibility has changed
4. plane's damage clips exist
5. plane's fb has flipped, but there were no damaged clips
And it generates a Selective Fetch area for the plane.
Each SF area follows plane geometry.
SF rect is calculated by intersecting a plane's dst rect and SU rect.
in order to follow the plane's src geometry, the intersected rect
is converted to the plane's src geometry.
The current implementation does not handle a fully obscured plane area.
In order to optimize calculating of SU area, it needs to subtract
the accumulated SU area from the visible area.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 9 +
drivers/gpu/drm/i915/display/intel_psr.c | 248 +++++++++++++++----
2 files changed, 211 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 5e0d42d82c11..b2969d8ff625 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -465,6 +465,15 @@ enum phy_fia {
(__i)++) \
for_each_if(plane)
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+ (__i) >= 0 && \
+ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(plane)
+
#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
for ((__i) = 0; \
(__i) < (__state)->base.dev->mode_config.num_crtc && \
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d9a395c486d3..f314f550b809 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1249,75 +1249,231 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
crtc_state->psr2_man_track_ctl = val;
}
-static void clip_area_update(struct drm_rect *overlap_damage_area,
- struct drm_rect *damage_area)
+/* calculate and update selective update rect with update rect */
+static void
+su_rect_update(struct drm_rect *su_rect, struct drm_rect *update_rect)
{
- if (overlap_damage_area->y1 == -1) {
- overlap_damage_area->y1 = damage_area->y1;
- overlap_damage_area->y2 = damage_area->y2;
+ if (drm_rect_height(update_rect) <= 0)
return;
+
+ if (!drm_rect_height(su_rect)) {
+ /* when select update rect is empty */
+ su_rect->y1 = update_rect->y1;
+ su_rect->y2 = update_rect->y2;
+ } else {
+ su_rect->y1 = min(su_rect->y1, update_rect->y1);
+ su_rect->y2 = max(su_rect->y2, update_rect->y2);
}
+}
+
+static void
+plane_get_damage_rect(const struct drm_plane_state *state,
+ struct drm_rect *damage_rect)
+{
+ struct drm_mode_rect *damage_clips;
+ int i;
+ u32 num_clips = drm_plane_get_damage_clips_count(state);
+
+
+ if (!num_clips)
+ return;
- if (damage_area->y1 < overlap_damage_area->y1)
- overlap_damage_area->y1 = damage_area->y1;
+ damage_clips = drm_plane_get_damage_clips(state);
- if (damage_area->y2 > overlap_damage_area->y2)
- overlap_damage_area->y2 = damage_area->y2;
+ /* initialize with first damage_clip */
+ damage_rect->x1 = damage_clips[0].x1;
+ damage_rect->y1 = damage_clips[0].y1;
+ damage_rect->x2 = damage_clips[0].x2;
+ damage_rect->y2 = damage_clips[0].y2;
+
+ for (i = 1; i < num_clips; i++) {
+ /* Selective Fetch has limitattion which only can have one rect */
+ damage_rect->x1 = min(damage_rect->x1, damage_clips[i].x1);
+ damage_rect->x2 = max(damage_rect->x2, damage_clips[i].x2);
+ damage_rect->y1 = min(damage_rect->y1, damage_clips[i].y1);
+ damage_rect->y2 = max(damage_rect->y2, damage_clips[i].y2);
+ }
}
-int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+/*
+ * Generate Selective Update area rect
+ * Todo: In order to optimize calculating of SU area, it should subtract
+ * accumulated SU area from the visible area.
+ */
+static void
+psr_generate_su_rect(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state,
+ struct drm_rect *su_rect)
{
- struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane_state *new_plane_state, *old_plane_state;
- struct drm_rect pipe_clip = { .y1 = -1 };
struct intel_plane *plane;
- bool full_update = false;
- int i, ret;
+ int i;
- if (!crtc_state->enable_psr2_sel_fetch)
- return 0;
+ for_each_oldnew_intel_plane_in_state_reverse(state, plane, old_plane_state,
+ new_plane_state, i) {
+ bool old_alpha, new_alpha, alpha_change;
+ bool visible, visibility_change;
+ bool flip, move;
+ u32 num_clips;
- ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
- if (ret)
- return ret;
+ if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+ continue;
- for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
- new_plane_state, i) {
- struct drm_rect *sel_fetch_area, temp;
+ if (plane->id == PLANE_CURSOR)
+ continue;
- if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+ new_alpha = new_plane_state->uapi.alpha != DRM_BLEND_ALPHA_OPAQUE;
+ old_alpha = old_plane_state->uapi.alpha != DRM_BLEND_ALPHA_OPAQUE;
+ alpha_change = new_alpha != old_alpha;
+ visible = new_plane_state->uapi.visible;
+ visibility_change =
+ old_plane_state->uapi.visible != new_plane_state->uapi.visible;
+ flip = new_plane_state->uapi.fb != old_plane_state->uapi.fb;
+ move = !drm_rect_equals(&new_plane_state->uapi.dst,
+ &old_plane_state->uapi.dst);
+
+ /* 1. plane has moved */
+ if (move && !visibility_change && visible) {
+ su_rect_update(su_rect, &old_plane_state->uapi.dst);
+ su_rect_update(su_rect, &new_plane_state->uapi.dst);
continue;
+ }
- /*
- * TODO: Not clear how to handle planes with negative position,
- * also planes are not updated if they have a negative X
- * position so for now doing a full update in this cases
- */
- if (new_plane_state->uapi.dst.y1 < 0 ||
- new_plane_state->uapi.dst.x1 < 0) {
- full_update = true;
- break;
+ /* 2. plane's alpha value has changed */
+ if (alpha_change && !visibility_change && visible) {
+ su_rect_update(su_rect, &new_plane_state->uapi.dst);
+ continue;
+ }
+
+ /* 3. plane's visibility has changed */
+ if (visibility_change) {
+ if (visible)
+ su_rect_update(su_rect, &new_plane_state->uapi.dst);
+ else
+ su_rect_update(su_rect, &old_plane_state->uapi.dst);
+ continue;
+ }
+
+ num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
+ /* 4. plane's damage clips exist */
+ if (num_clips && visible) {
+ struct drm_rect damage_rect, src_rect;
+
+ drm_rect_init(&damage_rect, 0, 0, 0, 0);
+ plane_get_damage_rect(&new_plane_state->uapi, &damage_rect);
+ /* convert fixed point float to int */
+ src_rect.x1 = new_plane_state->uapi.src.x1 >> 16;
+ src_rect.x2 = new_plane_state->uapi.src.x2 >> 16;
+ src_rect.y1 = new_plane_state->uapi.src.y1 >> 16;
+ src_rect.y2 = new_plane_state->uapi.src.y2 >> 16;
+
+ /* damage rect is based on src geometry */
+ if (drm_rect_intersect(&damage_rect, &src_rect)) {
+ /*
+ * su rect is based on dst geometry
+ * convert damage_rect's src geometry to dst geometry
+ */
+ damage_rect.x1 =
+ damage_rect.x1 - src_rect.x1 +
+ new_plane_state->uapi.dst.x1;
+ damage_rect.x2 =
+ damage_rect.x2 - src_rect.x1 +
+ new_plane_state->uapi.dst.x1;
+ damage_rect.y1 =
+ damage_rect.y1 - src_rect.y1 +
+ new_plane_state->uapi.dst.y1;
+ damage_rect.y2 =
+ damage_rect.y2 - src_rect.y1 +
+ new_plane_state->uapi.dst.y1;
+
+ su_rect_update(su_rect, &damage_rect);
+ }
+ continue;
+ }
+
+ /* 5. plane's fb has flipped, but there were no damaged clips */
+ if (flip && visible) {
+ su_rect_update(su_rect, &new_plane_state->uapi.dst);
+ continue;
}
+ }
+}
+
+/*
+ * Generate Plane's Selective Fetch rect from intersected area between
+ * Selective Update area rect and plane's dst rect.
+ * Todo: Consider to handle a fully obscured plane.
+ */
+static void
+psr_generate_plane_sf_rect(struct intel_atomic_state *state,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_rect *su_rect)
+{
+ struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct intel_plane *plane;
+ int i;
+
+ for_each_oldnew_intel_plane_in_state_reverse(state, plane, old_plane_state,
+ new_plane_state, i) {
+
+ struct drm_rect sf_rect = new_plane_state->uapi.dst;
+
+ if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+ continue;
+
+ if (plane->id == PLANE_CURSOR)
+ continue;
if (!new_plane_state->uapi.visible)
continue;
- /*
- * For now doing a selective fetch in the whole plane area,
- * optimizations will come in the future.
- */
- sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
- sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
- sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16;
-
- temp = *sel_fetch_area;
- temp.y1 += new_plane_state->uapi.dst.y1;
- temp.y2 += new_plane_state->uapi.dst.y2;
- clip_area_update(&pipe_clip, &temp);
+ if (drm_rect_intersect(&sf_rect, su_rect)) {
+ /*
+ * su rect is based on dst geometry and sf rect should
+ * follow src geometry. convert sf rect's dst geometry
+ * to dst geometry
+ */
+ sf_rect.x1 = sf_rect.x1 - new_plane_state->uapi.dst.x1 +
+ (new_plane_state->uapi.src.x1 >> 16);
+ sf_rect.x2 = sf_rect.x2 - new_plane_state->uapi.dst.x1 +
+ (new_plane_state->uapi.src.x1 >> 16);
+ sf_rect.y1 = sf_rect.y1 - new_plane_state->uapi.dst.y1 +
+ (new_plane_state->uapi.src.y1 >> 16);
+ sf_rect.y2 = sf_rect.y2 - new_plane_state->uapi.dst.y1 +
+ (new_plane_state->uapi.src.y1 >> 16);
+
+ new_plane_state->psr2_sel_fetch_area = sf_rect;
+ }
}
+}
+
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct drm_rect su_rect;
+ bool full_update = false;
+ int ret;
+
+ if (!crtc_state->enable_psr2_sel_fetch)
+ return 0;
+
+ ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
+ if (ret)
+ return ret;
+
+ /*
+ * Generate Selective Update area rect
+ * Todo: In order to optimize calculating of SU area, it should subtract
+ * accumulated SU area from the visible area.
+ */
+ drm_rect_init(&su_rect, 0, 0,
+ crtc_state->uapi.adjusted_mode.crtc_hdisplay, 0);
+ psr_generate_su_rect(state, crtc_state, &su_rect);
+ psr_generate_plane_sf_rect(state, crtc_state, &su_rect);
+ psr2_man_trk_ctl_calc(crtc_state, &su_rect, full_update);
- psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
return 0;
}
--
2.25.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [Intel-gfx] [PATCH v3 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/display/psr: Calculate Trancoder's SU rect and plane's SF rect Gwan-gyeong Mun
@ 2020-11-27 10:50 ` Gwan-gyeong Mun
2020-11-27 14:10 ` Souza, Jose
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 4/5] drm/i915/display/psr: Program Plane's calculated offset to Plane SF register Gwan-gyeong Mun
` (4 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Gwan-gyeong Mun @ 2020-11-27 10:50 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 62 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.h | 2 +
2 files changed, 42 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 595183f7b60f..da24f654a2f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3817,22 +3817,21 @@ static int intel_plane_max_height(struct intel_plane *plane,
return INT_MAX;
}
-static int skl_check_main_surface(struct intel_plane_state *plane_state)
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+ int *x, int *y, u32 *offset)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
- unsigned int rotation = plane_state->hw.rotation;
- int x = plane_state->uapi.src.x1 >> 16;
- int y = plane_state->uapi.src.y1 >> 16;
- int w = drm_rect_width(&plane_state->uapi.src) >> 16;
- int h = drm_rect_height(&plane_state->uapi.src) >> 16;
- int min_width = intel_plane_min_width(plane, fb, 0, rotation);
- int max_width = intel_plane_max_width(plane, fb, 0, rotation);
- int max_height = intel_plane_max_height(plane, fb, 0, rotation);
- int aux_plane = intel_main_to_aux_plane(fb, 0);
- u32 aux_offset = plane_state->color_plane[aux_plane].offset;
- u32 alignment, offset;
+ const unsigned int rotation = plane_state->hw.rotation;
+ const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
+ const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
+ const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
if (w > max_width || w < min_width || h > max_height) {
drm_dbg_kms(&dev_priv->drm,
@@ -3841,9 +3840,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- intel_add_fb_offsets(&x, &y, plane_state, 0);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
- alignment = intel_surf_alignment(fb, 0);
+ intel_add_fb_offsets(x, y, plane_state, 0);
+ *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
return -EINVAL;
@@ -3852,9 +3850,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* main surface offset, and it must be non-negative. Make
* sure that is what we will get.
*/
- if (aux_plane && offset > aux_offset)
- offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
- offset, aux_offset & ~(alignment - 1));
+ if (aux_plane && *offset > aux_offset)
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
+ *offset,
+ aux_offset & ~(alignment - 1));
/*
* When using an X-tiled surface, the plane blows up
@@ -3865,18 +3864,37 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
int cpp = fb->format->cpp[0];
- while ((x + w) * cpp > plane_state->color_plane[0].stride) {
- if (offset == 0) {
+ while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
+ if (*offset == 0) {
drm_dbg_kms(&dev_priv->drm,
"Unable to find suitable display surface offset due to X-tiling\n");
return -EINVAL;
}
- offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
- offset, offset - alignment);
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
+ *offset,
+ *offset - alignment);
}
}
+ return 0;
+}
+
+static int skl_check_main_surface(struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int x = plane_state->uapi.src.x1 >> 16;
+ int y = plane_state->uapi.src.y1 >> 16;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ u32 offset;
+ int ret;
+
+ ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
+ if (ret)
+ return ret;
/*
* CCS AUX surface doesn't have its own x/y offsets, we must make sure
* they match with the main surface x/y offsets.
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index b2969d8ff625..f9ce98eae020 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -636,6 +636,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
u32 skl_plane_stride(const struct intel_plane_state *plane_state,
int plane);
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+ int *x, int *y, u32 *offset);
int skl_check_plane_surface(struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() Gwan-gyeong Mun
@ 2020-11-27 14:10 ` Souza, Jose
0 siblings, 0 replies; 9+ messages in thread
From: Souza, Jose @ 2020-11-27 14:10 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Fri, 2020-11-27 at 12:50 +0200, Gwan-gyeong Mun wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> The calculation the offsets of the main surface will be needed by PSR2
> selective fetch code so here splitting and exporting it.
> No functional changes were done here.
>
> v3: Rebased
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 62 +++++++++++++-------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +
> 2 files changed, 42 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 595183f7b60f..da24f654a2f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3817,22 +3817,21 @@ static int intel_plane_max_height(struct intel_plane *plane,
> return INT_MAX;
> }
>
>
>
>
>
>
>
>
> -static int skl_check_main_surface(struct intel_plane_state *plane_state)
> +int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
> + int *x, int *y, u32 *offset)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> - unsigned int rotation = plane_state->hw.rotation;
> - int x = plane_state->uapi.src.x1 >> 16;
> - int y = plane_state->uapi.src.y1 >> 16;
> - int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> - int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> - int min_width = intel_plane_min_width(plane, fb, 0, rotation);
> - int max_width = intel_plane_max_width(plane, fb, 0, rotation);
> - int max_height = intel_plane_max_height(plane, fb, 0, rotation);
> - int aux_plane = intel_main_to_aux_plane(fb, 0);
> - u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> - u32 alignment, offset;
> + const unsigned int rotation = plane_state->hw.rotation;
> + const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
> + const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
> + const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
> + const int aux_plane = intel_main_to_aux_plane(fb, 0);
> + const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> + const u32 alignment = intel_surf_alignment(fb, 0);
> + const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> + const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
>
>
>
>
>
>
>
>
> if (w > max_width || w < min_width || h > max_height) {
This block should be kept in skl_check_main_surface(), also some variables above.
We don't need to run this checks again for PSR code.
> drm_dbg_kms(&dev_priv->drm,
> @@ -3841,9 +3840,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> return -EINVAL;
> }
>
>
>
>
> - intel_add_fb_offsets(&x, &y, plane_state, 0);
> - offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
> - alignment = intel_surf_alignment(fb, 0);
> + intel_add_fb_offsets(x, y, plane_state, 0);
> + *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
> if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
> return -EINVAL;
>
>
>
>
> @@ -3852,9 +3850,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> * main surface offset, and it must be non-negative. Make
> * sure that is what we will get.
> */
> - if (aux_plane && offset > aux_offset)
> - offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
> - offset, aux_offset & ~(alignment - 1));
> + if (aux_plane && *offset > aux_offset)
> + *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
> + *offset,
> + aux_offset & ~(alignment - 1));
>
>
>
>
> /*
> * When using an X-tiled surface, the plane blows up
> @@ -3865,18 +3864,37 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
> int cpp = fb->format->cpp[0];
>
>
>
>
> - while ((x + w) * cpp > plane_state->color_plane[0].stride) {
> - if (offset == 0) {
> + while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
> + if (*offset == 0) {
> drm_dbg_kms(&dev_priv->drm,
> "Unable to find suitable display surface offset due to X-tiling\n");
> return -EINVAL;
> }
>
>
>
>
> - offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
> - offset, offset - alignment);
> + *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
> + *offset,
> + *offset - alignment);
> }
> }
>
>
>
>
> + return 0;
> +}
> +
> +static int skl_check_main_surface(struct intel_plane_state *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int x = plane_state->uapi.src.x1 >> 16;
> + int y = plane_state->uapi.src.y1 >> 16;
> + const int aux_plane = intel_main_to_aux_plane(fb, 0);
> + const u32 alignment = intel_surf_alignment(fb, 0);
> + u32 offset;
> + int ret;
> +
> + ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
> + if (ret)
> + return ret;
> /*
> * CCS AUX surface doesn't have its own x/y offsets, we must make sure
> * they match with the main surface x/y offsets.
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index b2969d8ff625..f9ce98eae020 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -636,6 +636,8 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
> u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> int plane);
> +int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
> + int *x, int *y, u32 *offset);
> int skl_check_plane_surface(struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v3 4/5] drm/i915/display/psr: Program Plane's calculated offset to Plane SF register
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/display/psr: Calculate Trancoder's SU rect and plane's SF rect Gwan-gyeong Mun
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() Gwan-gyeong Mun
@ 2020-11-27 10:50 ` Gwan-gyeong Mun
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 5/5] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing Gwan-gyeong Mun
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Gwan-gyeong Mun @ 2020-11-27 10:50 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
It programs Plane's calculated x, y, offset to Plane SF register.
It does the calculation of x and y offsets using
skl_calc_main_surface_offset().
v3: Update commit message
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f314f550b809..03d46ea3fe7e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1186,7 +1186,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
const struct drm_rect *clip;
- u32 val;
+ u32 val, offset;
+ int ret, x, y;
if (!crtc_state->enable_psr2_sel_fetch)
return;
@@ -1203,9 +1204,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
val |= plane_state->uapi.dst.x1;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
- /* TODO: consider tiling and auxiliary surfaces */
- val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16;
- val |= plane_state->color_plane[color_plane].x;
+ /* TODO: consider auxiliary surfaces */
+ x = plane_state->uapi.src.x1 >> 16;
+ y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
+ ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
+ if (ret)
+ drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n",
+ ret);
+ val = y << 16 | x;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
val);
--
2.25.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread* [Intel-gfx] [PATCH v3 5/5] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
` (2 preceding siblings ...)
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 4/5] drm/i915/display/psr: Program Plane's calculated offset to Plane SF register Gwan-gyeong Mun
@ 2020-11-27 10:50 ` Gwan-gyeong Mun
2020-11-27 13:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Gwan-gyeong Mun @ 2020-11-27 10:50 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 330c03e2b4f7..b8b19270c339 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0600) \
- param(bool, enable_psr2_sel_fetch, false, 0600) \
+ param(bool, enable_psr2_sel_fetch, true, 0600) \
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
--
2.25.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
` (3 preceding siblings ...)
2020-11-27 10:50 ` [Intel-gfx] [PATCH v3 5/5] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing Gwan-gyeong Mun
@ 2020-11-27 13:46 ` Patchwork
2020-11-27 13:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-27 14:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-11-27 13:46 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0519f1c556bc drm/i915/display/psr: Calculate selective fetch plane registers
a394d94d01f2 drm/i915/display/psr: Calculate Trancoder's SU rect and plane's SF rect
-:42: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+ (__i) >= 0 && \
+ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(plane)
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'plane' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+ (__i) >= 0 && \
+ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(plane)
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/display/intel_display.h:468:
+#define for_each_oldnew_intel_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_total_plane - 1; \
+ (__i) >= 0 && \
+ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
+ (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(plane)
-:46: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_display.h:472:
+ (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
-:47: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_display.h:473:
+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
-:92: CHECK:LINE_SPACING: Please don't use multiple blank lines
#92: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1277:
+
+
-:261: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#261: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1418:
+ new_plane_state, i) {
+
total: 0 errors, 3 warnings, 5 checks, 292 lines checked
6f2d0e56e996 drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
4286e9f831a3 drm/i915/display/psr: Program Plane's calculated offset to Plane SF register
968a799d4c11 HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
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^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
` (4 preceding siblings ...)
2020-11-27 13:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers Patchwork
@ 2020-11-27 13:48 ` Patchwork
2020-11-27 14:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-11-27 13:48 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
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^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
2020-11-27 10:50 [Intel-gfx] [PATCH v3 1/5] drm/i915/display/psr: Calculate selective fetch plane registers Gwan-gyeong Mun
` (5 preceding siblings ...)
2020-11-27 13:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-11-27 14:17 ` Patchwork
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-11-27 14:17 UTC (permalink / raw)
To: Gwan-gyeong Mun; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 9172 bytes --]
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/display/psr: Calculate selective fetch plane registers
URL : https://patchwork.freedesktop.org/series/84340/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9398 -> Patchwork_18997
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18997 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18997, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18997:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-tgl-y: [PASS][1] -> [FAIL][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-y: [DMESG-WARN][3] ([i915#1982]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
New tests
---------
New tests have been introduced between CI_DRM_9398 and Patchwork_18997:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18997 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#402] / [k.org#205379])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@i915_module_load@reload.html
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#1982] / [k.org#205379])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@i915_pm_rpm@module-reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@i915_pm_rpm@module-reload.html
* igt@kms_busy@basic@flip:
- fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_busy@basic@flip.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_psr@primary_page_flip:
- fi-tgl-u2: [PASS][17] -> [SKIP][18] ([i915#668]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-u2/igt@kms_psr@primary_page_flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-u2/igt@kms_psr@primary_page_flip.html
* igt@vgem_basic@setversion:
- fi-tgl-y: [PASS][19] -> [DMESG-WARN][20] ([i915#402]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@vgem_basic@setversion.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@vgem_basic@setversion.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {fi-ehl-1}: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-ehl-1/igt@i915_pm_rpm@basic-pci-d3-state.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-ehl-1/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-apl-guc: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-apl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-apl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][29] ([i915#165]) -> [PASS][30] +15 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-tgl-y: [DMESG-WARN][31] ([i915#2411]) -> [DMESG-WARN][32] ([i915#1982] / [i915#2411])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-y: [DMESG-WARN][33] ([i915#1982]) -> [FAIL][34] ([i915#2416])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9398/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/fi-tgl-y/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (43 -> 40)
------------------------------
Additional (1): fi-cml-u2
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9398 -> Patchwork_18997
CI-20190529: 20190529
CI_DRM_9398: 31a04133814ab8f7b3aab042517e3f104df5ee2d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5873: b6321b58dcaa41ba1d28aced42d6b15dc3d49ca2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18997: 968a799d4c11722eccab3f1a190c81e2b5cfd9db @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
968a799d4c11 HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
4286e9f831a3 drm/i915/display/psr: Program Plane's calculated offset to Plane SF register
6f2d0e56e996 drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
a394d94d01f2 drm/i915/display/psr: Calculate Trancoder's SU rect and plane's SF rect
0519f1c556bc drm/i915/display/psr: Calculate selective fetch plane registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18997/index.html
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