* [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness
@ 2020-12-10 2:09 Chris Wilson
2020-12-10 3:18 ` [igt-dev] ✗ Fi.CI.BAT: failure for i915/gem_exec_schedule: Try to spot unfairness (rev12) Patchwork
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Chris Wilson @ 2020-12-10 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Chris Wilson
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work in client and asserts that they take an equal amount of
time.
Though we have never claimed to have a completely fair scheduler, that
is what is expected.
v2: igt_assert_f and more commentary; exclude vip from client stats,
include range of frame intervals from each individual client
v3: Write down what the test actually does!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
---
tests/i915/gem_exec_schedule.c | 954 +++++++++++++++++++++++++++++++++
1 file changed, 954 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index f23d63ac3..67cf88e72 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -29,6 +29,7 @@
#include <sys/poll.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
+#include <sys/resource.h>
#include <sys/syscall.h>
#include <sched.h>
#include <signal.h>
@@ -2516,6 +2517,926 @@ static void measure_semaphore_power(int i915)
rapl_close(&pkg);
}
+static int read_timestamp_frequency(int i915)
+{
+ int value = 0;
+ drm_i915_getparam_t gp = {
+ .value = &value,
+ .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY,
+ };
+ ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp);
+ return value;
+}
+
+static uint64_t div64_u64_round_up(uint64_t x, uint64_t y)
+{
+ return (x + y - 1) / y;
+}
+
+static uint64_t ns_to_ctx_ticks(int i915, uint64_t ns)
+{
+ int f = read_timestamp_frequency(i915);
+ if (intel_gen(intel_get_drm_devid(i915)) == 11)
+ f = 12500000; /* icl!!! are you feeling alright? CTX vs CS */
+ return div64_u64_round_up(ns * f, NSEC_PER_SEC);
+}
+
+static uint64_t ticks_to_ns(int i915, uint64_t ticks)
+{
+ return div64_u64_round_up(ticks * NSEC_PER_SEC,
+ read_timestamp_frequency(i915));
+}
+
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x) (x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF 0x32
+#define MI_MATH_REG_CF 0x33
+
+#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
+
+static void delay(int i915,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint64_t addr,
+ uint64_t ns)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+#define CS_GPR(x) (base + 0x600 + 8 * (x))
+#define RUNTIME (base + 0x3a8)
+ enum { START_TS, NOW_TS };
+ uint32_t *map, *cs, *jmp;
+
+ igt_require(base);
+
+ /* Loop until CTX_TIMESTAMP - initial > @ns */
+
+ cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE);
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(START_TS) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG;
+ *cs++ = RUNTIME;
+ *cs++ = CS_GPR(START_TS);
+
+ while (offset_in_page(cs) & 63)
+ *cs++ = 0;
+ jmp = cs;
+
+ *cs++ = 0x5 << 23; /* MI_ARB_CHECK */
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(NOW_TS) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG;
+ *cs++ = RUNTIME;
+ *cs++ = CS_GPR(NOW_TS);
+
+ /* delta = now - start; inverted to match COND_BBE */
+ *cs++ = MI_MATH(4);
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
+ *cs++ = MI_MATH_SUB;
+ *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
+
+ /* Save delta for reading by COND_BBE */
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = CS_GPR(NOW_TS);
+ *cs++ = addr + 4000;
+ *cs++ = addr >> 32;
+
+ /* Delay between SRM and COND_BBE to post the writes */
+ for (int n = 0; n < 8; n++) {
+ *cs++ = MI_STORE_DWORD_IMM;
+ if (use_64b) {
+ *cs++ = addr + 4064;
+ *cs++ = addr >> 32;
+ } else {
+ *cs++ = 0;
+ *cs++ = addr + 4064;
+ }
+ *cs++ = 0;
+ }
+
+ /* Break if delta [time elapsed] > ns */
+ *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b);
+ *cs++ = ~ns_to_ctx_ticks(i915, ns);
+ *cs++ = addr + 4000;
+ *cs++ = addr >> 32;
+
+ /* Otherwise back to recalculating delta */
+ *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b;
+ *cs++ = addr + offset_in_page(jmp);
+ *cs++ = addr >> 32;
+
+ munmap(map, 4096);
+}
+
+static struct drm_i915_gem_exec_object2
+delay_create(int i915, uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t target_ns)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = batch_create(i915),
+ .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .rsvd1 = ctx,
+ .flags = e->flags,
+ };
+
+ obj.offset = obj.handle << 12;
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, obj.handle);
+
+ delay(i915, e, obj.handle, obj.offset, target_ns);
+
+ obj.flags |= EXEC_OBJECT_PINNED;
+ return obj;
+}
+
+static void tslog(int i915,
+ const struct intel_execution_engine2 *e,
+ uint32_t handle,
+ uint64_t addr)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+#define CS_GPR(x) (base + 0x600 + 8 * (x))
+#define CS_TIMESTAMP (base + 0x358)
+ enum { INC, MASK, ADDR };
+ uint32_t *timestamp_lo, *addr_lo;
+ uint32_t *map, *cs;
+
+ igt_require(base);
+
+ map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE);
+ cs = map + 512;
+
+ /* Record the current CS_TIMESTAMP into a journal [a 512 slot ring]. */
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = CS_TIMESTAMP;
+ timestamp_lo = cs;
+ *cs++ = addr;
+ *cs++ = addr >> 32;
+
+ /* Load the address + inc & mask variables */
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(ADDR);
+ addr_lo = cs;
+ *cs++ = addr;
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(ADDR) + 4;
+ *cs++ = addr >> 32;
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(INC);
+ *cs++ = 4;
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(INC) + 4;
+ *cs++ = 0;
+
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(MASK);
+ *cs++ = 0xfffff7ff;
+ *cs++ = MI_LOAD_REGISTER_IMM;
+ *cs++ = CS_GPR(MASK) + 4;
+ *cs++ = 0xffffffff;
+
+ /* Increment the [ring] address for saving CS_TIMESTAMP */
+ *cs++ = MI_MATH(8);
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(INC));
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR));
+ *cs++ = MI_MATH_ADD;
+ *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU);
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR));
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK));
+ *cs++ = MI_MATH_AND;
+ *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU);
+
+ /* Rewrite the batch buffer for the next execution */
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = CS_GPR(ADDR);
+ *cs++ = addr + offset_in_page(timestamp_lo);
+ *cs++ = addr >> 32;
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = CS_GPR(ADDR);
+ *cs++ = addr + offset_in_page(addr_lo);
+ *cs++ = addr >> 32;
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ munmap(map, 4096);
+}
+
+static struct drm_i915_gem_exec_object2
+tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = batch_create(i915),
+ .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .rsvd1 = ctx,
+ .flags = e->flags,
+ };
+
+ obj.offset = obj.handle << 12;
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, obj.handle);
+
+ tslog(i915, e, obj.handle, obj.offset);
+
+ obj.flags |= EXEC_OBJECT_PINNED;
+ return obj;
+}
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const uint32_t *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static bool has_ctx_timestamp(int i915, const struct intel_execution_engine2 *e)
+{
+ const int gen = intel_gen(intel_get_drm_devid(i915));
+
+ if (gen == 8 && e->class == I915_ENGINE_CLASS_VIDEO)
+ return false; /* looks fubar */
+
+ return true;
+}
+
+static struct intel_execution_engine2
+pick_random_engine(int i915, const struct intel_execution_engine2 *not)
+{
+ const struct intel_execution_engine2 *e;
+ unsigned int count = 0;
+
+ __for_each_physical_engine(i915, e) {
+ if (e->flags == not->flags)
+ continue;
+ if (!gem_class_has_mutable_submission(i915, e->class))
+ continue;
+ count++;
+ }
+ if (!count)
+ return *not;
+
+ count = rand() % count;
+ __for_each_physical_engine(i915, e) {
+ if (e->flags == not->flags)
+ continue;
+ if (!gem_class_has_mutable_submission(i915, e->class))
+ continue;
+ if (!count--)
+ break;
+ }
+
+ return *e;
+}
+
+static void fair_child(int i915, uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t frame_ns,
+ int timeline,
+ uint32_t common,
+ unsigned int flags,
+ unsigned long *ctl,
+ unsigned long *median,
+ unsigned long *iqr)
+#define F_SYNC (1 << 0)
+#define F_PACE (1 << 1)
+#define F_FLOW (1 << 2)
+#define F_HALF (1 << 3)
+#define F_SOLO (1 << 4)
+#define F_SPARE (1 << 5)
+#define F_NEXT (1 << 6)
+#define F_VIP (1 << 7)
+#define F_RRUL (1 << 8)
+#define F_SHARE (1 << 9)
+#define F_PING (1 << 10)
+#define F_THROTTLE (1 << 11)
+#define F_ISOLATE (1 << 12)
+{
+ const int batches_per_frame = flags & F_SOLO ? 1 : 3;
+ struct drm_i915_gem_exec_object2 obj[4] = {
+ {},
+ {
+ .handle = common ?: gem_create(i915, 4096),
+ },
+ delay_create(i915, ctx, e, frame_ns / batches_per_frame),
+ delay_create(i915, ctx, e, frame_ns / batches_per_frame),
+ };
+ struct intel_execution_engine2 ping = *e;
+ int p_fence = -1, n_fence = -1;
+ unsigned long count = 0;
+ int n;
+
+ srandom(getpid());
+ if (flags & F_PING)
+ ping = pick_random_engine(i915, e);
+ obj[0] = tslog_create(i915, ctx, &ping);
+
+ while (!READ_ONCE(*ctl)) {
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(obj),
+ .buffer_count = 3,
+ .rsvd1 = ctx,
+ .rsvd2 = -1,
+ .flags = e->flags,
+ };
+
+ if (flags & F_FLOW) {
+ unsigned int seq;
+
+ seq = count;
+ if (flags & F_NEXT)
+ seq++;
+
+ execbuf.rsvd2 =
+ sw_sync_timeline_create_fence(timeline, seq);
+ execbuf.flags |= I915_EXEC_FENCE_IN;
+ }
+
+ execbuf.flags |= I915_EXEC_FENCE_OUT;
+ gem_execbuf_wr(i915, &execbuf);
+ n_fence = execbuf.rsvd2 >> 32;
+ execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN);
+ for (n = 1; n < batches_per_frame; n++)
+ gem_execbuf(i915, &execbuf);
+ close(execbuf.rsvd2);
+
+ execbuf.buffer_count = 1;
+ execbuf.batch_start_offset = 2048;
+ execbuf.flags = ping.flags | I915_EXEC_FENCE_IN;
+ execbuf.rsvd2 = n_fence;
+ gem_execbuf(i915, &execbuf);
+
+ if (flags & F_PACE && p_fence != -1) {
+ struct pollfd pfd = {
+ .fd = p_fence,
+ .events = POLLIN,
+ };
+ poll(&pfd, 1, -1);
+ }
+ close(p_fence);
+
+ if (flags & F_SYNC) {
+ struct pollfd pfd = {
+ .fd = n_fence,
+ .events = POLLIN,
+ };
+ poll(&pfd, 1, -1);
+ }
+
+ if (flags & F_THROTTLE)
+ igt_ioctl(i915, DRM_IOCTL_I915_GEM_THROTTLE, 0);
+
+ igt_swap(obj[2], obj[3]);
+ igt_swap(p_fence, n_fence);
+ count++;
+ }
+ close(p_fence);
+
+ gem_close(i915, obj[3].handle);
+ gem_close(i915, obj[2].handle);
+ if (obj[1].handle != common)
+ gem_close(i915, obj[1].handle);
+
+ gem_sync(i915, obj[0].handle);
+ if (median) {
+ uint32_t *map;
+
+ /*
+ * We recorded the CS_TIMESTAMP of each frame, and if
+ * the GPU is being shared completely fairly, we expect
+ * each frame to be at the same interval from the last.
+ *
+ * Compute the interval between frames and report back
+ * both the median interval and the range for this client.
+ */
+
+ map = gem_mmap__device_coherent(i915, obj[0].handle,
+ 0, 4096, PROT_WRITE);
+ for (n = 1; n < min(count, 512); n++) {
+ igt_assert(map[n]);
+ map[n - 1] = map[n] - map[n - 1];
+ }
+ qsort(map, --n, sizeof(*map), cmp_u32);
+ *iqr = ticks_to_ns(i915, map[(3 * n + 3) / 4] - map[n / 4]);
+ *median = ticks_to_ns(i915, map[n / 2]);
+ munmap(map, 4096);
+ }
+ gem_close(i915, obj[0].handle);
+}
+
+static int cmp_ul(const void *A, const void *B)
+{
+ const unsigned long *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static uint64_t d_cpu_time(const struct rusage *a, const struct rusage *b)
+{
+ uint64_t cpu_time = 0;
+
+ cpu_time += (a->ru_utime.tv_sec - b->ru_utime.tv_sec) * NSEC_PER_SEC;
+ cpu_time += (a->ru_utime.tv_usec - b->ru_utime.tv_usec) * 1000;
+
+ cpu_time += (a->ru_stime.tv_sec - b->ru_stime.tv_sec) * NSEC_PER_SEC;
+ cpu_time += (a->ru_stime.tv_usec - b->ru_stime.tv_usec) * 1000;
+
+ return cpu_time;
+}
+
+static void timeline_advance(int timeline, int delay_ns)
+{
+ struct timespec tv = { .tv_nsec = delay_ns };
+ nanosleep(&tv, NULL);
+ sw_sync_timeline_inc(timeline, 1);
+}
+
+static void fairness(int i915,
+ const struct intel_execution_engine2 *e,
+ int timeout, unsigned int flags)
+{
+ const int frame_ns = 16666 * 1000;
+ const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns;
+ unsigned long *result, *iqr;
+ uint32_t common = 0;
+
+ igt_require(has_ctx_timestamp(i915, e));
+ igt_require(gem_class_has_mutable_submission(i915, e->class));
+
+ if (flags & F_SHARE)
+ common = gem_create(i915, 4095);
+
+ result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(result != MAP_FAILED);
+ iqr = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
+ igt_assert(iqr != MAP_FAILED);
+
+ /*
+ * The combined workload always runs at a 60fps target (unless F_HALF!).
+ * This gives a frame of interval of 16ms that is evenly split across
+ * all the clients, so simulating a system with a bunch of clients that
+ * are perfectly balanced and can sustain 60fps. Our job is to ensure
+ * that each client does run at a smooth 60fps.
+ *
+ * Each client runs a fixed length delay loop (as a single request,
+ * or split into 3) and then records the CS_TIMESTAMP after completing
+ * its delay. Given a fair allotment of GPU time to each client,
+ * that timestamp will [ideally] be at a precise 16ms intervals.
+ * In practice, time is wasted on context switches, so as the number
+ * of clients increases, the proprotion of time spent on context
+ * switches grows. As we get to 64 render clients, we will be spending
+ * as much time in context switches as executing the client workloads.
+ *
+ * Each client frame may be paced by some throttling technique found
+ * in the wild. i.e. each client may wait until a simulated vblank
+ * to indicate the start of a new frame, or it may wait until the
+ * completion of a previous frame. This causes submission from each
+ * client and across the system to be chunky and uneven.
+ *
+ * We look at the variation of frame intervals within each client, and
+ * the variation of the medians across the clients to see if the
+ * distribution (budget) of GPU time was fair enough.
+ *
+ * Alternative (and important) metrics will be more latency centric;
+ * looking at how well we can sustain meeting deadline given competition
+ * by clients for the GPU.
+ */
+
+ for (int n = 2; n <= 256; n <<= 1) { /* 32 == 500us per client */
+ int timeline = sw_sync_timeline_create();
+ int nfences = timeout * NSEC_PER_SEC / fence_ns + 1;
+ int nchild = n - 1; /* odd for easy medians */
+ const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE));
+ const int lo = nchild / 4;
+ const int hi = (3 * nchild + 3) / 4 - 1;
+ struct rusage old_usage, usage;
+ uint64_t cpu_time, d_time;
+ struct timespec tv;
+ struct igt_mean m;
+
+ memset(result, 0, (nchild + 1) * sizeof(result[0]));
+
+ if (flags & F_PING) { /* fill the others with light bg load */
+ struct intel_execution_engine2 *ping;
+
+ __for_each_physical_engine(i915, ping) {
+ if (ping->flags == e->flags)
+ continue;
+
+ igt_fork(child, 1) {
+ uint32_t ctx = gem_context_clone_with_engines(i915, 0);
+
+ fair_child(i915, ctx, ping,
+ child_ns / 8,
+ -1, common,
+ F_SOLO | F_PACE | F_SHARE,
+ &result[nchild],
+ NULL, NULL);
+
+ gem_context_destroy(i915, ctx);
+ }
+ }
+ }
+
+ getrusage(RUSAGE_CHILDREN, &old_usage);
+ igt_nsec_elapsed(memset(&tv, 0, sizeof(tv)));
+ igt_fork(child, nchild) {
+ uint32_t ctx;
+
+ if (flags & F_ISOLATE) {
+ int clone, dmabuf = -1;
+
+ if (common)
+ dmabuf = prime_handle_to_fd(i915, common);
+
+ clone = gem_reopen_driver(i915);
+ gem_context_copy_engines(i915, 0, clone, 0);
+ i915 = clone;
+
+ if (dmabuf != -1)
+ common = prime_fd_to_handle(i915, dmabuf);
+ }
+
+ ctx = gem_context_clone_with_engines(i915, 0);
+
+ if (flags & F_VIP && child == 0) {
+ gem_context_set_priority(i915, ctx, MAX_PRIO);
+ flags |= F_FLOW;
+ }
+ if (flags & F_RRUL && child == 0)
+ flags |= F_SOLO | F_FLOW | F_SYNC;
+
+ fair_child(i915, ctx, e, child_ns,
+ timeline, common, flags,
+ &result[nchild],
+ &result[child], &iqr[child]);
+
+ gem_context_destroy(i915, ctx);
+ }
+
+ while (nfences--)
+ timeline_advance(timeline, fence_ns);
+
+ result[nchild] = 1;
+ for (int child = 0; child < nchild; child++) {
+ while (!READ_ONCE(result[child]))
+ timeline_advance(timeline, fence_ns);
+ }
+
+ igt_waitchildren();
+ close(timeline);
+
+ /*
+ * Are we running out of CPU time, and fail to submit frames?
+ *
+ * We try to rule out any undue impact on the GPU scheduling
+ * from the CPU scheduler by looking for core saturation. If
+ * we may be in a situation where the clients + kernel are
+ * taking a whole core (think lockdep), then it is increasingly
+ * likely that our measurements include delays from the CPU
+ * scheduler. Err on the side of caution.
+ */
+ d_time = igt_nsec_elapsed(&tv);
+ getrusage(RUSAGE_CHILDREN, &usage);
+ cpu_time = d_cpu_time(&usage, &old_usage);
+ igt_debug("CPU usage: %.0f%%\n", 100. * cpu_time / d_time);
+ if (4 * cpu_time > 3 * d_time) {
+ if (nchild > 7) /* good enough to judge pass/fail */
+ break;
+
+ igt_skip_on_f(4 * cpu_time > 3 * d_time,
+ "%.0f%% CPU usage, presuming capacity exceeded\n",
+ 100. * cpu_time / d_time);
+ }
+
+ /* With no contention, we should match our target frametime */
+ if (nchild == 1) {
+ igt_assert(4 * result[0] > 3 * fence_ns &&
+ 3 * result[0] < 4 * fence_ns);
+ continue;
+ }
+
+ /*
+ * The VIP should always be able to hit the target frame rate;
+ * regardless of budget contention from lessor clients.
+ */
+ if (flags & (F_VIP | F_RRUL)) {
+ igt_info("VIP interval %.2fms, range %.2fms\n",
+ 1e-6 * result[0], 1e-6 * iqr[0]);
+ igt_assert_f(4 * result[0] > 3 * fence_ns &&
+ 3 * result[0] < 4 * fence_ns,
+ "VIP expects to run exactly when it wants, expects an interval of %.2fms, was %.2fms\n",
+ 1e-6 * fence_ns, 1e-6 * result[0]);
+ igt_assert_f(2 * iqr[0] < result[0],
+ "VIP frame IQR %.2fms exceeded median threshold %.2fms\n",
+ 1e-6 * iqr[0],
+ 1e-6 * result[0] / 2);
+ if (!--nchild)
+ continue;
+
+ /* Exclude the VIP result from the plebian statistics */
+ memmove(result, result + 1, nchild * sizeof(*result));
+ memmove(iqr, iqr + 1, nchild * sizeof(*iqr));
+ }
+
+ igt_mean_init(&m);
+ for (int child = 0; child < nchild; child++)
+ igt_mean_add(&m, result[child]);
+
+ qsort(result, nchild, sizeof(*result), cmp_ul);
+ qsort(iqr, nchild, sizeof(*iqr), cmp_ul);
+
+ /*
+ * The target interval for median/mean is 16ms (fence_ns).
+ * However, this work is evenly split across the clients so
+ * the range (and median) of client medians may be much less
+ * than 16ms [16/3N]. We present median of medians to try
+ * and avoid any instability while running in CI; at the cost
+ * of insensitivity!
+ */
+ igt_info("%3d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f [%.1f, %.1f], mean: %.1f ± %.2f ms\n",
+ nchild,
+ 1e-6 * result[0], 1e-6 * result[nchild - 1],
+ 1e-6 * result[lo], 1e-6 * result[hi],
+ 1e-6 * result[nchild / 2],
+ 1e-6 * iqr[lo], 1e-6 * iqr[hi],
+ 1e-6 * igt_mean_get(&m),
+ 1e-6 * sqrt(igt_mean_get_variance(&m)));
+
+ igt_assert_f(iqr[nchild / 2] < 2 * result[nchild / 2],
+ "Child frame IQR %.2fms exceeded median threshold %.2fms\n",
+ 1e-6 * iqr[nchild / 2],
+ 1e-6 * result[nchild / 2] * 2);
+
+ igt_assert_f(4 * igt_mean_get(&m) > 3 * result[nchild / 2] &&
+ 3 * igt_mean_get(&m) < 4 * result[nchild / 2],
+ "Mean of client interval %.2fms differs from median %.2fms, distribution is skewed\n",
+
+ 1e-6 * igt_mean_get(&m), 1e-6 * result[nchild / 2]);
+
+ igt_assert_f(2 * (result[hi] - result[lo]) < result[nchild / 2],
+ "Interquartile range of client intervals %.2fms is as large as the median threshold %.2fms, clients are not evenly distributed!\n",
+ 1e-6 * (result[hi] - result[lo]),
+ 1e-6 * result[nchild / 2] / 2);
+
+ /* May be slowed due to sheer volume of context switches */
+ if (result[0] > 2 * fence_ns)
+ break;
+ }
+
+ munmap(iqr, 4096);
+ munmap(result, 4096);
+ if (common)
+ gem_close(i915, common);
+}
+
+static void test_fairness(int i915, int timeout)
+{
+ static const struct {
+ const char *name;
+ unsigned int flags;
+ } fair[] = {
+ /*
+ * none - maximal greed in each client
+ *
+ * Push as many frames from each client as fast as possible
+ */
+ { "none", 0 },
+ { "none-vip", F_VIP }, /* one vip client must meet deadlines */
+ { "none-solo", F_SOLO }, /* 1 batch per frame per client */
+ { "none-share", F_SHARE }, /* read from a common buffer */
+ { "none-rrul", F_RRUL }, /* "realtime-response under load" */
+ { "none-ping", F_PING }, /* measure inter-engine fairness */
+
+ /*
+ * throttle - original per client throttling
+ *
+ * Used for front buffering rendering where there is no
+ * extenal frame marker. Each client tries to only keep
+ * 20ms of work submitted, though that measurement is
+ * flawed...
+ *
+ * This is used by Xorg to try and maintain some resembalance
+ * of input/output consistency when being feed a continuous
+ * stream of X11 draw requests straight into scanout, where
+ * the clients may submit the work faster than can be drawn.
+ *
+ * Throttling tracks requests per-file (and assumes that
+ * all requests are in submission order across the whole file),
+ * so we split each child to its own fd.
+ */
+ { "throttle", F_THROTTLE | F_ISOLATE },
+ { "throttle-vip", F_THROTTLE | F_ISOLATE | F_VIP },
+ { "throttle-solo", F_THROTTLE | F_ISOLATE | F_SOLO },
+ { "throttle-share", F_THROTTLE | F_ISOLATE | F_SHARE },
+ { "throttle-rrul", F_THROTTLE | F_ISOLATE | F_RRUL },
+
+ /*
+ * pace - mesa "submit double buffering"
+ *
+ * Submit a frame, wait for previous frame to start. This
+ * prevents each client from getting too far ahead of its
+ * rendering, maintaining a consistent input/output latency.
+ */
+ { "pace", F_PACE },
+ { "pace-solo", F_PACE | F_SOLO },
+ { "pace-share", F_PACE | F_SOLO | F_SHARE },
+ { "pace-ping", F_PACE | F_SOLO | F_SHARE | F_PING},
+
+ /* sync - only submit a frame at a time */
+ { "sync", F_SYNC },
+ { "sync-vip", F_SYNC | F_VIP },
+ { "sync-solo", F_SYNC | F_SOLO },
+
+ /* flow - synchronise execution against the clock (vblank) */
+ { "flow", F_PACE | F_FLOW },
+ { "flow-solo", F_PACE | F_FLOW | F_SOLO },
+ { "flow-share", F_PACE | F_FLOW | F_SHARE },
+ { "flow-ping", F_PACE | F_FLOW | F_SHARE | F_PING },
+
+ /* next - submit ahead of the clock (vblank double buffering) */
+ { "next", F_PACE | F_FLOW | F_NEXT },
+ { "next-solo", F_PACE | F_FLOW | F_NEXT | F_SOLO },
+ { "next-share", F_PACE | F_FLOW | F_NEXT | F_SHARE },
+ { "next-ping", F_PACE | F_FLOW | F_NEXT | F_SHARE | F_PING },
+
+ /* spare - underutilise by a single client timeslice */
+ { "spare", F_PACE | F_FLOW | F_SPARE },
+ { "spare-solo", F_PACE | F_FLOW | F_SPARE | F_SOLO },
+
+ /* half - run at half pace (submit 16ms of work every 32ms) */
+ { "half", F_PACE | F_FLOW | F_HALF },
+ { "half-solo", F_PACE | F_FLOW | F_HALF | F_SOLO },
+
+ {}
+ };
+
+ igt_fixture {
+ igt_info("CS timestamp frequency: %d\n",
+ read_timestamp_frequency(i915));
+
+ igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8);
+ }
+
+ for (typeof(*fair) *f = fair; f->name; f++) {
+ igt_subtest_with_dynamic_f("fair-%s", f->name) {
+ const struct intel_execution_engine2 *e;
+
+ __for_each_physical_engine(i915, e) {
+ if (!gem_class_can_store_dword(i915, e->class))
+ continue;
+
+ igt_dynamic_f("%s", e->name)
+ fairness(i915, e, timeout, f->flags);
+ }
+ }
+ }
+}
+
+static uint32_t read_ctx_timestamp(int i915,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e)
+{
+ const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8;
+ const uint32_t base = gem_engine_mmio_base(i915, e->name);
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = gem_create(i915, 4096),
+ .offset = 32 << 20,
+ .relocs_ptr = to_user_pointer(&reloc),
+ .relocation_count = 1,
+ };
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = e->flags,
+ .rsvd1 = ctx,
+ };
+#define RUNTIME (base + 0x3a8)
+ uint32_t *map, *cs;
+ uint32_t ts;
+
+ igt_require(base);
+
+ cs = map = gem_mmap__device_coherent(i915, obj.handle,
+ 0, 4096, PROT_WRITE);
+
+ *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */
+ *cs++ = RUNTIME;
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.target_handle = obj.handle;
+ reloc.presumed_offset = obj.offset;
+ reloc.offset = offset_in_page(cs);
+ reloc.delta = 4000;
+ *cs++ = obj.offset + 4000;
+ *cs++ = obj.offset >> 32;
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, obj.handle);
+ gem_close(i915, obj.handle);
+
+ ts = map[1000];
+ munmap(map, 4096);
+
+ return ts;
+}
+
+static void fairslice(int i915,
+ const struct intel_execution_engine2 *e,
+ unsigned long flags)
+{
+ igt_spin_t *spin = NULL;
+ uint32_t ctx[3];
+ uint32_t ts[3];
+
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++) {
+ ctx[i] = gem_context_clone_with_engines(i915, 0);
+ if (spin == NULL) {
+ spin = __igt_spin_new(i915,
+ .ctx = ctx[i],
+ .engine = e->flags,
+ .flags = flags);
+ } else {
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&spin->obj[IGT_SPIN_BATCH]),
+ .flags = e->flags,
+ .rsvd1 = ctx[i],
+ };
+ gem_execbuf(i915, &eb);
+ }
+ }
+
+ sleep(2); /* over the course of many timeslices */
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ igt_spin_end(spin);
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++)
+ ts[i] = read_ctx_timestamp(i915, ctx[i], e);
+
+ for (int i = 0; i < ARRAY_SIZE(ctx); i++)
+ gem_context_destroy(i915, ctx[i]);
+ igt_spin_free(i915, spin);
+
+ qsort(ts, 3, sizeof(*ts), cmp_u32);
+ igt_info("%s: [%.1f, %.1f, %.1f] ms\n", e->name,
+ 1e-6 * ticks_to_ns(i915, ts[0]),
+ 1e-6 * ticks_to_ns(i915, ts[1]),
+ 1e-6 * ticks_to_ns(i915, ts[2]));
+
+ igt_assert_f(ts[2], "CTX_TIMESTAMP not reported!\n");
+ igt_assert_f((ts[2] - ts[0]) * 6 < ts[1],
+ "Range of timeslices greater than tolerable: %.2fms > %.2fms; unfair!\n",
+ 1e-6 * ticks_to_ns(i915, ts[2] - ts[0]),
+ 1e-6 * ticks_to_ns(i915, ts[1]) / 6);
+}
+
#define test_each_engine(T, i915, e) \
igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \
igt_dynamic_f("%s", e->name)
@@ -2582,6 +3503,35 @@ igt_main
test_each_engine("lateslice", fd, e)
lateslice(fd, e->flags);
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(gem_scheduler_has_semaphores(fd));
+ igt_require(gem_scheduler_has_preemption(fd));
+ igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8);
+ }
+
+ test_each_engine("fairslice", fd, e)
+ fairslice(fd, e, 0);
+
+ test_each_engine("u-fairslice", fd, e)
+ fairslice(fd, e, IGT_SPIN_USERPTR);
+
+ igt_subtest("fairslice-all") {
+ __for_each_physical_engine(fd, e) {
+ igt_fork(child, 1)
+ fairslice(fd, e, 0);
+ }
+ igt_waitchildren();
+ }
+ igt_subtest("u-fairslice-all") {
+ __for_each_physical_engine(fd, e) {
+ igt_fork(child, 1)
+ fairslice(fd, e, IGT_SPIN_USERPTR);
+ }
+ igt_waitchildren();
+ }
+ }
+
test_each_engine("submit-early-slice", fd, e)
submit_slice(fd, e, EARLY_SUBMIT);
test_each_engine("submit-golden-slice", fd, e)
@@ -2610,6 +3560,10 @@ igt_main
test_each_engine_store("promotion", fd, e)
promotion(fd, e->flags);
+ igt_subtest_group {
+ test_fairness(fd, 2);
+ }
+
igt_subtest_group {
igt_fixture {
igt_require(gem_scheduler_has_preemption(fd));
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for i915/gem_exec_schedule: Try to spot unfairness (rev12)
2020-12-10 2:09 [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Chris Wilson
@ 2020-12-10 3:18 ` Patchwork
2020-12-10 8:21 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_schedule: Try to spot unfairness (rev13) Patchwork
2020-12-10 11:06 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-12-10 3:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 6063 bytes --]
== Series Details ==
Series: i915/gem_exec_schedule: Try to spot unfairness (rev12)
URL : https://patchwork.freedesktop.org/series/77887/
State : failure
== Summary ==
CI Bug Log - changes from IGT_5887 -> IGTPW_5265
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5265 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5265, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5265:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5887/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
Known issues
------------
Here are the changes found in IGTPW_5265 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271]) +22 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][4] ([i915#2283])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html
* igt@i915_selftest@live@gt_timelines:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#2750])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5887/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [PASS][7] -> [DMESG-FAIL][8] ([i915#165])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5887/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5887/fi-tgl-y/igt@prime_vgem@basic-read.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-tgl-y/igt@prime_vgem@basic-read.html
* igt@runner@aborted:
- fi-snb-2600: NOTRUN -> [FAIL][11] ([i915#698])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-snb-2600/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u: [DMESG-WARN][12] ([i915#2605]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5887/fi-kbl-7500u/igt@i915_pm_rpm@module-reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-kbl-7500u/igt@i915_pm_rpm@module-reload.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5887/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#2750]: https://gitlab.freedesktop.org/drm/intel/issues/2750
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#698]: https://gitlab.freedesktop.org/drm/intel/issues/698
Participating hosts (43 -> 39)
------------------------------
Missing (4): fi-ilk-m540 fi-dg1-1 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5887 -> IGTPW_5265
CI-20190529: 20190529
CI_DRM_9467: 97bdde324e46e276a88de5d2d0c759b4309173c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5265: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/index.html
IGT_5887: 7d87d0f1a22544e6a78dc0920b3f54b64144a029 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_schedule@fairslice
+igt@gem_exec_schedule@fairslice-all
+igt@gem_exec_schedule@fair-flow
+igt@gem_exec_schedule@fair-flow-ping
+igt@gem_exec_schedule@fair-flow-share
+igt@gem_exec_schedule@fair-flow-solo
+igt@gem_exec_schedule@fair-half
+igt@gem_exec_schedule@fair-half-solo
+igt@gem_exec_schedule@fair-next
+igt@gem_exec_schedule@fair-next-ping
+igt@gem_exec_schedule@fair-next-share
+igt@gem_exec_schedule@fair-next-solo
+igt@gem_exec_schedule@fair-none
+igt@gem_exec_schedule@fair-none-ping
+igt@gem_exec_schedule@fair-none-rrul
+igt@gem_exec_schedule@fair-none-share
+igt@gem_exec_schedule@fair-none-solo
+igt@gem_exec_schedule@fair-none-vip
+igt@gem_exec_schedule@fair-pace
+igt@gem_exec_schedule@fair-pace-ping
+igt@gem_exec_schedule@fair-pace-share
+igt@gem_exec_schedule@fair-pace-solo
+igt@gem_exec_schedule@fair-spare
+igt@gem_exec_schedule@fair-spare-solo
+igt@gem_exec_schedule@fair-sync
+igt@gem_exec_schedule@fair-sync-solo
+igt@gem_exec_schedule@fair-sync-vip
+igt@gem_exec_schedule@fair-throttle
+igt@gem_exec_schedule@fair-throttle-rrul
+igt@gem_exec_schedule@fair-throttle-share
+igt@gem_exec_schedule@fair-throttle-solo
+igt@gem_exec_schedule@fair-throttle-vip
+igt@gem_exec_schedule@u-fairslice
+igt@gem_exec_schedule@u-fairslice-all
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5265/index.html
[-- Attachment #1.2: Type: text/html, Size: 7168 bytes --]
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 4+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_schedule: Try to spot unfairness (rev13)
2020-12-10 2:09 [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Chris Wilson
2020-12-10 3:18 ` [igt-dev] ✗ Fi.CI.BAT: failure for i915/gem_exec_schedule: Try to spot unfairness (rev12) Patchwork
@ 2020-12-10 8:21 ` Patchwork
2020-12-10 11:06 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-12-10 8:21 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 4451 bytes --]
== Series Details ==
Series: i915/gem_exec_schedule: Try to spot unfairness (rev13)
URL : https://patchwork.freedesktop.org/series/77887/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9468 -> IGTPW_5266
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/index.html
Known issues
------------
Here are the changes found in IGTPW_5266 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@create-fd-close:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-y/igt@gem_basic@create-fd-close.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/fi-tgl-y/igt@gem_basic@create-fd-close.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#2411] / [i915#402])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][7] -> [DMESG-WARN][8] ([i915#165]) +15 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Possible fixes ####
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 39)
------------------------------
Missing (4): fi-ilk-m540 fi-dg1-1 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5887 -> IGTPW_5266
CI-20190529: 20190529
CI_DRM_9468: b7b601789c54389ad15a5a3fd68e6988bb47631e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5266: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/index.html
IGT_5887: 7d87d0f1a22544e6a78dc0920b3f54b64144a029 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_schedule@fairslice
+igt@gem_exec_schedule@fairslice-all
+igt@gem_exec_schedule@fair-flow
+igt@gem_exec_schedule@fair-flow-ping
+igt@gem_exec_schedule@fair-flow-share
+igt@gem_exec_schedule@fair-flow-solo
+igt@gem_exec_schedule@fair-half
+igt@gem_exec_schedule@fair-half-solo
+igt@gem_exec_schedule@fair-next
+igt@gem_exec_schedule@fair-next-ping
+igt@gem_exec_schedule@fair-next-share
+igt@gem_exec_schedule@fair-next-solo
+igt@gem_exec_schedule@fair-none
+igt@gem_exec_schedule@fair-none-ping
+igt@gem_exec_schedule@fair-none-rrul
+igt@gem_exec_schedule@fair-none-share
+igt@gem_exec_schedule@fair-none-solo
+igt@gem_exec_schedule@fair-none-vip
+igt@gem_exec_schedule@fair-pace
+igt@gem_exec_schedule@fair-pace-ping
+igt@gem_exec_schedule@fair-pace-share
+igt@gem_exec_schedule@fair-pace-solo
+igt@gem_exec_schedule@fair-spare
+igt@gem_exec_schedule@fair-spare-solo
+igt@gem_exec_schedule@fair-sync
+igt@gem_exec_schedule@fair-sync-solo
+igt@gem_exec_schedule@fair-sync-vip
+igt@gem_exec_schedule@fair-throttle
+igt@gem_exec_schedule@fair-throttle-rrul
+igt@gem_exec_schedule@fair-throttle-share
+igt@gem_exec_schedule@fair-throttle-solo
+igt@gem_exec_schedule@fair-throttle-vip
+igt@gem_exec_schedule@u-fairslice
+igt@gem_exec_schedule@u-fairslice-all
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/index.html
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_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 4+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915/gem_exec_schedule: Try to spot unfairness (rev13)
2020-12-10 2:09 [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Chris Wilson
2020-12-10 3:18 ` [igt-dev] ✗ Fi.CI.BAT: failure for i915/gem_exec_schedule: Try to spot unfairness (rev12) Patchwork
2020-12-10 8:21 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_schedule: Try to spot unfairness (rev13) Patchwork
@ 2020-12-10 11:06 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-12-10 11:06 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: i915/gem_exec_schedule: Try to spot unfairness (rev13)
URL : https://patchwork.freedesktop.org/series/77887/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9468_full -> IGTPW_5266_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_5266_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_exec_schedule@fair-next-ping@vecs0} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1] +11 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb5/igt@gem_exec_schedule@fair-next-ping@vecs0.html
* {igt@gem_exec_schedule@fair-pace-ping@vcs0} (NEW):
- shard-tglb: NOTRUN -> [SKIP][2] +14 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-tglb8/igt@gem_exec_schedule@fair-pace-ping@vcs0.html
* {igt@gem_exec_schedule@fair-pace-share@vcs0} (NEW):
- shard-glk: NOTRUN -> [FAIL][3] +9 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-glk7/igt@gem_exec_schedule@fair-pace-share@vcs0.html
* {igt@gem_exec_schedule@fair-pace-solo@vcs0} (NEW):
- shard-kbl: NOTRUN -> [FAIL][4] +11 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-kbl7/igt@gem_exec_schedule@fair-pace-solo@vcs0.html
* {igt@gem_exec_schedule@fair-throttle-solo@vcs1} (NEW):
- shard-tglb: NOTRUN -> [FAIL][5] +46 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-tglb7/igt@gem_exec_schedule@fair-throttle-solo@vcs1.html
* {igt@gem_exec_schedule@fair-throttle@vcs0} (NEW):
- shard-iclb: NOTRUN -> [FAIL][6] +33 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb2/igt@gem_exec_schedule@fair-throttle@vcs0.html
New tests
---------
New tests have been introduced between CI_DRM_9468_full and IGTPW_5266_full:
### New IGT tests (189) ###
* igt@gem_exec_schedule@fair-flow:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-flow-ping:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-flow-ping@bcs0:
- Statuses : 5 skip(s)
- Exec time: [0.0, 4.21] s
* igt@gem_exec_schedule@fair-flow-ping@rcs0:
- Statuses : 5 skip(s)
- Exec time: [2.13, 4.22] s
* igt@gem_exec_schedule@fair-flow-ping@vcs0:
- Statuses : 5 skip(s)
- Exec time: [2.15, 4.22] s
* igt@gem_exec_schedule@fair-flow-ping@vcs1:
- Statuses : 2 skip(s)
- Exec time: [2.17, 4.21] s
* igt@gem_exec_schedule@fair-flow-ping@vecs0:
- Statuses : 5 skip(s)
- Exec time: [2.15, 4.22] s
* igt@gem_exec_schedule@fair-flow-share:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-flow-share@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.07] s
* igt@gem_exec_schedule@fair-flow-share@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.62, 13.09] s
* igt@gem_exec_schedule@fair-flow-share@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.63, 13.07] s
* igt@gem_exec_schedule@fair-flow-share@vcs1:
- Statuses : 2 pass(s)
- Exec time: [11.16, 13.07] s
* igt@gem_exec_schedule@fair-flow-share@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.62, 13.08] s
* igt@gem_exec_schedule@fair-flow-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-flow-solo@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 10.85] s
* igt@gem_exec_schedule@fair-flow-solo@rcs0:
- Statuses : 5 pass(s)
- Exec time: [10.63, 15.87] s
* igt@gem_exec_schedule@fair-flow-solo@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.94, 11.73] s
* igt@gem_exec_schedule@fair-flow-solo@vcs1:
- Statuses : 3 pass(s)
- Exec time: [10.65, 11.30] s
* igt@gem_exec_schedule@fair-flow-solo@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.92, 11.76] s
* igt@gem_exec_schedule@fair-flow@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.15] s
* igt@gem_exec_schedule@fair-flow@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.62, 13.11] s
* igt@gem_exec_schedule@fair-flow@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.63, 13.11] s
* igt@gem_exec_schedule@fair-flow@vcs1:
- Statuses : 2 pass(s)
- Exec time: [11.11, 13.11] s
* igt@gem_exec_schedule@fair-flow@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.62, 13.10] s
* igt@gem_exec_schedule@fair-half:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-half-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-half-solo@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.61] s
* igt@gem_exec_schedule@fair-half-solo@rcs0:
- Statuses : 5 pass(s)
- Exec time: [11.49, 15.62] s
* igt@gem_exec_schedule@fair-half-solo@vcs0:
- Statuses : 5 pass(s)
- Exec time: [11.48, 15.58] s
* igt@gem_exec_schedule@fair-half-solo@vcs1:
- Statuses : 2 pass(s)
- Exec time: [11.47, 13.40] s
* igt@gem_exec_schedule@fair-half-solo@vecs0:
- Statuses : 5 pass(s)
- Exec time: [11.59, 15.64] s
* igt@gem_exec_schedule@fair-half@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.48] s
* igt@gem_exec_schedule@fair-half@rcs0:
- Statuses : 5 pass(s)
- Exec time: [11.48, 16.36] s
* igt@gem_exec_schedule@fair-half@vcs0:
- Statuses : 5 pass(s)
- Exec time: [10.99, 13.56] s
* igt@gem_exec_schedule@fair-half@vcs1:
- Statuses : 2 pass(s)
- Exec time: [11.47, 13.48] s
* igt@gem_exec_schedule@fair-half@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.91, 13.46] s
* igt@gem_exec_schedule@fair-next:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-next-ping:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-next-ping@bcs0:
- Statuses : 5 skip(s)
- Exec time: [0.0, 4.22] s
* igt@gem_exec_schedule@fair-next-ping@rcs0:
- Statuses : 5 skip(s)
- Exec time: [2.14, 4.40] s
* igt@gem_exec_schedule@fair-next-ping@vcs0:
- Statuses : 5 skip(s)
- Exec time: [2.17, 4.22] s
* igt@gem_exec_schedule@fair-next-ping@vcs1:
- Statuses : 2 skip(s)
- Exec time: [2.16, 4.22] s
* igt@gem_exec_schedule@fair-next-ping@vecs0:
- Statuses : 5 skip(s)
- Exec time: [2.18, 4.22] s
* igt@gem_exec_schedule@fair-next-share:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-next-share@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.08] s
* igt@gem_exec_schedule@fair-next-share@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.60, 13.06] s
* igt@gem_exec_schedule@fair-next-share@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.59, 13.07] s
* igt@gem_exec_schedule@fair-next-share@vcs1:
- Statuses : 3 pass(s)
- Exec time: [10.88, 13.06] s
* igt@gem_exec_schedule@fair-next-share@vecs0:
- Statuses : 5 pass(s)
- Exec time: [9.02, 13.06] s
* igt@gem_exec_schedule@fair-next-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-next-solo@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 10.86] s
* igt@gem_exec_schedule@fair-next-solo@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.90, 11.54] s
* igt@gem_exec_schedule@fair-next-solo@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.92, 11.72] s
* igt@gem_exec_schedule@fair-next-solo@vcs1:
- Statuses : 3 pass(s)
- Exec time: [10.64, 11.31] s
* igt@gem_exec_schedule@fair-next-solo@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.94, 13.93] s
* igt@gem_exec_schedule@fair-next@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.45] s
* igt@gem_exec_schedule@fair-next@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.59, 13.10] s
* igt@gem_exec_schedule@fair-next@vcs0:
- Statuses : 5 pass(s)
- Exec time: [9.02, 13.52] s
* igt@gem_exec_schedule@fair-next@vcs1:
- Statuses : 3 pass(s)
- Exec time: [11.14, 13.49] s
* igt@gem_exec_schedule@fair-next@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.59, 13.11] s
* igt@gem_exec_schedule@fair-none:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-none-ping:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-none-rrul:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-none-rrul@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 11.98] s
* igt@gem_exec_schedule@fair-none-rrul@rcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [9.38, 11.73] s
* igt@gem_exec_schedule@fair-none-rrul@vcs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [6.87, 10.09] s
* igt@gem_exec_schedule@fair-none-rrul@vcs1:
- Statuses : 2 fail(s)
- Exec time: [9.06, 9.55] s
* igt@gem_exec_schedule@fair-none-rrul@vecs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [9.04, 12.00] s
* igt@gem_exec_schedule@fair-none-share:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-none-share@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 12.03] s
* igt@gem_exec_schedule@fair-none-share@rcs0:
- Statuses : 4 pass(s) 1 skip(s)
- Exec time: [7.08, 12.10] s
* igt@gem_exec_schedule@fair-none-share@vcs0:
- Statuses : 4 pass(s) 1 skip(s)
- Exec time: [7.49, 11.97] s
* igt@gem_exec_schedule@fair-none-share@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [9.66, 9.89] s
* igt@gem_exec_schedule@fair-none-share@vecs0:
- Statuses : 1 fail(s) 3 pass(s) 1 skip(s)
- Exec time: [7.51, 10.28] s
* igt@gem_exec_schedule@fair-none-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-none-solo@bcs0:
- Statuses : 2 fail(s) 3 skip(s)
- Exec time: [0.0, 14.25] s
* igt@gem_exec_schedule@fair-none-solo@rcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [10.70, 14.49] s
* igt@gem_exec_schedule@fair-none-solo@vcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [11.80, 17.01] s
* igt@gem_exec_schedule@fair-none-solo@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [13.34, 18.89] s
* igt@gem_exec_schedule@fair-none-solo@vecs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [11.94, 17.43] s
* igt@gem_exec_schedule@fair-none-vip:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-none-vip@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 13.01] s
* igt@gem_exec_schedule@fair-none-vip@rcs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [10.34, 12.65] s
* igt@gem_exec_schedule@fair-none-vip@vcs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [9.71, 13.77] s
* igt@gem_exec_schedule@fair-none-vip@vcs1:
- Statuses : 1 fail(s) 2 pass(s)
- Exec time: [9.73, 13.60] s
* igt@gem_exec_schedule@fair-none-vip@vecs0:
- Statuses : 1 fail(s) 3 pass(s) 1 skip(s)
- Exec time: [7.93, 13.69] s
* igt@gem_exec_schedule@fair-none@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 9.77] s
* igt@gem_exec_schedule@fair-none@rcs0:
- Statuses : 5 pass(s)
- Exec time: [9.43, 12.22] s
* igt@gem_exec_schedule@fair-none@vcs0:
- Statuses : 4 pass(s) 1 skip(s)
- Exec time: [7.54, 11.96] s
* igt@gem_exec_schedule@fair-none@vcs1:
- Statuses : 3 pass(s)
- Exec time: [9.79, 11.95] s
* igt@gem_exec_schedule@fair-none@vecs0:
- Statuses : 1 fail(s) 3 pass(s) 1 skip(s)
- Exec time: [7.51, 10.78] s
* igt@gem_exec_schedule@fair-pace:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-pace-ping:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-pace-ping@bcs0:
- Statuses : 5 skip(s)
- Exec time: [0.0, 4.18] s
* igt@gem_exec_schedule@fair-pace-ping@rcs0:
- Statuses : 5 skip(s)
- Exec time: [2.09, 4.19] s
* igt@gem_exec_schedule@fair-pace-ping@vcs0:
- Statuses : 5 skip(s)
- Exec time: [2.12, 4.18] s
* igt@gem_exec_schedule@fair-pace-ping@vcs1:
- Statuses : 3 skip(s)
- Exec time: [2.13, 4.18] s
* igt@gem_exec_schedule@fair-pace-ping@vecs0:
- Statuses : 5 skip(s)
- Exec time: [2.12, 4.18] s
* igt@gem_exec_schedule@fair-pace-share:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-pace-share@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 10.62] s
* igt@gem_exec_schedule@fair-pace-share@rcs0:
- Statuses : 4 fail(s) 1 pass(s)
- Exec time: [8.51, 11.61] s
* igt@gem_exec_schedule@fair-pace-share@vcs0:
- Statuses : 4 fail(s) 1 pass(s)
- Exec time: [8.42, 11.42] s
* igt@gem_exec_schedule@fair-pace-share@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [8.36, 8.61] s
* igt@gem_exec_schedule@fair-pace-share@vecs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [8.42, 11.53] s
* igt@gem_exec_schedule@fair-pace-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-pace-solo@bcs0:
- Statuses : 2 fail(s) 3 skip(s)
- Exec time: [0.0, 10.55] s
* igt@gem_exec_schedule@fair-pace-solo@rcs0:
- Statuses : 4 fail(s) 1 pass(s)
- Exec time: [8.45, 10.60] s
* igt@gem_exec_schedule@fair-pace-solo@vcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [8.56, 10.62] s
* igt@gem_exec_schedule@fair-pace-solo@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [8.38, 8.53] s
* igt@gem_exec_schedule@fair-pace-solo@vecs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [8.42, 10.83] s
* igt@gem_exec_schedule@fair-pace@bcs0:
- Statuses : 2 fail(s) 3 skip(s)
- Exec time: [0.0, 10.62] s
* igt@gem_exec_schedule@fair-pace@rcs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [8.50, 10.62] s
* igt@gem_exec_schedule@fair-pace@vcs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [8.44, 10.63] s
* igt@gem_exec_schedule@fair-pace@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [10.61, 10.96] s
* igt@gem_exec_schedule@fair-pace@vecs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [8.43, 10.96] s
* igt@gem_exec_schedule@fair-spare:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-spare-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-spare-solo@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 10.86] s
* igt@gem_exec_schedule@fair-spare-solo@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.93, 13.73] s
* igt@gem_exec_schedule@fair-spare-solo@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.91, 13.84] s
* igt@gem_exec_schedule@fair-spare-solo@vcs1:
- Statuses : 2 pass(s)
- Exec time: [10.73, 11.19] s
* igt@gem_exec_schedule@fair-spare-solo@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.92, 13.87] s
* igt@gem_exec_schedule@fair-spare@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.17] s
* igt@gem_exec_schedule@fair-spare@rcs0:
- Statuses : 5 pass(s)
- Exec time: [9.04, 13.35] s
* igt@gem_exec_schedule@fair-spare@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.61, 13.10] s
* igt@gem_exec_schedule@fair-spare@vcs1:
- Statuses : 2 pass(s)
- Exec time: [11.18, 13.10] s
* igt@gem_exec_schedule@fair-spare@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.61, 13.13] s
* igt@gem_exec_schedule@fair-sync:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-sync-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-sync-solo@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 10.56] s
* igt@gem_exec_schedule@fair-sync-solo@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.71, 12.43] s
* igt@gem_exec_schedule@fair-sync-solo@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.63, 12.20] s
* igt@gem_exec_schedule@fair-sync-solo@vcs1:
- Statuses : 3 pass(s)
- Exec time: [10.50, 10.96] s
* igt@gem_exec_schedule@fair-sync-solo@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.67, 12.10] s
* igt@gem_exec_schedule@fair-sync-vip:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-sync-vip@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 13.05] s
* igt@gem_exec_schedule@fair-sync-vip@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.91, 13.03] s
* igt@gem_exec_schedule@fair-sync-vip@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.68, 13.02] s
* igt@gem_exec_schedule@fair-sync-vip@vcs1:
- Statuses : 3 pass(s)
- Exec time: [8.69, 13.03] s
* igt@gem_exec_schedule@fair-sync-vip@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.71, 13.03] s
* igt@gem_exec_schedule@fair-sync@bcs0:
- Statuses : 2 pass(s) 3 skip(s)
- Exec time: [0.0, 12.93] s
* igt@gem_exec_schedule@fair-sync@rcs0:
- Statuses : 5 pass(s)
- Exec time: [8.89, 12.96] s
* igt@gem_exec_schedule@fair-sync@vcs0:
- Statuses : 5 pass(s)
- Exec time: [8.73, 12.93] s
* igt@gem_exec_schedule@fair-sync@vcs1:
- Statuses : 3 pass(s)
- Exec time: [10.60, 12.91] s
* igt@gem_exec_schedule@fair-sync@vecs0:
- Statuses : 5 pass(s)
- Exec time: [8.55, 12.93] s
* igt@gem_exec_schedule@fair-throttle:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-throttle-rrul:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-throttle-rrul@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 11.07] s
* igt@gem_exec_schedule@fair-throttle-rrul@rcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [8.74, 11.14] s
* igt@gem_exec_schedule@fair-throttle-rrul@vcs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [6.44, 9.15] s
* igt@gem_exec_schedule@fair-throttle-rrul@vcs1:
- Statuses : 2 fail(s)
- Exec time: [8.84, 11.12] s
* igt@gem_exec_schedule@fair-throttle-rrul@vecs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [8.61, 9.15] s
* igt@gem_exec_schedule@fair-throttle-share:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-throttle-share@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 11.44] s
* igt@gem_exec_schedule@fair-throttle-share@rcs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [8.78, 11.27] s
* igt@gem_exec_schedule@fair-throttle-share@vcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [9.00, 11.50] s
* igt@gem_exec_schedule@fair-throttle-share@vcs1:
- Statuses : 1 fail(s) 2 pass(s)
- Exec time: [9.12, 11.29] s
* igt@gem_exec_schedule@fair-throttle-share@vecs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [8.91, 11.76] s
* igt@gem_exec_schedule@fair-throttle-solo:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-throttle-solo@bcs0:
- Statuses : 2 fail(s) 3 skip(s)
- Exec time: [0.0, 12.86] s
* igt@gem_exec_schedule@fair-throttle-solo@rcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [9.11, 12.83] s
* igt@gem_exec_schedule@fair-throttle-solo@vcs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [12.06, 13.05] s
* igt@gem_exec_schedule@fair-throttle-solo@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [12.00, 12.44] s
* igt@gem_exec_schedule@fair-throttle-solo@vecs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [12.02, 12.98] s
* igt@gem_exec_schedule@fair-throttle-vip:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fair-throttle-vip@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 11.68] s
* igt@gem_exec_schedule@fair-throttle-vip@rcs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [8.97, 12.78] s
* igt@gem_exec_schedule@fair-throttle-vip@vcs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [9.22, 11.83] s
* igt@gem_exec_schedule@fair-throttle-vip@vcs1:
- Statuses : 1 fail(s) 1 pass(s)
- Exec time: [9.15, 11.53] s
* igt@gem_exec_schedule@fair-throttle-vip@vecs0:
- Statuses : 2 fail(s) 3 pass(s)
- Exec time: [9.06, 12.01] s
* igt@gem_exec_schedule@fair-throttle@bcs0:
- Statuses : 1 fail(s) 1 pass(s) 3 skip(s)
- Exec time: [0.0, 11.47] s
* igt@gem_exec_schedule@fair-throttle@rcs0:
- Statuses : 3 fail(s) 2 pass(s)
- Exec time: [8.78, 11.31] s
* igt@gem_exec_schedule@fair-throttle@vcs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [8.98, 11.58] s
* igt@gem_exec_schedule@fair-throttle@vcs1:
- Statuses : 2 fail(s) 1 pass(s)
- Exec time: [8.92, 11.63] s
* igt@gem_exec_schedule@fair-throttle@vecs0:
- Statuses : 1 fail(s) 4 pass(s)
- Exec time: [8.96, 11.89] s
* igt@gem_exec_schedule@fairslice:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@fairslice-all:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 2.10] s
* igt@gem_exec_schedule@fairslice@bcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@fairslice@rcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.02] s
* igt@gem_exec_schedule@fairslice@vcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.02] s
* igt@gem_exec_schedule@fairslice@vcs1:
- Statuses : 3 pass(s)
- Exec time: [2.01] s
* igt@gem_exec_schedule@fairslice@vecs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.02] s
* igt@gem_exec_schedule@u-fairslice:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_schedule@u-fairslice-all:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 2.15] s
* igt@gem_exec_schedule@u-fairslice@bcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@u-fairslice@rcs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.03] s
* igt@gem_exec_schedule@u-fairslice@vcs0:
- Statuses : 1 dmesg-warn(s) 4 pass(s)
- Exec time: [2.01, 2.04] s
* igt@gem_exec_schedule@u-fairslice@vcs1:
- Statuses : 2 pass(s)
- Exec time: [2.01] s
* igt@gem_exec_schedule@u-fairslice@vecs0:
- Statuses : 5 pass(s)
- Exec time: [2.01, 2.02] s
Known issues
------------
Here are the changes found in IGTPW_5266_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@file:
- shard-hsw: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-hsw2/igt@gem_ctx_persistence@file.html
* igt@gem_exec_create@forked:
- shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk9/igt@gem_exec_create@forked.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-glk9/igt@gem_exec_create@forked.html
* {igt@gem_exec_schedule@fair-flow-ping@rcs0} (NEW):
- shard-kbl: NOTRUN -> [SKIP][10] ([fdo#109271]) +44 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-kbl1/igt@gem_exec_schedule@fair-flow-ping@rcs0.html
* {igt@gem_exec_schedule@fair-flow-solo@bcs0} (NEW):
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271]) +47 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-apl7/igt@gem_exec_schedule@fair-flow-solo@bcs0.html
* {igt@gem_exec_schedule@fair-next-ping@vecs0} (NEW):
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271]) +39 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-glk6/igt@gem_exec_schedule@fair-next-ping@vecs0.html
* {igt@gem_exec_schedule@fair-none-vip} (NEW):
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271]) +33 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-snb7/igt@gem_exec_schedule@fair-none-vip.html
* {igt@gem_exec_schedule@fair-pace-ping@vcs1} (NEW):
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109276])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb1/igt@gem_exec_schedule@fair-pace-ping@vcs1.html
* {igt@gem_exec_schedule@fair-pace-solo} (NEW):
- shard-hsw: NOTRUN -> [SKIP][15] ([fdo#109271]) +38 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-hsw4/igt@gem_exec_schedule@fair-pace-solo.html
* {igt@gem_exec_schedule@u-fairslice@vcs0} (NEW):
- shard-apl: NOTRUN -> [DMESG-WARN][16] ([i915#1610])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-apl4/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-edp:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2768])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-edp.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-edp.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2597])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109274] / [fdo#109278])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb3/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][24] -> [FAIL][25] ([i915#79])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#49])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-glk5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111825]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109280]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-tglb: [PASS][30] -> [INCOMPLETE][31] ([i915#1436] / [i915#1602] / [i915#1887] / [i915#2411] / [i915#456])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-tglb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
- shard-glk: [PASS][32] -> [DMESG-WARN][33] ([i915#2635] / [i915#533])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-glk7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-glk7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
- shard-apl: [PASS][34] -> [DMESG-WARN][35] ([i915#2635] / [i915#533])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
- shard-kbl: [PASS][36] -> [INCOMPLETE][37] ([i915#155] / [i915#648])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
- shard-iclb: [PASS][38] -> [INCOMPLETE][39] ([i915#1185] / [i915#250])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-iclb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/shard-iclb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
- shard-hsw: [PASS][40] -> [DMESG-WARN][41] ([i915#2637])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9468/shard-hsw2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[41]: https://intel-gfx-ci.01.org/tree/drm
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5266/index.html
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2020-12-10 2:09 [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Chris Wilson
2020-12-10 3:18 ` [igt-dev] ✗ Fi.CI.BAT: failure for i915/gem_exec_schedule: Try to spot unfairness (rev12) Patchwork
2020-12-10 8:21 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_exec_schedule: Try to spot unfairness (rev13) Patchwork
2020-12-10 11:06 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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