[PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[Liu Ying]

This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
subsystems.

With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
by drivers.

v1->v2:
* Drop LPCG clocks as they can be registered directly in an in-tree new
  DT binding way.
* Add DC0 bypass clocks support.
* Correct the way to register DC0 display clocks.
* Trivial tweak.

Liu Ying (4):
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
  clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
  clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS
    subsystems

 drivers/clk/imx/clk-imx8qxp.c          | 26 ++++++++++++++++++++++++--
 include/dt-bindings/clock/imx8-clock.h |  2 ++
 2 files changed, 26 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[Liu Ying]

This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
subsystems.

With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
by drivers.

v1->v2:
* Drop LPCG clocks as they can be registered directly in an in-tree new
  DT binding way.
* Add DC0 bypass clocks support.
* Correct the way to register DC0 display clocks.
* Trivial tweak.

Liu Ying (4):
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
  clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
  clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS
    subsystems

 drivers/clk/imx/clk-imx8qxp.c          | 26 ++++++++++++++++++++++++--
 include/dt-bindings/clock/imx8-clock.h |  2 ++
 2 files changed, 26 insertions(+), 2 deletions(-)

-- 
2.7.4


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[PATCH v2 1/4] clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks

[Liu Ying]

This patch adds SCU clocks support for i.MX8qxp DC0 subsystem PLL clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Trivial tweak - Move PLL clocks down to display clocks.

 drivers/clk/imx/clk-imx8qxp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 5b3d4ed..b48643e 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -117,6 +117,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	/* Display controller SS */
 	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
 	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
+	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
+	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
 
 	/* MIPI-LVDS SS */
 	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
-- 
2.7.4

[PATCH v2 1/4] clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks

[Liu Ying]

This patch adds SCU clocks support for i.MX8qxp DC0 subsystem PLL clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Trivial tweak - Move PLL clocks down to display clocks.

 drivers/clk/imx/clk-imx8qxp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 5b3d4ed..b48643e 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -117,6 +117,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	/* Display controller SS */
 	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
 	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
+	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
+	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
 
 	/* MIPI-LVDS SS */
 	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
-- 
2.7.4


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[PATCH v2 2/4] clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks

[Liu Ying]

This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Newly introduced in v2.

 drivers/clk/imx/clk-imx8qxp.c          | 2 ++
 include/dt-bindings/clock/imx8-clock.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index b48643e..af6a545 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -119,6 +119,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
 	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
 	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
+	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 
 	/* MIPI-LVDS SS */
 	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 673a8c6..82b1fc8 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -64,6 +64,8 @@
 #define IMX_DC0_PLL1_CLK				81
 #define IMX_DC0_DISP0_CLK				82
 #define IMX_DC0_DISP1_CLK				83
+#define IMX_DC0_BYPASS0_CLK				84
+#define IMX_DC0_BYPASS1_CLK				85
 
 /* MIPI-LVDS SS */
 #define IMX_MIPI_IPG_CLK				90
-- 
2.7.4

[PATCH v2 2/4] clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks

[Liu Ying]

This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Newly introduced in v2.

 drivers/clk/imx/clk-imx8qxp.c          | 2 ++
 include/dt-bindings/clock/imx8-clock.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index b48643e..af6a545 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -119,6 +119,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
 	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
 	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
+	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 
 	/* MIPI-LVDS SS */
 	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 673a8c6..82b1fc8 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -64,6 +64,8 @@
 #define IMX_DC0_PLL1_CLK				81
 #define IMX_DC0_DISP0_CLK				82
 #define IMX_DC0_DISP1_CLK				83
+#define IMX_DC0_BYPASS0_CLK				84
+#define IMX_DC0_BYPASS1_CLK				85
 
 /* MIPI-LVDS SS */
 #define IMX_MIPI_IPG_CLK				90
-- 
2.7.4


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[PATCH v2 3/4] clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()

[Liu Ying]

This patch corrects display clocks for i.MX8qxp DC0 subsystem by
calling imx_clk_scu2() to register them, instead of calling
imx_clk_scu().  The reason is that the clocks can source from
various parents.  The clock source selection is controlled by
Distributed Slave System Controller(DSC).  According to the DSC spec,
the below table describes the generic source selections for clocks
with the same type in various subsystems.  And, the display controller
subsystem spec says the display clocks can source from PLL1, PLL2 or
bypass clock, thus we may specify the correct parents for imx_clk_scu2().

The bypass clock's parent is determined by the SCU firmware.
Currently, the parent is 'pixel_link_clk_in' from HW point of view.
To be more specific, the parent is dummy for i.MX8qxp DC0, while
HDMI TX PHY PLL for i.MX8qm DC0.  In practice, the display clocks
source from the bypass clock only when driving i.MX8qm HDMI TX.
So, for the both display clocks, we simply specify 'dc0_bypass0_clk'
bypass clock as a valid parent.

 -----------------------------------------
| src_sel[28:26] |                        |
 -----------------------------------------
| 0x0            | xtal24M                |
| 0x1            | PLL0                   |
| 0x2            | PLL1                   |
| 0x3            | PLL2                   |
| 0x4            | bypass reference clock |
| 0x5 to 0x7     | reserved               |
 -----------------------------------------

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Newly introduced in v2.

 drivers/clk/imx/clk-imx8qxp.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index af6a545..0b4bb2c 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -17,6 +17,14 @@
 #include <dt-bindings/clock/imx8-clock.h>
 #include <dt-bindings/firmware/imx/rsrc.h>
 
+static const char *dc0_sels[] = {
+	"clk_dummy",
+	"clk_dummy",
+	"dc0_pll0_clk",
+	"dc0_pll1_clk",
+	"dc0_bypass0_clk",
+};
+
 static int imx8qxp_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *ccm_node = pdev->dev.of_node;
@@ -115,8 +123,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_CONN_USB2_LPM_CLK]	= imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
 
 	/* Display controller SS */
-	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
-	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
+	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
+	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
 	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
 	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
 	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
-- 
2.7.4

[PATCH v2 3/4] clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()

[Liu Ying]

This patch corrects display clocks for i.MX8qxp DC0 subsystem by
calling imx_clk_scu2() to register them, instead of calling
imx_clk_scu().  The reason is that the clocks can source from
various parents.  The clock source selection is controlled by
Distributed Slave System Controller(DSC).  According to the DSC spec,
the below table describes the generic source selections for clocks
with the same type in various subsystems.  And, the display controller
subsystem spec says the display clocks can source from PLL1, PLL2 or
bypass clock, thus we may specify the correct parents for imx_clk_scu2().

The bypass clock's parent is determined by the SCU firmware.
Currently, the parent is 'pixel_link_clk_in' from HW point of view.
To be more specific, the parent is dummy for i.MX8qxp DC0, while
HDMI TX PHY PLL for i.MX8qm DC0.  In practice, the display clocks
source from the bypass clock only when driving i.MX8qm HDMI TX.
So, for the both display clocks, we simply specify 'dc0_bypass0_clk'
bypass clock as a valid parent.

 -----------------------------------------
| src_sel[28:26] |                        |
 -----------------------------------------
| 0x0            | xtal24M                |
| 0x1            | PLL0                   |
| 0x2            | PLL1                   |
| 0x3            | PLL2                   |
| 0x4            | bypass reference clock |
| 0x5 to 0x7     | reserved               |
 -----------------------------------------

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* Newly introduced in v2.

 drivers/clk/imx/clk-imx8qxp.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index af6a545..0b4bb2c 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -17,6 +17,14 @@
 #include <dt-bindings/clock/imx8-clock.h>
 #include <dt-bindings/firmware/imx/rsrc.h>
 
+static const char *dc0_sels[] = {
+	"clk_dummy",
+	"clk_dummy",
+	"dc0_pll0_clk",
+	"dc0_pll1_clk",
+	"dc0_bypass0_clk",
+};
+
 static int imx8qxp_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *ccm_node = pdev->dev.of_node;
@@ -115,8 +123,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_CONN_USB2_LPM_CLK]	= imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
 
 	/* Display controller SS */
-	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
-	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
+	clks[IMX_DC0_DISP0_CLK]		= imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
+	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
 	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
 	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
 	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
-- 
2.7.4


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[PATCH v2 4/4] clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems

[Liu Ying]

This patch adds some SCU clocks support for i.MX8qxp MIPI-LVDS subsystems.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.

 drivers/clk/imx/clk-imx8qxp.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 0b4bb2c..fbf1170 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -131,8 +131,18 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 
 	/* MIPI-LVDS SS */
+	clks[IMX_MIPI0_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI0_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	clks[IMX_MIPI0_LVDS_PHY_CLK]	= imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
 	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
 	clks[IMX_MIPI0_I2C1_CLK]	= imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI0_PWM0_CLK]	= imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
+	clks[IMX_MIPI1_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI1_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	clks[IMX_MIPI1_LVDS_PHY_CLK]	= imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
+	clks[IMX_MIPI1_I2C0_CLK]	= imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI1_I2C1_CLK]	= imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI1_PWM0_CLK]	= imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
 
 	/* MIPI CSI SS */
 	clks[IMX_CSI0_CORE_CLK]		= imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
-- 
2.7.4

[PATCH v2 4/4] clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems

[Liu Ying]

This patch adds some SCU clocks support for i.MX8qxp MIPI-LVDS subsystems.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
v1->v2:
* No change.

 drivers/clk/imx/clk-imx8qxp.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 0b4bb2c..fbf1170 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -131,8 +131,18 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
 
 	/* MIPI-LVDS SS */
+	clks[IMX_MIPI0_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI0_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	clks[IMX_MIPI0_LVDS_PHY_CLK]	= imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
 	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
 	clks[IMX_MIPI0_I2C1_CLK]	= imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI0_PWM0_CLK]	= imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
+	clks[IMX_MIPI1_LVDS_PIXEL_CLK]	= imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI1_LVDS_BYPASS_CLK]	= imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
+	clks[IMX_MIPI1_LVDS_PHY_CLK]	= imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
+	clks[IMX_MIPI1_I2C0_CLK]	= imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI1_I2C1_CLK]	= imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
+	clks[IMX_MIPI1_PWM0_CLK]	= imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
 
 	/* MIPI CSI SS */
 	clks[IMX_CSI0_CORE_CLK]		= imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
-- 
2.7.4


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Re: [PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[Stephen Boyd]

Quoting Liu Ying (2020-12-01 21:33:35)
> This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
> subsystems.
> 
> With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
> by drivers.
> 
> v1->v2:
> * Drop LPCG clocks as they can be registered directly in an in-tree new
>   DT binding way.
> * Add DC0 bypass clocks support.
> * Correct the way to register DC0 display clocks.
> * Trivial tweak.

Looks OK to me. I assume Shawn will pick them up.

> 
> Liu Ying (4):
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
>   clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
>   clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS
>     subsystems
> 
>  drivers/clk/imx/clk-imx8qxp.c          | 26 ++++++++++++++++++++++++--
>  include/dt-bindings/clock/imx8-clock.h |  2 ++
>  2 files changed, 26 insertions(+), 2 deletions(-)
> 
> -- 
> 2.7.4
>

Re: [PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[Stephen Boyd]

Quoting Liu Ying (2020-12-01 21:33:35)
> This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
> subsystems.
> 
> With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
> by drivers.
> 
> v1->v2:
> * Drop LPCG clocks as they can be registered directly in an in-tree new
>   DT binding way.
> * Add DC0 bypass clocks support.
> * Correct the way to register DC0 display clocks.
> * Trivial tweak.

Looks OK to me. I assume Shawn will pick them up.

> 
> Liu Ying (4):
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
>   clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
>   clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS
>     subsystems
> 
>  drivers/clk/imx/clk-imx8qxp.c          | 26 ++++++++++++++++++++++++--
>  include/dt-bindings/clock/imx8-clock.h |  2 ++
>  2 files changed, 26 insertions(+), 2 deletions(-)
> 
> -- 
> 2.7.4
>

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Re: [PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[Shawn Guo]

On Wed, Dec 02, 2020 at 01:33:35PM +0800, Liu Ying wrote:
> This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
> subsystems.
> 
> With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
> by drivers.
> 
> v1->v2:
> * Drop LPCG clocks as they can be registered directly in an in-tree new
>   DT binding way.
> * Add DC0 bypass clocks support.
> * Correct the way to register DC0 display clocks.
> * Trivial tweak.
> 
> Liu Ying (4):
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
>   clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
>   clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS
>     subsystems

Applied all, thanks.

Re: [PATCH v2 0/4] Add some clocks support for i.MX8qxp DC0/MIPI-LVDS subsystems

[Shawn Guo]

On Wed, Dec 02, 2020 at 01:33:35PM +0800, Liu Ying wrote:
> This patch set adds some SCU clocks support for i.MX8qxp DC0/MIPI-LVDS
> subsystems.
> 
> With this patch set, some basic clocks for i.MX8qxp LVDS displays can be got
> by drivers.
> 
> v1->v2:
> * Drop LPCG clocks as they can be registered directly in an in-tree new
>   DT binding way.
> * Add DC0 bypass clocks support.
> * Correct the way to register DC0 display clocks.
> * Trivial tweak.
> 
> Liu Ying (4):
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
>   clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
>   clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
>   clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS
>     subsystems

Applied all, thanks.

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