* soc: mediatek: Prepare MMSYS for DDP routing using function call @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group The following series are intended to prepare the mtk-mmsys driver to allow different DDP (Data Display Path) function call per SoC. base change: https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-4-enric.balletbo@collabora.com/ Change since v2: - fix review issue in v2 - add 8183 mmsys function call - add 8192 new component - add 8192 mmsys function call ^ permalink raw reply [flat|nested] 72+ messages in thread
* soc: mediatek: Prepare MMSYS for DDP routing using function call @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel The following series are intended to prepare the mtk-mmsys driver to allow different DDP (Data Display Path) function call per SoC. base change: https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-4-enric.balletbo@collabora.com/ Change since v2: - fix review issue in v2 - add 8183 mmsys function call - add 8192 new component - add 8192 mmsys function call _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* soc: mediatek: Prepare MMSYS for DDP routing using function call @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel The following series are intended to prepare the mtk-mmsys driver to allow different DDP (Data Display Path) function call per SoC. base change: https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-4-enric.balletbo@collabora.com/ Change since v2: - fix review issue in v2 - add 8183 mmsys function call - add 8192 new component - add 8192 mmsys function call _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* soc: mediatek: Prepare MMSYS for DDP routing using function call @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel The following series are intended to prepare the mtk-mmsys driver to allow different DDP (Data Display Path) function call per SoC. base change: https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-4-enric.balletbo@collabora.com/ Change since v2: - fix review issue in v2 - add 8183 mmsys function call - add 8192 new component - add 8192 mmsys function call _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu the mmsys will more and more complicated after support more and more SoCs, add an independent folder will be more clear Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 2 +- drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- 4 files changed, 383 insertions(+), 381 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..b5987ca 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..5d976d7 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c new file mode 100644 index 0000000..da2de8f --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao <jamesjj.liao@mediatek.com> + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +struct mtk_mmsys_driver_data { + const char *clk_driver; +}; + +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .clk_driver = "clk-mt2701-mm", +}; + +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .clk_driver = "clk-mt2712-mm", +}; + +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { + .clk_driver = "clk-mt6779-mm", +}; + +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { + .clk_driver = "clk-mt6797-mm", +}; + +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { + .clk_driver = "clk-mt8173-mm", +}; + +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .clk_driver = "clk-mt8183-mm", +}; + +struct mtk_mmsys { + void __iomem *regs; + const struct mtk_mmsys_driver_data *data; +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +void mtk_mmsys_ddp_connect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + + mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); + +void mtk_mmsys_ddp_disconnect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); + +static int mtk_mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct platform_device *clks; + struct platform_device *drm; + struct mtk_mmsys *mmsys; + int ret; + + mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); + if (!mmsys) + return -ENOMEM; + + mmsys->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmsys->regs)) { + ret = PTR_ERR(mmsys->regs); + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); + return ret; + } + + mmsys->data = of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, mmsys); + + clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(clks)) + return PTR_ERR(clks); + + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(drm)) { + platform_device_unregister(clks); + return PTR_ERR(drm); + } + + return 0; +} + +static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6779-mmsys", + .data = &mt6779_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6797-mmsys", + .data = &mt6797_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8173-mmsys", + .data = &mt8173_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data, + }, + { } +}; + +static struct platform_driver mtk_mmsys_drv = { + .driver = { + .name = "mtk-mmsys", + .of_match_table = of_match_mtk_mmsys, + }, + .probe = mtk_mmsys_probe, +}; + +builtin_platform_driver(mtk_mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c deleted file mode 100644 index da2de8f..0000000 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao <jamesjj.liao@mediatek.com> - */ - -#include <linux/device.h> -#include <linux/io.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/soc/mediatek/mtk-mmsys.h> - -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - -struct mtk_mmsys_driver_data { - const char *clk_driver; -}; - -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { - .clk_driver = "clk-mt2701-mm", -}; - -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { - .clk_driver = "clk-mt2712-mm", -}; - -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { - .clk_driver = "clk-mt6779-mm", -}; - -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { - .clk_driver = "clk-mt6797-mm", -}; - -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { - .clk_driver = "clk-mt8173-mm", -}; - -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { - .clk_driver = "clk-mt8183-mm", -}; - -struct mtk_mmsys { - void __iomem *regs; - const struct mtk_mmsys_driver_data *data; -}; - -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } - - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); - -static int mtk_mmsys_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct platform_device *clks; - struct platform_device *drm; - struct mtk_mmsys *mmsys; - int ret; - - mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); - if (!mmsys) - return -ENOMEM; - - mmsys->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mmsys->regs)) { - ret = PTR_ERR(mmsys->regs); - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); - return ret; - } - - mmsys->data = of_device_get_match_data(&pdev->dev); - platform_set_drvdata(pdev, mmsys); - - clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(clks)) - return PTR_ERR(clks); - - drm = platform_device_register_data(&pdev->dev, "mediatek-drm", - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(drm)) { - platform_device_unregister(clks); - return PTR_ERR(drm); - } - - return 0; -} - -static const struct of_device_id of_match_mtk_mmsys[] = { - { - .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, - }, - { } -}; - -static struct platform_driver mtk_mmsys_drv = { - .driver = { - .name = "mtk-mmsys", - .of_match_table = of_match_mtk_mmsys, - }, - .probe = mtk_mmsys_probe, -}; - -builtin_platform_driver(mtk_mmsys_drv); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel the mmsys will more and more complicated after support more and more SoCs, add an independent folder will be more clear Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 2 +- drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- 4 files changed, 383 insertions(+), 381 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..b5987ca 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..5d976d7 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c new file mode 100644 index 0000000..da2de8f --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao <jamesjj.liao@mediatek.com> + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +struct mtk_mmsys_driver_data { + const char *clk_driver; +}; + +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .clk_driver = "clk-mt2701-mm", +}; + +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .clk_driver = "clk-mt2712-mm", +}; + +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { + .clk_driver = "clk-mt6779-mm", +}; + +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { + .clk_driver = "clk-mt6797-mm", +}; + +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { + .clk_driver = "clk-mt8173-mm", +}; + +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .clk_driver = "clk-mt8183-mm", +}; + +struct mtk_mmsys { + void __iomem *regs; + const struct mtk_mmsys_driver_data *data; +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +void mtk_mmsys_ddp_connect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + + mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); + +void mtk_mmsys_ddp_disconnect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); + +static int mtk_mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct platform_device *clks; + struct platform_device *drm; + struct mtk_mmsys *mmsys; + int ret; + + mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); + if (!mmsys) + return -ENOMEM; + + mmsys->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmsys->regs)) { + ret = PTR_ERR(mmsys->regs); + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); + return ret; + } + + mmsys->data = of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, mmsys); + + clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(clks)) + return PTR_ERR(clks); + + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(drm)) { + platform_device_unregister(clks); + return PTR_ERR(drm); + } + + return 0; +} + +static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6779-mmsys", + .data = &mt6779_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6797-mmsys", + .data = &mt6797_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8173-mmsys", + .data = &mt8173_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data, + }, + { } +}; + +static struct platform_driver mtk_mmsys_drv = { + .driver = { + .name = "mtk-mmsys", + .of_match_table = of_match_mtk_mmsys, + }, + .probe = mtk_mmsys_probe, +}; + +builtin_platform_driver(mtk_mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c deleted file mode 100644 index da2de8f..0000000 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao <jamesjj.liao@mediatek.com> - */ - -#include <linux/device.h> -#include <linux/io.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/soc/mediatek/mtk-mmsys.h> - -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - -struct mtk_mmsys_driver_data { - const char *clk_driver; -}; - -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { - .clk_driver = "clk-mt2701-mm", -}; - -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { - .clk_driver = "clk-mt2712-mm", -}; - -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { - .clk_driver = "clk-mt6779-mm", -}; - -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { - .clk_driver = "clk-mt6797-mm", -}; - -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { - .clk_driver = "clk-mt8173-mm", -}; - -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { - .clk_driver = "clk-mt8183-mm", -}; - -struct mtk_mmsys { - void __iomem *regs; - const struct mtk_mmsys_driver_data *data; -}; - -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } - - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); - -static int mtk_mmsys_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct platform_device *clks; - struct platform_device *drm; - struct mtk_mmsys *mmsys; - int ret; - - mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); - if (!mmsys) - return -ENOMEM; - - mmsys->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mmsys->regs)) { - ret = PTR_ERR(mmsys->regs); - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); - return ret; - } - - mmsys->data = of_device_get_match_data(&pdev->dev); - platform_set_drvdata(pdev, mmsys); - - clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(clks)) - return PTR_ERR(clks); - - drm = platform_device_register_data(&pdev->dev, "mediatek-drm", - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(drm)) { - platform_device_unregister(clks); - return PTR_ERR(drm); - } - - return 0; -} - -static const struct of_device_id of_match_mtk_mmsys[] = { - { - .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, - }, - { } -}; - -static struct platform_driver mtk_mmsys_drv = { - .driver = { - .name = "mtk-mmsys", - .of_match_table = of_match_mtk_mmsys, - }, - .probe = mtk_mmsys_probe, -}; - -builtin_platform_driver(mtk_mmsys_drv); -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel the mmsys will more and more complicated after support more and more SoCs, add an independent folder will be more clear Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 2 +- drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- 4 files changed, 383 insertions(+), 381 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..b5987ca 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..5d976d7 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c new file mode 100644 index 0000000..da2de8f --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao <jamesjj.liao@mediatek.com> + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +struct mtk_mmsys_driver_data { + const char *clk_driver; +}; + +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .clk_driver = "clk-mt2701-mm", +}; + +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .clk_driver = "clk-mt2712-mm", +}; + +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { + .clk_driver = "clk-mt6779-mm", +}; + +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { + .clk_driver = "clk-mt6797-mm", +}; + +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { + .clk_driver = "clk-mt8173-mm", +}; + +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .clk_driver = "clk-mt8183-mm", +}; + +struct mtk_mmsys { + void __iomem *regs; + const struct mtk_mmsys_driver_data *data; +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +void mtk_mmsys_ddp_connect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + + mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); + +void mtk_mmsys_ddp_disconnect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); + +static int mtk_mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct platform_device *clks; + struct platform_device *drm; + struct mtk_mmsys *mmsys; + int ret; + + mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); + if (!mmsys) + return -ENOMEM; + + mmsys->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmsys->regs)) { + ret = PTR_ERR(mmsys->regs); + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); + return ret; + } + + mmsys->data = of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, mmsys); + + clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(clks)) + return PTR_ERR(clks); + + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(drm)) { + platform_device_unregister(clks); + return PTR_ERR(drm); + } + + return 0; +} + +static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6779-mmsys", + .data = &mt6779_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6797-mmsys", + .data = &mt6797_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8173-mmsys", + .data = &mt8173_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data, + }, + { } +}; + +static struct platform_driver mtk_mmsys_drv = { + .driver = { + .name = "mtk-mmsys", + .of_match_table = of_match_mtk_mmsys, + }, + .probe = mtk_mmsys_probe, +}; + +builtin_platform_driver(mtk_mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c deleted file mode 100644 index da2de8f..0000000 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao <jamesjj.liao@mediatek.com> - */ - -#include <linux/device.h> -#include <linux/io.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/soc/mediatek/mtk-mmsys.h> - -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - -struct mtk_mmsys_driver_data { - const char *clk_driver; -}; - -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { - .clk_driver = "clk-mt2701-mm", -}; - -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { - .clk_driver = "clk-mt2712-mm", -}; - -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { - .clk_driver = "clk-mt6779-mm", -}; - -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { - .clk_driver = "clk-mt6797-mm", -}; - -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { - .clk_driver = "clk-mt8173-mm", -}; - -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { - .clk_driver = "clk-mt8183-mm", -}; - -struct mtk_mmsys { - void __iomem *regs; - const struct mtk_mmsys_driver_data *data; -}; - -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } - - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); - -static int mtk_mmsys_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct platform_device *clks; - struct platform_device *drm; - struct mtk_mmsys *mmsys; - int ret; - - mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); - if (!mmsys) - return -ENOMEM; - - mmsys->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mmsys->regs)) { - ret = PTR_ERR(mmsys->regs); - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); - return ret; - } - - mmsys->data = of_device_get_match_data(&pdev->dev); - platform_set_drvdata(pdev, mmsys); - - clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(clks)) - return PTR_ERR(clks); - - drm = platform_device_register_data(&pdev->dev, "mediatek-drm", - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(drm)) { - platform_device_unregister(clks); - return PTR_ERR(drm); - } - - return 0; -} - -static const struct of_device_id of_match_mtk_mmsys[] = { - { - .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, - }, - { } -}; - -static struct platform_driver mtk_mmsys_drv = { - .driver = { - .name = "mtk-mmsys", - .of_match_table = of_match_mtk_mmsys, - }, - .probe = mtk_mmsys_probe, -}; - -builtin_platform_driver(mtk_mmsys_drv); -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel the mmsys will more and more complicated after support more and more SoCs, add an independent folder will be more clear Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/Makefile | 2 +- drivers/soc/mediatek/mmsys/Makefile | 2 + drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- 4 files changed, 383 insertions(+), 381 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..b5987ca 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 0000000..5d976d7 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c new file mode 100644 index 0000000..da2de8f --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao <jamesjj.liao@mediatek.com> + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +struct mtk_mmsys_driver_data { + const char *clk_driver; +}; + +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .clk_driver = "clk-mt2701-mm", +}; + +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .clk_driver = "clk-mt2712-mm", +}; + +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { + .clk_driver = "clk-mt6779-mm", +}; + +static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { + .clk_driver = "clk-mt6797-mm", +}; + +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { + .clk_driver = "clk-mt8173-mm", +}; + +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .clk_driver = "clk-mt8183-mm", +}; + +struct mtk_mmsys { + void __iomem *regs; + const struct mtk_mmsys_driver_data *data; +}; + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +void mtk_mmsys_ddp_connect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + + mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); + +void mtk_mmsys_ddp_disconnect(struct device *dev, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + unsigned int addr, value, reg; + + value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } + + value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } +} +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); + +static int mtk_mmsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct platform_device *clks; + struct platform_device *drm; + struct mtk_mmsys *mmsys; + int ret; + + mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); + if (!mmsys) + return -ENOMEM; + + mmsys->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mmsys->regs)) { + ret = PTR_ERR(mmsys->regs); + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); + return ret; + } + + mmsys->data = of_device_get_match_data(&pdev->dev); + platform_set_drvdata(pdev, mmsys); + + clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(clks)) + return PTR_ERR(clks); + + drm = platform_device_register_data(&pdev->dev, "mediatek-drm", + PLATFORM_DEVID_AUTO, NULL, 0); + if (IS_ERR(drm)) { + platform_device_unregister(clks); + return PTR_ERR(drm); + } + + return 0; +} + +static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6779-mmsys", + .data = &mt6779_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt6797-mmsys", + .data = &mt6797_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8173-mmsys", + .data = &mt8173_mmsys_driver_data, + }, + { + .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data, + }, + { } +}; + +static struct platform_driver mtk_mmsys_drv = { + .driver = { + .name = "mtk-mmsys", + .of_match_table = of_match_mtk_mmsys, + }, + .probe = mtk_mmsys_probe, +}; + +builtin_platform_driver(mtk_mmsys_drv); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c deleted file mode 100644 index da2de8f..0000000 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao <jamesjj.liao@mediatek.com> - */ - -#include <linux/device.h> -#include <linux/io.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/soc/mediatek/mtk-mmsys.h> - -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - -struct mtk_mmsys_driver_data { - const char *clk_driver; -}; - -static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { - .clk_driver = "clk-mt2701-mm", -}; - -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { - .clk_driver = "clk-mt2712-mm", -}; - -static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { - .clk_driver = "clk-mt6779-mm", -}; - -static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { - .clk_driver = "clk-mt6797-mm", -}; - -static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { - .clk_driver = "clk-mt8173-mm", -}; - -static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { - .clk_driver = "clk-mt8183-mm", -}; - -struct mtk_mmsys { - void __iomem *regs; - const struct mtk_mmsys_driver_data *data; -}; - -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } - - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) | value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - struct mtk_mmsys *mmsys = dev_get_drvdata(dev); - unsigned int addr, value, reg; - - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } - - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); - if (value) { - reg = readl_relaxed(mmsys->regs + addr) & ~value; - writel_relaxed(reg, mmsys->regs + addr); - } -} -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); - -static int mtk_mmsys_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct platform_device *clks; - struct platform_device *drm; - struct mtk_mmsys *mmsys; - int ret; - - mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); - if (!mmsys) - return -ENOMEM; - - mmsys->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(mmsys->regs)) { - ret = PTR_ERR(mmsys->regs); - dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); - return ret; - } - - mmsys->data = of_device_get_match_data(&pdev->dev); - platform_set_drvdata(pdev, mmsys); - - clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(clks)) - return PTR_ERR(clks); - - drm = platform_device_register_data(&pdev->dev, "mediatek-drm", - PLATFORM_DEVID_AUTO, NULL, 0); - if (IS_ERR(drm)) { - platform_device_unregister(clks); - return PTR_ERR(drm); - } - - return 0; -} - -static const struct of_device_id of_match_mtk_mmsys[] = { - { - .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, - }, - { } -}; - -static struct platform_driver mtk_mmsys_drv = { - .driver = { - .name = "mtk-mmsys", - .of_match_table = of_match_mtk_mmsys, - }, - .probe = mtk_mmsys_probe, -}; - -builtin_platform_driver(mtk_mmsys_drv); -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-31 1:21 ` Nicolas Boichat -1 siblings, 0 replies; 72+ messages in thread From: Nicolas Boichat @ 2020-12-31 1:21 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, linux-arm Mailing List On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > the mmsys will more and more complicated after support > more and more SoCs, add an independent folder will be > more clear > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 2 +- > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- I wonder why this doesn't get detected as a rename? > 4 files changed, 383 insertions(+), 381 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 01f9f87..b5987ca 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..5d976d7 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > \ No newline at end of file Nit: newline at end of file please. ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2020-12-31 1:21 ` Nicolas Boichat 0 siblings, 0 replies; 72+ messages in thread From: Nicolas Boichat @ 2020-12-31 1:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, linux-arm Mailing List On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > the mmsys will more and more complicated after support > more and more SoCs, add an independent folder will be > more clear > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 2 +- > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- I wonder why this doesn't get detected as a rename? > 4 files changed, 383 insertions(+), 381 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 01f9f87..b5987ca 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..5d976d7 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > \ No newline at end of file Nit: newline at end of file please. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2020-12-31 1:21 ` Nicolas Boichat 0 siblings, 0 replies; 72+ messages in thread From: Nicolas Boichat @ 2020-12-31 1:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, linux-arm Mailing List On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > the mmsys will more and more complicated after support > more and more SoCs, add an independent folder will be > more clear > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 2 +- > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- I wonder why this doesn't get detected as a rename? > 4 files changed, 383 insertions(+), 381 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 01f9f87..b5987ca 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..5d976d7 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > \ No newline at end of file Nit: newline at end of file please. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2020-12-31 1:21 ` Nicolas Boichat 0 siblings, 0 replies; 72+ messages in thread From: Nicolas Boichat @ 2020-12-31 1:21 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, linux-arm Mailing List On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu <yongqiang.niu@mediatek.com> wrote: > > the mmsys will more and more complicated after support > more and more SoCs, add an independent folder will be > more clear > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/Makefile | 2 +- > drivers/soc/mediatek/mmsys/Makefile | 2 + > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- I wonder why this doesn't get detected as a rename? > 4 files changed, 383 insertions(+), 381 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index 01f9f87..b5987ca 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 0000000..5d976d7 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > \ No newline at end of file Nit: newline at end of file please. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder 2020-12-31 1:21 ` Nicolas Boichat (?) (?) @ 2021-01-04 3:08 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 3:08 UTC (permalink / raw) To: Nicolas Boichat Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? the rename message displayed when git commit -s git show will not show the rename information > > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. it will be fixed in next version ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2021-01-04 3:08 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 3:08 UTC (permalink / raw) To: Nicolas Boichat Cc: Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? the rename message displayed when git commit -s git show will not show the rename information > > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. it will be fixed in next version _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2021-01-04 3:08 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 3:08 UTC (permalink / raw) To: Nicolas Boichat Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? the rename message displayed when git commit -s git show will not show the rename information > > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. it will be fixed in next version _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2021-01-04 3:08 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 3:08 UTC (permalink / raw) To: Nicolas Boichat Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? the rename message displayed when git commit -s git show will not show the rename information > > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. it will be fixed in next version _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder 2020-12-31 1:21 ` Nicolas Boichat (?) (?) @ 2021-01-04 5:57 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 5:57 UTC (permalink / raw) To: Nicolas Boichat Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? > git commit --amend [detached HEAD 1f10c05] soc: mediatek: mmsys: create mmsys folder 3 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile rename drivers/soc/mediatek/{ => mmsys}/mtk-mmsys.c (100%) > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2021-01-04 5:57 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 5:57 UTC (permalink / raw) To: Nicolas Boichat Cc: Mark Rutland, Devicetree List, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? > git commit --amend [detached HEAD 1f10c05] soc: mediatek: mmsys: create mmsys folder 3 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile rename drivers/soc/mediatek/{ => mmsys}/mtk-mmsys.c (100%) > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2021-01-04 5:57 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 5:57 UTC (permalink / raw) To: Nicolas Boichat Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? > git commit --amend [detached HEAD 1f10c05] soc: mediatek: mmsys: create mmsys folder 3 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile rename drivers/soc/mediatek/{ => mmsys}/mtk-mmsys.c (100%) > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder @ 2021-01-04 5:57 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2021-01-04 5:57 UTC (permalink / raw) To: Nicolas Boichat Cc: Mark Rutland, Devicetree List, Daniel Vetter, David Airlie, lkml, dri-devel, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, linux-arm Mailing List On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote: > On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu > <yongqiang.niu@mediatek.com> wrote: > > > > the mmsys will more and more complicated after support > > more and more SoCs, add an independent folder will be > > more clear > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/Makefile | 2 +- > > drivers/soc/mediatek/mmsys/Makefile | 2 + > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 380 --------------------------------- > > I wonder why this doesn't get detected as a rename? > git commit --amend [detached HEAD 1f10c05] soc: mediatek: mmsys: create mmsys folder 3 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile rename drivers/soc/mediatek/{ => mmsys}/mtk-mmsys.c (100%) > > 4 files changed, 383 insertions(+), 381 deletions(-) > > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index 01f9f87..b5987ca 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile > > new file mode 100644 > > index 0000000..5d976d7 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mmsys/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > > \ No newline at end of file > > Nit: newline at end of file please. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3, 2/8] soc: mediatek: mmsys: Use function call for setting the routing registers 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu Actually, setting the registers for routing, use multiple 'if-else' for different routes, but this code would be more and more complicated while we support more and more SoCs. Change that and use a function call per SoC so the code will be more portable and clear. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 3 +- drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 233 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 241 +++--------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 14 ++ 4 files changed, 268 insertions(+), 223 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 5d976d7..ac03025 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file +obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..40576d3 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index da2de8f..c35bda1 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -10,91 +10,34 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -106,176 +49,26 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (!funcs) + return; + + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + funcs->sout_sel(mmsys->regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); @@ -289,14 +82,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; + + if (!funcs) + return; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..17e8b91 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,20 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 2/8] soc: mediatek: mmsys: Use function call for setting the routing registers @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel Actually, setting the registers for routing, use multiple 'if-else' for different routes, but this code would be more and more complicated while we support more and more SoCs. Change that and use a function call per SoC so the code will be more portable and clear. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 3 +- drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 233 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 241 +++--------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 14 ++ 4 files changed, 268 insertions(+), 223 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 5d976d7..ac03025 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file +obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..40576d3 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index da2de8f..c35bda1 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -10,91 +10,34 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -106,176 +49,26 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (!funcs) + return; + + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + funcs->sout_sel(mmsys->regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); @@ -289,14 +82,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; + + if (!funcs) + return; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..17e8b91 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,20 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 2/8] soc: mediatek: mmsys: Use function call for setting the routing registers @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel Actually, setting the registers for routing, use multiple 'if-else' for different routes, but this code would be more and more complicated while we support more and more SoCs. Change that and use a function call per SoC so the code will be more portable and clear. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 3 +- drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 233 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 241 +++--------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 14 ++ 4 files changed, 268 insertions(+), 223 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 5d976d7..ac03025 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file +obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..40576d3 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index da2de8f..c35bda1 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -10,91 +10,34 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -106,176 +49,26 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (!funcs) + return; + + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + funcs->sout_sel(mmsys->regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); @@ -289,14 +82,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; + + if (!funcs) + return; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..17e8b91 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,20 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 2/8] soc: mediatek: mmsys: Use function call for setting the routing registers @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel Actually, setting the registers for routing, use multiple 'if-else' for different routes, but this code would be more and more complicated while we support more and more SoCs. Change that and use a function call per SoC so the code will be more portable and clear. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 3 +- drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 233 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 241 +++--------------------------- include/linux/soc/mediatek/mtk-mmsys.h | 14 ++ 4 files changed, 268 insertions(+), 223 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 5d976d7..ac03025 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o \ No newline at end of file +obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c new file mode 100644 index 0000000..40576d3 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL 0x04c +#define DISP_REG_CONFIG_DSI_SEL 0x050 +#define DISP_REG_CONFIG_DPI_SEL 0x064 + +#define OVL0_MOUT_EN_COLOR0 0x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR1 0x1 +#define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DPI1 0x3 +#define RDMA0_SOUT_DSI1 0x1 +#define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 +#define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define DSI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_BLS 0x0 +#define DSI_SEL_IN_RDMA 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_COLOR0; + } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; + value = OVL_MOUT_EN_RDMA; + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD_MOUT_EN_RDMA0; + } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; + value = UFOE_MOUT_EN_DSI0; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; + value = OVL1_MOUT_EN_COLOR1; + } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; + value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { + *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; + value = COLOR0_SEL_IN_OVL0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { + *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; + value = COLOR1_SEL_IN_OVL1; + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + *addr = DISP_REG_CONFIG_DSI_SEL; + value = DSI_SEL_IN_BLS; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { + writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, + config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { + writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, + config_regs + DISP_REG_CONFIG_OUT_SEL); + writel_relaxed(DSI_SEL_IN_RDMA, + config_regs + DISP_REG_CONFIG_DSI_SEL); + writel_relaxed(DPI_SEL_IN_BLS, + config_regs + DISP_REG_CONFIG_DPI_SEL); + } +} + +struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index da2de8f..c35bda1 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -10,91 +10,34 @@ #include <linux/platform_device.h> #include <linux/soc/mediatek/mtk-mmsys.h> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 -#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 -#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 -#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 -#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 - -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 -#define DISP_REG_CONFIG_OUT_SEL 0x04c -#define DISP_REG_CONFIG_DSI_SEL 0x050 -#define DISP_REG_CONFIG_DPI_SEL 0x064 - -#define OVL0_MOUT_EN_COLOR0 0x1 -#define OD_MOUT_EN_RDMA0 0x1 -#define OD1_MOUT_EN_RDMA1 BIT(16) -#define UFOE_MOUT_EN_DSI0 0x1 -#define COLOR0_SEL_IN_OVL0 0x1 -#define OVL1_MOUT_EN_COLOR1 0x1 -#define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA0_SOUT_DPI0 0x2 -#define RDMA0_SOUT_DPI1 0x3 -#define RDMA0_SOUT_DSI1 0x1 -#define RDMA0_SOUT_DSI2 0x4 -#define RDMA0_SOUT_DSI3 0x5 -#define RDMA1_SOUT_DPI0 0x2 -#define RDMA1_SOUT_DPI1 0x3 -#define RDMA1_SOUT_DSI1 0x1 -#define RDMA1_SOUT_DSI2 0x4 -#define RDMA1_SOUT_DSI3 0x5 -#define RDMA2_SOUT_DPI0 0x2 -#define RDMA2_SOUT_DPI1 0x3 -#define RDMA2_SOUT_DSI1 0x1 -#define RDMA2_SOUT_DSI2 0x4 -#define RDMA2_SOUT_DSI3 0x5 -#define DPI0_SEL_IN_RDMA1 0x1 -#define DPI0_SEL_IN_RDMA2 0x3 -#define DPI1_SEL_IN_RDMA1 (0x1 << 8) -#define DPI1_SEL_IN_RDMA2 (0x3 << 8) -#define DSI0_SEL_IN_RDMA1 0x1 -#define DSI0_SEL_IN_RDMA2 0x4 -#define DSI1_SEL_IN_RDMA1 0x1 -#define DSI1_SEL_IN_RDMA2 0x4 -#define DSI2_SEL_IN_RDMA1 (0x1 << 16) -#define DSI2_SEL_IN_RDMA2 (0x4 << 16) -#define DSI3_SEL_IN_RDMA1 (0x1 << 16) -#define DSI3_SEL_IN_RDMA2 (0x4 << 16) -#define COLOR1_SEL_IN_OVL1 0x1 - -#define OVL_MOUT_EN_RDMA 0x1 -#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 -#define BLS_TO_DPI_RDMA1_TO_DSI 0x2 -#define DSI_SEL_IN_BLS 0x0 -#define DPI_SEL_IN_BLS 0x0 -#define DSI_SEL_IN_RDMA 0x1 - struct mtk_mmsys_driver_data { const char *clk_driver; + const struct mtk_mmsys_conn_funcs *funcs; }; static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", + .funcs = &mt2701_mmsys_funcs, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { @@ -106,176 +49,26 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; }; -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN; - value = OVL0_MOUT_EN_COLOR0; - } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; - value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD_MOUT_EN_RDMA0; - } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN; - value = UFOE_MOUT_EN_DSI0; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN; - value = OVL1_MOUT_EN_COLOR1; - } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; - value = GAMMA_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; - value = OD1_MOUT_EN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; - value = RDMA0_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DSI3; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; - value = RDMA1_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI0; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DPI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; - value = RDMA2_SOUT_DSI3; - } else { - value = 0; - } - - return value; -} - -static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next, - unsigned int *addr) -{ - unsigned int value; - - if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) { - *addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN; - value = COLOR0_SEL_IN_OVL0; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI3_SEL_IN_RDMA1; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { - *addr = DISP_REG_CONFIG_DPI_SEL_IN; - value = DPI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { - *addr = DISP_REG_CONFIG_DSIO_SEL_IN; - value = DSI1_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI2_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI3_SEL_IN_RDMA2; - } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { - *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; - value = COLOR1_SEL_IN_OVL1; - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSI_SEL; - value = DSI_SEL_IN_BLS; - } else { - value = 0; - } - - return value; -} - -static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) -{ - if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) { - writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1, - config_regs + DISP_REG_CONFIG_OUT_SEL); - } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { - writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, - config_regs + DISP_REG_CONFIG_OUT_SEL); - writel_relaxed(DSI_SEL_IN_RDMA, - config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); - } -} - void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + if (!funcs) + return; + + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } - mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next); + funcs->sout_sel(mmsys->regs, cur, next); - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); @@ -289,14 +82,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); unsigned int addr, value, reg; + const struct mtk_mmsys_conn_funcs *funcs = mmsys->data->funcs; + + if (!funcs) + return; - value = mtk_mmsys_ddp_mout_en(cur, next, &addr); + value = funcs->mout_en(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } - value = mtk_mmsys_ddp_sel_in(cur, next, &addr); + value = funcs->sel_in(cur, next, &addr); if (value) { reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..17e8b91 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -42,6 +42,20 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; +struct mtk_mmsys_conn_funcs { + u32 (*mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + u32 (*sel_in)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); + void (*sout_sel)(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next); +}; + +extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index c35bda1..dae665b 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index c35bda1..dae665b 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index c35bda1..dae665b 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel add mt8183 function call for setting the routing registers Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 1 + include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 93 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index ac03025..25eeb9e5 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c new file mode 100644 index 0000000..192b4ab --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define DISP_OVL0_MOUT_EN 0xf00 +#define DISP_OVL0_2L_MOUT_EN 0xf04 +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define DISP_DITHER0_MOUT_EN 0xf0c +#define DISP_PATH0_SEL_IN 0xf24 +#define DISP_DSI0_SEL_IN 0xf2c +#define DISP_DPI0_SEL_IN 0xf30 +#define DISP_RDMA0_SOUT_SEL_IN 0xf50 +#define DISP_RDMA1_SOUT_SEL_IN 0xf54 + +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0) +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DITHER0_MOUT_IN_DSI0 BIT(0) +#define DISP_PATH0_SEL_IN_OVL0_2L 0x1 +#define DSI0_SEL_IN_RDMA0 0x1 +#define DSI0_SEL_IN_RDMA1 0x3 +#define DPI0_SEL_IN_RDMA0 0x1 +#define DPI0_SEL_IN_RDMA1 0x2 +#define RDMA0_SOUT_COLOR0 0x1 +#define RDMA1_SOUT_DSI0 0x1 + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) { + *addr = DISP_OVL0_MOUT_EN; + value = OVL0_MOUT_EN_OVL0_2L; + } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_2L_MOUT_EN_DISP_PATH0; + } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_OVL1_2L_MOUT_EN; + value = OVL1_2L_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_IN_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_PATH0_SEL_IN; + value = DISP_PATH0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_DPI0_SEL_IN; + value = DPI0_SEL_IN_RDMA1; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL_IN); + } +} + +struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index c35bda1..dae665b 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", + .funcs = &mt8183_mmsys_funcs, }; struct mtk_mmsys { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 17e8b91..4b6c514 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -55,6 +55,7 @@ struct mtk_mmsys_conn_funcs { }; extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4b6c514..42476c2 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4b6c514..42476c2 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4b6c514..42476c2 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 4b6c514..42476c2 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-29 15:23 ` Chun-Kuang Hu -1 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:23 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component OVL_2L2 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 4b6c514..42476c2 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2020-12-29 15:23 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:23 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component OVL_2L2 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 4b6c514..42476c2 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2020-12-29 15:23 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:23 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component OVL_2L2 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 4b6c514..42476c2 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2020-12-29 15:23 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:23 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component OVL_2L2 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 4b6c514..42476c2 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 2020-12-29 15:23 ` Chun-Kuang Hu (?) (?) @ 2021-03-22 15:05 ` Chun-Kuang Hu -1 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2021-03-22 15:05 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Matthias: Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2020年12月29日 週二 下午11:23寫道： > > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > > > This patch add component OVL_2L2 > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> How do you think about this patch? One drm patch [1] depends on this patch. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-2-hsinyi@chromium.org/ Regards, Chun-Kuang. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 4b6c514..42476c2 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_OVL_2L0, > > DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL_2L2, > > DDP_COMPONENT_OVL1, > > DDP_COMPONENT_PWM0, > > DDP_COMPONENT_PWM1, > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2021-03-22 15:05 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2021-03-22 15:05 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, Yongqiang Niu, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Matthias: Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2020年12月29日 週二 下午11:23寫道： > > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > > > This patch add component OVL_2L2 > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> How do you think about this patch? One drm patch [1] depends on this patch. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-2-hsinyi@chromium.org/ Regards, Chun-Kuang. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 4b6c514..42476c2 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_OVL_2L0, > > DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL_2L2, > > DDP_COMPONENT_OVL1, > > DDP_COMPONENT_PWM0, > > DDP_COMPONENT_PWM1, > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2021-03-22 15:05 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2021-03-22 15:05 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Matthias: Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2020年12月29日 週二 下午11:23寫道： > > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > > > This patch add component OVL_2L2 > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> How do you think about this patch? One drm patch [1] depends on this patch. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-2-hsinyi@chromium.org/ Regards, Chun-Kuang. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 4b6c514..42476c2 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_OVL_2L0, > > DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL_2L2, > > DDP_COMPONENT_OVL1, > > DDP_COMPONENT_PWM0, > > DDP_COMPONENT_PWM1, > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 @ 2021-03-22 15:05 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2021-03-22 15:05 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Yongqiang Niu, CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Matthias: Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2020年12月29日 週二 下午11:23寫道： > > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > > > This patch add component OVL_2L2 > > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> How do you think about this patch? One drm patch [1] depends on this patch. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210202081237.774442-2-hsinyi@chromium.org/ Regards, Chun-Kuang. > > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index 4b6c514..42476c2 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id { > > DDP_COMPONENT_OVL0, > > DDP_COMPONENT_OVL_2L0, > > DDP_COMPONENT_OVL_2L1, > > + DDP_COMPONENT_OVL_2L2, > > DDP_COMPONENT_OVL1, > > DDP_COMPONENT_PWM0, > > DDP_COMPONENT_PWM1, > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3, 5/8] soc: mediatek: mmsys: add component POSTMASK 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu This patch add component POSTMASK Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 42476c2..09ee424 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -31,6 +31,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 5/8] soc: mediatek: mmsys: add component POSTMASK @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel This patch add component POSTMASK Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 42476c2..09ee424 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -31,6 +31,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 5/8] soc: mediatek: mmsys: add component POSTMASK @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add component POSTMASK Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 42476c2..09ee424 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -31,6 +31,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 5/8] soc: mediatek: mmsys: add component POSTMASK @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add component POSTMASK Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 42476c2..09ee424 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -31,6 +31,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 09ee424..aa4f60e 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 09ee424..aa4f60e 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 09ee424..aa4f60e 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 09ee424..aa4f60e 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-29 15:24 ` Chun-Kuang Hu -1 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:24 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component RDMA4 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 09ee424..aa4f60e 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 @ 2020-12-29 15:24 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:24 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component RDMA4 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 09ee424..aa4f60e 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 @ 2020-12-29 15:24 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:24 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component RDMA4 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 09ee424..aa4f60e 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 @ 2020-12-29 15:24 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-29 15:24 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:37寫道： > > This patch add component RDMA4 Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 09ee424..aa4f60e 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -38,6 +38,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu Use function call for setting mmsys ovl mout register Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index dae665b..ea36a11 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + if (funcs->ovl_mout_en) { + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index aa4f60e..220203d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { u32 (*mout_en)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); u32 (*sel_in)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel Use function call for setting mmsys ovl mout register Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index dae665b..ea36a11 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + if (funcs->ovl_mout_en) { + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index aa4f60e..220203d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { u32 (*mout_en)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); u32 (*sel_in)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel Use function call for setting mmsys ovl mout register Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index dae665b..ea36a11 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + if (funcs->ovl_mout_en) { + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index aa4f60e..220203d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { u32 (*mout_en)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); u32 (*sel_in)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel Use function call for setting mmsys ovl mout register Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 23 insertions(+) diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index dae665b..ea36a11 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + if (funcs->ovl_mout_en) { + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) | value; + writel_relaxed(reg, mmsys->regs + addr); + } + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, reg = readl_relaxed(mmsys->regs + addr) & ~value; writel_relaxed(reg, mmsys->regs + addr); } + + if (!funcs->ovl_mout_en) + return; + + value = funcs->ovl_mout_en(cur, next, &addr); + if (value) { + reg = readl_relaxed(mmsys->regs + addr) & ~value; + writel_relaxed(reg, mmsys->regs + addr); + } } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index aa4f60e..220203d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { u32 (*mout_en)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr); u32 (*sel_in)(enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr); -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 16:38 ` Chun-Kuang Hu -1 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-28 16:38 UTC (permalink / raw) To: Yongqiang Niu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > Use function call for setting mmsys ovl mout register > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > index dae665b..ea36a11 100644 > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) | value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + if (funcs->ovl_mout_en) { > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) | value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > + } mtk_mmsys_ddp_mout_en() could write register inside it rather than return value and write register in mtk_mmsys_ddp_connect(). So you could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). Regards, Chun-Kuang. > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) & ~value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index aa4f60e..220203d 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-28 16:38 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-28 16:38 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > Use function call for setting mmsys ovl mout register > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > index dae665b..ea36a11 100644 > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) | value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + if (funcs->ovl_mout_en) { > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) | value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > + } mtk_mmsys_ddp_mout_en() could write register inside it rather than return value and write register in mtk_mmsys_ddp_connect(). So you could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). Regards, Chun-Kuang. > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) & ~value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index aa4f60e..220203d 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-28 16:38 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-28 16:38 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > Use function call for setting mmsys ovl mout register > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > index dae665b..ea36a11 100644 > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) | value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + if (funcs->ovl_mout_en) { > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) | value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > + } mtk_mmsys_ddp_mout_en() could write register inside it rather than return value and write register in mtk_mmsys_ddp_connect(). So you could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). Regards, Chun-Kuang. > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) & ~value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index aa4f60e..220203d 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-28 16:38 ` Chun-Kuang Hu 0 siblings, 0 replies; 72+ messages in thread From: Chun-Kuang Hu @ 2020-12-28 16:38 UTC (permalink / raw) To: Yongqiang Niu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > Use function call for setting mmsys ovl mout register > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > index dae665b..ea36a11 100644 > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) | value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + if (funcs->ovl_mout_en) { > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) | value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > + } mtk_mmsys_ddp_mout_en() could write register inside it rather than return value and write register in mtk_mmsys_ddp_connect(). So you could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). Regards, Chun-Kuang. > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > reg = readl_relaxed(mmsys->regs + addr) & ~value; > writel_relaxed(reg, mmsys->regs + addr); > } > + > + if (!funcs->ovl_mout_en) > + return; > + > + value = funcs->ovl_mout_en(cur, next, &addr); > + if (value) { > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > + writel_relaxed(reg, mmsys->regs + addr); > + } > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index aa4f60e..220203d 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > + enum mtk_ddp_comp_id next, > + unsigned int *addr); > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next, > unsigned int *addr); > -- > 1.8.1.1.dirty > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register 2020-12-28 16:38 ` Chun-Kuang Hu (?) (?) @ 2020-12-29 0:52 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 0:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. if that, there will be many repeat code like this: if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-29 0:52 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 0:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. if that, there will be many repeat code like this: if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-29 0:52 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 0:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. if that, there will be many repeat code like this: if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-29 0:52 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 0:52 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. if that, there will be many repeat code like this: if (value) { reg = readl_relaxed(mmsys->regs + addr) | value; writel_relaxed(reg, mmsys->regs + addr); } > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register 2020-12-28 16:38 ` Chun-Kuang Hu (?) (?) @ 2020-12-29 1:34 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 1:34 UTC (permalink / raw) To: Chun-Kuang Hu Cc: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger, Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. i will add this modification in next version > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-29 1:34 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 1:34 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. i will add this modification in next version > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-29 1:34 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 1:34 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. i will add this modification in next version > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register @ 2020-12-29 1:34 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-29 1:34 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Mark Rutland, DTML, Daniel Vetter, David Airlie, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group, Matthias Brugger, Rob Herring, moderated list:ARM/Mediatek SoC support, Philipp Zabel, CK Hu, Linux ARM On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote: > Hi, Yongqiang: > > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月28日 週一 下午4:38寫道： > > > > Use function call for setting mmsys ovl mout register > > > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 ++++++++++++++++++++ > > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > index dae665b..ea36a11 100644 > > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) | value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + if (funcs->ovl_mout_en) { > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) | value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > + } > > mtk_mmsys_ddp_mout_en() could write register inside it rather than > return value and write register in mtk_mmsys_ddp_connect(). So you > could do ovl_mout_en() in mtk_mmsys_ddp_mout_en(). > > Regards, > Chun-Kuang. i will add this modification in next version > > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); > > > > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > reg = readl_relaxed(mmsys->regs + addr) & ~value; > > writel_relaxed(reg, mmsys->regs + addr); > > } > > + > > + if (!funcs->ovl_mout_en) > > + return; > > + > > + value = funcs->ovl_mout_en(cur, next, &addr); > > + if (value) { > > + reg = readl_relaxed(mmsys->regs + addr) & ~value; > > + writel_relaxed(reg, mmsys->regs + addr); > > + } > > } > > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > > index aa4f60e..220203d 100644 > > --- a/include/linux/soc/mediatek/mtk-mmsys.h > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs { > > u32 (*mout_en)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > + u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur, > > + enum mtk_ddp_comp_id next, > > + unsigned int *addr); > > u32 (*sel_in)(enum mtk_ddp_comp_id cur, > > enum mtk_ddp_comp_id next, > > unsigned int *addr); > > -- > > 1.8.1.1.dirty > > _______________________________________________ > > Linux-mediatek mailing list > > Linux-mediatek@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support 2020-12-28 8:37 ` Yongqiang Niu (?) (?) @ 2020-12-28 8:37 ` Yongqiang Niu -1 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Yongqiang Niu add mt8192 mmsys support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 +++ include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 130 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 25eeb9e5..7508cd3 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c new file mode 100644 index 0000000..a5145ff --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define MMSYS_OVL_MOUT_EN 0xf04 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_OVL0_GO_BG BIT(1) +#define DISP_OVL0_2L_GO_BLEND BIT(2) +#define DISP_OVL0_2L_GO_BG BIT(3) +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DISP_OVL0_2L_MOUT_EN 0xf18 +#define DISP_OVL0_MOUT_EN 0xf1c +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define DISP_RDMA0_SEL_IN 0xf2c +#define RDMA0_SEL_IN_OVL0_2L 0x3 +#define DISP_RDMA0_SOUT_SEL 0xf30 +#define RDMA0_SOUT_COLOR0 0x1 +#define DISP_CCORR0_SOUT_SEL 0xf34 +#define CCORR0_SOUT_AAL0 0x1 +#define DISP_AAL0_SEL_IN 0xf38 +#define AAL0_SEL_IN_CCORR0 0x1 +#define DISP_DITHER0_MOUT_EN 0xf3c +#define DITHER0_MOUT_DSI0 BIT(0) +#define DISP_DSI0_SEL_IN 0xf40 +#define DSI0_SEL_IN_DITHER0 0x1 +#define DISP_OVL2_2L_MOUT_EN 0xf4c +#define OVL2_2L_MOUT_RDMA4 BIT(0) + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_MOUT_EN_DISP_RDMA0; + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) { + *addr = DISP_OVL2_2L_MOUT_EN; + value = OVL2_2L_MOUT_RDMA4; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_RDMA0_SEL_IN; + value = RDMA0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + *addr = DISP_AAL0_SEL_IN; + value = AAL0_SEL_IN_CCORR0; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DSI0_SEL_IN; + value = DSI0_SEL_IN_DITHER0; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL); + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL); + } +} + +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + *addr = MMSYS_OVL_MOUT_EN; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_GO_BG; + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0) + value = DISP_OVL0_2L_GO_BG; + else if (cur == DDP_COMPONENT_OVL0) + value = DISP_OVL0_GO_BLEND; + else if (cur == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_2L_GO_BLEND; + else + value = 0; + + return value; +} + +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .ovl_mout_en = mtk_mmsys_ovl_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index ea36a11..42a9f51 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -45,6 +45,11 @@ struct mtk_mmsys_driver_data { .funcs = &mt8183_mmsys_funcs, }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .funcs = &mt8192_mmsys_funcs, +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -184,6 +189,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 220203d..efa07b9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs { extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, linux-arm-kernel add mt8192 mmsys support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 +++ include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 130 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 25eeb9e5..7508cd3 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c new file mode 100644 index 0000000..a5145ff --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define MMSYS_OVL_MOUT_EN 0xf04 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_OVL0_GO_BG BIT(1) +#define DISP_OVL0_2L_GO_BLEND BIT(2) +#define DISP_OVL0_2L_GO_BG BIT(3) +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DISP_OVL0_2L_MOUT_EN 0xf18 +#define DISP_OVL0_MOUT_EN 0xf1c +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define DISP_RDMA0_SEL_IN 0xf2c +#define RDMA0_SEL_IN_OVL0_2L 0x3 +#define DISP_RDMA0_SOUT_SEL 0xf30 +#define RDMA0_SOUT_COLOR0 0x1 +#define DISP_CCORR0_SOUT_SEL 0xf34 +#define CCORR0_SOUT_AAL0 0x1 +#define DISP_AAL0_SEL_IN 0xf38 +#define AAL0_SEL_IN_CCORR0 0x1 +#define DISP_DITHER0_MOUT_EN 0xf3c +#define DITHER0_MOUT_DSI0 BIT(0) +#define DISP_DSI0_SEL_IN 0xf40 +#define DSI0_SEL_IN_DITHER0 0x1 +#define DISP_OVL2_2L_MOUT_EN 0xf4c +#define OVL2_2L_MOUT_RDMA4 BIT(0) + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_MOUT_EN_DISP_RDMA0; + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) { + *addr = DISP_OVL2_2L_MOUT_EN; + value = OVL2_2L_MOUT_RDMA4; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_RDMA0_SEL_IN; + value = RDMA0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + *addr = DISP_AAL0_SEL_IN; + value = AAL0_SEL_IN_CCORR0; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DSI0_SEL_IN; + value = DSI0_SEL_IN_DITHER0; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL); + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL); + } +} + +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + *addr = MMSYS_OVL_MOUT_EN; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_GO_BG; + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0) + value = DISP_OVL0_2L_GO_BG; + else if (cur == DDP_COMPONENT_OVL0) + value = DISP_OVL0_GO_BLEND; + else if (cur == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_2L_GO_BLEND; + else + value = 0; + + return value; +} + +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .ovl_mout_en = mtk_mmsys_ovl_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index ea36a11..42a9f51 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -45,6 +45,11 @@ struct mtk_mmsys_driver_data { .funcs = &mt8183_mmsys_funcs, }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .funcs = &mt8192_mmsys_funcs, +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -184,6 +189,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 220203d..efa07b9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs { extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel add mt8192 mmsys support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 +++ include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 130 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 25eeb9e5..7508cd3 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c new file mode 100644 index 0000000..a5145ff --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define MMSYS_OVL_MOUT_EN 0xf04 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_OVL0_GO_BG BIT(1) +#define DISP_OVL0_2L_GO_BLEND BIT(2) +#define DISP_OVL0_2L_GO_BG BIT(3) +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DISP_OVL0_2L_MOUT_EN 0xf18 +#define DISP_OVL0_MOUT_EN 0xf1c +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define DISP_RDMA0_SEL_IN 0xf2c +#define RDMA0_SEL_IN_OVL0_2L 0x3 +#define DISP_RDMA0_SOUT_SEL 0xf30 +#define RDMA0_SOUT_COLOR0 0x1 +#define DISP_CCORR0_SOUT_SEL 0xf34 +#define CCORR0_SOUT_AAL0 0x1 +#define DISP_AAL0_SEL_IN 0xf38 +#define AAL0_SEL_IN_CCORR0 0x1 +#define DISP_DITHER0_MOUT_EN 0xf3c +#define DITHER0_MOUT_DSI0 BIT(0) +#define DISP_DSI0_SEL_IN 0xf40 +#define DSI0_SEL_IN_DITHER0 0x1 +#define DISP_OVL2_2L_MOUT_EN 0xf4c +#define OVL2_2L_MOUT_RDMA4 BIT(0) + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_MOUT_EN_DISP_RDMA0; + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) { + *addr = DISP_OVL2_2L_MOUT_EN; + value = OVL2_2L_MOUT_RDMA4; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_RDMA0_SEL_IN; + value = RDMA0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + *addr = DISP_AAL0_SEL_IN; + value = AAL0_SEL_IN_CCORR0; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DSI0_SEL_IN; + value = DSI0_SEL_IN_DITHER0; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL); + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL); + } +} + +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + *addr = MMSYS_OVL_MOUT_EN; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_GO_BG; + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0) + value = DISP_OVL0_2L_GO_BG; + else if (cur == DDP_COMPONENT_OVL0) + value = DISP_OVL0_GO_BLEND; + else if (cur == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_2L_GO_BLEND; + else + value = 0; + + return value; +} + +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .ovl_mout_en = mtk_mmsys_ovl_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index ea36a11..42a9f51 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -45,6 +45,11 @@ struct mtk_mmsys_driver_data { .funcs = &mt8183_mmsys_funcs, }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .funcs = &mt8192_mmsys_funcs, +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -184,6 +189,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 220203d..efa07b9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs { extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 72+ messages in thread
* [PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support @ 2020-12-28 8:37 ` Yongqiang Niu 0 siblings, 0 replies; 72+ messages in thread From: Yongqiang Niu @ 2020-12-28 8:37 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Rob Herring, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, linux-mediatek, Daniel Vetter, linux-arm-kernel add mt8192 mmsys support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mmsys/Makefile | 1 + drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++ drivers/soc/mediatek/mmsys/mtk-mmsys.c | 9 +++ include/linux/soc/mediatek/mtk-mmsys.h | 1 + 4 files changed, 130 insertions(+) create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile index 25eeb9e5..7508cd3 100644 --- a/drivers/soc/mediatek/mmsys/Makefile +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c new file mode 100644 index 0000000..a5145ff --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-mmsys.h> + +#define MMSYS_OVL_MOUT_EN 0xf04 +#define DISP_OVL0_GO_BLEND BIT(0) +#define DISP_OVL0_GO_BG BIT(1) +#define DISP_OVL0_2L_GO_BLEND BIT(2) +#define DISP_OVL0_2L_GO_BG BIT(3) +#define DISP_OVL1_2L_MOUT_EN 0xf08 +#define OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define DISP_OVL0_2L_MOUT_EN 0xf18 +#define DISP_OVL0_MOUT_EN 0xf1c +#define OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define OVL0_MOUT_EN_OVL0_2L BIT(4) +#define DISP_RDMA0_SEL_IN 0xf2c +#define RDMA0_SEL_IN_OVL0_2L 0x3 +#define DISP_RDMA0_SOUT_SEL 0xf30 +#define RDMA0_SOUT_COLOR0 0x1 +#define DISP_CCORR0_SOUT_SEL 0xf34 +#define CCORR0_SOUT_AAL0 0x1 +#define DISP_AAL0_SEL_IN 0xf38 +#define AAL0_SEL_IN_CCORR0 0x1 +#define DISP_DITHER0_MOUT_EN 0xf3c +#define DITHER0_MOUT_DSI0 BIT(0) +#define DISP_DSI0_SEL_IN 0xf40 +#define DSI0_SEL_IN_DITHER0 0x1 +#define DISP_OVL2_2L_MOUT_EN 0xf4c +#define OVL2_2L_MOUT_RDMA4 BIT(0) + +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_OVL0_2L_MOUT_EN; + value = OVL0_MOUT_EN_DISP_RDMA0; + } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) { + *addr = DISP_OVL2_2L_MOUT_EN; + value = OVL2_2L_MOUT_RDMA4; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DITHER0_MOUT_EN; + value = DITHER0_MOUT_DSI0; + } else { + value = 0; + } + + return value; +} + +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) { + *addr = DISP_RDMA0_SEL_IN; + value = RDMA0_SEL_IN_OVL0_2L; + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + *addr = DISP_AAL0_SEL_IN; + value = AAL0_SEL_IN_CCORR0; + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) { + *addr = DISP_DSI0_SEL_IN; + value = DSI0_SEL_IN_DITHER0; + } else { + value = 0; + } + + return value; +} + +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs, + enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next) +{ + if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { + writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL); + } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) { + writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL); + } +} + +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur, + enum mtk_ddp_comp_id next, + unsigned int *addr) +{ + unsigned int value; + + *addr = MMSYS_OVL_MOUT_EN; + + if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_GO_BG; + else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0) + value = DISP_OVL0_2L_GO_BG; + else if (cur == DDP_COMPONENT_OVL0) + value = DISP_OVL0_GO_BLEND; + else if (cur == DDP_COMPONENT_OVL_2L0) + value = DISP_OVL0_2L_GO_BLEND; + else + value = 0; + + return value; +} + +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = { + .mout_en = mtk_mmsys_ddp_mout_en, + .ovl_mout_en = mtk_mmsys_ovl_mout_en, + .sel_in = mtk_mmsys_ddp_sel_in, + .sout_sel = mtk_mmsys_ddp_sout_sel, +}; diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c index ea36a11..42a9f51 100644 --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -45,6 +45,11 @@ struct mtk_mmsys_driver_data { .funcs = &mt8183_mmsys_funcs, }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .funcs = &mt8192_mmsys_funcs, +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -184,6 +189,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 220203d..efa07b9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs { extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs; extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs; +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs; void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 72+ messages in thread
end of thread, other threads:[~2021-03-22 15:07 UTC | newest] Thread overview: 72+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-12-28 8:37 soc: mediatek: Prepare MMSYS for DDP routing using function call Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-31 1:21 ` Nicolas Boichat 2020-12-31 1:21 ` Nicolas Boichat 2020-12-31 1:21 ` Nicolas Boichat 2020-12-31 1:21 ` Nicolas Boichat 2021-01-04 3:08 ` Yongqiang Niu 2021-01-04 3:08 ` Yongqiang Niu 2021-01-04 3:08 ` Yongqiang Niu 2021-01-04 3:08 ` Yongqiang Niu 2021-01-04 5:57 ` Yongqiang Niu 2021-01-04 5:57 ` Yongqiang Niu 2021-01-04 5:57 ` Yongqiang Niu 2021-01-04 5:57 ` Yongqiang Niu 2020-12-28 8:37 ` [PATCH v3, 2/8] soc: mediatek: mmsys: Use function call for setting the routing registers Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` [PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 " Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` [PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2 Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-29 15:23 ` Chun-Kuang Hu 2020-12-29 15:23 ` Chun-Kuang Hu 2020-12-29 15:23 ` Chun-Kuang Hu 2020-12-29 15:23 ` Chun-Kuang Hu 2021-03-22 15:05 ` Chun-Kuang Hu 2021-03-22 15:05 ` Chun-Kuang Hu 2021-03-22 15:05 ` Chun-Kuang Hu 2021-03-22 15:05 ` Chun-Kuang Hu 2020-12-28 8:37 ` [PATCH v3, 5/8] soc: mediatek: mmsys: add component POSTMASK Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` [PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4 Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-29 15:24 ` Chun-Kuang Hu 2020-12-29 15:24 ` Chun-Kuang Hu 2020-12-29 15:24 ` Chun-Kuang Hu 2020-12-29 15:24 ` Chun-Kuang Hu 2020-12-28 8:37 ` [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 16:38 ` Chun-Kuang Hu 2020-12-28 16:38 ` Chun-Kuang Hu 2020-12-28 16:38 ` Chun-Kuang Hu 2020-12-28 16:38 ` Chun-Kuang Hu 2020-12-29 0:52 ` Yongqiang Niu 2020-12-29 0:52 ` Yongqiang Niu 2020-12-29 0:52 ` Yongqiang Niu 2020-12-29 0:52 ` Yongqiang Niu 2020-12-29 1:34 ` Yongqiang Niu 2020-12-29 1:34 ` Yongqiang Niu 2020-12-29 1:34 ` Yongqiang Niu 2020-12-29 1:34 ` Yongqiang Niu 2020-12-28 8:37 ` [PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu 2020-12-28 8:37 ` Yongqiang Niu
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