* [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
@ 2021-01-09 15:49 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:49 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Mika Kuoppala, Prathap Kumar Valsan,
Akeem G Abodunrin, Jon Bloomfield, Rodrigo Vivi, Randy Wright,
stable
MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
based on plaform and the number of EU based on the number of slices and
subslices. This is a fixed number per platform/gt, so appropriately
limit the number of threads we spawn to match the device.
v2: Oversaturate the system with tasks to force execution on every HW
thread; if the thread idles it is returned to the pool and may be reused
again before an unused thread.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Randy Wright <rwright@hpe.com>
Cc: stable@vger.kernel.org # v5.7+
---
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 91 ++++++++++++----------
1 file changed, 49 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index d93d85cd3027..3ea7c9cc0f3d 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -7,8 +7,6 @@
#include "i915_drv.h"
#include "intel_gpu_commands.h"
-#define MAX_URB_ENTRIES 64
-#define STATE_SIZE (4 * 1024)
#define GT3_INLINE_DATA_DELAYS 0x1E00
#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
@@ -34,38 +32,57 @@ struct batch_chunk {
};
struct batch_vals {
- u32 max_primitives;
- u32 max_urb_entries;
- u32 cmd_size;
- u32 state_size;
+ u32 max_threads;
u32 state_start;
- u32 batch_size;
+ u32 surface_start;
u32 surface_height;
u32 surface_width;
- u32 scratch_size;
- u32 max_size;
+ u32 size;
};
+static inline int num_primitives(const struct batch_vals *bv)
+{
+ /*
+ * We need to oversaturate the GPU with work in order to dispatch
+ * a shader on every HW thread.
+ */
+ return bv->max_threads + 2;
+}
+
static void
batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
{
if (IS_HASWELL(i915)) {
- bv->max_primitives = 280;
- bv->max_urb_entries = MAX_URB_ENTRIES;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1:
+ bv->max_threads = 70;
+ break;
+ case 2:
+ bv->max_threads = 140;
+ break;
+ case 3:
+ bv->max_threads = 280;
+ break;
+ }
bv->surface_height = 16 * 16;
bv->surface_width = 32 * 2 * 16;
} else {
- bv->max_primitives = 128;
- bv->max_urb_entries = MAX_URB_ENTRIES / 2;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1: /* including vlv */
+ bv->max_threads = 36;
+ break;
+ case 2:
+ bv->max_threads = 128;
+ break;
+ }
bv->surface_height = 16 * 8;
bv->surface_width = 32 * 16;
}
- bv->cmd_size = bv->max_primitives * 4096;
- bv->state_size = STATE_SIZE;
- bv->state_start = bv->cmd_size;
- bv->batch_size = bv->cmd_size + bv->state_size;
- bv->scratch_size = bv->surface_height * bv->surface_width;
- bv->max_size = bv->batch_size + bv->scratch_size;
+ bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
+ bv->surface_start = bv->state_start + SZ_4K;
+ bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
}
static void batch_init(struct batch_chunk *bc,
@@ -155,7 +172,8 @@ static u32
gen7_fill_binding_table(struct batch_chunk *state,
const struct batch_vals *bv)
{
- u32 surface_start = gen7_fill_surface_state(state, bv->batch_size, bv);
+ u32 surface_start =
+ gen7_fill_surface_state(state, bv->surface_start, bv);
u32 *cs = batch_alloc_items(state, 32, 8);
u32 offset = batch_offset(state, cs);
@@ -244,8 +262,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
u32 urb_size, u32 curbe_size,
u32 mode)
{
- u32 urb_entries = bv->max_urb_entries;
- u32 threads = bv->max_primitives - 1;
+ u32 threads = bv->max_threads - 1;
u32 *cs = batch_alloc_items(batch, 32, 8);
*cs++ = MEDIA_VFE_STATE | (8 - 2);
@@ -254,7 +271,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
*cs++ = 0;
/* number of threads & urb entries for GPGPU vs Media Mode */
- *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
+ *cs++ = threads << 16 | 1 << 8 | mode << 2;
*cs++ = 0;
@@ -293,17 +310,12 @@ gen7_emit_media_object(struct batch_chunk *batch,
{
unsigned int x_offset = (media_object_index % 16) * 64;
unsigned int y_offset = (media_object_index / 16) * 16;
- unsigned int inline_data_size;
- unsigned int media_batch_size;
- unsigned int i;
+ unsigned int pkt = 6 + 3;
u32 *cs;
- inline_data_size = 112 * 8;
- media_batch_size = inline_data_size + 6;
+ cs = batch_alloc_items(batch, 8, pkt);
- cs = batch_alloc_items(batch, 8, media_batch_size);
-
- *cs++ = MEDIA_OBJECT | (media_batch_size - 2);
+ *cs++ = MEDIA_OBJECT | (pkt - 2);
/* interface descriptor offset */
*cs++ = 0;
@@ -320,8 +332,6 @@ gen7_emit_media_object(struct batch_chunk *batch,
*cs++ = (y_offset << 16) | (x_offset);
*cs++ = 0;
*cs++ = GT3_INLINE_DATA_DELAYS;
- for (i = 3; i < inline_data_size; i++)
- *cs++ = 0;
batch_advance(batch, cs);
}
@@ -350,8 +360,8 @@ static void emit_batch(struct i915_vma * const vma,
u32 interface_descriptor;
unsigned int i;
- batch_init(&cmds, vma, start, 0, bv->cmd_size);
- batch_init(&state, vma, start, bv->state_start, bv->state_size);
+ batch_init(&cmds, vma, start, 0, bv->state_start);
+ batch_init(&state, vma, start, bv->state_start, SZ_4K);
interface_descriptor =
gen7_fill_interface_descriptor(&state, bv,
@@ -359,19 +369,16 @@ static void emit_batch(struct i915_vma * const vma,
&cb_kernel_hsw :
&cb_kernel_ivb,
desc_count);
- gen7_emit_pipeline_flush(&cmds);
batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
- batch_add(&cmds, MI_NOOP);
gen7_emit_state_base_address(&cmds, interface_descriptor);
gen7_emit_pipeline_flush(&cmds);
gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
-
gen7_emit_interface_descriptor_load(&cmds,
interface_descriptor,
desc_count);
- for (i = 0; i < bv->max_primitives; i++)
+ for (i = 0; i < num_primitives(bv); i++)
gen7_emit_media_object(&cmds, i);
batch_add(&cmds, MI_BATCH_BUFFER_END);
@@ -385,15 +392,15 @@ int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine,
batch_get_defaults(engine->i915, &bv);
if (!vma)
- return bv.max_size;
+ return bv.size;
- GEM_BUG_ON(vma->obj->base.size < bv.max_size);
+ GEM_BUG_ON(vma->obj->base.size < bv.size);
batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
if (IS_ERR(batch))
return PTR_ERR(batch);
- emit_batch(vma, memset(batch, 0, bv.max_size), &bv);
+ emit_batch(vma, memset(batch, 0, bv.size), &bv);
i915_gem_object_flush_map(vma->obj);
__i915_gem_object_release_map(vma->obj);
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
@ 2021-01-09 15:49 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Randy Wright, Chris Wilson, stable
MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
based on plaform and the number of EU based on the number of slices and
subslices. This is a fixed number per platform/gt, so appropriately
limit the number of threads we spawn to match the device.
v2: Oversaturate the system with tasks to force execution on every HW
thread; if the thread idles it is returned to the pool and may be reused
again before an unused thread.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Randy Wright <rwright@hpe.com>
Cc: stable@vger.kernel.org # v5.7+
---
drivers/gpu/drm/i915/gt/gen7_renderclear.c | 91 ++++++++++++----------
1 file changed, 49 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index d93d85cd3027..3ea7c9cc0f3d 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -7,8 +7,6 @@
#include "i915_drv.h"
#include "intel_gpu_commands.h"
-#define MAX_URB_ENTRIES 64
-#define STATE_SIZE (4 * 1024)
#define GT3_INLINE_DATA_DELAYS 0x1E00
#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
@@ -34,38 +32,57 @@ struct batch_chunk {
};
struct batch_vals {
- u32 max_primitives;
- u32 max_urb_entries;
- u32 cmd_size;
- u32 state_size;
+ u32 max_threads;
u32 state_start;
- u32 batch_size;
+ u32 surface_start;
u32 surface_height;
u32 surface_width;
- u32 scratch_size;
- u32 max_size;
+ u32 size;
};
+static inline int num_primitives(const struct batch_vals *bv)
+{
+ /*
+ * We need to oversaturate the GPU with work in order to dispatch
+ * a shader on every HW thread.
+ */
+ return bv->max_threads + 2;
+}
+
static void
batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
{
if (IS_HASWELL(i915)) {
- bv->max_primitives = 280;
- bv->max_urb_entries = MAX_URB_ENTRIES;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1:
+ bv->max_threads = 70;
+ break;
+ case 2:
+ bv->max_threads = 140;
+ break;
+ case 3:
+ bv->max_threads = 280;
+ break;
+ }
bv->surface_height = 16 * 16;
bv->surface_width = 32 * 2 * 16;
} else {
- bv->max_primitives = 128;
- bv->max_urb_entries = MAX_URB_ENTRIES / 2;
+ switch (INTEL_INFO(i915)->gt) {
+ default:
+ case 1: /* including vlv */
+ bv->max_threads = 36;
+ break;
+ case 2:
+ bv->max_threads = 128;
+ break;
+ }
bv->surface_height = 16 * 8;
bv->surface_width = 32 * 16;
}
- bv->cmd_size = bv->max_primitives * 4096;
- bv->state_size = STATE_SIZE;
- bv->state_start = bv->cmd_size;
- bv->batch_size = bv->cmd_size + bv->state_size;
- bv->scratch_size = bv->surface_height * bv->surface_width;
- bv->max_size = bv->batch_size + bv->scratch_size;
+ bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
+ bv->surface_start = bv->state_start + SZ_4K;
+ bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
}
static void batch_init(struct batch_chunk *bc,
@@ -155,7 +172,8 @@ static u32
gen7_fill_binding_table(struct batch_chunk *state,
const struct batch_vals *bv)
{
- u32 surface_start = gen7_fill_surface_state(state, bv->batch_size, bv);
+ u32 surface_start =
+ gen7_fill_surface_state(state, bv->surface_start, bv);
u32 *cs = batch_alloc_items(state, 32, 8);
u32 offset = batch_offset(state, cs);
@@ -244,8 +262,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
u32 urb_size, u32 curbe_size,
u32 mode)
{
- u32 urb_entries = bv->max_urb_entries;
- u32 threads = bv->max_primitives - 1;
+ u32 threads = bv->max_threads - 1;
u32 *cs = batch_alloc_items(batch, 32, 8);
*cs++ = MEDIA_VFE_STATE | (8 - 2);
@@ -254,7 +271,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
*cs++ = 0;
/* number of threads & urb entries for GPGPU vs Media Mode */
- *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
+ *cs++ = threads << 16 | 1 << 8 | mode << 2;
*cs++ = 0;
@@ -293,17 +310,12 @@ gen7_emit_media_object(struct batch_chunk *batch,
{
unsigned int x_offset = (media_object_index % 16) * 64;
unsigned int y_offset = (media_object_index / 16) * 16;
- unsigned int inline_data_size;
- unsigned int media_batch_size;
- unsigned int i;
+ unsigned int pkt = 6 + 3;
u32 *cs;
- inline_data_size = 112 * 8;
- media_batch_size = inline_data_size + 6;
+ cs = batch_alloc_items(batch, 8, pkt);
- cs = batch_alloc_items(batch, 8, media_batch_size);
-
- *cs++ = MEDIA_OBJECT | (media_batch_size - 2);
+ *cs++ = MEDIA_OBJECT | (pkt - 2);
/* interface descriptor offset */
*cs++ = 0;
@@ -320,8 +332,6 @@ gen7_emit_media_object(struct batch_chunk *batch,
*cs++ = (y_offset << 16) | (x_offset);
*cs++ = 0;
*cs++ = GT3_INLINE_DATA_DELAYS;
- for (i = 3; i < inline_data_size; i++)
- *cs++ = 0;
batch_advance(batch, cs);
}
@@ -350,8 +360,8 @@ static void emit_batch(struct i915_vma * const vma,
u32 interface_descriptor;
unsigned int i;
- batch_init(&cmds, vma, start, 0, bv->cmd_size);
- batch_init(&state, vma, start, bv->state_start, bv->state_size);
+ batch_init(&cmds, vma, start, 0, bv->state_start);
+ batch_init(&state, vma, start, bv->state_start, SZ_4K);
interface_descriptor =
gen7_fill_interface_descriptor(&state, bv,
@@ -359,19 +369,16 @@ static void emit_batch(struct i915_vma * const vma,
&cb_kernel_hsw :
&cb_kernel_ivb,
desc_count);
- gen7_emit_pipeline_flush(&cmds);
batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
- batch_add(&cmds, MI_NOOP);
gen7_emit_state_base_address(&cmds, interface_descriptor);
gen7_emit_pipeline_flush(&cmds);
gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
-
gen7_emit_interface_descriptor_load(&cmds,
interface_descriptor,
desc_count);
- for (i = 0; i < bv->max_primitives; i++)
+ for (i = 0; i < num_primitives(bv); i++)
gen7_emit_media_object(&cmds, i);
batch_add(&cmds, MI_BATCH_BUFFER_END);
@@ -385,15 +392,15 @@ int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine,
batch_get_defaults(engine->i915, &bv);
if (!vma)
- return bv.max_size;
+ return bv.size;
- GEM_BUG_ON(vma->obj->base.size < bv.max_size);
+ GEM_BUG_ON(vma->obj->base.size < bv.size);
batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
if (IS_ERR(batch))
return PTR_ERR(batch);
- emit_batch(vma, memset(batch, 0, bv.max_size), &bv);
+ emit_batch(vma, memset(batch, 0, bv.size), &bv);
i915_gem_object_flush_map(vma->obj);
__i915_gem_object_release_map(vma->obj);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
(?)
@ 2021-01-09 15:49 ` Chris Wilson
2021-01-11 20:48 ` Abodunrin, Akeem G
-1 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The mitigation is required for all gen7 platforms, now that it does not
cause GPU hangs, restore it for Ivybridge and Baytrail.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Bloomfield Jon <jon.bloomfield@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 4ea741f488a8..72d4722441bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1326,7 +1326,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
- if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
+ if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
err = gen7_ctx_switch_bb_init(engine);
if (err)
goto err_ring_unpin;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/3] drm/i915: Allow the user to override security mitigations
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
@ 2021-01-09 15:49 ` Chris Wilson
-1 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:49 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Joonas Lahtinen, Jon Bloomfield, Rodrigo Vivi, stable
The clear-residuals mitigate is a relatively heavy hammer and under some
circumstances the user may wish to forgo the context isolation in order
to meet some performance requirement. Introduce a generic module
parameter to allow selectively enabling/disabling different mitigations.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@vger.kernel.org # v5.7
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 +-
drivers/gpu/drm/i915/i915_mitigations.c | 119 ++++++++++++++++++
drivers/gpu/drm/i915/i915_mitigations.h | 13 ++
4 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.c
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..48f82c354611 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -38,6 +38,7 @@ i915-y += i915_drv.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
+ i915_mitigations.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 72d4722441bf..d529608d4456 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -32,6 +32,7 @@
#include "gen6_ppgtt.h"
#include "gen7_renderclear.h"
#include "i915_drv.h"
+#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -920,7 +921,8 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
if (engine->wa_ctx.vma && ce != engine->kernel_context) {
- if (engine->wa_ctx.vma->private != ce) {
+ if (engine->wa_ctx.vma->private != ce &&
+ i915_mitigate_clear_residuals()) {
ret = clear_residuals(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_mitigations.c b/drivers/gpu/drm/i915/i915_mitigations.c
new file mode 100644
index 000000000000..825af550a11c
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include "i915_mitigations.h"
+
+static unsigned long mitigations = ~0UL;
+
+enum {
+ CLEAR_RESIDUALS = 0,
+};
+
+bool i915_mitigate_clear_residuals(void)
+{
+ return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
+}
+
+static int mitigations_parse(const char *arg)
+{
+ unsigned long new = ~0UL;
+ char *str, *sep, *tok;
+ bool first = true;
+ int err = 0;
+
+ str = kstrdup(arg, GFP_KERNEL);
+ if (!str)
+ return -ENOMEM;
+
+ for (sep = strim(str); (tok = strsep(&sep, ","));) {
+ bool enable = true;
+
+ if (first) {
+ first = false;
+
+ if (!strcmp(tok, "auto")) {
+ new = ~0UL;
+ continue;
+ }
+
+ new = 0;
+ if (!strcmp(tok, "off"))
+ continue;
+ }
+
+ if (*tok == '!') {
+ enable = !enable;
+ tok++;
+ }
+
+ if (!strncmp(tok, "no", 2)) {
+ enable = !enable;
+ tok += 2;
+ }
+
+ if (*tok == '\0')
+ continue;
+
+ if (!strcmp(tok, "residuals")) {
+ if (enable)
+ new |= BIT(CLEAR_RESIDUALS);
+ else
+ new &= ~BIT(CLEAR_RESIDUALS);
+ } else {
+ err = -EINVAL;
+ break;
+ }
+ }
+ kfree(str);
+ if (err)
+ return err;
+
+ WRITE_ONCE(mitigations, new);
+ return 0;
+}
+
+static int mitigations_set(const char *val, const struct kernel_param *kp)
+{
+ int err;
+
+ err = mitigations_parse(val);
+ if (err)
+ return err;
+
+ err = param_set_charp(val, kp);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct kernel_param_ops ops = {
+ .set = mitigations_set,
+ .get = param_get_charp,
+ .free = param_free_charp
+};
+
+static char *param;
+module_param_cb_unsafe(mitigations, &ops, ¶m, 0400);
+MODULE_PARM_DESC(mitigations,
+"Selectively enable security mitigations for all Intel® GPUs.\n"
+"\n"
+" auto -- enables all mitigations required for the platform [default]\n"
+" off -- disables all mitigations\n"
+"\n"
+"Individual mitigations can be enabled by passing a comma-separated string,\n"
+"e.g. mitigations=residuals to enable only clearing residuals or\n"
+"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n"
+"Either '!' or 'no' may be used to switch from enabling the mitigation to\n"
+"disabling it.\n"
+"\n"
+"Active mitigations for Ivybridge, Baytrail, Haswell:\n"
+" residuals -- clear all thread-local registers between contexts"
+);
diff --git a/drivers/gpu/drm/i915/i915_mitigations.h b/drivers/gpu/drm/i915/i915_mitigations.h
new file mode 100644
index 000000000000..1359d8135287
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_MITIGATIONS_H__
+#define __I915_MITIGATIONS_H__
+
+#include <linux/types.h>
+
+bool i915_mitigate_clear_residuals(void);
+
+#endif /* __I915_MITIGATIONS_H__ */
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Allow the user to override security mitigations
@ 2021-01-09 15:49 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:49 UTC (permalink / raw)
To: intel-gfx; +Cc: stable, Chris Wilson
The clear-residuals mitigate is a relatively heavy hammer and under some
circumstances the user may wish to forgo the context isolation in order
to meet some performance requirement. Introduce a generic module
parameter to allow selectively enabling/disabling different mitigations.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@vger.kernel.org # v5.7
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 +-
drivers/gpu/drm/i915/i915_mitigations.c | 119 ++++++++++++++++++
drivers/gpu/drm/i915/i915_mitigations.h | 13 ++
4 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.c
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..48f82c354611 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -38,6 +38,7 @@ i915-y += i915_drv.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
+ i915_mitigations.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 72d4722441bf..d529608d4456 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -32,6 +32,7 @@
#include "gen6_ppgtt.h"
#include "gen7_renderclear.h"
#include "i915_drv.h"
+#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -920,7 +921,8 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
if (engine->wa_ctx.vma && ce != engine->kernel_context) {
- if (engine->wa_ctx.vma->private != ce) {
+ if (engine->wa_ctx.vma->private != ce &&
+ i915_mitigate_clear_residuals()) {
ret = clear_residuals(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_mitigations.c b/drivers/gpu/drm/i915/i915_mitigations.c
new file mode 100644
index 000000000000..825af550a11c
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include "i915_mitigations.h"
+
+static unsigned long mitigations = ~0UL;
+
+enum {
+ CLEAR_RESIDUALS = 0,
+};
+
+bool i915_mitigate_clear_residuals(void)
+{
+ return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
+}
+
+static int mitigations_parse(const char *arg)
+{
+ unsigned long new = ~0UL;
+ char *str, *sep, *tok;
+ bool first = true;
+ int err = 0;
+
+ str = kstrdup(arg, GFP_KERNEL);
+ if (!str)
+ return -ENOMEM;
+
+ for (sep = strim(str); (tok = strsep(&sep, ","));) {
+ bool enable = true;
+
+ if (first) {
+ first = false;
+
+ if (!strcmp(tok, "auto")) {
+ new = ~0UL;
+ continue;
+ }
+
+ new = 0;
+ if (!strcmp(tok, "off"))
+ continue;
+ }
+
+ if (*tok == '!') {
+ enable = !enable;
+ tok++;
+ }
+
+ if (!strncmp(tok, "no", 2)) {
+ enable = !enable;
+ tok += 2;
+ }
+
+ if (*tok == '\0')
+ continue;
+
+ if (!strcmp(tok, "residuals")) {
+ if (enable)
+ new |= BIT(CLEAR_RESIDUALS);
+ else
+ new &= ~BIT(CLEAR_RESIDUALS);
+ } else {
+ err = -EINVAL;
+ break;
+ }
+ }
+ kfree(str);
+ if (err)
+ return err;
+
+ WRITE_ONCE(mitigations, new);
+ return 0;
+}
+
+static int mitigations_set(const char *val, const struct kernel_param *kp)
+{
+ int err;
+
+ err = mitigations_parse(val);
+ if (err)
+ return err;
+
+ err = param_set_charp(val, kp);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct kernel_param_ops ops = {
+ .set = mitigations_set,
+ .get = param_get_charp,
+ .free = param_free_charp
+};
+
+static char *param;
+module_param_cb_unsafe(mitigations, &ops, ¶m, 0400);
+MODULE_PARM_DESC(mitigations,
+"Selectively enable security mitigations for all Intel® GPUs.\n"
+"\n"
+" auto -- enables all mitigations required for the platform [default]\n"
+" off -- disables all mitigations\n"
+"\n"
+"Individual mitigations can be enabled by passing a comma-separated string,\n"
+"e.g. mitigations=residuals to enable only clearing residuals or\n"
+"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n"
+"Either '!' or 'no' may be used to switch from enabling the mitigation to\n"
+"disabling it.\n"
+"\n"
+"Active mitigations for Ivybridge, Baytrail, Haswell:\n"
+" residuals -- clear all thread-local registers between contexts"
+);
diff --git a/drivers/gpu/drm/i915/i915_mitigations.h b/drivers/gpu/drm/i915/i915_mitigations.h
new file mode 100644
index 000000000000..1359d8135287
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_MITIGATIONS_H__
+#define __I915_MITIGATIONS_H__
+
+#include <linux/types.h>
+
+bool i915_mitigate_clear_residuals(void);
+
+#endif /* __I915_MITIGATIONS_H__ */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] drm/i915: Allow the user to override security mitigations
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
@ 2021-01-09 15:59 ` Chris Wilson
-1 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:59 UTC (permalink / raw)
To: intel-gfx
Cc: Chris Wilson, Joonas Lahtinen, Jon Bloomfield, Rodrigo Vivi, stable
The clear-residuals mitigate is a relatively heavy hammer and under some
circumstances the user may wish to forgo the context isolation in order
to meet some performance requirement. Introduce a generic module
parameter to allow selectively enabling/disabling different mitigations.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@vger.kernel.org # v5.7
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 +-
drivers/gpu/drm/i915/i915_mitigations.c | 119 ++++++++++++++++++
drivers/gpu/drm/i915/i915_mitigations.h | 13 ++
4 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.c
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..48f82c354611 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -38,6 +38,7 @@ i915-y += i915_drv.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
+ i915_mitigations.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 72d4722441bf..d529608d4456 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -32,6 +32,7 @@
#include "gen6_ppgtt.h"
#include "gen7_renderclear.h"
#include "i915_drv.h"
+#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -920,7 +921,8 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
if (engine->wa_ctx.vma && ce != engine->kernel_context) {
- if (engine->wa_ctx.vma->private != ce) {
+ if (engine->wa_ctx.vma->private != ce &&
+ i915_mitigate_clear_residuals()) {
ret = clear_residuals(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_mitigations.c b/drivers/gpu/drm/i915/i915_mitigations.c
new file mode 100644
index 000000000000..01ad74721e65
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include "i915_mitigations.h"
+
+static unsigned long mitigations = ~0UL;
+
+enum {
+ CLEAR_RESIDUALS = 0,
+};
+
+bool i915_mitigate_clear_residuals(void)
+{
+ return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
+}
+
+static int mitigations_parse(const char *arg)
+{
+ unsigned long new = ~0UL;
+ char *str, *sep, *tok;
+ bool first = true;
+ int err = 0;
+
+ str = kstrdup(arg, GFP_KERNEL);
+ if (!str)
+ return -ENOMEM;
+
+ for (sep = strim(str); (tok = strsep(&sep, ","));) {
+ bool enable = true;
+
+ if (first) {
+ first = false;
+
+ if (!strcmp(tok, "auto")) {
+ new = ~0UL;
+ continue;
+ }
+
+ new = 0;
+ if (!strcmp(tok, "off"))
+ continue;
+ }
+
+ if (*tok == '!') {
+ enable = !enable;
+ tok++;
+ }
+
+ if (!strncmp(tok, "no", 2)) {
+ enable = !enable;
+ tok += 2;
+ }
+
+ if (*tok == '\0')
+ continue;
+
+ if (!strcmp(tok, "residuals")) {
+ if (enable)
+ new |= BIT(CLEAR_RESIDUALS);
+ else
+ new &= ~BIT(CLEAR_RESIDUALS);
+ } else {
+ err = -EINVAL;
+ break;
+ }
+ }
+ kfree(str);
+ if (err)
+ return err;
+
+ WRITE_ONCE(mitigations, new);
+ return 0;
+}
+
+static int mitigations_set(const char *val, const struct kernel_param *kp)
+{
+ int err;
+
+ err = mitigations_parse(val);
+ if (err)
+ return err;
+
+ err = param_set_charp(val, kp);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct kernel_param_ops ops = {
+ .set = mitigations_set,
+ .get = param_get_charp,
+ .free = param_free_charp
+};
+
+static char *param;
+module_param_cb_unsafe(mitigations, &ops, ¶m, 0600);
+MODULE_PARM_DESC(mitigations,
+"Selectively enable security mitigations for all Intel® GPUs.\n"
+"\n"
+" auto -- enables all mitigations required for the platform [default]\n"
+" off -- disables all mitigations\n"
+"\n"
+"Individual mitigations can be enabled by passing a comma-separated string,\n"
+"e.g. mitigations=residuals to enable only clearing residuals or\n"
+"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n"
+"Either '!' or 'no' may be used to switch from enabling the mitigation to\n"
+"disabling it.\n"
+"\n"
+"Active mitigations for Ivybridge, Baytrail, Haswell:\n"
+" residuals -- clear all thread-local registers between contexts"
+);
diff --git a/drivers/gpu/drm/i915/i915_mitigations.h b/drivers/gpu/drm/i915/i915_mitigations.h
new file mode 100644
index 000000000000..1359d8135287
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_MITIGATIONS_H__
+#define __I915_MITIGATIONS_H__
+
+#include <linux/types.h>
+
+bool i915_mitigate_clear_residuals(void);
+
+#endif /* __I915_MITIGATIONS_H__ */
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Allow the user to override security mitigations
@ 2021-01-09 15:59 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2021-01-09 15:59 UTC (permalink / raw)
To: intel-gfx; +Cc: stable, Chris Wilson
The clear-residuals mitigate is a relatively heavy hammer and under some
circumstances the user may wish to forgo the context isolation in order
to meet some performance requirement. Introduce a generic module
parameter to allow selectively enabling/disabling different mitigations.
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@vger.kernel.org # v5.7
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 4 +-
drivers/gpu/drm/i915/i915_mitigations.c | 119 ++++++++++++++++++
drivers/gpu/drm/i915/i915_mitigations.h | 13 ++
4 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.c
create mode 100644 drivers/gpu/drm/i915/i915_mitigations.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4074d8cb0d6e..48f82c354611 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -38,6 +38,7 @@ i915-y += i915_drv.o \
i915_config.o \
i915_irq.o \
i915_getparam.o \
+ i915_mitigations.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 72d4722441bf..d529608d4456 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -32,6 +32,7 @@
#include "gen6_ppgtt.h"
#include "gen7_renderclear.h"
#include "i915_drv.h"
+#include "i915_mitigations.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
#include "intel_gt.h"
@@ -920,7 +921,8 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
if (engine->wa_ctx.vma && ce != engine->kernel_context) {
- if (engine->wa_ctx.vma->private != ce) {
+ if (engine->wa_ctx.vma->private != ce &&
+ i915_mitigate_clear_residuals()) {
ret = clear_residuals(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_mitigations.c b/drivers/gpu/drm/i915/i915_mitigations.c
new file mode 100644
index 000000000000..01ad74721e65
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include "i915_mitigations.h"
+
+static unsigned long mitigations = ~0UL;
+
+enum {
+ CLEAR_RESIDUALS = 0,
+};
+
+bool i915_mitigate_clear_residuals(void)
+{
+ return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
+}
+
+static int mitigations_parse(const char *arg)
+{
+ unsigned long new = ~0UL;
+ char *str, *sep, *tok;
+ bool first = true;
+ int err = 0;
+
+ str = kstrdup(arg, GFP_KERNEL);
+ if (!str)
+ return -ENOMEM;
+
+ for (sep = strim(str); (tok = strsep(&sep, ","));) {
+ bool enable = true;
+
+ if (first) {
+ first = false;
+
+ if (!strcmp(tok, "auto")) {
+ new = ~0UL;
+ continue;
+ }
+
+ new = 0;
+ if (!strcmp(tok, "off"))
+ continue;
+ }
+
+ if (*tok == '!') {
+ enable = !enable;
+ tok++;
+ }
+
+ if (!strncmp(tok, "no", 2)) {
+ enable = !enable;
+ tok += 2;
+ }
+
+ if (*tok == '\0')
+ continue;
+
+ if (!strcmp(tok, "residuals")) {
+ if (enable)
+ new |= BIT(CLEAR_RESIDUALS);
+ else
+ new &= ~BIT(CLEAR_RESIDUALS);
+ } else {
+ err = -EINVAL;
+ break;
+ }
+ }
+ kfree(str);
+ if (err)
+ return err;
+
+ WRITE_ONCE(mitigations, new);
+ return 0;
+}
+
+static int mitigations_set(const char *val, const struct kernel_param *kp)
+{
+ int err;
+
+ err = mitigations_parse(val);
+ if (err)
+ return err;
+
+ err = param_set_charp(val, kp);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct kernel_param_ops ops = {
+ .set = mitigations_set,
+ .get = param_get_charp,
+ .free = param_free_charp
+};
+
+static char *param;
+module_param_cb_unsafe(mitigations, &ops, ¶m, 0600);
+MODULE_PARM_DESC(mitigations,
+"Selectively enable security mitigations for all Intel® GPUs.\n"
+"\n"
+" auto -- enables all mitigations required for the platform [default]\n"
+" off -- disables all mitigations\n"
+"\n"
+"Individual mitigations can be enabled by passing a comma-separated string,\n"
+"e.g. mitigations=residuals to enable only clearing residuals or\n"
+"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n"
+"Either '!' or 'no' may be used to switch from enabling the mitigation to\n"
+"disabling it.\n"
+"\n"
+"Active mitigations for Ivybridge, Baytrail, Haswell:\n"
+" residuals -- clear all thread-local registers between contexts"
+);
diff --git a/drivers/gpu/drm/i915/i915_mitigations.h b/drivers/gpu/drm/i915/i915_mitigations.h
new file mode 100644
index 000000000000..1359d8135287
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_mitigations.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __I915_MITIGATIONS_H__
+#define __I915_MITIGATIONS_H__
+
+#include <linux/types.h>
+
+bool i915_mitigate_clear_residuals(void);
+
+#endif /* __I915_MITIGATIONS_H__ */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
` (2 preceding siblings ...)
(?)
@ 2021-01-09 16:05 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-01-09 16:05 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT
URL : https://patchwork.freedesktop.org/series/85653/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
729eccddb489 drm/i915/gt: Limit VFE threads based on GT
933b2c1db98b drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
e76144518cf5 drm/i915: Allow the user to override security mitigations
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#53:
new file mode 100644
-:163: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#163: FILE: drivers/gpu/drm/i915/i915_mitigations.c:106:
+MODULE_PARM_DESC(mitigations,
+"Selectively enable security mitigations for all Intel® GPUs.\n"
total: 0 errors, 1 warnings, 1 checks, 155 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
` (3 preceding siblings ...)
(?)
@ 2021-01-09 16:36 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-01-09 16:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5508 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT
URL : https://patchwork.freedesktop.org/series/85653/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9571 -> Patchwork_19306
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19306 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19306, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19306:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-byt-j1900: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hangcheck:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-bxt-dsi/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-bxt-dsi/igt@i915_selftest@live@hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_19306 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][7] -> [DMESG-FAIL][8] ([i915#165])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-j1900: [PASS][9] -> [FAIL][10] ([i915#49])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-byt-j1900/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-byt-j1900/igt@kms_frontbuffer_tracking@basic.html
* igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][11] ([i915#2426])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-bxt-dsi/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_parallel@engines@contexts:
- fi-tgl-y: [FAIL][12] ([i915#2780]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-tgl-y/igt@gem_exec_parallel@engines@contexts.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-tgl-y/igt@gem_exec_parallel@engines@contexts.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][14] ([i915#2411] / [i915#402]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@gem_tiled_pread_basic:
- fi-tgl-y: [DMESG-WARN][16] ([i915#402]) -> [PASS][17] +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9571/fi-tgl-y/igt@gem_tiled_pread_basic.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/fi-tgl-y/igt@gem_tiled_pread_basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2780]: https://gitlab.freedesktop.org/drm/intel/issues/2780
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
Participating hosts (43 -> 38)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9571 -> Patchwork_19306
CI-20190529: 20190529
CI_DRM_9571: 707b4c70cf8fda42dedf74612233208661f287d8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5953: 65c5eea699141e6f942ce0a8fc85db76ce53cd19 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19306: e76144518cf52af910a37d900e69cd99c2f9a2b1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e76144518cf5 drm/i915: Allow the user to override security mitigations
933b2c1db98b drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
729eccddb489 drm/i915/gt: Limit VFE threads based on GT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19306/index.html
[-- Attachment #1.2: Type: text/html, Size: 6445 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT (rev2)
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
` (4 preceding siblings ...)
(?)
@ 2021-01-09 17:19 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-01-09 17:19 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT (rev2)
URL : https://patchwork.freedesktop.org/series/85653/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f681682ed1e0 drm/i915/gt: Limit VFE threads based on GT
372aab8a2085 drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
9a6a61f41d50 drm/i915: Allow the user to override security mitigations
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#53:
new file mode 100644
-:163: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#163: FILE: drivers/gpu/drm/i915/i915_mitigations.c:106:
+MODULE_PARM_DESC(mitigations,
+"Selectively enable security mitigations for all Intel® GPUs.\n"
total: 0 errors, 1 warnings, 1 checks, 155 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT (rev2)
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
` (5 preceding siblings ...)
(?)
@ 2021-01-09 17:50 ` Patchwork
-1 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2021-01-09 17:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5153 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT (rev2)
URL : https://patchwork.freedesktop.org/series/85653/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9572 -> Patchwork_19307
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19307 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19307, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19307:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-byt-j1900: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-byt-j1900/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hugepages:
- fi-bsw-n3050: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-bsw-n3050/igt@i915_selftest@live@hugepages.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-bsw-n3050/igt@i915_selftest@live@hugepages.html
Known issues
------------
Here are the changes found in Patchwork_19307 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-tgl-y: NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +6 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-tgl-y/igt@amdgpu/amd_basic@cs-compute.html
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-tgl-y/igt@gem_mmap_gtt@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-tgl-y/igt@gem_mmap_gtt@basic.html
* igt@i915_selftest@live@reset:
- fi-bsw-n3050: [PASS][8] -> [SKIP][9] ([fdo#109271]) +10 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-bsw-n3050/igt@i915_selftest@live@reset.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-bsw-n3050/igt@i915_selftest@live@reset.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][10] ([i915#1436])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][11] ([i915#2411] / [i915#402]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@gem_sync@basic-all:
- fi-bsw-kefka: [DMESG-WARN][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-bsw-kefka/igt@gem_sync@basic-all.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-bsw-kefka/igt@gem_sync@basic-all.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9572/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9572 -> Patchwork_19307
CI-20190529: 20190529
CI_DRM_9572: 0c76c385e473fb20cd257e43a123cdf3877199b7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5953: 65c5eea699141e6f942ce0a8fc85db76ce53cd19 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19307: 9a6a61f41d5020c5963c13fa45cca357271c2d04 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9a6a61f41d50 drm/i915: Allow the user to override security mitigations
372aab8a2085 drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
f681682ed1e0 drm/i915/gt: Limit VFE threads based on GT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19307/index.html
[-- Attachment #1.2: Type: text/html, Size: 6142 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
@ 2021-01-11 20:25 ` Abodunrin, Akeem G
-1 siblings, 0 replies; 16+ messages in thread
From: Abodunrin, Akeem G @ 2021-01-11 20:25 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Cc: Mika Kuoppala, Kumar Valsan, Prathap, Bloomfield, Jon, Vivi,
Rodrigo, Randy Wright, stable
> -----Original Message-----
> From: Chris Wilson <chris@chris-wilson.co.uk>
> Sent: Saturday, January 09, 2021 7:49 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson <chris@chris-wilson.co.uk>; Mika Kuoppala
> <mika.kuoppala@linux.intel.com>; Kumar Valsan, Prathap
> <prathap.kumar.valsan@intel.com>; Abodunrin, Akeem G
> <akeem.g.abodunrin@intel.com>; Bloomfield, Jon
> <jon.bloomfield@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Randy
> Wright <rwright@hpe.com>; stable@vger.kernel.org
> Subject: [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
>
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately limit the
> number of threads we spawn to match the device.
>
> v2: Oversaturate the system with tasks to force execution on every HW
> thread; if the thread idles it is returned to the pool and may be reused again
> before an unused thread.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Jon Bloomfield <jon.bloomfield@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Randy Wright <rwright@hpe.com>
> Cc: stable@vger.kernel.org # v5.7+
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 91 ++++++++++++----------
> 1 file changed, 49 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index d93d85cd3027..3ea7c9cc0f3d 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -7,8 +7,6 @@
> #include "i915_drv.h"
> #include "intel_gpu_commands.h"
>
> -#define MAX_URB_ENTRIES 64
> -#define STATE_SIZE (4 * 1024)
> #define GT3_INLINE_DATA_DELAYS 0x1E00
> #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
>
> @@ -34,38 +32,57 @@ struct batch_chunk { };
>
> struct batch_vals {
> - u32 max_primitives;
> - u32 max_urb_entries;
> - u32 cmd_size;
> - u32 state_size;
> + u32 max_threads;
> u32 state_start;
> - u32 batch_size;
> + u32 surface_start;
> u32 surface_height;
> u32 surface_width;
> - u32 scratch_size;
> - u32 max_size;
> + u32 size;
> };
>
> +static inline int num_primitives(const struct batch_vals *bv) {
> + /*
> + * We need to oversaturate the GPU with work in order to dispatch
> + * a shader on every HW thread.
> + */
> + return bv->max_threads + 2;
> +}
> +
> static void
> batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) {
> if (IS_HASWELL(i915)) {
> - bv->max_primitives = 280;
> - bv->max_urb_entries = MAX_URB_ENTRIES;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1:
> + bv->max_threads = 70;
> + break;
> + case 2:
> + bv->max_threads = 140;
> + break;
> + case 3:
> + bv->max_threads = 280;
> + break;
> + }
> bv->surface_height = 16 * 16;
> bv->surface_width = 32 * 2 * 16;
> } else {
> - bv->max_primitives = 128;
> - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1: /* including vlv */
> + bv->max_threads = 36;
> + break;
> + case 2:
> + bv->max_threads = 128;
> + break;
> + }
Do we really need to hardcode max number of threads per gt/platform? Why not calculating the number of active threads from the no_of_slices * 1024? - Also, is "64" not the minimum number of threads supported?
Thanks,
~Akeem
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
@ 2021-01-11 20:25 ` Abodunrin, Akeem G
0 siblings, 0 replies; 16+ messages in thread
From: Abodunrin, Akeem G @ 2021-01-11 20:25 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: stable, Randy Wright
> -----Original Message-----
> From: Chris Wilson <chris@chris-wilson.co.uk>
> Sent: Saturday, January 09, 2021 7:49 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson <chris@chris-wilson.co.uk>; Mika Kuoppala
> <mika.kuoppala@linux.intel.com>; Kumar Valsan, Prathap
> <prathap.kumar.valsan@intel.com>; Abodunrin, Akeem G
> <akeem.g.abodunrin@intel.com>; Bloomfield, Jon
> <jon.bloomfield@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Randy
> Wright <rwright@hpe.com>; stable@vger.kernel.org
> Subject: [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
>
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately limit the
> number of threads we spawn to match the device.
>
> v2: Oversaturate the system with tasks to force execution on every HW
> thread; if the thread idles it is returned to the pool and may be reused again
> before an unused thread.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Jon Bloomfield <jon.bloomfield@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Randy Wright <rwright@hpe.com>
> Cc: stable@vger.kernel.org # v5.7+
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 91 ++++++++++++----------
> 1 file changed, 49 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index d93d85cd3027..3ea7c9cc0f3d 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -7,8 +7,6 @@
> #include "i915_drv.h"
> #include "intel_gpu_commands.h"
>
> -#define MAX_URB_ENTRIES 64
> -#define STATE_SIZE (4 * 1024)
> #define GT3_INLINE_DATA_DELAYS 0x1E00
> #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
>
> @@ -34,38 +32,57 @@ struct batch_chunk { };
>
> struct batch_vals {
> - u32 max_primitives;
> - u32 max_urb_entries;
> - u32 cmd_size;
> - u32 state_size;
> + u32 max_threads;
> u32 state_start;
> - u32 batch_size;
> + u32 surface_start;
> u32 surface_height;
> u32 surface_width;
> - u32 scratch_size;
> - u32 max_size;
> + u32 size;
> };
>
> +static inline int num_primitives(const struct batch_vals *bv) {
> + /*
> + * We need to oversaturate the GPU with work in order to dispatch
> + * a shader on every HW thread.
> + */
> + return bv->max_threads + 2;
> +}
> +
> static void
> batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) {
> if (IS_HASWELL(i915)) {
> - bv->max_primitives = 280;
> - bv->max_urb_entries = MAX_URB_ENTRIES;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1:
> + bv->max_threads = 70;
> + break;
> + case 2:
> + bv->max_threads = 140;
> + break;
> + case 3:
> + bv->max_threads = 280;
> + break;
> + }
> bv->surface_height = 16 * 16;
> bv->surface_width = 32 * 2 * 16;
> } else {
> - bv->max_primitives = 128;
> - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1: /* including vlv */
> + bv->max_threads = 36;
> + break;
> + case 2:
> + bv->max_threads = 128;
> + break;
> + }
Do we really need to hardcode max number of threads per gt/platform? Why not calculating the number of active threads from the no_of_slices * 1024? - Also, is "64" not the minimum number of threads supported?
Thanks,
~Akeem
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
2021-01-09 15:49 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail Chris Wilson
@ 2021-01-11 20:48 ` Abodunrin, Akeem G
0 siblings, 0 replies; 16+ messages in thread
From: Abodunrin, Akeem G @ 2021-01-11 20:48 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
> -----Original Message-----
> From: Chris Wilson <chris@chris-wilson.co.uk>
> Sent: Saturday, January 09, 2021 7:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson <chris@chris-wilson.co.uk>; Mika Kuoppala
> <mika.kuoppala@linux.intel.com>; Kumar Valsan, Prathap
> <prathap.kumar.valsan@intel.com>; Abodunrin, Akeem G
> <akeem.g.abodunrin@intel.com>; Bloomfield, Jon
> <jon.bloomfield@intel.com>
> Subject: [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for
> Ivybridge, Baytrail
>
> The mitigation is required for all gen7 platforms, now that it does not cause
> GPU hangs, restore it for Ivybridge and Baytrail.
>
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Cc: Bloomfield Jon <jon.bloomfield@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 4ea741f488a8..72d4722441bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1326,7 +1326,7 @@ int intel_ring_submission_setup(struct
> intel_engine_cs *engine)
>
> GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
>
> - if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
> + if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
> err = gen7_ctx_switch_bb_init(engine);
> if (err)
> goto err_ring_unpin;
> --
> 2.20.1
I tried hard to remember why checking for HSW platform specifically in this case, since mitigation is applicable to all gen 7 (including 7.5) platforms - but couldn't recall why, and see no reason in the code doing it that way - so the changes make sense...
Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
2021-01-11 20:25 ` [Intel-gfx] " Abodunrin, Akeem G
(?)
@ 2021-01-11 21:02 ` Chris Wilson
2021-01-11 21:10 ` Abodunrin, Akeem G
-1 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2021-01-11 21:02 UTC (permalink / raw)
To: Abodunrin, Akeem G, intel-gfx; +Cc: Randy Wright, stable
Quoting Abodunrin, Akeem G (2021-01-11 20:25:34)
> > static void
> > batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv) {
> > if (IS_HASWELL(i915)) {
> > - bv->max_primitives = 280;
> > - bv->max_urb_entries = MAX_URB_ENTRIES;
> > + switch (INTEL_INFO(i915)->gt) {
> > + default:
> > + case 1:
> > + bv->max_threads = 70;
> > + break;
> > + case 2:
> > + bv->max_threads = 140;
> > + break;
> > + case 3:
> > + bv->max_threads = 280;
> > + break;
> > + }
> > bv->surface_height = 16 * 16;
> > bv->surface_width = 32 * 2 * 16;
> > } else {
> > - bv->max_primitives = 128;
> > - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> > + switch (INTEL_INFO(i915)->gt) {
> > + default:
> > + case 1: /* including vlv */
> > + bv->max_threads = 36;
> > + break;
> > + case 2:
> > + bv->max_threads = 128;
> > + break;
> > + }
> Do we really need to hardcode max number of threads per gt/platform? Why not calculating the number of active threads from the no_of_slices * 1024? - Also, is "64" not the minimum number of threads supported?
ivb,byt,hsw each has different numbers of threads per subslice, and each
gt has a different number of subslice/slice (and not a simple doubling
of subslice/slice from 1 -> 2 -> 3, although the total is!).
It's a choice between encoding a tuple for (num_threads, num_subslices,
num_slices) or the combined value.
The goal is to run a shader in each HW thread to clear the thread-local
registers, and only one shader in each.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT
2021-01-11 21:02 ` Chris Wilson
@ 2021-01-11 21:10 ` Abodunrin, Akeem G
0 siblings, 0 replies; 16+ messages in thread
From: Abodunrin, Akeem G @ 2021-01-11 21:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: stable@, Randy Wright
> -----Original Message-----
> From: Chris Wilson <chris@chris-wilson.co.uk>
> Sent: Monday, January 11, 2021 1:03 PM
> To: Abodunrin, Akeem G <akeem.g.abodunrin@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: stable@ <vger.kernel.org stable@vger.kernel.org>; Randy Wright
> <rwright@hpe.com>
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on
> GT
>
> Quoting Abodunrin, Akeem G (2021-01-11 20:25:34)
> > > static void
> > > batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> {
> > > if (IS_HASWELL(i915)) {
> > > - bv->max_primitives = 280;
> > > - bv->max_urb_entries = MAX_URB_ENTRIES;
> > > + switch (INTEL_INFO(i915)->gt) {
> > > + default:
> > > + case 1:
> > > + bv->max_threads = 70;
> > > + break;
> > > + case 2:
> > > + bv->max_threads = 140;
> > > + break;
> > > + case 3:
> > > + bv->max_threads = 280;
> > > + break;
> > > + }
> > > bv->surface_height = 16 * 16;
> > > bv->surface_width = 32 * 2 * 16;
> > > } else {
> > > - bv->max_primitives = 128;
> > > - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> > > + switch (INTEL_INFO(i915)->gt) {
> > > + default:
> > > + case 1: /* including vlv */
> > > + bv->max_threads = 36;
> > > + break;
> > > + case 2:
> > > + bv->max_threads = 128;
> > > + break;
> > > + }
> > Do we really need to hardcode max number of threads per gt/platform?
> Why not calculating the number of active threads from the no_of_slices *
> 1024? - Also, is "64" not the minimum number of threads supported?
>
> ivb,byt,hsw each has different numbers of threads per subslice, and each gt
> has a different number of subslice/slice (and not a simple doubling of
> subslice/slice from 1 -> 2 -> 3, although the total is!).
>
> It's a choice between encoding a tuple for (num_threads, num_subslices,
> num_slices) or the combined value.
>
> The goal is to run a shader in each HW thread to clear the thread-local
> registers, and only one shader in each.
> -Chris
Okay, let's go with simplified solution to achieve our goal here, instead of complex calculation...
Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-01-11 21:10 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-09 15:49 [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT Chris Wilson
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
2021-01-09 15:49 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail Chris Wilson
2021-01-11 20:48 ` Abodunrin, Akeem G
2021-01-09 15:49 ` [PATCH 3/3] drm/i915: Allow the user to override security mitigations Chris Wilson
2021-01-09 15:49 ` [Intel-gfx] " Chris Wilson
2021-01-09 15:59 ` [PATCH] " Chris Wilson
2021-01-09 15:59 ` [Intel-gfx] " Chris Wilson
2021-01-09 16:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT Patchwork
2021-01-09 16:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-09 17:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gt: Limit VFE threads based on GT (rev2) Patchwork
2021-01-09 17:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-11 20:25 ` [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT Abodunrin, Akeem G
2021-01-11 20:25 ` [Intel-gfx] " Abodunrin, Akeem G
2021-01-11 21:02 ` Chris Wilson
2021-01-11 21:10 ` Abodunrin, Akeem G
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