[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/41] drm/i915/selftests: Check for engine-reset errors in the middle of workarounds

[Patchwork <patchwork@emeril.freedesktop.org>]

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== Series Details ==

Series: series starting with [01/41] drm/i915/selftests: Check for engine-reset errors in the middle of workarounds
URL   : https://patchwork.freedesktop.org/series/86259/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9680 -> Patchwork_19487
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19487/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_19487:

### IGT changes ###

#### Possible regressions ####

  * {igt@i915_selftest@live@scheduler} (NEW):
    - fi-snb-2520m:       NOTRUN -> [DMESG-FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19487/fi-snb-2520m/igt@i915_selftest@live@scheduler.html
    - fi-snb-2600:        NOTRUN -> [DMESG-FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19487/fi-snb-2600/igt@i915_selftest@live@scheduler.html

  
New tests
---------

  New tests have been introduced between CI_DRM_9680 and Patchwork_19487:

### New IGT tests (1) ###

  * igt@i915_selftest@live@scheduler:
    - Statuses : 2 dmesg-fail(s) 29 pass(s)
    - Exec time: [0.72, 8.80] s

  

Known issues
------------

  Here are the changes found in Patchwork_19487 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@prime_vgem@basic-gtt:
    - fi-tgl-y:           [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/fi-tgl-y/igt@prime_vgem@basic-gtt.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19487/fi-tgl-y/igt@prime_vgem@basic-gtt.html

  
#### Possible fixes ####

  * igt@prime_vgem@basic-fence-flip:
    - fi-tgl-y:           [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9680/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19487/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (39 -> 35)
------------------------------

  Missing    (4): fi-ctg-p8600 fi-jsl-1 fi-ilk-m540 fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_9680 -> Patchwork_19487

  CI-20190529: 20190529
  CI_DRM_9680: 9e03236ed9687144929d42404341384cc1e501b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5971: abef2b7d6ff30f3b948b3e5d39653debb73083f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19487: ac942d24c88f5e0b7247d62f73b254f29a02145c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ac942d24c88f drm/i915: Support secure dispatch on gen6/gen7
4743bbd27620 drm/i915/gt: Enable ring scheduling for gen5-7
bf0a549d2293 drm/i915/gt: Implement ring scheduler for gen4-7
a07f5ba0a10d drm/i915/gt: Infrastructure for ring scheduling
0337feb5791a drm/i915/gt: Use client timeline address for seqno writes
209430537935 drm/i915/gt: Support creation of 'internal' rings
593e08f61ffd drm/i915/gt: Couple tasklet scheduling for all CS interrupts
cf05a88e82c0 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"
913207bf89cd drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines
b9b643d59b9d drm/i915/selftests: Exercise relative timeline modes
0a3936960afc drm/i915/gt: Use indices for writing into relative timelines
9bb8f60faea0 drm/i915/gt: Add timeline "mode"
fc7e917f62a1 drm/i915/gt: Track timeline GGTT offset separately from subpage offset
1edd11623282 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb
75ecbfad42e2 drm/i915: Bump default timeslicing quantum to 5ms
4e61621ac116 drm/i915: Move saturated workload detection back to the context
e4a776414370 drm/i915/gt: Support virtual engine queues
010d86d0ecb1 drm/i915: Extend the priority boosting for the display with a deadline
f93f85ad482a drm/i915/gt: Specify a deadline for the heartbeat
4cabd30226f5 drm/i915: Fair low-latency scheduling
48a6729c987b drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper
4abff63c4cfe drm/i915: Replace priolist rbtree with a skiplist
3839efb97bae drm/i915/gt: Show scheduler queues when dumping state
3744cfde0c1b drm/i915: Move tasklet from execlists to sched
0597492c1e44 drm/i915: Move scheduler queue
4ab371f1d39d drm/i915: Move common active lists from engine to i915_scheduler
d6eb9d01bae2 drm/i915: Fix the iterative dfs for defering requests
bf3ba20370f6 drm/i915: Extract the ability to defer and rerun a request later
f04573d14fc7 drm/i915: Extract request suspension from the execlists
db49df2e5ac7 drm/i915: Extract request rewinding from execlists
1dac44d403d7 drm/i915: Extract request submission from execlists
f6b8b7362118 drm/i915/selftests: Exercise cross-process context isolation
ddf444ae329e drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
9b002fc62d1f drm/i915: Improve DFS for priority inheritance
22c3f3836779 drm/i915/selftests: Exercise priority inheritance around an engine loop
f1443908248f drm/i915/selftests: Measure set-priority duration
7b140da51266 drm/i915: Restructure priority inheritance
b5ca2c04b198 drm/i915: Teach the i915_dependency to use a double-lock
0611644e4ddf drm/i915: Replace engine->schedule() with a known request operation
367f5e603c5d drm/i915/gt: Move the defer_request waiter active assertion
e4e577627c26 drm/i915/selftests: Check for engine-reset errors in the middle of workarounds

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19487/index.html

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