* [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count
@ 2021-02-05 9:07 Ramalingam C
2021-02-05 9:53 ` Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Ramalingam C @ 2021-02-05 9:07 UTC (permalink / raw)
To: igt-dev; +Cc: Chris wilson
Calculate obj size for the sanity check of module reload
based on the engines count.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
CC: Chris wilson <chris.p.wilson@intel.com>
---
tests/i915/i915_module_load.c | 37 +++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 06522ba6191b..00494bcb3480 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -46,7 +46,7 @@ static void store_all(int fd)
struct drm_i915_gem_relocation_entry reloc[2 * ARRAY_SIZE(engines)];
struct drm_i915_gem_execbuffer2 execbuf;
const struct intel_execution_engine2 *e;
- uint32_t batch[16];
+ uint32_t batch[16], obj_size;
uint64_t offset;
unsigned nengine;
int value;
@@ -56,10 +56,19 @@ static void store_all(int fd)
execbuf.buffers_ptr = (uintptr_t)obj;
execbuf.buffer_count = 2;
+ nengine = 0;
+ __for_each_physical_engine(fd, e) {
+ if (!gem_class_can_store_dword(fd, e->class))
+ continue;
+ nengine++;
+ }
+
+ obj_size = 2 * (nengine + 1) *sizeof(batch);
+
memset(reloc, 0, sizeof(reloc));
memset(obj, 0, sizeof(obj));
- obj[0].handle = gem_create(fd, 4096);
- obj[1].handle = gem_create(fd, 4096);
+ obj[0].handle = gem_create(fd, obj_size);
+ obj[1].handle = gem_create(fd, obj_size);
obj[1].relocation_count = 1;
offset = sizeof(uint32_t);
@@ -79,24 +88,22 @@ static void store_all(int fd)
batch[value = ++i] = 0xc0ffee;
batch[++i] = MI_BATCH_BUFFER_END;
- nengine = 0;
+ i = 0;
intel_detect_and_clear_missed_interrupts(fd);
__for_each_physical_engine(fd, e) {
if (!gem_class_can_store_dword(fd, e->class))
continue;
- igt_assert(2 * (nengine + 1) * sizeof(batch) <= 4096);
-
- engines[nengine] = e->flags;
+ engines[i] = e->flags;
if (gen < 6)
- engines[nengine] |= I915_EXEC_SECURE;
- execbuf.flags = engines[nengine];
+ engines[i] |= I915_EXEC_SECURE;
+ execbuf.flags = engines[i];
- j = 2*nengine;
+ j = 2*i;
reloc[j].target_handle = obj[0].handle;
reloc[j].presumed_offset = ~0;
reloc[j].offset = j*sizeof(batch) + offset;
- reloc[j].delta = nengine*sizeof(uint32_t);
+ reloc[j].delta = i*sizeof(uint32_t);
reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
obj[1].relocs_ptr = (uintptr_t)&reloc[j];
@@ -107,22 +114,22 @@ static void store_all(int fd)
execbuf.batch_start_offset = j*sizeof(batch);
gem_execbuf(fd, &execbuf);
- j = 2*nengine + 1;
+ j = 2*i + 1;
reloc[j].target_handle = obj[0].handle;
reloc[j].presumed_offset = ~0;
reloc[j].offset = j*sizeof(batch) + offset;
- reloc[j].delta = nengine*sizeof(uint32_t);
+ reloc[j].delta = i*sizeof(uint32_t);
reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
obj[1].relocs_ptr = (uintptr_t)&reloc[j];
- batch[value] = nengine;
+ batch[value] = i;
gem_write(fd, obj[1].handle, j*sizeof(batch),
batch, sizeof(batch));
execbuf.batch_start_offset = j*sizeof(batch);
gem_execbuf(fd, &execbuf);
- nengine++;
+ i++;
}
gem_sync(fd, obj[1].handle);
--
2.20.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count 2021-02-05 9:07 [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count Ramalingam C @ 2021-02-05 9:53 ` Chris Wilson 2021-02-05 10:06 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Chris Wilson @ 2021-02-05 9:53 UTC (permalink / raw) To: Ramalingam C, igt-dev Quoting Ramalingam C (2021-02-05 09:07:43) > Calculate obj size for the sanity check of module reload > based on the engines count. > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > CC: Chris wilson <chris.p.wilson@intel.com> Oh dear, I've seen a few more things that got lost in translation. > --- > tests/i915/i915_module_load.c | 37 +++++++++++++++++++++-------------- > 1 file changed, 22 insertions(+), 15 deletions(-) > > diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c > index 06522ba6191b..00494bcb3480 100644 > --- a/tests/i915/i915_module_load.c > +++ b/tests/i915/i915_module_load.c > @@ -46,7 +46,7 @@ static void store_all(int fd) > struct drm_i915_gem_relocation_entry reloc[2 * ARRAY_SIZE(engines)]; > struct drm_i915_gem_execbuffer2 execbuf; > const struct intel_execution_engine2 *e; > - uint32_t batch[16]; > + uint32_t batch[16], obj_size; > uint64_t offset; > unsigned nengine; > int value; > @@ -56,10 +56,19 @@ static void store_all(int fd) > execbuf.buffers_ptr = (uintptr_t)obj; > execbuf.buffer_count = 2; > > + nengine = 0; > + __for_each_physical_engine(fd, e) { > + if (!gem_class_can_store_dword(fd, e->class)) > + continue; > + nengine++; > + } > + > + obj_size = 2 * (nengine + 1) *sizeof(batch); > + > memset(reloc, 0, sizeof(reloc)); > memset(obj, 0, sizeof(obj)); > - obj[0].handle = gem_create(fd, 4096); > - obj[1].handle = gem_create(fd, 4096); > + obj[0].handle = gem_create(fd, obj_size); obj[0] needs only 4 * nengine obj[1] indeed needs batch_size * nengine; > + obj[1].handle = gem_create(fd, obj_size); > obj[1].relocation_count = 1; > > offset = sizeof(uint32_t); > @@ -79,24 +88,22 @@ static void store_all(int fd) > batch[value = ++i] = 0xc0ffee; > batch[++i] = MI_BATCH_BUFFER_END; > > - nengine = 0; > + i = 0; > intel_detect_and_clear_missed_interrupts(fd); > __for_each_physical_engine(fd, e) { > if (!gem_class_can_store_dword(fd, e->class)) > continue; > > - igt_assert(2 * (nengine + 1) * sizeof(batch) <= 4096); > - > - engines[nengine] = e->flags; > + engines[i] = e->flags; > if (gen < 6) > - engines[nengine] |= I915_EXEC_SECURE; > - execbuf.flags = engines[nengine]; > + engines[i] |= I915_EXEC_SECURE; > + execbuf.flags = engines[i]; > > - j = 2*nengine; > + j = 2*i; > reloc[j].target_handle = obj[0].handle; > reloc[j].presumed_offset = ~0; > reloc[j].offset = j*sizeof(batch) + offset; > - reloc[j].delta = nengine*sizeof(uint32_t); > + reloc[j].delta = i*sizeof(uint32_t); > reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; > reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; This should be (RENDER, RENDER) INSTRUCTION, INSTRUCTION is special setting for a gen6 pipecontrol w/a We don't want to confuse things for a basic liveness check. > obj[1].relocs_ptr = (uintptr_t)&reloc[j]; > @@ -107,22 +114,22 @@ static void store_all(int fd) > execbuf.batch_start_offset = j*sizeof(batch); > gem_execbuf(fd, &execbuf); > > - j = 2*nengine + 1; > + j = 2*i + 1; > reloc[j].target_handle = obj[0].handle; > reloc[j].presumed_offset = ~0; > reloc[j].offset = j*sizeof(batch) + offset; > - reloc[j].delta = nengine*sizeof(uint32_t); > + reloc[j].delta = i*sizeof(uint32_t); > reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; > reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; > obj[1].relocs_ptr = (uintptr_t)&reloc[j]; And we only need one batch, halving the amount of work we have to do. > > - batch[value] = nengine; > + batch[value] = i; Just set the first batch to emit batch[value] = i -Chris _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for tests/i915_module_load: obj size based on the engine count 2021-02-05 9:07 [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count Ramalingam C 2021-02-05 9:53 ` Chris Wilson @ 2021-02-05 10:06 ` Patchwork 2021-02-05 10:10 ` [igt-dev] " Chris Wilson ` (2 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-02-05 10:06 UTC (permalink / raw) To: Ramalingam C; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 3551 bytes --] == Series Details == Series: tests/i915_module_load: obj size based on the engine count URL : https://patchwork.freedesktop.org/series/86748/ State : success == Summary == CI Bug Log - changes from CI_DRM_9736 -> IGTPW_5484 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/index.html Known issues ------------ Here are the changes found in IGTPW_5484 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html * igt@gem_linear_blits@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/fi-tgl-y/igt@gem_linear_blits@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/fi-tgl-y/igt@gem_linear_blits@basic.html * igt@i915_pm_rpm@module-reload: - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([i915#2605]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/fi-kbl-7500u/igt@i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/fi-kbl-7500u/igt@i915_pm_rpm@module-reload.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([i915#1372]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html #### Possible fixes #### * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][9] ([i915#1982] / [i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/fi-tgl-y/igt@debugfs_test@read_all_entries.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) ------------------------------ Missing (5): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-dg1-1 fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5992 -> IGTPW_5484 CI-20190529: 20190529 CI_DRM_9736: 361561fb8050ccab1b4527c781f3e18595e545a0 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5484: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/index.html IGT_5992: b781a32b06a0173a71b4e1ac30d18dd7164a67c4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/index.html [-- Attachment #1.2: Type: text/html, Size: 4421 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH i-g-t] i915/module_load: Tidy up gem_exec_store workalike 2021-02-05 9:07 [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count Ramalingam C @ 2021-02-05 10:10 ` Chris Wilson 2021-02-05 10:06 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Chris Wilson @ 2021-02-05 10:10 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev, Chris Wilson We emit a store on each GPU after loading the module to confirm the basic liveness of command submission. Trim away some of the chaff. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ramalingam C <ramalingam.c@intel.com> --- tests/i915/i915_module_load.c | 146 ++++++++++++++-------------------- 1 file changed, 58 insertions(+), 88 deletions(-) diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c index 06522ba61..f1fb13914 100644 --- a/tests/i915/i915_module_load.c +++ b/tests/i915/i915_module_load.c @@ -37,41 +37,45 @@ #include "igt_sysfs.h" #include "igt_core.h" -static void store_all(int fd) +static void store_all(int i915) { - const unsigned int gen = intel_gen(intel_get_drm_devid(fd)); - unsigned int permuted[I915_EXEC_RING_MASK + 1]; - unsigned int engines[I915_EXEC_RING_MASK + 1]; - struct drm_i915_gem_exec_object2 obj[2]; - struct drm_i915_gem_relocation_entry reloc[2 * ARRAY_SIZE(engines)]; - struct drm_i915_gem_execbuffer2 execbuf; - const struct intel_execution_engine2 *e; + const unsigned int gen = intel_gen(intel_get_drm_devid(i915)); + uint32_t engines[I915_EXEC_RING_MASK + 1]; uint32_t batch[16]; - uint64_t offset; - unsigned nengine; - int value; - int i, j; - - memset(&execbuf, 0, sizeof(execbuf)); - execbuf.buffers_ptr = (uintptr_t)obj; - execbuf.buffer_count = 2; - - memset(reloc, 0, sizeof(reloc)); - memset(obj, 0, sizeof(obj)); - obj[0].handle = gem_create(fd, 4096); - obj[1].handle = gem_create(fd, 4096); - obj[1].relocation_count = 1; - - offset = sizeof(uint32_t); + unsigned int sz = ALIGN(sizeof(batch) * ARRAY_SIZE(engines), 4096); + struct drm_i915_gem_relocation_entry reloc = { + .offset = sizeof(uint32_t), + .read_domains = I915_GEM_DOMAIN_RENDER, + .write_domain = I915_GEM_DOMAIN_RENDER, + }; + struct drm_i915_gem_exec_object2 obj[2] = { + { .handle = gem_create(i915, sizeof(engines)) }, + { + .handle = gem_create(i915, sz), + .relocation_count = 1, + .relocs_ptr = to_user_pointer(&reloc), + }, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(obj), + .buffer_count = 2, + }; + const struct intel_execution_engine2 *e; + int reloc_sz = sizeof(uint32_t); + unsigned int nengine, value; + void *cs; + int i; + i = 0; batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); if (gen >= 8) { batch[++i] = 0; batch[++i] = 0; + reloc_sz = sizeof(uint64_t); } else if (gen >= 4) { batch[++i] = 0; batch[++i] = 0; - offset += sizeof(uint32_t); + reloc.offset += sizeof(uint32_t); } else { batch[i]--; batch[++i] = 0; @@ -80,74 +84,43 @@ static void store_all(int fd) batch[++i] = MI_BATCH_BUFFER_END; nengine = 0; - intel_detect_and_clear_missed_interrupts(fd); - __for_each_physical_engine(fd, e) { - if (!gem_class_can_store_dword(fd, e->class)) + cs = gem_mmap__device_coherent(i915, obj[1].handle, 0, sz, PROT_WRITE); + __for_each_physical_engine(i915, e) { + uint64_t addr; + + igt_assert(reloc.presumed_offset != -1); + addr = reloc.presumed_offset + reloc.delta; + + if (!gem_class_can_store_dword(i915, e->class)) continue; - igt_assert(2 * (nengine + 1) * sizeof(batch) <= 4096); + engines[nengine] = nengine; + batch[value] = engines[nengine]; - engines[nengine] = e->flags; + execbuf.flags = e->flags; if (gen < 6) - engines[nengine] |= I915_EXEC_SECURE; - execbuf.flags = engines[nengine]; - - j = 2*nengine; - reloc[j].target_handle = obj[0].handle; - reloc[j].presumed_offset = ~0; - reloc[j].offset = j*sizeof(batch) + offset; - reloc[j].delta = nengine*sizeof(uint32_t); - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; - - batch[value] = 0xdeadbeef; - gem_write(fd, obj[1].handle, j*sizeof(batch), - batch, sizeof(batch)); - execbuf.batch_start_offset = j*sizeof(batch); - gem_execbuf(fd, &execbuf); - - j = 2*nengine + 1; - reloc[j].target_handle = obj[0].handle; - reloc[j].presumed_offset = ~0; - reloc[j].offset = j*sizeof(batch) + offset; - reloc[j].delta = nengine*sizeof(uint32_t); - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; - - batch[value] = nengine; - gem_write(fd, obj[1].handle, j*sizeof(batch), - batch, sizeof(batch)); - execbuf.batch_start_offset = j*sizeof(batch); - gem_execbuf(fd, &execbuf); - - nengine++; - } - gem_sync(fd, obj[1].handle); - - for (i = 0; i < nengine; i++) { - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i]; - execbuf.batch_start_offset = 2*i*sizeof(batch); - memcpy(permuted, engines, nengine*sizeof(engines[0])); - igt_permute_array(permuted, nengine, igt_exchange_int); - for (j = 0; j < nengine; j++) { - execbuf.flags = permuted[j]; - gem_execbuf(fd, &execbuf); - } - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i+1]; - execbuf.batch_start_offset = (2*i+1)*sizeof(batch); - execbuf.flags = engines[i]; - gem_execbuf(fd, &execbuf); + execbuf.flags |= I915_EXEC_SECURE; + execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT; + + memcpy(cs + execbuf.batch_start_offset, batch, sizeof(batch)); + memcpy(cs + reloc.offset, &addr, reloc_sz); + gem_execbuf(i915, &execbuf); + + if (++nengine == ARRAY_SIZE(engines)) + break; + + reloc.delta += sizeof(uint32_t); + reloc.offset += sizeof(batch); + execbuf.batch_start_offset += sizeof(batch); } - gem_close(fd, obj[1].handle); + munmap(cs, sz); + gem_close(i915, obj[1].handle); - gem_read(fd, obj[0].handle, 0, engines, sizeof(engines)); - gem_close(fd, obj[0].handle); + gem_read(i915, obj[0].handle, 0, engines, sizeof(engines)); + gem_close(i915, obj[0].handle); for (i = 0; i < nengine; i++) igt_assert_eq_u32(engines[i], i); - igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); } static int open_parameters(const char *module_name) @@ -196,11 +169,8 @@ static void gem_sanitycheck(void) err = 0; if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args)) err = -errno; - if (err == -ENOENT) { - igt_fork_hang_detector(i915); + if (err == -ENOENT) store_all(i915); - igt_stop_hang_detector(); - } errno = 0; close(i915); -- 2.30.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/module_load: Tidy up gem_exec_store workalike @ 2021-02-05 10:10 ` Chris Wilson 0 siblings, 0 replies; 9+ messages in thread From: Chris Wilson @ 2021-02-05 10:10 UTC (permalink / raw) To: intel-gfx; +Cc: igt-dev, Chris Wilson We emit a store on each GPU after loading the module to confirm the basic liveness of command submission. Trim away some of the chaff. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ramalingam C <ramalingam.c@intel.com> --- tests/i915/i915_module_load.c | 146 ++++++++++++++-------------------- 1 file changed, 58 insertions(+), 88 deletions(-) diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c index 06522ba61..f1fb13914 100644 --- a/tests/i915/i915_module_load.c +++ b/tests/i915/i915_module_load.c @@ -37,41 +37,45 @@ #include "igt_sysfs.h" #include "igt_core.h" -static void store_all(int fd) +static void store_all(int i915) { - const unsigned int gen = intel_gen(intel_get_drm_devid(fd)); - unsigned int permuted[I915_EXEC_RING_MASK + 1]; - unsigned int engines[I915_EXEC_RING_MASK + 1]; - struct drm_i915_gem_exec_object2 obj[2]; - struct drm_i915_gem_relocation_entry reloc[2 * ARRAY_SIZE(engines)]; - struct drm_i915_gem_execbuffer2 execbuf; - const struct intel_execution_engine2 *e; + const unsigned int gen = intel_gen(intel_get_drm_devid(i915)); + uint32_t engines[I915_EXEC_RING_MASK + 1]; uint32_t batch[16]; - uint64_t offset; - unsigned nengine; - int value; - int i, j; - - memset(&execbuf, 0, sizeof(execbuf)); - execbuf.buffers_ptr = (uintptr_t)obj; - execbuf.buffer_count = 2; - - memset(reloc, 0, sizeof(reloc)); - memset(obj, 0, sizeof(obj)); - obj[0].handle = gem_create(fd, 4096); - obj[1].handle = gem_create(fd, 4096); - obj[1].relocation_count = 1; - - offset = sizeof(uint32_t); + unsigned int sz = ALIGN(sizeof(batch) * ARRAY_SIZE(engines), 4096); + struct drm_i915_gem_relocation_entry reloc = { + .offset = sizeof(uint32_t), + .read_domains = I915_GEM_DOMAIN_RENDER, + .write_domain = I915_GEM_DOMAIN_RENDER, + }; + struct drm_i915_gem_exec_object2 obj[2] = { + { .handle = gem_create(i915, sizeof(engines)) }, + { + .handle = gem_create(i915, sz), + .relocation_count = 1, + .relocs_ptr = to_user_pointer(&reloc), + }, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(obj), + .buffer_count = 2, + }; + const struct intel_execution_engine2 *e; + int reloc_sz = sizeof(uint32_t); + unsigned int nengine, value; + void *cs; + int i; + i = 0; batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); if (gen >= 8) { batch[++i] = 0; batch[++i] = 0; + reloc_sz = sizeof(uint64_t); } else if (gen >= 4) { batch[++i] = 0; batch[++i] = 0; - offset += sizeof(uint32_t); + reloc.offset += sizeof(uint32_t); } else { batch[i]--; batch[++i] = 0; @@ -80,74 +84,43 @@ static void store_all(int fd) batch[++i] = MI_BATCH_BUFFER_END; nengine = 0; - intel_detect_and_clear_missed_interrupts(fd); - __for_each_physical_engine(fd, e) { - if (!gem_class_can_store_dword(fd, e->class)) + cs = gem_mmap__device_coherent(i915, obj[1].handle, 0, sz, PROT_WRITE); + __for_each_physical_engine(i915, e) { + uint64_t addr; + + igt_assert(reloc.presumed_offset != -1); + addr = reloc.presumed_offset + reloc.delta; + + if (!gem_class_can_store_dword(i915, e->class)) continue; - igt_assert(2 * (nengine + 1) * sizeof(batch) <= 4096); + engines[nengine] = nengine; + batch[value] = engines[nengine]; - engines[nengine] = e->flags; + execbuf.flags = e->flags; if (gen < 6) - engines[nengine] |= I915_EXEC_SECURE; - execbuf.flags = engines[nengine]; - - j = 2*nengine; - reloc[j].target_handle = obj[0].handle; - reloc[j].presumed_offset = ~0; - reloc[j].offset = j*sizeof(batch) + offset; - reloc[j].delta = nengine*sizeof(uint32_t); - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; - - batch[value] = 0xdeadbeef; - gem_write(fd, obj[1].handle, j*sizeof(batch), - batch, sizeof(batch)); - execbuf.batch_start_offset = j*sizeof(batch); - gem_execbuf(fd, &execbuf); - - j = 2*nengine + 1; - reloc[j].target_handle = obj[0].handle; - reloc[j].presumed_offset = ~0; - reloc[j].offset = j*sizeof(batch) + offset; - reloc[j].delta = nengine*sizeof(uint32_t); - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; - - batch[value] = nengine; - gem_write(fd, obj[1].handle, j*sizeof(batch), - batch, sizeof(batch)); - execbuf.batch_start_offset = j*sizeof(batch); - gem_execbuf(fd, &execbuf); - - nengine++; - } - gem_sync(fd, obj[1].handle); - - for (i = 0; i < nengine; i++) { - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i]; - execbuf.batch_start_offset = 2*i*sizeof(batch); - memcpy(permuted, engines, nengine*sizeof(engines[0])); - igt_permute_array(permuted, nengine, igt_exchange_int); - for (j = 0; j < nengine; j++) { - execbuf.flags = permuted[j]; - gem_execbuf(fd, &execbuf); - } - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i+1]; - execbuf.batch_start_offset = (2*i+1)*sizeof(batch); - execbuf.flags = engines[i]; - gem_execbuf(fd, &execbuf); + execbuf.flags |= I915_EXEC_SECURE; + execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT; + + memcpy(cs + execbuf.batch_start_offset, batch, sizeof(batch)); + memcpy(cs + reloc.offset, &addr, reloc_sz); + gem_execbuf(i915, &execbuf); + + if (++nengine == ARRAY_SIZE(engines)) + break; + + reloc.delta += sizeof(uint32_t); + reloc.offset += sizeof(batch); + execbuf.batch_start_offset += sizeof(batch); } - gem_close(fd, obj[1].handle); + munmap(cs, sz); + gem_close(i915, obj[1].handle); - gem_read(fd, obj[0].handle, 0, engines, sizeof(engines)); - gem_close(fd, obj[0].handle); + gem_read(i915, obj[0].handle, 0, engines, sizeof(engines)); + gem_close(i915, obj[0].handle); for (i = 0; i < nengine; i++) igt_assert_eq_u32(engines[i], i); - igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); } static int open_parameters(const char *module_name) @@ -196,11 +169,8 @@ static void gem_sanitycheck(void) err = 0; if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args)) err = -errno; - if (err == -ENOENT) { - igt_fork_hang_detector(i915); + if (err == -ENOENT) store_all(i915); - igt_stop_hang_detector(); - } errno = 0; close(i915); -- 2.30.0 _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/module_load: Tidy up gem_exec_store workalike 2021-02-05 10:10 ` [igt-dev] " Chris Wilson @ 2021-02-05 17:43 ` Ramalingam C -1 siblings, 0 replies; 9+ messages in thread From: Ramalingam C @ 2021-02-05 17:43 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev, intel-gfx On 2021-02-05 at 10:10:05 +0000, Chris Wilson wrote: > We emit a store on each GPU after loading the module to confirm the > basic liveness of command submission. Trim away some of the chaff. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Ramalingam C <ramalingam.c@intel.com> Looks good to me Reviewed-by: Ramalingam C <ramalingam.c@intel.com> > --- > tests/i915/i915_module_load.c | 146 ++++++++++++++-------------------- > 1 file changed, 58 insertions(+), 88 deletions(-) > > diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c > index 06522ba61..f1fb13914 100644 > --- a/tests/i915/i915_module_load.c > +++ b/tests/i915/i915_module_load.c > @@ -37,41 +37,45 @@ > #include "igt_sysfs.h" > #include "igt_core.h" > > -static void store_all(int fd) > +static void store_all(int i915) > { > - const unsigned int gen = intel_gen(intel_get_drm_devid(fd)); > - unsigned int permuted[I915_EXEC_RING_MASK + 1]; > - unsigned int engines[I915_EXEC_RING_MASK + 1]; > - struct drm_i915_gem_exec_object2 obj[2]; > - struct drm_i915_gem_relocation_entry reloc[2 * ARRAY_SIZE(engines)]; > - struct drm_i915_gem_execbuffer2 execbuf; > - const struct intel_execution_engine2 *e; > + const unsigned int gen = intel_gen(intel_get_drm_devid(i915)); > + uint32_t engines[I915_EXEC_RING_MASK + 1]; > uint32_t batch[16]; > - uint64_t offset; > - unsigned nengine; > - int value; > - int i, j; > - > - memset(&execbuf, 0, sizeof(execbuf)); > - execbuf.buffers_ptr = (uintptr_t)obj; > - execbuf.buffer_count = 2; > - > - memset(reloc, 0, sizeof(reloc)); > - memset(obj, 0, sizeof(obj)); > - obj[0].handle = gem_create(fd, 4096); > - obj[1].handle = gem_create(fd, 4096); > - obj[1].relocation_count = 1; > - > - offset = sizeof(uint32_t); > + unsigned int sz = ALIGN(sizeof(batch) * ARRAY_SIZE(engines), 4096); > + struct drm_i915_gem_relocation_entry reloc = { > + .offset = sizeof(uint32_t), > + .read_domains = I915_GEM_DOMAIN_RENDER, > + .write_domain = I915_GEM_DOMAIN_RENDER, > + }; > + struct drm_i915_gem_exec_object2 obj[2] = { > + { .handle = gem_create(i915, sizeof(engines)) }, > + { > + .handle = gem_create(i915, sz), > + .relocation_count = 1, > + .relocs_ptr = to_user_pointer(&reloc), > + }, > + }; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(obj), > + .buffer_count = 2, > + }; > + const struct intel_execution_engine2 *e; > + int reloc_sz = sizeof(uint32_t); > + unsigned int nengine, value; > + void *cs; > + int i; > + > i = 0; > batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); > if (gen >= 8) { > batch[++i] = 0; > batch[++i] = 0; > + reloc_sz = sizeof(uint64_t); > } else if (gen >= 4) { > batch[++i] = 0; > batch[++i] = 0; > - offset += sizeof(uint32_t); > + reloc.offset += sizeof(uint32_t); > } else { > batch[i]--; > batch[++i] = 0; > @@ -80,74 +84,43 @@ static void store_all(int fd) > batch[++i] = MI_BATCH_BUFFER_END; > > nengine = 0; > - intel_detect_and_clear_missed_interrupts(fd); > - __for_each_physical_engine(fd, e) { > - if (!gem_class_can_store_dword(fd, e->class)) > + cs = gem_mmap__device_coherent(i915, obj[1].handle, 0, sz, PROT_WRITE); > + __for_each_physical_engine(i915, e) { > + uint64_t addr; > + > + igt_assert(reloc.presumed_offset != -1); > + addr = reloc.presumed_offset + reloc.delta; > + > + if (!gem_class_can_store_dword(i915, e->class)) > continue; > > - igt_assert(2 * (nengine + 1) * sizeof(batch) <= 4096); > + engines[nengine] = nengine; > + batch[value] = engines[nengine]; > > - engines[nengine] = e->flags; > + execbuf.flags = e->flags; > if (gen < 6) > - engines[nengine] |= I915_EXEC_SECURE; > - execbuf.flags = engines[nengine]; > - > - j = 2*nengine; > - reloc[j].target_handle = obj[0].handle; > - reloc[j].presumed_offset = ~0; > - reloc[j].offset = j*sizeof(batch) + offset; > - reloc[j].delta = nengine*sizeof(uint32_t); > - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; > - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; > - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; > - > - batch[value] = 0xdeadbeef; > - gem_write(fd, obj[1].handle, j*sizeof(batch), > - batch, sizeof(batch)); > - execbuf.batch_start_offset = j*sizeof(batch); > - gem_execbuf(fd, &execbuf); > - > - j = 2*nengine + 1; > - reloc[j].target_handle = obj[0].handle; > - reloc[j].presumed_offset = ~0; > - reloc[j].offset = j*sizeof(batch) + offset; > - reloc[j].delta = nengine*sizeof(uint32_t); > - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; > - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; > - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; > - > - batch[value] = nengine; > - gem_write(fd, obj[1].handle, j*sizeof(batch), > - batch, sizeof(batch)); > - execbuf.batch_start_offset = j*sizeof(batch); > - gem_execbuf(fd, &execbuf); > - > - nengine++; > - } > - gem_sync(fd, obj[1].handle); > - > - for (i = 0; i < nengine; i++) { > - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i]; > - execbuf.batch_start_offset = 2*i*sizeof(batch); > - memcpy(permuted, engines, nengine*sizeof(engines[0])); > - igt_permute_array(permuted, nengine, igt_exchange_int); > - for (j = 0; j < nengine; j++) { > - execbuf.flags = permuted[j]; > - gem_execbuf(fd, &execbuf); > - } > - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i+1]; > - execbuf.batch_start_offset = (2*i+1)*sizeof(batch); > - execbuf.flags = engines[i]; > - gem_execbuf(fd, &execbuf); > + execbuf.flags |= I915_EXEC_SECURE; > + execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT; > + > + memcpy(cs + execbuf.batch_start_offset, batch, sizeof(batch)); > + memcpy(cs + reloc.offset, &addr, reloc_sz); > + gem_execbuf(i915, &execbuf); > + > + if (++nengine == ARRAY_SIZE(engines)) > + break; > + > + reloc.delta += sizeof(uint32_t); > + reloc.offset += sizeof(batch); > + execbuf.batch_start_offset += sizeof(batch); > } > - gem_close(fd, obj[1].handle); > + munmap(cs, sz); > + gem_close(i915, obj[1].handle); > > - gem_read(fd, obj[0].handle, 0, engines, sizeof(engines)); > - gem_close(fd, obj[0].handle); > + gem_read(i915, obj[0].handle, 0, engines, sizeof(engines)); > + gem_close(i915, obj[0].handle); > > for (i = 0; i < nengine; i++) > igt_assert_eq_u32(engines[i], i); > - igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); > } > > static int open_parameters(const char *module_name) > @@ -196,11 +169,8 @@ static void gem_sanitycheck(void) > err = 0; > if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args)) > err = -errno; > - if (err == -ENOENT) { > - igt_fork_hang_detector(i915); > + if (err == -ENOENT) > store_all(i915); > - igt_stop_hang_detector(); > - } > errno = 0; > > close(i915); > -- > 2.30.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/module_load: Tidy up gem_exec_store workalike @ 2021-02-05 17:43 ` Ramalingam C 0 siblings, 0 replies; 9+ messages in thread From: Ramalingam C @ 2021-02-05 17:43 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev, intel-gfx On 2021-02-05 at 10:10:05 +0000, Chris Wilson wrote: > We emit a store on each GPU after loading the module to confirm the > basic liveness of command submission. Trim away some of the chaff. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Ramalingam C <ramalingam.c@intel.com> Looks good to me Reviewed-by: Ramalingam C <ramalingam.c@intel.com> > --- > tests/i915/i915_module_load.c | 146 ++++++++++++++-------------------- > 1 file changed, 58 insertions(+), 88 deletions(-) > > diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c > index 06522ba61..f1fb13914 100644 > --- a/tests/i915/i915_module_load.c > +++ b/tests/i915/i915_module_load.c > @@ -37,41 +37,45 @@ > #include "igt_sysfs.h" > #include "igt_core.h" > > -static void store_all(int fd) > +static void store_all(int i915) > { > - const unsigned int gen = intel_gen(intel_get_drm_devid(fd)); > - unsigned int permuted[I915_EXEC_RING_MASK + 1]; > - unsigned int engines[I915_EXEC_RING_MASK + 1]; > - struct drm_i915_gem_exec_object2 obj[2]; > - struct drm_i915_gem_relocation_entry reloc[2 * ARRAY_SIZE(engines)]; > - struct drm_i915_gem_execbuffer2 execbuf; > - const struct intel_execution_engine2 *e; > + const unsigned int gen = intel_gen(intel_get_drm_devid(i915)); > + uint32_t engines[I915_EXEC_RING_MASK + 1]; > uint32_t batch[16]; > - uint64_t offset; > - unsigned nengine; > - int value; > - int i, j; > - > - memset(&execbuf, 0, sizeof(execbuf)); > - execbuf.buffers_ptr = (uintptr_t)obj; > - execbuf.buffer_count = 2; > - > - memset(reloc, 0, sizeof(reloc)); > - memset(obj, 0, sizeof(obj)); > - obj[0].handle = gem_create(fd, 4096); > - obj[1].handle = gem_create(fd, 4096); > - obj[1].relocation_count = 1; > - > - offset = sizeof(uint32_t); > + unsigned int sz = ALIGN(sizeof(batch) * ARRAY_SIZE(engines), 4096); > + struct drm_i915_gem_relocation_entry reloc = { > + .offset = sizeof(uint32_t), > + .read_domains = I915_GEM_DOMAIN_RENDER, > + .write_domain = I915_GEM_DOMAIN_RENDER, > + }; > + struct drm_i915_gem_exec_object2 obj[2] = { > + { .handle = gem_create(i915, sizeof(engines)) }, > + { > + .handle = gem_create(i915, sz), > + .relocation_count = 1, > + .relocs_ptr = to_user_pointer(&reloc), > + }, > + }; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(obj), > + .buffer_count = 2, > + }; > + const struct intel_execution_engine2 *e; > + int reloc_sz = sizeof(uint32_t); > + unsigned int nengine, value; > + void *cs; > + int i; > + > i = 0; > batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0); > if (gen >= 8) { > batch[++i] = 0; > batch[++i] = 0; > + reloc_sz = sizeof(uint64_t); > } else if (gen >= 4) { > batch[++i] = 0; > batch[++i] = 0; > - offset += sizeof(uint32_t); > + reloc.offset += sizeof(uint32_t); > } else { > batch[i]--; > batch[++i] = 0; > @@ -80,74 +84,43 @@ static void store_all(int fd) > batch[++i] = MI_BATCH_BUFFER_END; > > nengine = 0; > - intel_detect_and_clear_missed_interrupts(fd); > - __for_each_physical_engine(fd, e) { > - if (!gem_class_can_store_dword(fd, e->class)) > + cs = gem_mmap__device_coherent(i915, obj[1].handle, 0, sz, PROT_WRITE); > + __for_each_physical_engine(i915, e) { > + uint64_t addr; > + > + igt_assert(reloc.presumed_offset != -1); > + addr = reloc.presumed_offset + reloc.delta; > + > + if (!gem_class_can_store_dword(i915, e->class)) > continue; > > - igt_assert(2 * (nengine + 1) * sizeof(batch) <= 4096); > + engines[nengine] = nengine; > + batch[value] = engines[nengine]; > > - engines[nengine] = e->flags; > + execbuf.flags = e->flags; > if (gen < 6) > - engines[nengine] |= I915_EXEC_SECURE; > - execbuf.flags = engines[nengine]; > - > - j = 2*nengine; > - reloc[j].target_handle = obj[0].handle; > - reloc[j].presumed_offset = ~0; > - reloc[j].offset = j*sizeof(batch) + offset; > - reloc[j].delta = nengine*sizeof(uint32_t); > - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; > - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; > - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; > - > - batch[value] = 0xdeadbeef; > - gem_write(fd, obj[1].handle, j*sizeof(batch), > - batch, sizeof(batch)); > - execbuf.batch_start_offset = j*sizeof(batch); > - gem_execbuf(fd, &execbuf); > - > - j = 2*nengine + 1; > - reloc[j].target_handle = obj[0].handle; > - reloc[j].presumed_offset = ~0; > - reloc[j].offset = j*sizeof(batch) + offset; > - reloc[j].delta = nengine*sizeof(uint32_t); > - reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION; > - reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; > - obj[1].relocs_ptr = (uintptr_t)&reloc[j]; > - > - batch[value] = nengine; > - gem_write(fd, obj[1].handle, j*sizeof(batch), > - batch, sizeof(batch)); > - execbuf.batch_start_offset = j*sizeof(batch); > - gem_execbuf(fd, &execbuf); > - > - nengine++; > - } > - gem_sync(fd, obj[1].handle); > - > - for (i = 0; i < nengine; i++) { > - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i]; > - execbuf.batch_start_offset = 2*i*sizeof(batch); > - memcpy(permuted, engines, nengine*sizeof(engines[0])); > - igt_permute_array(permuted, nengine, igt_exchange_int); > - for (j = 0; j < nengine; j++) { > - execbuf.flags = permuted[j]; > - gem_execbuf(fd, &execbuf); > - } > - obj[1].relocs_ptr = (uintptr_t)&reloc[2*i+1]; > - execbuf.batch_start_offset = (2*i+1)*sizeof(batch); > - execbuf.flags = engines[i]; > - gem_execbuf(fd, &execbuf); > + execbuf.flags |= I915_EXEC_SECURE; > + execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT; > + > + memcpy(cs + execbuf.batch_start_offset, batch, sizeof(batch)); > + memcpy(cs + reloc.offset, &addr, reloc_sz); > + gem_execbuf(i915, &execbuf); > + > + if (++nengine == ARRAY_SIZE(engines)) > + break; > + > + reloc.delta += sizeof(uint32_t); > + reloc.offset += sizeof(batch); > + execbuf.batch_start_offset += sizeof(batch); > } > - gem_close(fd, obj[1].handle); > + munmap(cs, sz); > + gem_close(i915, obj[1].handle); > > - gem_read(fd, obj[0].handle, 0, engines, sizeof(engines)); > - gem_close(fd, obj[0].handle); > + gem_read(i915, obj[0].handle, 0, engines, sizeof(engines)); > + gem_close(i915, obj[0].handle); > > for (i = 0; i < nengine; i++) > igt_assert_eq_u32(engines[i], i); > - igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); > } > > static int open_parameters(const char *module_name) > @@ -196,11 +169,8 @@ static void gem_sanitycheck(void) > err = 0; > if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args)) > err = -errno; > - if (err == -ENOENT) { > - igt_fork_hang_detector(i915); > + if (err == -ENOENT) > store_all(i915); > - igt_stop_hang_detector(); > - } > errno = 0; > > close(i915); > -- > 2.30.0 > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for tests/i915_module_load: obj size based on the engine count (rev2) 2021-02-05 9:07 [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count Ramalingam C ` (2 preceding siblings ...) 2021-02-05 10:10 ` [igt-dev] " Chris Wilson @ 2021-02-05 12:04 ` Patchwork 2021-02-05 18:48 ` [igt-dev] ✓ Fi.CI.IGT: success for tests/i915_module_load: obj size based on the engine count Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-02-05 12:04 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 4790 bytes --] == Series Details == Series: tests/i915_module_load: obj size based on the engine count (rev2) URL : https://patchwork.freedesktop.org/series/86748/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9737 -> IGTPW_5486 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_5486 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_5486, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_5486: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live@client: - fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-glk-dsi/igt@i915_selftest@live@client.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-glk-dsi/igt@i915_selftest@live@client.html Known issues ------------ Here are the changes found in IGTPW_5486 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-tgl-y/igt@debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_module_load@reload: - fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([i915#2605]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-kbl-7500u/igt@i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-kbl-7500u/igt@i915_module_load@reload.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][9] -> [INCOMPLETE][10] ([i915#2940]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-bsw-n3050/igt@i915_selftest@live@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-bsw-n3050/igt@i915_selftest@live@execlists.html * igt@runner@aborted: - fi-bsw-n3050: NOTRUN -> [FAIL][11] ([i915#1436]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-bsw-n3050/igt@runner@aborted.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][12] ([i915#1888]) -> [PASS][13] +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html * igt@gem_linear_blits@basic: - fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9737/fi-tgl-y/igt@gem_linear_blits@basic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/fi-tgl-y/igt@gem_linear_blits@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 37) ------------------------------ Missing (6): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-icl-u2 fi-dg1-1 fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_5992 -> IGTPW_5486 CI-20190529: 20190529 CI_DRM_9737: 8fef45d7241af38b7d68a8ad3b11ce8ab38b4491 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5486: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/index.html IGT_5992: b781a32b06a0173a71b4e1ac30d18dd7164a67c4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5486/index.html [-- Attachment #1.2: Type: text/html, Size: 5600 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for tests/i915_module_load: obj size based on the engine count 2021-02-05 9:07 [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count Ramalingam C ` (3 preceding siblings ...) 2021-02-05 12:04 ` [igt-dev] ✗ Fi.CI.BAT: failure for tests/i915_module_load: obj size based on the engine count (rev2) Patchwork @ 2021-02-05 18:48 ` Patchwork 4 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-02-05 18:48 UTC (permalink / raw) To: Chris Wilson; +Cc: igt-dev [-- Attachment #1.1: Type: text/plain, Size: 30276 bytes --] == Series Details == Series: tests/i915_module_load: obj size based on the engine count URL : https://patchwork.freedesktop.org/series/86748/ State : success == Summary == CI Bug Log - changes from CI_DRM_9736_full -> IGTPW_5484_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/index.html Known issues ------------ Here are the changes found in IGTPW_5484_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][3] -> [FAIL][4] ([i915#2846]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl7/igt@gem_exec_fair@basic-deadline.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl7/igt@gem_exec_fair@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][5] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl6/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html - shard-glk: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][18] ([i915#2389]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl7/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#2803]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb5/igt@gem_exec_schedule@u-fairslice@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb2/igt@gem_exec_schedule@u-fairslice@rcs0.html - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#2803]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-tglb5/igt@gem_exec_schedule@u-fairslice@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb6/igt@gem_exec_schedule@u-fairslice@rcs0.html * igt@gem_userptr_blits@input-checking: - shard-kbl: NOTRUN -> [DMESG-WARN][23] ([i915#3002]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl6/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-tglb: NOTRUN -> [INCOMPLETE][24] ([i915#2502] / [i915#2667]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb6/igt@gem_userptr_blits@vma-merge.html * igt@gem_vm_create@destroy-race: - shard-tglb: [PASS][25] -> [TIMEOUT][26] ([i915#2795]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-tglb2/igt@gem_vm_create@destroy-race.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb2/igt@gem_vm_create@destroy-race.html * igt@gen7_exec_parse@batch-without-end: - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109289]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb3/igt@gen7_exec_parse@batch-without-end.html - shard-tglb: NOTRUN -> [SKIP][28] ([fdo#109289]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb3/igt@gen7_exec_parse@batch-without-end.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#1937]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html - shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#1937]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a: - shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#1937]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk9/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-tglb: NOTRUN -> [SKIP][32] ([fdo#111644] / [i915#1397] / [i915#2411]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb8/igt@i915_pm_rpm@dpms-non-lpsp.html - shard-iclb: NOTRUN -> [SKIP][33] ([fdo#110892]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb7/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109506] / [i915#2411]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb8/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271]) +75 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl1/igt@i915_pm_rpm@modeset-lpsp-stress.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-iclb: NOTRUN -> [SKIP][36] ([i915#1769]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html - shard-tglb: NOTRUN -> [SKIP][37] ([i915#1769]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111615]) +3 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt@kms_chamelium@dp-crc-single: - shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-snb6/igt@kms_chamelium@dp-crc-single.html - shard-hsw: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw1/igt@kms_chamelium@dp-crc-single.html * igt@kms_chamelium@dp-mode-timings: - shard-glk: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk1/igt@kms_chamelium@dp-mode-timings.html - shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109284] / [fdo#111827]) +2 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb3/igt@kms_chamelium@dp-mode-timings.html * igt@kms_chamelium@vga-frame-dump: - shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +7 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb8/igt@kms_chamelium@vga-frame-dump.html * igt@kms_color@pipe-b-ctm-0-25: - shard-iclb: NOTRUN -> [FAIL][44] ([i915#1149] / [i915#315]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb7/igt@kms_color@pipe-b-ctm-0-25.html - shard-tglb: NOTRUN -> [FAIL][45] ([i915#1149] / [i915#315]) +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb6/igt@kms_color@pipe-b-ctm-0-25.html * igt@kms_color@pipe-b-legacy-gamma-reset: - shard-apl: [PASS][46] -> [FAIL][47] ([i915#2964]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl1/igt@kms_color@pipe-b-legacy-gamma-reset.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl7/igt@kms_color@pipe-b-legacy-gamma-reset.html - shard-kbl: [PASS][48] -> [FAIL][49] ([i915#2964]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl6/igt@kms_color@pipe-b-legacy-gamma-reset.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl2/igt@kms_color@pipe-b-legacy-gamma-reset.html * igt@kms_color_chamelium@pipe-a-ctm-0-75: - shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +4 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-c-ctm-max: - shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +8 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl4/igt@kms_color_chamelium@pipe-c-ctm-max.html * igt@kms_content_protection@atomic: - shard-tglb: NOTRUN -> [SKIP][52] ([fdo#111828]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb3/igt@kms_content_protection@atomic.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding: - shard-kbl: [PASS][53] -> [FAIL][54] ([i915#54]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html - shard-apl: [PASS][55] -> [FAIL][56] ([i915#54]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: NOTRUN -> [DMESG-WARN][57] ([i915#180]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-glk: [PASS][58] -> [FAIL][59] ([i915#54]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-glk8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen: - shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109279]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109274] / [fdo#109278]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt@kms_flip@2x-flip-vs-dpms: - shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109274]) +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb8/igt@kms_flip@2x-flip-vs-dpms.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-tglb: [PASS][63] -> [FAIL][64] ([i915#2598]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271]) +32 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render: - shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109280]) +4 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt: - shard-hsw: NOTRUN -> [SKIP][67] ([fdo#109271]) +24 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff: - shard-tglb: NOTRUN -> [SKIP][68] ([fdo#111825]) +22 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: [PASS][70] -> [DMESG-WARN][71] ([i915#180]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-apl: NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +2 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-glk: NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html - shard-kbl: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb: - shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271]) +8 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk3/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html - shard-hsw: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#533]) +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw6/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html - shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109278]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb2/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2: - shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5: - shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html - shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html - shard-iclb: NOTRUN -> [SKIP][81] ([i915#658]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-tglb: NOTRUN -> [SKIP][82] ([i915#2920]) +1 similar issue [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][83] -> [SKIP][84] ([fdo#109441]) +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_psr@sprite_plane_onoff: - shard-snb: NOTRUN -> [SKIP][85] ([fdo#109271]) +28 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-snb5/igt@kms_psr@sprite_plane_onoff.html - shard-hsw: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#1072]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw1/igt@kms_psr@sprite_plane_onoff.html * igt@kms_tv_load_detect@load-detect: - shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109309]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb6/igt@kms_tv_load_detect@load-detect.html * igt@kms_writeback@writeback-invalid-parameters: - shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2437]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl6/igt@kms_writeback@writeback-invalid-parameters.html * igt@perf@polling-parameterized: - shard-glk: [PASS][89] -> [FAIL][90] ([i915#1542]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-glk1/igt@perf@polling-parameterized.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk3/igt@perf@polling-parameterized.html * igt@prime_nv_api@nv_self_import_to_different_fd: - shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109291]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb3/igt@prime_nv_api@nv_self_import_to_different_fd.html - shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109291]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb1/igt@prime_nv_api@nv_self_import_to_different_fd.html * igt@sysfs_clients@recycle: - shard-hsw: [PASS][93] -> [FAIL][94] ([i915#3028]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-hsw4/igt@sysfs_clients@recycle.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw1/igt@sysfs_clients@recycle.html - shard-apl: [PASS][95] -> [FAIL][96] ([i915#3028]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl6/igt@sysfs_clients@recycle.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl2/igt@sysfs_clients@recycle.html * igt@sysfs_clients@sema-10@rcs0: - shard-kbl: [PASS][97] -> [SKIP][98] ([fdo#109271] / [i915#3026]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl2/igt@sysfs_clients@sema-10@rcs0.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl6/igt@sysfs_clients@sema-10@rcs0.html * igt@sysfs_clients@split-10@bcs0: - shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#3026]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl6/igt@sysfs_clients@split-10@bcs0.html #### Possible fixes #### * igt@gem_exec_fair@basic-none-share@rcs0: - shard-apl: [SKIP][100] ([fdo#109271]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl8/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][102] ([i915#2842]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html - shard-glk: [FAIL][104] ([i915#2842]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_schedule@u-fairslice-all: - shard-tglb: [DMESG-WARN][106] ([i915#2803]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-tglb6/igt@gem_exec_schedule@u-fairslice-all.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-tglb6/igt@gem_exec_schedule@u-fairslice-all.html * igt@i915_selftest@live@hangcheck: - shard-hsw: [INCOMPLETE][108] ([i915#2782]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-hsw4/igt@i915_selftest@live@hangcheck.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw8/igt@i915_selftest@live@hangcheck.html * igt@i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +1 similar issue [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html * igt@kms_color@pipe-c-legacy-gamma-reset: - shard-kbl: [FAIL][112] ([i915#2964]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl6/igt@kms_color@pipe-c-legacy-gamma-reset.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl4/igt@kms_color@pipe-c-legacy-gamma-reset.html - shard-apl: [FAIL][114] ([i915#2964]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl7/igt@kms_color@pipe-c-legacy-gamma-reset.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl2/igt@kms_color@pipe-c-legacy-gamma-reset.html - shard-glk: [FAIL][116] ([i915#2964]) -> [PASS][117] [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-glk7/igt@kms_color@pipe-c-legacy-gamma-reset.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk7/igt@kms_color@pipe-c-legacy-gamma-reset.html - shard-hsw: [FAIL][118] ([i915#2964]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-hsw2/igt@kms_color@pipe-c-legacy-gamma-reset.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw1/igt@kms_color@pipe-c-legacy-gamma-reset.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [FAIL][120] ([i915#54]) -> [PASS][121] [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html - shard-apl: [FAIL][122] ([i915#54]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge: - shard-kbl: [DMESG-WARN][124] ([i915#165] / [i915#180]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl2/igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl2/igt@kms_cursor_edge_walk@pipe-c-64x64-top-edge.html * igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1: - shard-hsw: [INCOMPLETE][126] ([i915#2055]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-hsw4/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw4/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: [DMESG-WARN][128] ([i915#180]) -> [PASS][129] +1 similar issue [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_psr@psr2_dpms: - shard-iclb: [SKIP][130] ([fdo#109441]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb3/igt@kms_psr@psr2_dpms.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb2/igt@kms_psr@psr2_dpms.html * {igt@sysfs_clients@recycle-many}: - shard-glk: [FAIL][132] ([i915#3028]) -> [PASS][133] +1 similar issue [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-glk3/igt@sysfs_clients@recycle-many.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-glk3/igt@sysfs_clients@recycle-many.html - shard-hsw: [FAIL][134] ([i915#3028]) -> [PASS][135] [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-hsw6/igt@sysfs_clients@recycle-many.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-hsw6/igt@sysfs_clients@recycle-many.html * igt@sysfs_clients@sema-10@vcs0: - shard-apl: [SKIP][136] ([fdo#109271] / [i915#3026]) -> [PASS][137] +2 similar issues [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-apl3/igt@sysfs_clients@sema-10@vcs0.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-apl8/igt@sysfs_clients@sema-10@vcs0.html * igt@testdisplay: - shard-kbl: [DMESG-WARN][138] ([i915#165] / [i915#180] / [i915#78]) -> [PASS][139] [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl2/igt@testdisplay.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl3/igt@testdisplay.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][140] ([i915#2684]) -> [WARN][141] ([i915#1804] / [i915#2684]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][142] ([i915#2684]) -> [WARN][143] ([i915#2681] / [i915#2684]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-iclb: [SKIP][144] ([i915#2920]) -> [SKIP][145] ([i915#658]) +2 similar issues [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-iclb: [SKIP][146] ([i915#658]) -> [SKIP][147] ([i915#2920]) +2 similar issues [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@runner@aborted: - shard-kbl: ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151]) ([i915#1814] / [i915#2295] / [i915#2505] / [i915#3002]) -> ([FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156]) ([i915#1436] / [i915#2295] / [i915#2505] / [i915#3002]) [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl3/igt@runner@aborted.html [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl3/igt@runner@aborted.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl6/igt@runner@aborted.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9736/shard-kbl4/igt@runner@aborted.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl6/igt@runner@aborted.html [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl1/igt@runner@aborted.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl6/igt@runner@aborted.html [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/shard-kbl3/igt@r == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5484/index.html [-- Attachment #1.2: Type: text/html, Size: 34077 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-02-05 18:48 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-02-05 9:07 [igt-dev] [PATCH i-g-t] tests/i915_module_load: obj size based on the engine count Ramalingam C 2021-02-05 9:53 ` Chris Wilson 2021-02-05 10:06 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork 2021-02-05 10:10 ` [Intel-gfx] [PATCH i-g-t] i915/module_load: Tidy up gem_exec_store workalike Chris Wilson 2021-02-05 10:10 ` [igt-dev] " Chris Wilson 2021-02-05 17:43 ` [Intel-gfx] " Ramalingam C 2021-02-05 17:43 ` [igt-dev] " Ramalingam C 2021-02-05 12:04 ` [igt-dev] ✗ Fi.CI.BAT: failure for tests/i915_module_load: obj size based on the engine count (rev2) Patchwork 2021-02-05 18:48 ` [igt-dev] ✓ Fi.CI.IGT: success for tests/i915_module_load: obj size based on the engine count Patchwork
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