* [PATCH V2 1/3] perf/x86/rapl: Add msr mask support
@ 2021-02-04 16:18 Zhang Rui
2021-02-04 16:18 ` [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters Zhang Rui
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Zhang Rui @ 2021-02-04 16:18 UTC (permalink / raw)
To: peterz, mingo, acme
Cc: mark.rutland, alexander.shishkin, jolsa, namhyung, linux-kernel,
x86, kan.liang, ak
In some cases, when probing a perf MSR, we're probing certain bits of the
MSR instead of the whole register, thus only these bits should be checked.
For example, for RAPL ENERGY_STATUS MSR, only the lower 32 bits represents
the energy counter, and the higher 32bits are reserved.
Introduce a new mask field in struct perf_msr to allow probing certain
bits of a MSR.
This change is transparent to the current perf_msr_probe() users.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/probe.c | 5 ++++-
arch/x86/events/probe.h | 7 ++++---
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c
index 136a1e847254..a0a19c404cb5 100644
--- a/arch/x86/events/probe.c
+++ b/arch/x86/events/probe.c
@@ -28,6 +28,7 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
for (bit = 0; bit < cnt; bit++) {
if (!msr[bit].no_check) {
struct attribute_group *grp = msr[bit].grp;
+ u64 mask;
/* skip entry with no group */
if (!grp)
@@ -44,8 +45,10 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data)
/* Virt sucks; you cannot tell if a R/O MSR is present :/ */
if (rdmsrl_safe(msr[bit].msr, &val))
continue;
+
+ mask = msr[bit].mask ? msr[bit].mask : U64_MAX;
/* Disable zero counters if requested. */
- if (!zero && !val)
+ if (!zero && !(val & mask))
continue;
grp->is_visible = NULL;
diff --git a/arch/x86/events/probe.h b/arch/x86/events/probe.h
index 4c8e0afc5fb5..261b9bda24e3 100644
--- a/arch/x86/events/probe.h
+++ b/arch/x86/events/probe.h
@@ -4,10 +4,11 @@
#include <linux/sysfs.h>
struct perf_msr {
- u64 msr;
- struct attribute_group *grp;
+ u64 msr;
+ struct attribute_group *grp;
bool (*test)(int idx, void *data);
- bool no_check;
+ bool no_check;
+ u64 mask;
};
unsigned long
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters 2021-02-04 16:18 [PATCH V2 1/3] perf/x86/rapl: Add msr mask support Zhang Rui @ 2021-02-04 16:18 ` Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] " tip-bot2 for Zhang Rui 2021-02-04 16:18 ` [PATCH V2 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] perf/x86/rapl: Add msr mask support tip-bot2 for Zhang Rui 2 siblings, 1 reply; 6+ messages in thread From: Zhang Rui @ 2021-02-04 16:18 UTC (permalink / raw) To: peterz, mingo, acme Cc: mark.rutland, alexander.shishkin, jolsa, namhyung, linux-kernel, x86, kan.liang, ak In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the energy counter. On previous platforms, the higher 32bits are reverved and always return Zero. But on Intel SapphireRapids platform, the higher 32bits are reused for other purpose and return non-zero value. Thus check the lower 32bits only for these ENERGY_COUTNER MSRs, to make sure the RAPL PMU events are not added erroneously when higher 32bits contain non-zero value. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/events/rapl.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 7dbbeaacd995..7ed25b2ba05f 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -523,12 +523,15 @@ static bool test_msr(int idx, void *data) return test_bit(idx, (unsigned long *) data); } +/* Only lower 32bits of the MSR represents the energy counter */ +#define RAPL_MSR_MASK 0xFFFFFFFF + static struct perf_msr intel_rapl_msrs[] = { - [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr }, - [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr }, - [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr }, - [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr }, - [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr }, + [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK }, }; /* -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/core] perf/x86/rapl: Only check lower 32bits for RAPL energy counters 2021-02-04 16:18 ` [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters Zhang Rui @ 2021-02-10 13:59 ` tip-bot2 for Zhang Rui 0 siblings, 0 replies; 6+ messages in thread From: tip-bot2 for Zhang Rui @ 2021-02-10 13:59 UTC (permalink / raw) To: linux-tip-commits Cc: Zhang Rui, Peter Zijlstra (Intel), Andi Kleen, x86, linux-kernel The following commit has been merged into the perf/core branch of tip: Commit-ID: b6f78d3fba7f605f673185d7292d84af7576fdc1 Gitweb: https://git.kernel.org/tip/b6f78d3fba7f605f673185d7292d84af7576fdc1 Author: Zhang Rui <rui.zhang@intel.com> AuthorDate: Fri, 05 Feb 2021 00:18:15 +08:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Wed, 10 Feb 2021 14:44:55 +01:00 perf/x86/rapl: Only check lower 32bits for RAPL energy counters In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the energy counter. On previous platforms, the higher 32bits are reverved and always return Zero. But on Intel SapphireRapids platform, the higher 32bits are reused for other purpose and return non-zero value. Thus check the lower 32bits only for these ENERGY_COUTNER MSRs, to make sure the RAPL PMU events are not added erroneously when higher 32bits contain non-zero value. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210204161816.12649-2-rui.zhang@intel.com --- arch/x86/events/rapl.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 7dbbeaa..7ed25b2 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -523,12 +523,15 @@ static bool test_msr(int idx, void *data) return test_bit(idx, (unsigned long *) data); } +/* Only lower 32bits of the MSR represents the energy counter */ +#define RAPL_MSR_MASK 0xFFFFFFFF + static struct perf_msr intel_rapl_msrs[] = { - [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr }, - [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr }, - [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr }, - [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr }, - [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr }, + [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK }, }; /* ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V2 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform 2021-02-04 16:18 [PATCH V2 1/3] perf/x86/rapl: Add msr mask support Zhang Rui 2021-02-04 16:18 ` [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters Zhang Rui @ 2021-02-04 16:18 ` Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] " tip-bot2 for Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] perf/x86/rapl: Add msr mask support tip-bot2 for Zhang Rui 2 siblings, 1 reply; 6+ messages in thread From: Zhang Rui @ 2021-02-04 16:18 UTC (permalink / raw) To: peterz, mingo, acme Cc: mark.rutland, alexander.shishkin, jolsa, namhyung, linux-kernel, x86, kan.liang, ak There are several things special for the RAPL Psys energy counter, on Intel Sapphire Rapids platform. 1. it contains one Psys master package, and only CPUs on the master package can read valid value of the Psys energy counter, reading the MSR on CPUs in the slave package returns 0. 2. The master package does not have to be Physical package 0. And when all the CPUs on the Psys master package are offlined, we lose the Psys energy counter, at runtime. 3. The Psys energy counter can be disabled by BIOS, while all the other energy counters are not affected. It is not easy to handle all of these in the current RAPL PMU design because a) perf_msr_probe() validates the MSR on some random CPU, which may either be in the Psys master package or in the Psys slave package. b) all the RAPL events share the same PMU, and there is not API to remove the psys-energy event cleanly, without affecting the other events in the same PMU. This patch addresses the problems in a simple way. First, by setting .no_check bit for RAPL Psys MSR, the psys-energy event is always added, so we don't have to check the Psys ENERGY_STATUS MSR on master package. Then, by removing rapl_not_visible(), the psys-energy event is always available in sysfs. This does not affect the previous code because, for the RAPL MSRs with .no_check cleared, the .is_visible() callback is always overriden in the perf_msr_probe() function. Note, although RAPL PMU is die-based, and the Psys energy counter MSR on Intel SPR is package scope, this is not a problem because there is only one die in each package on SPR. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/events/rapl.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 7ed25b2ba05f..f42a70496a24 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -454,16 +454,9 @@ static struct attribute *rapl_events_cores[] = { NULL, }; -static umode_t -rapl_not_visible(struct kobject *kobj, struct attribute *attr, int i) -{ - return 0; -} - static struct attribute_group rapl_events_cores_group = { .name = "events", .attrs = rapl_events_cores, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_pkg[] = { @@ -476,7 +469,6 @@ static struct attribute *rapl_events_pkg[] = { static struct attribute_group rapl_events_pkg_group = { .name = "events", .attrs = rapl_events_pkg, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_ram[] = { @@ -489,7 +481,6 @@ static struct attribute *rapl_events_ram[] = { static struct attribute_group rapl_events_ram_group = { .name = "events", .attrs = rapl_events_ram, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_gpu[] = { @@ -502,7 +493,6 @@ static struct attribute *rapl_events_gpu[] = { static struct attribute_group rapl_events_gpu_group = { .name = "events", .attrs = rapl_events_gpu, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_psys[] = { @@ -515,7 +505,6 @@ static struct attribute *rapl_events_psys[] = { static struct attribute_group rapl_events_psys_group = { .name = "events", .attrs = rapl_events_psys, - .is_visible = rapl_not_visible, }; static bool test_msr(int idx, void *data) @@ -534,6 +523,14 @@ static struct perf_msr intel_rapl_msrs[] = { [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK }, }; +static struct perf_msr intel_rapl_spr_msrs[] = { + [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, true, RAPL_MSR_MASK }, +}; + /* * Force to PERF_RAPL_MAX size due to: * - perf_msr_probe(PERF_RAPL_MAX) @@ -764,7 +761,7 @@ static struct rapl_model model_spr = { BIT(PERF_RAPL_PSYS), .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR, .msr_power_unit = MSR_RAPL_POWER_UNIT, - .rapl_msrs = intel_rapl_msrs, + .rapl_msrs = intel_rapl_spr_msrs, }; static struct rapl_model model_amd_fam17h = { -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/core] perf/x86/rapl: Fix psys-energy event on Intel SPR platform 2021-02-04 16:18 ` [PATCH V2 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui @ 2021-02-10 13:59 ` tip-bot2 for Zhang Rui 0 siblings, 0 replies; 6+ messages in thread From: tip-bot2 for Zhang Rui @ 2021-02-10 13:59 UTC (permalink / raw) To: linux-tip-commits Cc: Zhang Rui, Peter Zijlstra (Intel), Andi Kleen, x86, linux-kernel The following commit has been merged into the perf/core branch of tip: Commit-ID: 838342a6d6b7ecc475dc052d4a405c4ffb3ad1b5 Gitweb: https://git.kernel.org/tip/838342a6d6b7ecc475dc052d4a405c4ffb3ad1b5 Author: Zhang Rui <rui.zhang@intel.com> AuthorDate: Fri, 05 Feb 2021 00:18:16 +08:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Wed, 10 Feb 2021 14:44:55 +01:00 perf/x86/rapl: Fix psys-energy event on Intel SPR platform There are several things special for the RAPL Psys energy counter, on Intel Sapphire Rapids platform. 1. it contains one Psys master package, and only CPUs on the master package can read valid value of the Psys energy counter, reading the MSR on CPUs in the slave package returns 0. 2. The master package does not have to be Physical package 0. And when all the CPUs on the Psys master package are offlined, we lose the Psys energy counter, at runtime. 3. The Psys energy counter can be disabled by BIOS, while all the other energy counters are not affected. It is not easy to handle all of these in the current RAPL PMU design because a) perf_msr_probe() validates the MSR on some random CPU, which may either be in the Psys master package or in the Psys slave package. b) all the RAPL events share the same PMU, and there is not API to remove the psys-energy event cleanly, without affecting the other events in the same PMU. This patch addresses the problems in a simple way. First, by setting .no_check bit for RAPL Psys MSR, the psys-energy event is always added, so we don't have to check the Psys ENERGY_STATUS MSR on master package. Then, by removing rapl_not_visible(), the psys-energy event is always available in sysfs. This does not affect the previous code because, for the RAPL MSRs with .no_check cleared, the .is_visible() callback is always overriden in the perf_msr_probe() function. Note, although RAPL PMU is die-based, and the Psys energy counter MSR on Intel SPR is package scope, this is not a problem because there is only one die in each package on SPR. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210204161816.12649-3-rui.zhang@intel.com --- arch/x86/events/rapl.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 7ed25b2..f42a704 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -454,16 +454,9 @@ static struct attribute *rapl_events_cores[] = { NULL, }; -static umode_t -rapl_not_visible(struct kobject *kobj, struct attribute *attr, int i) -{ - return 0; -} - static struct attribute_group rapl_events_cores_group = { .name = "events", .attrs = rapl_events_cores, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_pkg[] = { @@ -476,7 +469,6 @@ static struct attribute *rapl_events_pkg[] = { static struct attribute_group rapl_events_pkg_group = { .name = "events", .attrs = rapl_events_pkg, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_ram[] = { @@ -489,7 +481,6 @@ static struct attribute *rapl_events_ram[] = { static struct attribute_group rapl_events_ram_group = { .name = "events", .attrs = rapl_events_ram, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_gpu[] = { @@ -502,7 +493,6 @@ static struct attribute *rapl_events_gpu[] = { static struct attribute_group rapl_events_gpu_group = { .name = "events", .attrs = rapl_events_gpu, - .is_visible = rapl_not_visible, }; static struct attribute *rapl_events_psys[] = { @@ -515,7 +505,6 @@ static struct attribute *rapl_events_psys[] = { static struct attribute_group rapl_events_psys_group = { .name = "events", .attrs = rapl_events_psys, - .is_visible = rapl_not_visible, }; static bool test_msr(int idx, void *data) @@ -534,6 +523,14 @@ static struct perf_msr intel_rapl_msrs[] = { [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, false, RAPL_MSR_MASK }, }; +static struct perf_msr intel_rapl_spr_msrs[] = { + [PERF_RAPL_PP0] = { MSR_PP0_ENERGY_STATUS, &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PKG] = { MSR_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_RAM] = { MSR_DRAM_ENERGY_STATUS, &rapl_events_ram_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PP1] = { MSR_PP1_ENERGY_STATUS, &rapl_events_gpu_group, test_msr, false, RAPL_MSR_MASK }, + [PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group, test_msr, true, RAPL_MSR_MASK }, +}; + /* * Force to PERF_RAPL_MAX size due to: * - perf_msr_probe(PERF_RAPL_MAX) @@ -764,7 +761,7 @@ static struct rapl_model model_spr = { BIT(PERF_RAPL_PSYS), .unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR, .msr_power_unit = MSR_RAPL_POWER_UNIT, - .rapl_msrs = intel_rapl_msrs, + .rapl_msrs = intel_rapl_spr_msrs, }; static struct rapl_model model_amd_fam17h = { ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [tip: perf/core] perf/x86/rapl: Add msr mask support 2021-02-04 16:18 [PATCH V2 1/3] perf/x86/rapl: Add msr mask support Zhang Rui 2021-02-04 16:18 ` [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters Zhang Rui 2021-02-04 16:18 ` [PATCH V2 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui @ 2021-02-10 13:59 ` tip-bot2 for Zhang Rui 2 siblings, 0 replies; 6+ messages in thread From: tip-bot2 for Zhang Rui @ 2021-02-10 13:59 UTC (permalink / raw) To: linux-tip-commits Cc: Zhang Rui, Peter Zijlstra (Intel), Andi Kleen, x86, linux-kernel The following commit has been merged into the perf/core branch of tip: Commit-ID: ffb20c2e52e8709b5fc9951e8863e31efb1f2cba Gitweb: https://git.kernel.org/tip/ffb20c2e52e8709b5fc9951e8863e31efb1f2cba Author: Zhang Rui <rui.zhang@intel.com> AuthorDate: Fri, 05 Feb 2021 00:18:14 +08:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Wed, 10 Feb 2021 14:44:54 +01:00 perf/x86/rapl: Add msr mask support In some cases, when probing a perf MSR, we're probing certain bits of the MSR instead of the whole register, thus only these bits should be checked. For example, for RAPL ENERGY_STATUS MSR, only the lower 32 bits represents the energy counter, and the higher 32bits are reserved. Introduce a new mask field in struct perf_msr to allow probing certain bits of a MSR. This change is transparent to the current perf_msr_probe() users. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/20210204161816.12649-1-rui.zhang@intel.com --- arch/x86/events/probe.c | 7 ++++++- arch/x86/events/probe.h | 7 ++++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c index 136a1e8..600bf8d 100644 --- a/arch/x86/events/probe.c +++ b/arch/x86/events/probe.c @@ -28,6 +28,7 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data) for (bit = 0; bit < cnt; bit++) { if (!msr[bit].no_check) { struct attribute_group *grp = msr[bit].grp; + u64 mask; /* skip entry with no group */ if (!grp) @@ -44,8 +45,12 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, void *data) /* Virt sucks; you cannot tell if a R/O MSR is present :/ */ if (rdmsrl_safe(msr[bit].msr, &val)) continue; + + mask = msr[bit].mask; + if (!mask) + mask = ~0ULL; /* Disable zero counters if requested. */ - if (!zero && !val) + if (!zero && !(val & mask)) continue; grp->is_visible = NULL; diff --git a/arch/x86/events/probe.h b/arch/x86/events/probe.h index 4c8e0af..261b9bd 100644 --- a/arch/x86/events/probe.h +++ b/arch/x86/events/probe.h @@ -4,10 +4,11 @@ #include <linux/sysfs.h> struct perf_msr { - u64 msr; - struct attribute_group *grp; + u64 msr; + struct attribute_group *grp; bool (*test)(int idx, void *data); - bool no_check; + bool no_check; + u64 mask; }; unsigned long ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-02-10 14:03 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-02-04 16:18 [PATCH V2 1/3] perf/x86/rapl: Add msr mask support Zhang Rui 2021-02-04 16:18 ` [PATCH V2 2/3] perf/x86/rapl: Only check lower 32bits for RAPL energy counters Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] " tip-bot2 for Zhang Rui 2021-02-04 16:18 ` [PATCH V2 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] " tip-bot2 for Zhang Rui 2021-02-10 13:59 ` [tip: perf/core] perf/x86/rapl: Add msr mask support tip-bot2 for Zhang Rui
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