* [PATCH 0/3] HDMI2.1 PCON Misc Fixes
@ 2021-02-04 6:48 ` Ankit Nautiyal
0 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, dri-devel
Patch1: fixes gitlab issue:
https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Patch2: Tweaks the drm_helpers for PCON configuration
Patch3: Removes unwanted code not applicable for older platforms.
Ankit Nautiyal (3):
i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
i915/display: Remove FRL related code from disable DP sequence for
older platforms
drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++-----
include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
3 files changed, 59 insertions(+), 21 deletions(-)
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 0/3] HDMI2.1 PCON Misc Fixes
@ 2021-02-04 6:48 ` Ankit Nautiyal
0 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Patch1: fixes gitlab issue:
https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Patch2: Tweaks the drm_helpers for PCON configuration
Patch3: Removes unwanted code not applicable for older platforms.
Ankit Nautiyal (3):
i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
i915/display: Remove FRL related code from disable DP sequence for
older platforms
drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++-----
include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
3 files changed, 59 insertions(+), 21 deletions(-)
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-04 6:48 ` Ankit Nautiyal
-1 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, dri-devel
DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
Do not read the registers if DPCD rev < 1.4.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c12d5375607..2b83f0f433a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
/* Clear the cached register set to avoid using stale values */
-
memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
+ if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
+ return;
+
if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
intel_dp->pcon_dsc_dpcd,
sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
--
2.29.2
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-04 6:48 ` Ankit Nautiyal
0 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
Do not read the registers if DPCD rev < 1.4.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c12d5375607..2b83f0f433a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
/* Clear the cached register set to avoid using stale values */
-
memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
+ if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
+ return;
+
if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
intel_dp->pcon_dsc_dpcd,
sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
--
2.29.2
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-04 6:48 ` Ankit Nautiyal
-1 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, dri-devel
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Defines FRL training type and link bring up sequence mode as enum.
-Fixes the drm_helpers for FRL Training configuration to use these enums.
-Modifies the calls to the above drm_helpers in i915/intel_dp as per the
above change.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
3 files changed, 56 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..2ca4ab5af470 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
- * @concurrent_mode: true if concurrent mode or operation is required,
- * false otherwise.
+ * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode)
+ enum dp_pcon_frl_train_mode frl_mode)
{
int ret;
u8 buf;
@@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
if (ret < 0)
return ret;
- if (concurrent_mode)
+ if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT)
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
@@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
- * @extended_train_mode : true for Extended Mode, false for Normal Mode.
- * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
- * from min, and stops when link training is successful. In Extended mode, all
- * frl bw selected in the mask are trained by the PCON.
+ * @frl_type : FRL training type, can be Extended, or Normal.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode)
+ enum dp_pcon_frl_train_type frl_type)
{
int ret;
u8 buf = max_frl_mask;
- if (extended_train_mode)
+ if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED)
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
+ else
+ buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2b83f0f433a2..1962d6dd8641 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
{
-#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
-#define PCON_CONCURRENT_MODE (1 > 0)
-#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
-#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
#define TIMEOUT_FRL_READY_MS 500
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
@@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
return -ETIMEDOUT;
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
- ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
+ ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
+ DP_PCON_FRL_MODE_SEQUENTIAL);
if (ret < 0)
return ret;
- ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
+ ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
+ DP_PCON_FRL_TRAIN_NORMAL);
if (ret < 0)
return ret;
ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..c3f56e87a5ec 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1646,6 +1646,48 @@ enum dp_content_type {
DP_CONTENT_TYPE_GAME = 0x04,
};
+/**
+ * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type
+ *
+ * This enum is used to select FRL training type for FRL training between
+ * an HDMI2.1 PCON and an HDMI2.1 sink.
+ *
+ * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
+ * Sec 6.1 Table-3.
+ * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK
+ * starting from min, and stops when link training is successful.
+ * In Extended FRL training, all frl bw selected in the mask are trained by the
+ * PCON.
+ *
+ * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal
+ * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended
+ */
+enum dp_pcon_frl_train_type {
+ DP_PCON_FRL_TRAIN_NORMAL = 0,
+ DP_PCON_FRL_TRAIN_EXTENDED = 1,
+};
+
+/**
+ * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode
+ *
+ * This enum is used to select mode for FRL Link bringup between an HDMI2.1
+ * PCON and an HDMI2.1 sink.
+ *
+ * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
+ * Sec 6.1 Table-3.
+ * In Concurrent Mode, the FRL link bring up can be done along with DP Link
+ * training. In Sequential mode, the FRL link bring up is done prior to the
+ * DP Link training.
+ *
+ * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode
+ * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode
+ */
+
+enum dp_pcon_frl_train_mode {
+ DP_PCON_FRL_MODE_SEQUENTIAL = 0,
+ DP_PCON_FRL_MODE_CONCURRENT = 1,
+};
+
/**
* struct drm_dp_vsc_sdp - drm DP VSC SDP
*
@@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode);
+ enum dp_pcon_frl_train_mode frl_mode);
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode);
+ enum dp_pcon_frl_train_type frl_type);
int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
--
2.29.2
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
@ 2021-02-04 6:48 ` Ankit Nautiyal
0 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Defines FRL training type and link bring up sequence mode as enum.
-Fixes the drm_helpers for FRL Training configuration to use these enums.
-Modifies the calls to the above drm_helpers in i915/intel_dp as per the
above change.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
3 files changed, 56 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..2ca4ab5af470 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
- * @concurrent_mode: true if concurrent mode or operation is required,
- * false otherwise.
+ * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode)
+ enum dp_pcon_frl_train_mode frl_mode)
{
int ret;
u8 buf;
@@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
if (ret < 0)
return ret;
- if (concurrent_mode)
+ if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT)
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
@@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
- * @extended_train_mode : true for Extended Mode, false for Normal Mode.
- * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
- * from min, and stops when link training is successful. In Extended mode, all
- * frl bw selected in the mask are trained by the PCON.
+ * @frl_type : FRL training type, can be Extended, or Normal.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode)
+ enum dp_pcon_frl_train_type frl_type)
{
int ret;
u8 buf = max_frl_mask;
- if (extended_train_mode)
+ if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED)
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
+ else
+ buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2b83f0f433a2..1962d6dd8641 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
{
-#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
-#define PCON_CONCURRENT_MODE (1 > 0)
-#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
-#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
#define TIMEOUT_FRL_READY_MS 500
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
@@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
return -ETIMEDOUT;
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
- ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
+ ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
+ DP_PCON_FRL_MODE_SEQUENTIAL);
if (ret < 0)
return ret;
- ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
+ ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
+ DP_PCON_FRL_TRAIN_NORMAL);
if (ret < 0)
return ret;
ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..c3f56e87a5ec 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1646,6 +1646,48 @@ enum dp_content_type {
DP_CONTENT_TYPE_GAME = 0x04,
};
+/**
+ * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type
+ *
+ * This enum is used to select FRL training type for FRL training between
+ * an HDMI2.1 PCON and an HDMI2.1 sink.
+ *
+ * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
+ * Sec 6.1 Table-3.
+ * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK
+ * starting from min, and stops when link training is successful.
+ * In Extended FRL training, all frl bw selected in the mask are trained by the
+ * PCON.
+ *
+ * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal
+ * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended
+ */
+enum dp_pcon_frl_train_type {
+ DP_PCON_FRL_TRAIN_NORMAL = 0,
+ DP_PCON_FRL_TRAIN_EXTENDED = 1,
+};
+
+/**
+ * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode
+ *
+ * This enum is used to select mode for FRL Link bringup between an HDMI2.1
+ * PCON and an HDMI2.1 sink.
+ *
+ * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
+ * Sec 6.1 Table-3.
+ * In Concurrent Mode, the FRL link bring up can be done along with DP Link
+ * training. In Sequential mode, the FRL link bring up is done prior to the
+ * DP Link training.
+ *
+ * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode
+ * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode
+ */
+
+enum dp_pcon_frl_train_mode {
+ DP_PCON_FRL_MODE_SEQUENTIAL = 0,
+ DP_PCON_FRL_MODE_CONCURRENT = 1,
+};
+
/**
* struct drm_dp_vsc_sdp - drm DP VSC SDP
*
@@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode);
+ enum dp_pcon_frl_train_mode frl_mode);
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode);
+ enum dp_pcon_frl_train_type frl_type);
int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
--
2.29.2
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-04 6:48 ` Ankit Nautiyal
-1 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, dri-devel
Remove code for resetting frl related members from intel_disable_dp, as
this is not applicable for older platforms.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1962d6dd8641..9d94bdf5f517 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state,
intel_edp_backlight_off(old_conn_state);
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
intel_pps_off(intel_dp);
- intel_dp->frl.is_trained = false;
- intel_dp->frl.trained_rate_gbps = 0;
}
static void g4x_disable_dp(struct intel_atomic_state *state,
--
2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms
@ 2021-02-04 6:48 ` Ankit Nautiyal
0 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-04 6:48 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Remove code for resetting frl related members from intel_disable_dp, as
this is not applicable for older platforms.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1962d6dd8641..9d94bdf5f517 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state,
intel_edp_backlight_off(old_conn_state);
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
intel_pps_off(intel_dp);
- intel_dp->frl.is_trained = false;
- intel_dp->frl.trained_rate_gbps = 0;
}
static void g4x_disable_dp(struct intel_atomic_state *state,
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
` (3 preceding siblings ...)
(?)
@ 2021-02-04 7:34 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-02-04 7:34 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes
URL : https://patchwork.freedesktop.org/series/86677/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1400:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1400:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1400:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1459:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1459:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1459:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:284:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:284:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:284:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:277:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:277:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:277:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:331:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:331:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:331:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:92:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/a
_______________________________________________
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for HDMI2.1 PCON Misc Fixes
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
` (4 preceding siblings ...)
(?)
@ 2021-02-04 8:01 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-02-04 8:01 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3344 bytes --]
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes
URL : https://patchwork.freedesktop.org/series/86677/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9729 -> Patchwork_19583
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/index.html
Known issues
------------
Here are the changes found in Patchwork_19583 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@sync-gfx0.html
* igt@gem_ringfill@basic-all:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/fi-tgl-y/igt@gem_ringfill@basic-all.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/fi-tgl-y/igt@gem_ringfill@basic-all.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][4] ([i915#2411] / [i915#402]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][6] ([i915#2940]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/fi-tgl-y/igt@prime_vgem@basic-userptr.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/fi-tgl-y/igt@prime_vgem@basic-userptr.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 39)
------------------------------
Missing (5): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9729 -> Patchwork_19583
CI-20190529: 20190529
CI_DRM_9729: f5c0d295953da801ec6f504a0b3de020e43b55b4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5989: 57a96840fd5aa7ec48c2f84b30e0420f84ec7386 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19583: 5c5357769b1891aa1a10e74e0867f2e48d24dfed @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5c5357769b18 i915/display: Remove FRL related code from disable DP sequence for older platforms
61ee4530371e drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
5fa4c89ea9a4 i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for HDMI2.1 PCON Misc Fixes
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
` (5 preceding siblings ...)
(?)
@ 2021-02-04 9:38 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-02-04 9:38 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
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== Series Details ==
Series: HDMI2.1 PCON Misc Fixes
URL : https://patchwork.freedesktop.org/series/86677/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9729_full -> Patchwork_19583_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19583_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-glk8/igt@gem_exec_fair@basic-pace@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1610] / [i915#2803])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@gem_exec_schedule@u-fairslice@rcs0.html
- shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([i915#2803])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb2/igt@gem_exec_schedule@u-fairslice@rcs0.html
- shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1610] / [i915#2803])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1610])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-apl2/igt@gem_exec_schedule@u-fairslice@vecs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl8/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl9/igt@gem_huc_copy@huc-copy.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#768])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][17] ([i915#3002])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [INCOMPLETE][18] ([i915#2502] / [i915#2667])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#112306])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-tglb6/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@shadow-peek:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2856])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [PASS][22] -> [FAIL][23] ([i915#1860])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-hsw2/igt@i915_pm_rc6_residency@rc6-idle.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-hsw6/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#110892])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_query@query-topology-unsupported:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#109302])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@i915_query@query-topology-unsupported.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][26] -> [DMESG-WARN][27] ([i915#180])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl6/igt@i915_suspend@debugfs-reader.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl4/igt@i915_suspend@debugfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: NOTRUN -> [FAIL][28] ([i915#2521])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#404])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_joiner@basic:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#2705])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-c-bad-aux-stride:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111304]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@kms_ccs@pipe-c-bad-aux-stride.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +18 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl9/igt@kms_color@pipe-a-ctm-0-75.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl7/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_color@pipe-d-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109278] / [i915#1149])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_color@pipe-d-ctm-max.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-glk: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl8/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding:
- shard-skl: NOTRUN -> [FAIL][40] ([i915#54])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#54]) +10 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [fdo#109279])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_cursor_crc@pipe-c-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109278]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-64x64-rapid-movement.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109274] / [fdo#109278])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][46] ([i915#2346] / [i915#533])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_dp_tiled_display@basic-test-pattern:
- shard-glk: NOTRUN -> [SKIP][48] ([fdo#109271]) +17 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@kms_dp_tiled_display@basic-test-pattern.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109274]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: NOTRUN -> [FAIL][50] ([i915#79])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][51] -> [FAIL][52] ([i915#79]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][53] -> [DMESG-WARN][54] ([i915#180])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#2122]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2672])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271]) +197 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271]) +30 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271]) +26 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][62] -> [FAIL][63] ([i915#1188])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl8/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][66] -> [FAIL][67] ([fdo#108145] / [i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][69] ([i915#265])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][70] ([fdo#112054])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-tglb6/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#658])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-glk: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +5 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl10/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][75] -> [SKIP][76] ([fdo#109642] / [fdo#111068] / [i915#658])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb2/igt@kms_psr2_su@page_flip.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb6/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][77] -> [SKIP][78] ([fdo#109441]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109441])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_psr@psr2_suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-iclb: NOTRUN -> [SKIP][80] ([i915#2437])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2437])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#2530])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@nouveau_crc@pipe-c-source-outp-inactive.html
* igt@perf@blocking:
- shard-skl: NOTRUN -> [FAIL][83] ([i915#1542])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl4/igt@perf@blocking.html
* igt@perf_pmu@event-wait@rcs0:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#112283])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@perf_pmu@event-wait@rcs0.html
* igt@prime_nv_api@i915_nv_double_export:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@prime_nv_api@i915_nv_double_export.html
* igt@sysfs_preempt_timeout@timeout@rcs0:
- shard-skl: [PASS][86] -> [FAIL][87] ([i915#1755])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl1/igt@sysfs_preempt_timeout@timeout@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@sysfs_preempt_timeout@timeout@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-glk: [INCOMPLETE][88] -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-glk3/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][90] ([i915#1895] / [i915#2295] / [i915#3031]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb4/igt@gem_exec_balancer@hang.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb8/igt@gem_exec_balancer@hang.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [FAIL][92] ([i915#2842]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-glk2/igt@gem_exec_fair@basic-none@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-glk6/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][94] ([i915#2842]) -> [PASS][95] +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][98] ([i915#2842]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][100] ([i915#2849]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl: [FAIL][102] ([i915#2389]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-apl4/igt@gem_exec_reloc@basic-many-active@rcs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl7/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-apl: [DMESG-WARN][104] ([i915#1610]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-apl2/igt@gem_exec_schedule@u-fairslice@rcs0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-apl8/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-semaphore-codependency:
- shard-skl: [DMESG-WARN][106] ([i915#1610]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl4/igt@gem_exec_schedule@u-semaphore-codependency.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl10/igt@gem_exec_schedule@u-semaphore-codependency.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][108] ([i915#1436] / [i915#716]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [FAIL][112] ([i915#54]) -> [PASS][113] +4 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-hsw: [FAIL][114] ([i915#2370]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [FAIL][116] ([i915#2122]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [INCOMPLETE][118] ([i915#123] / [i915#1982]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl3/igt@kms_frontbuffer_tracking@psr-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl8/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][120] ([i915#1188]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl8/igt@kms_hdr@bpc-switch.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl2/igt@kms_hdr@bpc-switch.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][122] ([fdo#109441]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* {igt@sysfs_clients@busy@bcs0}:
- shard-skl: [FAIL][124] ([i915#3019]) -> [PASS][125] +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl9/igt@sysfs_clients@busy@bcs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl6/igt@sysfs_clients@busy@bcs0.html
* {igt@sysfs_clients@recycle}:
- shard-hsw: [FAIL][126] ([i915#3028]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-hsw7/igt@sysfs_clients@recycle.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-hsw4/igt@sysfs_clients@recycle.html
- shard-tglb: [FAIL][128] ([i915#3028]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-tglb3/igt@sysfs_clients@recycle.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-tglb3/igt@sysfs_clients@recycle.html
* {igt@sysfs_clients@recycle-many}:
- shard-kbl: [FAIL][130] ([i915#3028]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl4/igt@sysfs_clients@recycle-many.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl1/igt@sysfs_clients@recycle-many.html
* {igt@sysfs_clients@sema-10@rcs0}:
- shard-kbl: [SKIP][132] ([fdo#109271] / [i915#3026]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl6/igt@sysfs_clients@sema-10@rcs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-kbl1/igt@sysfs_clients@sema-10@rcs0.html
* {igt@sysfs_clients@split-10@rcs0}:
- shard-skl: [SKIP][134] ([fdo#109271] / [i915#3026]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-skl1/igt@sysfs_clients@split-10@rcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-skl3/igt@sysfs_clients@split-10@rcs0.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][136] ([i915#2681] / [i915#2684]) -> [WARN][137] ([i915#1804] / [i915#2684])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][138] ([i915#1226]) -> [SKIP][139] ([fdo#109349])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-iclb: [SKIP][140] ([i915#658]) -> [SKIP][141] ([i915#2920]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][142] ([i915#2920]) -> [SKIP][143] ([i915#658]) +2 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([i915#2295] / [i915#3002]) -> ([FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153]) ([i915#2295] / [i915#2426] / [i915#3002])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl4/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl4/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-kbl4/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9729/shard-
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19583/index.html
[-- Attachment #1.2: Type: text/html, Size: 33457 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-05 19:58 ` Ville Syrjälä
-1 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 19:58 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, uma.shankar, dri-devel
On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> Do not read the registers if DPCD rev < 1.4.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c12d5375607..2b83f0f433a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> /* Clear the cached register set to avoid using stale values */
> -
> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
>
> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> + return;
> +
Can't check the spec, but makes sense that this stuff is only valid
for recent DCPD revisions.
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> intel_dp->pcon_dsc_dpcd,
> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> --
> 2.29.2
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-05 19:58 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 19:58 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> Do not read the registers if DPCD rev < 1.4.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c12d5375607..2b83f0f433a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> /* Clear the cached register set to avoid using stale values */
> -
> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
>
> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> + return;
> +
Can't check the spec, but makes sense that this stuff is only valid
for recent DCPD revisions.
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> intel_dp->pcon_dsc_dpcd,
> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> --
> 2.29.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-05 20:00 ` Ville Syrjälä
-1 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 20:00 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, uma.shankar, dri-devel
On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote:
> Currently the FRL training mode (Concurrent, Sequential) and
> training type (Normal, Extended) are not defined properly and
> are passed as bool values in drm_helpers for pcon
> configuration for FRL training.
>
> This patch:
> -Defines FRL training type and link bring up sequence mode as enum.
> -Fixes the drm_helpers for FRL Training configuration to use these enums.
> -Modifies the calls to the above drm_helpers in i915/intel_dp as per the
> above change.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
> include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
> 3 files changed, 56 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index eedbb48815b7..2ca4ab5af470 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
> * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
> * @aux: DisplayPort AUX channel
> * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
> - * @concurrent_mode: true if concurrent mode or operation is required,
> - * false otherwise.
> + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
> *
> * Returns 0 if success, else returns negative error code.
> */
>
> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> - bool concurrent_mode)
> + enum dp_pcon_frl_train_mode frl_mode)
> {
> int ret;
> u8 buf;
> @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> if (ret < 0)
> return ret;
>
> - if (concurrent_mode)
> + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT)
> buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
> else
> buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
> @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
> * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
> * @aux: DisplayPort AUX channel
> * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
> - * @extended_train_mode : true for Extended Mode, false for Normal Mode.
> - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
> - * from min, and stops when link training is successful. In Extended mode, all
> - * frl bw selected in the mask are trained by the PCON.
> + * @frl_type : FRL training type, can be Extended, or Normal.
> *
> * Returns 0 if success, else returns negative error code.
> */
> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
> - bool extended_train_mode)
> + enum dp_pcon_frl_train_type frl_type)
> {
> int ret;
> u8 buf = max_frl_mask;
>
> - if (extended_train_mode)
> + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED)
> buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
> + else
> + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
These names are annoyingly close to each other. Prettu much
guaranteed to mix them up at some point. We should try to come
up something a bit more distinctive for the enum, or just forget
the enum and use the register values directly.
>
> ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
> if (ret < 0)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2b83f0f433a2..1962d6dd8641 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>
> static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
> {
> -#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
> -#define PCON_CONCURRENT_MODE (1 > 0)
> -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
> -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
> #define TIMEOUT_FRL_READY_MS 500
> #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
>
> @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
> return -ETIMEDOUT;
>
> max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
> - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
> + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
> + DP_PCON_FRL_MODE_SEQUENTIAL);
> if (ret < 0)
> return ret;
> - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
> + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
> + DP_PCON_FRL_TRAIN_NORMAL);
> if (ret < 0)
> return ret;
> ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index edffd1dcca3e..c3f56e87a5ec 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1646,6 +1646,48 @@ enum dp_content_type {
> DP_CONTENT_TYPE_GAME = 0x04,
> };
>
> +/**
> + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type
> + *
> + * This enum is used to select FRL training type for FRL training between
> + * an HDMI2.1 PCON and an HDMI2.1 sink.
> + *
> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
> + * Sec 6.1 Table-3.
> + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK
> + * starting from min, and stops when link training is successful.
> + * In Extended FRL training, all frl bw selected in the mask are trained by the
> + * PCON.
> + *
> + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal
> + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended
> + */
> +enum dp_pcon_frl_train_type {
> + DP_PCON_FRL_TRAIN_NORMAL = 0,
> + DP_PCON_FRL_TRAIN_EXTENDED = 1,
> +};
> +
> +/**
> + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode
> + *
> + * This enum is used to select mode for FRL Link bringup between an HDMI2.1
> + * PCON and an HDMI2.1 sink.
> + *
> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
> + * Sec 6.1 Table-3.
> + * In Concurrent Mode, the FRL link bring up can be done along with DP Link
> + * training. In Sequential mode, the FRL link bring up is done prior to the
> + * DP Link training.
> + *
> + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode
> + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode
> + */
> +
> +enum dp_pcon_frl_train_mode {
> + DP_PCON_FRL_MODE_SEQUENTIAL = 0,
> + DP_PCON_FRL_MODE_CONCURRENT = 1,
> +};
> +
> /**
> * struct drm_dp_vsc_sdp - drm DP VSC SDP
> *
> @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
> bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> - bool concurrent_mode);
> + enum dp_pcon_frl_train_mode frl_mode);
> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
> - bool extended_train_mode);
> + enum dp_pcon_frl_train_type frl_type);
> int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
> int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>
> --
> 2.29.2
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
@ 2021-02-05 20:00 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 20:00 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote:
> Currently the FRL training mode (Concurrent, Sequential) and
> training type (Normal, Extended) are not defined properly and
> are passed as bool values in drm_helpers for pcon
> configuration for FRL training.
>
> This patch:
> -Defines FRL training type and link bring up sequence mode as enum.
> -Fixes the drm_helpers for FRL Training configuration to use these enums.
> -Modifies the calls to the above drm_helpers in i915/intel_dp as per the
> above change.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
> include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
> 3 files changed, 56 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index eedbb48815b7..2ca4ab5af470 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
> * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
> * @aux: DisplayPort AUX channel
> * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
> - * @concurrent_mode: true if concurrent mode or operation is required,
> - * false otherwise.
> + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
> *
> * Returns 0 if success, else returns negative error code.
> */
>
> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> - bool concurrent_mode)
> + enum dp_pcon_frl_train_mode frl_mode)
> {
> int ret;
> u8 buf;
> @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> if (ret < 0)
> return ret;
>
> - if (concurrent_mode)
> + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT)
> buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
> else
> buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
> @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
> * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
> * @aux: DisplayPort AUX channel
> * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
> - * @extended_train_mode : true for Extended Mode, false for Normal Mode.
> - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
> - * from min, and stops when link training is successful. In Extended mode, all
> - * frl bw selected in the mask are trained by the PCON.
> + * @frl_type : FRL training type, can be Extended, or Normal.
> *
> * Returns 0 if success, else returns negative error code.
> */
> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
> - bool extended_train_mode)
> + enum dp_pcon_frl_train_type frl_type)
> {
> int ret;
> u8 buf = max_frl_mask;
>
> - if (extended_train_mode)
> + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED)
> buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
> + else
> + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
These names are annoyingly close to each other. Prettu much
guaranteed to mix them up at some point. We should try to come
up something a bit more distinctive for the enum, or just forget
the enum and use the register values directly.
>
> ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
> if (ret < 0)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2b83f0f433a2..1962d6dd8641 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>
> static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
> {
> -#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
> -#define PCON_CONCURRENT_MODE (1 > 0)
> -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
> -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
> #define TIMEOUT_FRL_READY_MS 500
> #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
>
> @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
> return -ETIMEDOUT;
>
> max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
> - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
> + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
> + DP_PCON_FRL_MODE_SEQUENTIAL);
> if (ret < 0)
> return ret;
> - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
> + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
> + DP_PCON_FRL_TRAIN_NORMAL);
> if (ret < 0)
> return ret;
> ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index edffd1dcca3e..c3f56e87a5ec 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1646,6 +1646,48 @@ enum dp_content_type {
> DP_CONTENT_TYPE_GAME = 0x04,
> };
>
> +/**
> + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type
> + *
> + * This enum is used to select FRL training type for FRL training between
> + * an HDMI2.1 PCON and an HDMI2.1 sink.
> + *
> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
> + * Sec 6.1 Table-3.
> + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK
> + * starting from min, and stops when link training is successful.
> + * In Extended FRL training, all frl bw selected in the mask are trained by the
> + * PCON.
> + *
> + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal
> + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended
> + */
> +enum dp_pcon_frl_train_type {
> + DP_PCON_FRL_TRAIN_NORMAL = 0,
> + DP_PCON_FRL_TRAIN_EXTENDED = 1,
> +};
> +
> +/**
> + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode
> + *
> + * This enum is used to select mode for FRL Link bringup between an HDMI2.1
> + * PCON and an HDMI2.1 sink.
> + *
> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
> + * Sec 6.1 Table-3.
> + * In Concurrent Mode, the FRL link bring up can be done along with DP Link
> + * training. In Sequential mode, the FRL link bring up is done prior to the
> + * DP Link training.
> + *
> + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode
> + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode
> + */
> +
> +enum dp_pcon_frl_train_mode {
> + DP_PCON_FRL_MODE_SEQUENTIAL = 0,
> + DP_PCON_FRL_MODE_CONCURRENT = 1,
> +};
> +
> /**
> * struct drm_dp_vsc_sdp - drm DP VSC SDP
> *
> @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
> bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
> - bool concurrent_mode);
> + enum dp_pcon_frl_train_mode frl_mode);
> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
> - bool extended_train_mode);
> + enum dp_pcon_frl_train_type frl_type);
> int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
> int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>
> --
> 2.29.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-05 20:01 ` Ville Syrjälä
-1 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 20:01 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, uma.shankar, dri-devel
On Thu, Feb 04, 2021 at 12:18:42PM +0530, Ankit Nautiyal wrote:
> Remove code for resetting frl related members from intel_disable_dp, as
> this is not applicable for older platforms.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1962d6dd8641..9d94bdf5f517 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state,
> intel_edp_backlight_off(old_conn_state);
> intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
> intel_pps_off(intel_dp);
> - intel_dp->frl.is_trained = false;
> - intel_dp->frl.trained_rate_gbps = 0;
If we don't need it in the ddi path we don't need it here.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> }
>
> static void g4x_disable_dp(struct intel_atomic_state *state,
> --
> 2.29.2
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms
@ 2021-02-05 20:01 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 20:01 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Feb 04, 2021 at 12:18:42PM +0530, Ankit Nautiyal wrote:
> Remove code for resetting frl related members from intel_disable_dp, as
> this is not applicable for older platforms.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1962d6dd8641..9d94bdf5f517 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2387,8 +2387,6 @@ static void intel_disable_dp(struct intel_atomic_state *state,
> intel_edp_backlight_off(old_conn_state);
> intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
> intel_pps_off(intel_dp);
> - intel_dp->frl.is_trained = false;
> - intel_dp->frl.trained_rate_gbps = 0;
If we don't need it in the ddi path we don't need it here.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> }
>
> static void g4x_disable_dp(struct intel_atomic_state *state,
> --
> 2.29.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-05 20:07 ` Navare, Manasi
@ 2021-02-05 20:06 ` Ville Syrjälä
-1 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 20:06 UTC (permalink / raw)
To: Navare, Manasi; +Cc: Ankit Nautiyal, intel-gfx, dri-devel
On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote:
> On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > > Do not read the registers if DPCD rev < 1.4.
> > >
> > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 8c12d5375607..2b83f0f433a2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > >
> > > /* Clear the cached register set to avoid using stale values */
> > > -
> > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> > >
> > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> > > + return;
> > > +
> >
> > Can't check the spec, but makes sense that this stuff is only valid
> > for recent DCPD revisions.
> >
> > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Yes checked the DP 1.4 spec and this is correct
I didn't think this is in the DP spec, but rather some special extra
spec which I do not have.
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Manasi
>
> >
> > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> > > intel_dp->pcon_dsc_dpcd,
> > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> > > --
> > > 2.29.2
> >
> > --
> > Ville Syrjälä
> > Intel
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-05 20:06 ` Ville Syrjälä
0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2021-02-05 20:06 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx, dri-devel
On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote:
> On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > > Do not read the registers if DPCD rev < 1.4.
> > >
> > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 8c12d5375607..2b83f0f433a2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > >
> > > /* Clear the cached register set to avoid using stale values */
> > > -
> > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> > >
> > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> > > + return;
> > > +
> >
> > Can't check the spec, but makes sense that this stuff is only valid
> > for recent DCPD revisions.
> >
> > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Yes checked the DP 1.4 spec and this is correct
I didn't think this is in the DP spec, but rather some special extra
spec which I do not have.
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Manasi
>
> >
> > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> > > intel_dp->pcon_dsc_dpcd,
> > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> > > --
> > > 2.29.2
> >
> > --
> > Ville Syrjälä
> > Intel
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-05 19:58 ` [Intel-gfx] " Ville Syrjälä
@ 2021-02-05 20:07 ` Navare, Manasi
-1 siblings, 0 replies; 36+ messages in thread
From: Navare, Manasi @ 2021-02-05 20:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Ankit Nautiyal, intel-gfx, dri-devel
On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > Do not read the registers if DPCD rev < 1.4.
> >
> > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8c12d5375607..2b83f0f433a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > /* Clear the cached register set to avoid using stale values */
> > -
> > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> >
> > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> > + return;
> > +
>
> Can't check the spec, but makes sense that this stuff is only valid
> for recent DCPD revisions.
>
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Yes checked the DP 1.4 spec and this is correct
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> > intel_dp->pcon_dsc_dpcd,
> > sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> > --
> > 2.29.2
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-05 20:07 ` Navare, Manasi
0 siblings, 0 replies; 36+ messages in thread
From: Navare, Manasi @ 2021-02-05 20:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > Do not read the registers if DPCD rev < 1.4.
> >
> > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8c12d5375607..2b83f0f433a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > /* Clear the cached register set to avoid using stale values */
> > -
> > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> >
> > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> > + return;
> > +
>
> Can't check the spec, but makes sense that this stuff is only valid
> for recent DCPD revisions.
>
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Yes checked the DP 1.4 spec and this is correct
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> > intel_dp->pcon_dsc_dpcd,
> > sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> > --
> > 2.29.2
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-05 20:06 ` Ville Syrjälä
@ 2021-02-05 20:22 ` Navare, Manasi
-1 siblings, 0 replies; 36+ messages in thread
From: Navare, Manasi @ 2021-02-05 20:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Ankit Nautiyal, intel-gfx, dri-devel
On Fri, Feb 05, 2021 at 10:06:48PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote:
> > On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > > > Do not read the registers if DPCD rev < 1.4.
> > > >
> > > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 8c12d5375607..2b83f0f433a2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > >
> > > > /* Clear the cached register set to avoid using stale values */
> > > > -
> > > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> > > >
> > > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> > > > + return;
> > > > +
> > >
> > > Can't check the spec, but makes sense that this stuff is only valid
> > > for recent DCPD revisions.
> > >
> > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Yes checked the DP 1.4 spec and this is correct
>
> I didn't think this is in the DP spec, but rather some special extra
> spec which I do not have.
Yes I meant just double checked that the DSC support itself from DP 1.4 and hence
makes sense that the PCON DSC regs also from >= 1.4
Manasi
>
> >
> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >
> > Manasi
> >
> > >
> > > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> > > > intel_dp->pcon_dsc_dpcd,
> > > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> > > > --
> > > > 2.29.2
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-05 20:22 ` Navare, Manasi
0 siblings, 0 replies; 36+ messages in thread
From: Navare, Manasi @ 2021-02-05 20:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Fri, Feb 05, 2021 at 10:06:48PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote:
> > On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > > > Do not read the registers if DPCD rev < 1.4.
> > > >
> > > > Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> > > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> > > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 8c12d5375607..2b83f0f433a2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > >
> > > > /* Clear the cached register set to avoid using stale values */
> > > > -
> > > > memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
> > > >
> > > > + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> > > > + return;
> > > > +
> > >
> > > Can't check the spec, but makes sense that this stuff is only valid
> > > for recent DCPD revisions.
> > >
> > > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Yes checked the DP 1.4 spec and this is correct
>
> I didn't think this is in the DP spec, but rather some special extra
> spec which I do not have.
Yes I meant just double checked that the DSC support itself from DP 1.4 and hence
makes sense that the PCON DSC regs also from >= 1.4
Manasi
>
> >
> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >
> > Manasi
> >
> > >
> > > > if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> > > > intel_dp->pcon_dsc_dpcd,
> > > > sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
> > > > --
> > > > 2.29.2
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-08 11:15 ` Jani Nikula
-1 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-02-08 11:15 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx; +Cc: uma.shankar, dri-devel
On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> Do not read the registers if DPCD rev < 1.4.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Please use Fixes: to reference commits that this patch fixes.
Please use Closes: to reference issues that this patch fixes.
No need to resend for this, can be fixed while applying, but please tell
me the commit that introduced the problem.
BR,
Jani.
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c12d5375607..2b83f0f433a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> /* Clear the cached register set to avoid using stale values */
> -
> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
>
> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> + return;
> +
> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> intel_dp->pcon_dsc_dpcd,
> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-08 11:15 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2021-02-08 11:15 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx; +Cc: dri-devel
On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> Do not read the registers if DPCD rev < 1.4.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
Please use Fixes: to reference commits that this patch fixes.
Please use Closes: to reference issues that this patch fixes.
No need to resend for this, can be fixed while applying, but please tell
me the commit that introduced the problem.
BR,
Jani.
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8c12d5375607..2b83f0f433a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> /* Clear the cached register set to avoid using stale values */
> -
> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
>
> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
> + return;
> +
> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
> intel_dp->pcon_dsc_dpcd,
> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-08 11:15 ` [Intel-gfx] " Jani Nikula
@ 2021-02-08 11:44 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 36+ messages in thread
From: Nautiyal, Ankit K @ 2021-02-08 11:44 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: uma.shankar, dri-devel
On 2/8/2021 4:45 PM, Jani Nikula wrote:
> On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
>> Do not read the registers if DPCD rev < 1.4.
>>
>> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> Please use Fixes: to reference commits that this patch fixes.
>
> Please use Closes: to reference issues that this patch fixes.
>
> No need to resend for this, can be fixed while applying, but please tell
> me the commit that introduced the problem.
>
> BR,
> Jani.
>
Alright will take care. Please find below the commit that introduced this:
b9d96dacdc3d983eae234b52401edb56dbceb764
Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
https://patchwork.freedesktop.org/patch/408779/
Thanks & Regards,
Ankit
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 8c12d5375607..2b83f0f433a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>
>> /* Clear the cached register set to avoid using stale values */
>> -
>> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
>>
>> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
>> + return;
>> +
>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
>> intel_dp->pcon_dsc_dpcd,
>> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-02-08 11:44 ` Nautiyal, Ankit K
0 siblings, 0 replies; 36+ messages in thread
From: Nautiyal, Ankit K @ 2021-02-08 11:44 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: dri-devel
On 2/8/2021 4:45 PM, Jani Nikula wrote:
> On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
>> Do not read the registers if DPCD rev < 1.4.
>>
>> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> Please use Fixes: to reference commits that this patch fixes.
>
> Please use Closes: to reference issues that this patch fixes.
>
> No need to resend for this, can be fixed while applying, but please tell
> me the commit that introduced the problem.
>
> BR,
> Jani.
>
Alright will take care. Please find below the commit that introduced this:
b9d96dacdc3d983eae234b52401edb56dbceb764
Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
https://patchwork.freedesktop.org/patch/408779/
Thanks & Regards,
Ankit
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 8c12d5375607..2b83f0f433a2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>
>> /* Clear the cached register set to avoid using stale values */
>> -
>> memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
>>
>> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
>> + return;
>> +
>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
>> intel_dp->pcon_dsc_dpcd,
>> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v2 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
@ 2021-02-11 6:43 ` Ankit Nautiyal
-1 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-11 6:43 UTC (permalink / raw)
To: intel-gfx; +Cc: airlied, uma.shankar, dri-devel
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Add register masks for Sequential and Normal FRL training options.
-Fixes the drm_helpers for FRL Training configuration to use the
appropriate masks.
-Modifies the calls to the above drm_helpers in i915/intel_dp as per
the above change.
v2: Re-used the register masks for these options, instead of enum. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 24 ++++++++++++++----------
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------
include/drm/drm_dp_helper.h | 6 ++++--
3 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..cb2f53e56685 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
- * @concurrent_mode: true if concurrent mode or operation is required,
- * false otherwise.
+ * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
+ * In Concurrent Mode, the FRL link bring up can be done along with
+ * DP Link training. In Sequential mode, the FRL link bring up is done prior to
+ * the DP Link training.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode)
+ u8 frl_mode)
{
int ret;
u8 buf;
@@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
if (ret < 0)
return ret;
- if (concurrent_mode)
+ if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
@@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
- * @extended_train_mode : true for Extended Mode, false for Normal Mode.
- * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
- * from min, and stops when link training is successful. In Extended mode, all
- * frl bw selected in the mask are trained by the PCON.
+ * @frl_type : FRL training type, can be Extended, or Normal.
+ * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
+ * starting from min, and stops when link training is successful. In Extended
+ * FRL training, all frl bw selected in the mask are trained by the PCON.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode)
+ u8 frl_type)
{
int ret;
u8 buf = max_frl_mask;
- if (extended_train_mode)
+ if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
+ else
+ buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 61beeb3161e2..510c6b442c1b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2559,10 +2559,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
{
-#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
-#define PCON_CONCURRENT_MODE (1 > 0)
-#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
-#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
#define TIMEOUT_FRL_READY_MS 500
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
@@ -2596,10 +2592,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
return -ETIMEDOUT;
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
- ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
+ ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
+ DP_PCON_ENABLE_SEQUENTIAL_LINK);
if (ret < 0)
return ret;
- ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
+ ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
+ DP_PCON_FRL_LINK_TRAIN_NORMAL);
if (ret < 0)
return ret;
ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..f1c7e09728d4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1171,6 +1171,7 @@ struct drm_device;
# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
+# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
# define DP_PCON_ENABLE_HPD_READY (1 << 6)
# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
@@ -1185,6 +1186,7 @@ struct drm_device;
# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
+# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
/* PCON HDMI LINK STATUS */
#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
@@ -2149,9 +2151,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode);
+ u8 frl_mode);
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode);
+ u8 frl_type);
int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
--
2.29.2
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
@ 2021-02-11 6:43 ` Ankit Nautiyal
0 siblings, 0 replies; 36+ messages in thread
From: Ankit Nautiyal @ 2021-02-11 6:43 UTC (permalink / raw)
To: intel-gfx; +Cc: airlied, dri-devel
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Add register masks for Sequential and Normal FRL training options.
-Fixes the drm_helpers for FRL Training configuration to use the
appropriate masks.
-Modifies the calls to the above drm_helpers in i915/intel_dp as per
the above change.
v2: Re-used the register masks for these options, instead of enum. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 24 ++++++++++++++----------
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++------
include/drm/drm_dp_helper.h | 6 ++++--
3 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..cb2f53e56685 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
- * @concurrent_mode: true if concurrent mode or operation is required,
- * false otherwise.
+ * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
+ * In Concurrent Mode, the FRL link bring up can be done along with
+ * DP Link training. In Sequential mode, the FRL link bring up is done prior to
+ * the DP Link training.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode)
+ u8 frl_mode)
{
int ret;
u8 buf;
@@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
if (ret < 0)
return ret;
- if (concurrent_mode)
+ if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
@@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
- * @extended_train_mode : true for Extended Mode, false for Normal Mode.
- * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
- * from min, and stops when link training is successful. In Extended mode, all
- * frl bw selected in the mask are trained by the PCON.
+ * @frl_type : FRL training type, can be Extended, or Normal.
+ * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
+ * starting from min, and stops when link training is successful. In Extended
+ * FRL training, all frl bw selected in the mask are trained by the PCON.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode)
+ u8 frl_type)
{
int ret;
u8 buf = max_frl_mask;
- if (extended_train_mode)
+ if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
+ else
+ buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 61beeb3161e2..510c6b442c1b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2559,10 +2559,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
{
-#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
-#define PCON_CONCURRENT_MODE (1 > 0)
-#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
-#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
#define TIMEOUT_FRL_READY_MS 500
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
@@ -2596,10 +2592,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
return -ETIMEDOUT;
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
- ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
+ ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
+ DP_PCON_ENABLE_SEQUENTIAL_LINK);
if (ret < 0)
return ret;
- ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
+ ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
+ DP_PCON_FRL_LINK_TRAIN_NORMAL);
if (ret < 0)
return ret;
ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..f1c7e09728d4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1171,6 +1171,7 @@ struct drm_device;
# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
+# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
# define DP_PCON_ENABLE_HPD_READY (1 << 6)
# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
@@ -1185,6 +1186,7 @@ struct drm_device;
# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
+# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
/* PCON HDMI LINK STATUS */
#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
@@ -2149,9 +2151,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode);
+ u8 frl_mode);
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode);
+ u8 frl_type);
int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
--
2.29.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
2021-02-05 20:00 ` [Intel-gfx] " Ville Syrjälä
@ 2021-02-11 6:56 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 36+ messages in thread
From: Nautiyal, Ankit K @ 2021-02-11 6:56 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, uma.shankar, dri-devel
On 2/6/2021 1:30 AM, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote:
>> Currently the FRL training mode (Concurrent, Sequential) and
>> training type (Normal, Extended) are not defined properly and
>> are passed as bool values in drm_helpers for pcon
>> configuration for FRL training.
>>
>> This patch:
>> -Defines FRL training type and link bring up sequence mode as enum.
>> -Fixes the drm_helpers for FRL Training configuration to use these enums.
>> -Modifies the calls to the above drm_helpers in i915/intel_dp as per the
>> above change.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
>> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
>> include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
>> 3 files changed, 56 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index eedbb48815b7..2ca4ab5af470 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
>> * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
>> * @aux: DisplayPort AUX channel
>> * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
>> - * @concurrent_mode: true if concurrent mode or operation is required,
>> - * false otherwise.
>> + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
>> *
>> * Returns 0 if success, else returns negative error code.
>> */
>>
>> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> - bool concurrent_mode)
>> + enum dp_pcon_frl_train_mode frl_mode)
>> {
>> int ret;
>> u8 buf;
>> @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> if (ret < 0)
>> return ret;
>>
>> - if (concurrent_mode)
>> + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT)
>> buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
>> else
>> buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
>> @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
>> * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
>> * @aux: DisplayPort AUX channel
>> * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
>> - * @extended_train_mode : true for Extended Mode, false for Normal Mode.
>> - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
>> - * from min, and stops when link training is successful. In Extended mode, all
>> - * frl bw selected in the mask are trained by the PCON.
>> + * @frl_type : FRL training type, can be Extended, or Normal.
>> *
>> * Returns 0 if success, else returns negative error code.
>> */
>> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
>> - bool extended_train_mode)
>> + enum dp_pcon_frl_train_type frl_type)
>> {
>> int ret;
>> u8 buf = max_frl_mask;
>>
>> - if (extended_train_mode)
>> + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED)
>> buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
>> + else
>> + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
> These names are annoyingly close to each other. Prettu much
> guaranteed to mix them up at some point. We should try to come
> up something a bit more distinctive for the enum, or just forget
> the enum and use the register values directly.
Agreed. Sent next version of the patch, dropping the enum and used only
appropriate register values.
Thanks & Regards,
Ankit
>>
>> ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
>> if (ret < 0)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2b83f0f433a2..1962d6dd8641 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>>
>> static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
>> {
>> -#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
>> -#define PCON_CONCURRENT_MODE (1 > 0)
>> -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
>> -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
>> #define TIMEOUT_FRL_READY_MS 500
>> #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
>>
>> @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
>> return -ETIMEDOUT;
>>
>> max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
>> - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
>> + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
>> + DP_PCON_FRL_MODE_SEQUENTIAL);
>> if (ret < 0)
>> return ret;
>> - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
>> + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
>> + DP_PCON_FRL_TRAIN_NORMAL);
>> if (ret < 0)
>> return ret;
>> ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index edffd1dcca3e..c3f56e87a5ec 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -1646,6 +1646,48 @@ enum dp_content_type {
>> DP_CONTENT_TYPE_GAME = 0x04,
>> };
>>
>> +/**
>> + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type
>> + *
>> + * This enum is used to select FRL training type for FRL training between
>> + * an HDMI2.1 PCON and an HDMI2.1 sink.
>> + *
>> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
>> + * Sec 6.1 Table-3.
>> + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK
>> + * starting from min, and stops when link training is successful.
>> + * In Extended FRL training, all frl bw selected in the mask are trained by the
>> + * PCON.
>> + *
>> + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal
>> + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended
>> + */
>> +enum dp_pcon_frl_train_type {
>> + DP_PCON_FRL_TRAIN_NORMAL = 0,
>> + DP_PCON_FRL_TRAIN_EXTENDED = 1,
>> +};
>> +
>> +/**
>> + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode
>> + *
>> + * This enum is used to select mode for FRL Link bringup between an HDMI2.1
>> + * PCON and an HDMI2.1 sink.
>> + *
>> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
>> + * Sec 6.1 Table-3.
>> + * In Concurrent Mode, the FRL link bring up can be done along with DP Link
>> + * training. In Sequential mode, the FRL link bring up is done prior to the
>> + * DP Link training.
>> + *
>> + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode
>> + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode
>> + */
>> +
>> +enum dp_pcon_frl_train_mode {
>> + DP_PCON_FRL_MODE_SEQUENTIAL = 0,
>> + DP_PCON_FRL_MODE_CONCURRENT = 1,
>> +};
>> +
>> /**
>> * struct drm_dp_vsc_sdp - drm DP VSC SDP
>> *
>> @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>> int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
>> bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
>> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> - bool concurrent_mode);
>> + enum dp_pcon_frl_train_mode frl_mode);
>> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
>> - bool extended_train_mode);
>> + enum dp_pcon_frl_train_type frl_type);
>> int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
>> int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>>
>> --
>> 2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
@ 2021-02-11 6:56 ` Nautiyal, Ankit K
0 siblings, 0 replies; 36+ messages in thread
From: Nautiyal, Ankit K @ 2021-02-11 6:56 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On 2/6/2021 1:30 AM, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote:
>> Currently the FRL training mode (Concurrent, Sequential) and
>> training type (Normal, Extended) are not defined properly and
>> are passed as bool values in drm_helpers for pcon
>> configuration for FRL training.
>>
>> This patch:
>> -Defines FRL training type and link bring up sequence mode as enum.
>> -Fixes the drm_helpers for FRL Training configuration to use these enums.
>> -Modifies the calls to the above drm_helpers in i915/intel_dp as per the
>> above change.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 18 +++++-----
>> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++---
>> include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++--
>> 3 files changed, 56 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index eedbb48815b7..2ca4ab5af470 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
>> * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
>> * @aux: DisplayPort AUX channel
>> * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
>> - * @concurrent_mode: true if concurrent mode or operation is required,
>> - * false otherwise.
>> + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
>> *
>> * Returns 0 if success, else returns negative error code.
>> */
>>
>> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> - bool concurrent_mode)
>> + enum dp_pcon_frl_train_mode frl_mode)
>> {
>> int ret;
>> u8 buf;
>> @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> if (ret < 0)
>> return ret;
>>
>> - if (concurrent_mode)
>> + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT)
>> buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
>> else
>> buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
>> @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
>> * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
>> * @aux: DisplayPort AUX channel
>> * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
>> - * @extended_train_mode : true for Extended Mode, false for Normal Mode.
>> - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
>> - * from min, and stops when link training is successful. In Extended mode, all
>> - * frl bw selected in the mask are trained by the PCON.
>> + * @frl_type : FRL training type, can be Extended, or Normal.
>> *
>> * Returns 0 if success, else returns negative error code.
>> */
>> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
>> - bool extended_train_mode)
>> + enum dp_pcon_frl_train_type frl_type)
>> {
>> int ret;
>> u8 buf = max_frl_mask;
>>
>> - if (extended_train_mode)
>> + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED)
>> buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
>> + else
>> + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
> These names are annoyingly close to each other. Prettu much
> guaranteed to mix them up at some point. We should try to come
> up something a bit more distinctive for the enum, or just forget
> the enum and use the register values directly.
Agreed. Sent next version of the patch, dropping the enum and used only
appropriate register values.
Thanks & Regards,
Ankit
>>
>> ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
>> if (ret < 0)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 2b83f0f433a2..1962d6dd8641 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>>
>> static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
>> {
>> -#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
>> -#define PCON_CONCURRENT_MODE (1 > 0)
>> -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
>> -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
>> #define TIMEOUT_FRL_READY_MS 500
>> #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
>>
>> @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
>> return -ETIMEDOUT;
>>
>> max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
>> - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
>> + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
>> + DP_PCON_FRL_MODE_SEQUENTIAL);
>> if (ret < 0)
>> return ret;
>> - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
>> + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
>> + DP_PCON_FRL_TRAIN_NORMAL);
>> if (ret < 0)
>> return ret;
>> ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index edffd1dcca3e..c3f56e87a5ec 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -1646,6 +1646,48 @@ enum dp_content_type {
>> DP_CONTENT_TYPE_GAME = 0x04,
>> };
>>
>> +/**
>> + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type
>> + *
>> + * This enum is used to select FRL training type for FRL training between
>> + * an HDMI2.1 PCON and an HDMI2.1 sink.
>> + *
>> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
>> + * Sec 6.1 Table-3.
>> + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK
>> + * starting from min, and stops when link training is successful.
>> + * In Extended FRL training, all frl bw selected in the mask are trained by the
>> + * PCON.
>> + *
>> + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal
>> + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended
>> + */
>> +enum dp_pcon_frl_train_type {
>> + DP_PCON_FRL_TRAIN_NORMAL = 0,
>> + DP_PCON_FRL_TRAIN_EXTENDED = 1,
>> +};
>> +
>> +/**
>> + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode
>> + *
>> + * This enum is used to select mode for FRL Link bringup between an HDMI2.1
>> + * PCON and an HDMI2.1 sink.
>> + *
>> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification
>> + * Sec 6.1 Table-3.
>> + * In Concurrent Mode, the FRL link bring up can be done along with DP Link
>> + * training. In Sequential mode, the FRL link bring up is done prior to the
>> + * DP Link training.
>> + *
>> + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode
>> + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode
>> + */
>> +
>> +enum dp_pcon_frl_train_mode {
>> + DP_PCON_FRL_MODE_SEQUENTIAL = 0,
>> + DP_PCON_FRL_MODE_CONCURRENT = 1,
>> +};
>> +
>> /**
>> * struct drm_dp_vsc_sdp - drm DP VSC SDP
>> *
>> @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>> int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
>> bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
>> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
>> - bool concurrent_mode);
>> + enum dp_pcon_frl_train_mode frl_mode);
>> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
>> - bool extended_train_mode);
>> + enum dp_pcon_frl_train_type frl_type);
>> int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
>> int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
>>
>> --
>> 2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes (rev2)
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
` (6 preceding siblings ...)
(?)
@ 2021-02-11 7:38 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-02-11 7:38 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes (rev2)
URL : https://patchwork.freedesktop.org/series/86677/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1399:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1400:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1400:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1400:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1459:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1459:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1459:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:284:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:284:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:284:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:277:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:277:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:277:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:331:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:331:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:331:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:92:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/a
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for HDMI2.1 PCON Misc Fixes (rev2)
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
` (7 preceding siblings ...)
(?)
@ 2021-02-11 8:05 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-02-11 8:05 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3025 bytes --]
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes (rev2)
URL : https://patchwork.freedesktop.org/series/86677/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9761 -> Patchwork_19658
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/index.html
Known issues
------------
Here are the changes found in Patchwork_19658 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/fi-tgl-y/igt@gem_mmap_gtt@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/fi-tgl-y/igt@gem_mmap_gtt@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][3] -> [INCOMPLETE][4] ([i915#142] / [i915#2405])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@runner@aborted:
- fi-byt-j1900: NOTRUN -> [FAIL][5] ([i915#1814] / [i915#2505])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/fi-byt-j1900/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 39)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9761 -> Patchwork_19658
CI-20190529: 20190529
CI_DRM_9761: fc52fc2a7332bd301f802ca3a0444a8fb9fe4f7f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6001: d0d6f5e14ef181c93e4b503b05d9c18fa480e09d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19658: bca376cff954e27b863d6eb0c6f93893a9a370a2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bca376cff954 i915/display: Remove FRL related code from disable DP sequence for older platforms
32f0512988b4 drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
3a1860f8a654 i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/index.html
[-- Attachment #1.2: Type: text/html, Size: 3787 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for HDMI2.1 PCON Misc Fixes (rev2)
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
` (8 preceding siblings ...)
(?)
@ 2021-02-11 13:33 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2021-02-11 13:33 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30253 bytes --]
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes (rev2)
URL : https://patchwork.freedesktop.org/series/86677/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9761_full -> Patchwork_19658_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19658_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19658_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19658_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb5/igt@gem_ctx_persistence@many-contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
* igt@kms_cursor_legacy@pipe-a-torture-bo:
- shard-glk: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk2/igt@kms_cursor_legacy@pipe-a-torture-bo.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk7/igt@kms_cursor_legacy@pipe-a-torture-bo.html
Known issues
------------
Here are the changes found in Patchwork_19658_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][5] ([i915#3002])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl8/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +36 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl8/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_schedule@u-fairslice@bcs0:
- shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#2803])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb7/igt@gem_exec_schedule@u-fairslice@bcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb8/igt@gem_exec_schedule@u-fairslice@bcs0.html
* igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#112306])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-oversize:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#2527])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@gen9_exec_parse@bb-oversize.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#1902])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@i915_pm_lpsp@screens-disabled.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl1/igt@i915_suspend@sysfs-reader.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_chamelium@dp-hpd-fast:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb8/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-c-ctm-negative:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl5/igt@kms_color_chamelium@pipe-c-ctm-negative.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109278] / [fdo#109279])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
- shard-skl: [PASS][24] -> [FAIL][25] ([i915#54]) +5 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#72])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][28] -> [INCOMPLETE][29] ([i915#155] / [i915#180] / [i915#636])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@absolute-wf_vblank@a-edp1:
- shard-skl: [PASS][30] -> [DMESG-WARN][31] ([i915#1982])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl2/igt@kms_flip@absolute-wf_vblank@a-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl1/igt@kms_flip@absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][32] -> [FAIL][33] ([i915#2598])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-apl: NOTRUN -> [FAIL][34] ([i915#2641])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109280]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [PASS][36] -> [DMESG-WARN][37] ([i915#180]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][38] ([fdo#108145] / [i915#265])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@kms_plane_lowres@pipe-d-tiling-x.html
* igt@kms_psr2_su@frontbuffer:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#658]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl5/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][43] -> [DMESG-WARN][44] ([i915#180] / [i915#295])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: [PASS][45] -> [INCOMPLETE][46] ([i915#146] / [i915#198] / [i915#2828])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271]) +16 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@prime_nv_api@i915_self_import_to_different_fd:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109291])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@prime_nv_api@i915_self_import_to_different_fd.html
* igt@sysfs_clients@split-25@vcs0:
- shard-skl: [PASS][49] -> [SKIP][50] ([fdo#109271]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl2/igt@sysfs_clients@split-25@vcs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl1/igt@sysfs_clients@split-25@vcs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-glk: [TIMEOUT][51] ([i915#2918]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk9/igt@gem_ctx_persistence@close-replace-race.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk9/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][53] ([i915#1037] / [i915#3063]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb3/igt@gem_eio@unwedge-stress.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb3/igt@gem_eio@unwedge-stress.html
- shard-iclb: [TIMEOUT][55] ([i915#1037] / [i915#2481]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb8/igt@gem_eio@unwedge-stress.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][57] ([i915#2842]) -> [PASS][58] +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [SKIP][59] ([fdo#109271]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][61] ([i915#2842]) -> [PASS][62] +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][63] ([i915#2842]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [DMESG-WARN][65] ([i915#2803]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@gem_exec_schedule@u-fairslice@rcs0.html
- shard-tglb: [DMESG-WARN][67] ([i915#2803]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb7/igt@gem_exec_schedule@u-fairslice@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb8/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_sync@basic-each:
- shard-apl: [INCOMPLETE][69] ([i915#2944]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl3/igt@gem_sync@basic-each.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@gem_sync@basic-each.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [TIMEOUT][71] ([i915#2795]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb8/igt@gem_vm_create@destroy-race.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb8/igt@gem_vm_create@destroy-race.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][73] ([i915#1436] / [i915#716]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl4/igt@gen9_exec_parse@allowed-single.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: [INCOMPLETE][75] ([i915#146] / [i915#151]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl1/igt@i915_pm_rpm@system-suspend-modeset.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl5/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [DMESG-WARN][77] ([i915#1982]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl10/igt@kms_color@pipe-a-ctm-0-75.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl6/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-skl: [FAIL][79] ([i915#54]) -> [PASS][80] +6 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [FAIL][81] ([i915#2346]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1:
- shard-skl: [FAIL][83] ([i915#2122]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl10/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk: [FAIL][85] ([i915#79]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html
* igt@kms_hdr@bpc-switch:
- shard-kbl: [DMESG-WARN][87] ([i915#180] / [i915#78]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl2/igt@kms_hdr@bpc-switch.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl7/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][89] ([fdo#108145] / [i915#265]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][91] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][93] ([fdo#109441]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* {igt@sysfs_clients@recycle-many}:
- shard-skl: [FAIL][95] ([i915#3028]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl3/igt@sysfs_clients@recycle-many.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl2/igt@sysfs_clients@recycle-many.html
* igt@testdisplay:
- shard-kbl: [DMESG-WARN][97] ([i915#165] / [i915#180] / [i915#78]) -> [PASS][98] +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl2/igt@testdisplay.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl7/igt@testdisplay.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][99] ([i915#2842]) -> [FAIL][100] ([i915#2852])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [FAIL][101] ([i915#2876]) -> [FAIL][102] ([i915#2842])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][103] ([i915#658]) -> [SKIP][104] ([i915#588])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][105] ([i915#2684]) -> [WARN][106] ([i915#2681] / [i915#2684])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][107] ([i915#2684]) -> [WARN][108] ([i915#1804] / [i915#2684])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-kbl: [DMESG-FAIL][109] ([i915#165]) -> [FAIL][110] ([i915#2641])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][111] ([i915#658]) -> [SKIP][112] ([i915#2920]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][113] ([i915#2920]) -> [SKIP][114] ([i915#658]) +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][115], [FAIL][116], [FAIL][117]) ([i915#2295] / [i915#3002]) -> ([FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125]) ([i915#1814] / [i915#2292] / [i915#2295] / [i915#2505] / [i915#3002] / [i915#602] / [i915#92])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl2/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl2/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl4/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl6/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl3/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-kbl4/igt@runner@aborted.html
- shard-iclb: ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][130], [FAIL][131], [FAIL][132]) ([i915#2295] / [i915#2724] / [i915#3002])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb2/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb2/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-iclb6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb3/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb6/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-iclb3/igt@runner@aborted.html
- shard-apl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1610] / [i915#1814] / [i915#2295] / [i915#2722] / [i915#3002] / [i915#62]) -> ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([fdo#109271] / [i915#1814] / [i915#2295] / [i915#3002])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl2/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-apl3/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl3/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl8/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl8/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl8/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-apl1/igt@runner@aborted.html
- shard-glk: ([FAIL][148], [FAIL][149], [FAIL][150]) ([i915#2295] / [i915#3002] / [k.org#202321]) -> ([FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154]) ([i915#1814] / [i915#2295] / [i915#3002] / [k.org#202321])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk5/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk4/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-glk7/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk6/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk7/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk7/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-glk1/igt@runner@aborted.html
- shard-skl: ([FAIL][155], [FAIL][156], [FAIL][157]) ([i915#1436] / [i915#2295] / [i915#3002]) -> ([FAIL][158], [FAIL][159], [FAIL][160]) ([i915#2295] / [i915#3002])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl4/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl9/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9761/shard-skl1/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl7/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl9/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/shard-skl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19658/index.html
[-- Attachment #1.2: Type: text/html, Size: 34571 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
2021-02-08 11:44 ` [Intel-gfx] " Nautiyal, Ankit K
@ 2021-03-09 4:28 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 36+ messages in thread
From: Nautiyal, Ankit K @ 2021-03-09 4:28 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: uma.shankar, dri-devel
As I realized, this patch is mixing DPCD rev and DP version, need an
appropriate check instead.
As for the gitlab issue
https://gitlab.freedesktop.org/drm/intel/-/issues/2868 this seems to be
not due to a DPCD register not defined for an older sink.
The DPCD read in that case should have been 0, instead of timeout.
I will drop this patch for now, from the series and revisit it later.
Thanks & Regards,
Ankit
On 2/8/2021 5:14 PM, Nautiyal, Ankit K wrote:
>
> On 2/8/2021 4:45 PM, Jani Nikula wrote:
>> On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
>>> Do not read the registers if DPCD rev < 1.4.
>>>
>>> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
>> Please use Fixes: to reference commits that this patch fixes.
>>
>> Please use Closes: to reference issues that this patch fixes.
>>
>> No need to resend for this, can be fixed while applying, but please tell
>> me the commit that introduced the problem.
>>
>> BR,
>> Jani.
>>
> Alright will take care. Please find below the commit that introduced
> this:
>
> b9d96dacdc3d983eae234b52401edb56dbceb764
>
> Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
> https://patchwork.freedesktop.org/patch/408779/
>
>
> Thanks & Regards,
>
> Ankit
>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 8c12d5375607..2b83f0f433a2 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct
>>> intel_dp *intel_dp)
>>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>> /* Clear the cached register set to avoid using stale values */
>>> -
>>> memset(intel_dp->pcon_dsc_dpcd, 0,
>>> sizeof(intel_dp->pcon_dsc_dpcd));
>>> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
>>> + return;
>>> +
>>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
>>> intel_dp->pcon_dsc_dpcd,
>>> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
@ 2021-03-09 4:28 ` Nautiyal, Ankit K
0 siblings, 0 replies; 36+ messages in thread
From: Nautiyal, Ankit K @ 2021-03-09 4:28 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: dri-devel
As I realized, this patch is mixing DPCD rev and DP version, need an
appropriate check instead.
As for the gitlab issue
https://gitlab.freedesktop.org/drm/intel/-/issues/2868 this seems to be
not due to a DPCD register not defined for an older sink.
The DPCD read in that case should have been 0, instead of timeout.
I will drop this patch for now, from the series and revisit it later.
Thanks & Regards,
Ankit
On 2/8/2021 5:14 PM, Nautiyal, Ankit K wrote:
>
> On 2/8/2021 4:45 PM, Jani Nikula wrote:
>> On Thu, 04 Feb 2021, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
>>> Do not read the registers if DPCD rev < 1.4.
>>>
>>> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
>> Please use Fixes: to reference commits that this patch fixes.
>>
>> Please use Closes: to reference issues that this patch fixes.
>>
>> No need to resend for this, can be fixed while applying, but please tell
>> me the commit that introduced the problem.
>>
>> BR,
>> Jani.
>>
> Alright will take care. Please find below the commit that introduced
> this:
>
> b9d96dacdc3d983eae234b52401edb56dbceb764
>
> Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder
> https://patchwork.freedesktop.org/patch/408779/
>
>
> Thanks & Regards,
>
> Ankit
>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 8c12d5375607..2b83f0f433a2 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct
>>> intel_dp *intel_dp)
>>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>> /* Clear the cached register set to avoid using stale values */
>>> -
>>> memset(intel_dp->pcon_dsc_dpcd, 0,
>>> sizeof(intel_dp->pcon_dsc_dpcd));
>>> + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14)
>>> + return;
>>> +
>>> if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
>>> intel_dp->pcon_dsc_dpcd,
>>> sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2021-03-09 4:28 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-04 6:48 [PATCH 0/3] HDMI2.1 PCON Misc Fixes Ankit Nautiyal
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
2021-02-04 6:48 ` [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4 Ankit Nautiyal
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
2021-02-05 19:58 ` Ville Syrjälä
2021-02-05 19:58 ` [Intel-gfx] " Ville Syrjälä
2021-02-05 20:07 ` Navare, Manasi
2021-02-05 20:07 ` Navare, Manasi
2021-02-05 20:06 ` Ville Syrjälä
2021-02-05 20:06 ` Ville Syrjälä
2021-02-05 20:22 ` Navare, Manasi
2021-02-05 20:22 ` Navare, Manasi
2021-02-08 11:15 ` Jani Nikula
2021-02-08 11:15 ` [Intel-gfx] " Jani Nikula
2021-02-08 11:44 ` Nautiyal, Ankit K
2021-02-08 11:44 ` [Intel-gfx] " Nautiyal, Ankit K
2021-03-09 4:28 ` Nautiyal, Ankit K
2021-03-09 4:28 ` [Intel-gfx] " Nautiyal, Ankit K
2021-02-04 6:48 ` [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON Ankit Nautiyal
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
2021-02-05 20:00 ` Ville Syrjälä
2021-02-05 20:00 ` [Intel-gfx] " Ville Syrjälä
2021-02-11 6:56 ` Nautiyal, Ankit K
2021-02-11 6:56 ` [Intel-gfx] " Nautiyal, Ankit K
2021-02-11 6:43 ` [PATCH v2 " Ankit Nautiyal
2021-02-11 6:43 ` [Intel-gfx] " Ankit Nautiyal
2021-02-04 6:48 ` [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms Ankit Nautiyal
2021-02-04 6:48 ` [Intel-gfx] " Ankit Nautiyal
2021-02-05 20:01 ` Ville Syrjälä
2021-02-05 20:01 ` [Intel-gfx] " Ville Syrjälä
2021-02-04 7:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes Patchwork
2021-02-04 8:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-04 9:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-11 7:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes (rev2) Patchwork
2021-02-11 8:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-11 13:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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