From: Jim Shu <cwshu@andestech.com> To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Jim Shu <cwshu@andestech.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed Date: Sun, 21 Feb 2021 22:01:22 +0800 [thread overview] Message-ID: <1613916082-19528-4-git-send-email-cwshu@andestech.com> (raw) In-Reply-To: <1613916082-19528-1-git-send-email-cwshu@andestech.com> If PMP permission of any address has been changed by updating PMP entry, flush all TLB pages to prevent from getting old permission. Signed-off-by: Jim Shu <cwshu@andestech.com> --- target/riscv/pmp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ebd874cde3..cff020122a 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" +#include "exec/exec-all.h" static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); @@ -347,6 +348,9 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, cfg_val = (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } + + /* If PMP permission of any addr has been changed, flush TLB pages. */ + tlb_flush(env_cpu(env)); } -- 2.30.1
WARNING: multiple messages have this Message-ID (diff)
From: Jim Shu <cwshu@andestech.com> To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org> Cc: Jim Shu <cwshu@andestech.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Subject: [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed Date: Sun, 21 Feb 2021 22:01:22 +0800 [thread overview] Message-ID: <1613916082-19528-4-git-send-email-cwshu@andestech.com> (raw) In-Reply-To: <1613916082-19528-1-git-send-email-cwshu@andestech.com> If PMP permission of any address has been changed by updating PMP entry, flush all TLB pages to prevent from getting old permission. Signed-off-by: Jim Shu <cwshu@andestech.com> --- target/riscv/pmp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ebd874cde3..cff020122a 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" +#include "exec/exec-all.h" static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); @@ -347,6 +348,9 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, cfg_val = (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } + + /* If PMP permission of any addr has been changed, flush TLB pages. */ + tlb_flush(env_cpu(env)); } -- 2.30.1
next prev parent reply other threads:[~2021-02-21 15:31 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-21 14:01 [PATCH 0/3] target/riscv: fix PMP permission checking when softmmu's TLB hits Jim Shu 2021-02-21 14:01 ` Jim Shu 2021-02-21 14:01 ` [PATCH 1/3] target/riscv: propagate PMP permission to TLB page Jim Shu 2021-02-21 14:01 ` Jim Shu 2021-03-16 20:01 ` Alistair Francis 2021-03-16 20:01 ` Alistair Francis 2021-02-21 14:01 ` [PATCH 2/3] target/riscv: add log of PMP permission checking Jim Shu 2021-02-21 14:01 ` Jim Shu 2021-02-21 14:01 ` Jim Shu [this message] 2021-02-21 14:01 ` [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed Jim Shu 2021-03-16 20:02 ` Alistair Francis 2021-03-16 20:02 ` Alistair Francis 2021-03-17 17:47 ` [PATCH 0/3] target/riscv: fix PMP permission checking when softmmu's TLB hits Alistair Francis 2021-03-17 17:47 ` Alistair Francis [not found] <1613914370-17285-1-git-send-email-cwshu@andestech.com> 2021-02-21 13:32 ` [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed Jim Shu 2021-02-21 13:32 ` Jim Shu
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