* [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's .get_config() from MST .get_config()
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
@ 2021-02-24 14:42 ` Ville Syrjala
2021-03-04 10:42 ` Kahola, Mika
2021-02-24 14:42 ` [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout Ville Syrjala
` (9 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2021-02-24 14:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop assuming intel_ddi_get_config() is all we need from the primary
encoder, and instead call it via the .get_config() vfunc. This
will allow customized .get_config() for the primary, which I plan
to use to handle the differences in the clock readout between various
platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8e316146b6d1..906860ad8eb8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -591,7 +591,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
struct intel_digital_port *dig_port = intel_mst->primary;
- intel_ddi_get_config(&dig_port->base, pipe_config);
+ dig_port->base.get_config(&dig_port->base, pipe_config);
}
static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's .get_config() from MST .get_config()
2021-02-24 14:42 ` [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's .get_config() from MST .get_config() Ville Syrjala
@ 2021-03-04 10:42 ` Kahola, Mika
0 siblings, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-04 10:42 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's
> .get_config() from MST .get_config()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop assuming intel_ddi_get_config() is all we need from the primary
> encoder, and instead call it via the .get_config() vfunc. This will allow
> customized .get_config() for the primary, which I plan to use to handle the
> differences in the clock readout between various platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 8e316146b6d1..906860ad8eb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -591,7 +591,7 @@ static void intel_dp_mst_enc_get_config(struct
> intel_encoder *encoder,
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
> struct intel_digital_port *dig_port = intel_mst->primary;
>
> - intel_ddi_get_config(&dig_port->base, pipe_config);
> + dig_port->base.get_config(&dig_port->base, pipe_config);
> }
>
> static bool intel_dp_mst_initial_fastset_check(struct intel_encoder
> *encoder,
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
2021-02-24 14:42 ` [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's .get_config() from MST .get_config() Ville Syrjala
@ 2021-02-24 14:42 ` Ville Syrjala
2021-02-25 16:12 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-03-04 10:43 ` [Intel-gfx] [PATCH " Kahola, Mika
2021-02-24 14:42 ` [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL state tracking Ville Syrjala
` (8 subsequent siblings)
10 siblings, 2 replies; 20+ messages in thread
From: Ville Syrjala @ 2021-02-24 14:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The clock readout for DDI encoders needs to moved into the encoders.
To that end intel_dpll_readout_hw_state() needs to happen after
the encoder readout as otherwise it can't correctly populate
the PLL crtc_mask/active_mask bitmasks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d0da88751c72..b34620545d3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13444,8 +13444,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
readout_plane_state(dev_priv);
- intel_dpll_readout_hw_state(dev_priv);
-
for_each_intel_encoder(dev, encoder) {
pipe = 0;
@@ -13480,6 +13478,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
pipe_name(pipe));
}
+ intel_dpll_readout_hw_state(dev_priv);
+
drm_connector_list_iter_begin(dev, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (connector->get_hw_state(connector)) {
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Intel-gfx] [PATCH v2 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
2021-02-24 14:42 ` [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout Ville Syrjala
@ 2021-02-25 16:12 ` Ville Syrjala
2021-03-08 11:43 ` Kahola, Mika
2021-03-04 10:43 ` [Intel-gfx] [PATCH " Kahola, Mika
1 sibling, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2021-02-25 16:12 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The clock readout for DDI encoders needs to moved into the encoders.
To that end intel_dpll_readout_hw_state() needs to happen after
the encoder readout as otherwise it can't correctly populate
the PLL crtc_mask/active_mask bitmasks.
v2: Populate DPLL ref clocks before the encoder->get_config()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++++++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d0da88751c72..faf9507c9da2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12908,6 +12908,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_update_czclk(i915);
intel_modeset_init_hw(i915);
+ intel_dpll_update_ref_clks(i915);
intel_hdcp_component_init(i915);
@@ -13444,8 +13445,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
readout_plane_state(dev_priv);
- intel_dpll_readout_hw_state(dev_priv);
-
for_each_intel_encoder(dev, encoder) {
pipe = 0;
@@ -13480,6 +13479,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
pipe_name(pipe));
}
+ intel_dpll_readout_hw_state(dev_priv);
+
drm_connector_list_iter_begin(dev, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (connector->get_hw_state(connector)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 529b1d569af2..ac6460962e29 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4612,12 +4612,15 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
pll->info->name, pll->state.crtc_mask, pll->on);
}
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
{
- int i;
-
if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
i915->dpll.mgr->update_ref_clks(i915);
+}
+
+void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+{
+ int i;
for (i = 0; i < i915->dpll.num_shared_dpll; i++)
readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2eb7618ef957..81e67639dadb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -410,6 +410,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_device *dev);
+void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
2021-02-25 16:12 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2021-03-08 11:43 ` Kahola, Mika
0 siblings, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-08 11:43 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Thursday, February 25, 2021 6:12 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915: Do
> intel_dpll_readout_hw_state() after encoder readout
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The clock readout for DDI encoders needs to moved into the encoders.
> To that end intel_dpll_readout_hw_state() needs to happen after the
> encoder readout as otherwise it can't correctly populate the PLL
> crtc_mask/active_mask bitmasks.
>
> v2: Populate DPLL ref clocks before the encoder->get_config()
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++++++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d0da88751c72..faf9507c9da2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12908,6 +12908,7 @@ int intel_modeset_init_nogem(struct
> drm_i915_private *i915)
>
> intel_update_czclk(i915);
> intel_modeset_init_hw(i915);
> + intel_dpll_update_ref_clks(i915);
>
> intel_hdcp_component_init(i915);
>
> @@ -13444,8 +13445,6 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
>
> readout_plane_state(dev_priv);
>
> - intel_dpll_readout_hw_state(dev_priv);
> -
> for_each_intel_encoder(dev, encoder) {
> pipe = 0;
>
> @@ -13480,6 +13479,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> pipe_name(pipe));
> }
>
> + intel_dpll_readout_hw_state(dev_priv);
> +
> drm_connector_list_iter_begin(dev, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> if (connector->get_hw_state(connector)) { diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 529b1d569af2..ac6460962e29 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4612,12 +4612,15 @@ static void readout_dpll_hw_state(struct
> drm_i915_private *i915,
> pll->info->name, pll->state.crtc_mask, pll->on); }
>
> -void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
> +void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
> {
> - int i;
> -
> if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
> i915->dpll.mgr->update_ref_clks(i915);
> +}
> +
> +void intel_dpll_readout_hw_state(struct drm_i915_private *i915) {
> + int i;
>
> for (i = 0; i < i915->dpll.num_shared_dpll; i++)
> readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 2eb7618ef957..81e67639dadb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -410,6 +410,7 @@ void intel_enable_shared_dpll(const struct
> intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state); void intel_shared_dpll_swap_state(struct
> intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device
> *dev);
> +void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
> void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void
> intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
>
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
2021-02-24 14:42 ` [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout Ville Syrjala
2021-02-25 16:12 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
@ 2021-03-04 10:43 ` Kahola, Mika
1 sibling, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-04 10:43 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state()
> after encoder readout
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The clock readout for DDI encoders needs to moved into the encoders.
> To that end intel_dpll_readout_hw_state() needs to happen after the
> encoder readout as otherwise it can't correctly populate the PLL
> crtc_mask/active_mask bitmasks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d0da88751c72..b34620545d3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13444,8 +13444,6 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
>
> readout_plane_state(dev_priv);
>
> - intel_dpll_readout_hw_state(dev_priv);
> -
> for_each_intel_encoder(dev, encoder) {
> pipe = 0;
>
> @@ -13480,6 +13478,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> pipe_name(pipe));
> }
>
> + intel_dpll_readout_hw_state(dev_priv);
> +
> drm_connector_list_iter_begin(dev, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> if (connector->get_hw_state(connector)) {
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL state tracking
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
2021-02-24 14:42 ` [Intel-gfx] [PATCH 1/6] drm/i915: Call primary encoder's .get_config() from MST .get_config() Ville Syrjala
2021-02-24 14:42 ` [Intel-gfx] [PATCH 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout Ville Syrjala
@ 2021-02-24 14:42 ` Ville Syrjala
2021-03-04 10:52 ` Kahola, Mika
2021-02-24 14:42 ` [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (7 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2021-02-24 14:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the other places we have use pipes instead of crtc indices
when tracking resource usage. Life is easier when we do it
the same way always, so switch the dpll mgr to using pipes as
well. Looks like it was actually mixing these up in some cases
so it would not even have worked correctly except when the
device has a contiguous set of pipes starting from pipe A.
Granted, that is the typical case but supposedly it may not
always hold on modern hw.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++--------
.../drm/i915/display/intel_display_debugfs.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 ++++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 ++--
4 files changed, 51 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b34620545d3b..958c2a796bae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9653,7 +9653,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
struct intel_crtc_state *new_crtc_state)
{
struct intel_dpll_hw_state dpll_hw_state;
- unsigned int crtc_mask;
+ u8 pipe_mask;
bool active;
memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
@@ -9666,34 +9666,34 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
I915_STATE_WARN(!pll->on && pll->active_mask,
"pll in active use but not on in sw tracking\n");
I915_STATE_WARN(pll->on && !pll->active_mask,
- "pll is on but not used by any active crtc\n");
+ "pll is on but not used by any active pipe\n");
I915_STATE_WARN(pll->on != active,
"pll on state mismatch (expected %i, found %i)\n",
pll->on, active);
}
if (!crtc) {
- I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
- "more active pll users than references: %x vs %x\n",
- pll->active_mask, pll->state.crtc_mask);
+ I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
+ "more active pll users than references: 0x%x vs 0x%x\n",
+ pll->active_mask, pll->state.pipe_mask);
return;
}
- crtc_mask = drm_crtc_mask(&crtc->base);
+ pipe_mask = BIT(crtc->pipe);
if (new_crtc_state->hw.active)
- I915_STATE_WARN(!(pll->active_mask & crtc_mask),
- "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
+ I915_STATE_WARN(!(pll->active_mask & pipe_mask),
+ "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
pipe_name(crtc->pipe), pll->active_mask);
else
- I915_STATE_WARN(pll->active_mask & crtc_mask,
- "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
+ I915_STATE_WARN(pll->active_mask & pipe_mask,
+ "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
pipe_name(crtc->pipe), pll->active_mask);
- I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
- "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
- crtc_mask, pll->state.crtc_mask);
+ I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
+ "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
+ pipe_mask, pll->state.pipe_mask);
I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
&dpll_hw_state,
@@ -9713,15 +9713,15 @@ verify_shared_dpll_state(struct intel_crtc *crtc,
if (old_crtc_state->shared_dpll &&
old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
- unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
+ u8 pipe_mask = BIT(crtc->pipe);
struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
- I915_STATE_WARN(pll->active_mask & crtc_mask,
- "pll active mismatch (didn't expect pipe %c in active mask)\n",
- pipe_name(crtc->pipe));
- I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
- "pll enabled crtcs mismatch (found %x in enabled mask)\n",
- pipe_name(crtc->pipe));
+ I915_STATE_WARN(pll->active_mask & pipe_mask,
+ "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
+ pipe_name(crtc->pipe), pll->active_mask);
+ I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
+ "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
+ pipe_name(crtc->pipe), pll->state.pipe_mask);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 35f176ea8280..20194ccfec05 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1094,8 +1094,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
pll->info->id);
- seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
- pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
+ seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
+ pll->state.pipe_mask, pll->active_mask, yesno(pll->on));
seq_printf(m, " tracked hardware state:\n");
seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
seq_printf(m, " dpll_md: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 529b1d569af2..a68ae90b07e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -176,7 +176,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
return;
mutex_lock(&dev_priv->dpll.lock);
- drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask);
+ drm_WARN_ON(&dev_priv->drm, !pll->state.pipe_mask);
if (!pll->active_mask) {
drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name);
drm_WARN_ON(&dev_priv->drm, pll->on);
@@ -198,7 +198,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
+ unsigned int pipe_mask = BIT(crtc->pipe);
unsigned int old_mask;
if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
@@ -207,16 +207,16 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
mutex_lock(&dev_priv->dpll.lock);
old_mask = pll->active_mask;
- if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask & crtc_mask)) ||
- drm_WARN_ON(&dev_priv->drm, pll->active_mask & crtc_mask))
+ if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) ||
+ drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask))
goto out;
- pll->active_mask |= crtc_mask;
+ pll->active_mask |= pipe_mask;
drm_dbg_kms(&dev_priv->drm,
- "enable %s (active %x, on? %d) for crtc %d\n",
+ "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
pll->info->name, pll->active_mask, pll->on,
- crtc->base.base.id);
+ crtc->base.base.id, crtc->base.name);
if (old_mask) {
drm_WARN_ON(&dev_priv->drm, !pll->on);
@@ -244,7 +244,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
+ unsigned int pipe_mask = BIT(crtc->pipe);
/* PCH only available on ILK+ */
if (INTEL_GEN(dev_priv) < 5)
@@ -254,18 +254,20 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
return;
mutex_lock(&dev_priv->dpll.lock);
- if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask)))
+ if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask),
+ "%s not used by [CRTC:%d:%s]\n", pll->info->name,
+ crtc->base.base.id, crtc->base.name))
goto out;
drm_dbg_kms(&dev_priv->drm,
- "disable %s (active %x, on? %d) for crtc %d\n",
+ "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
pll->info->name, pll->active_mask, pll->on,
- crtc->base.base.id);
+ crtc->base.base.id, crtc->base.name);
assert_shared_dpll_enabled(dev_priv, pll);
drm_WARN_ON(&dev_priv->drm, !pll->on);
- pll->active_mask &= ~crtc_mask;
+ pll->active_mask &= ~pipe_mask;
if (pll->active_mask)
goto out;
@@ -296,7 +298,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
pll = &dev_priv->dpll.shared_dplls[i];
/* Only want to check enabled timings first */
- if (shared_dpll[i].crtc_mask == 0) {
+ if (shared_dpll[i].pipe_mask == 0) {
if (!unused_pll)
unused_pll = pll;
continue;
@@ -306,10 +308,10 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
&shared_dpll[i].hw_state,
sizeof(*pll_state)) == 0) {
drm_dbg_kms(&dev_priv->drm,
- "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
+ "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
crtc->base.base.id, crtc->base.name,
pll->info->name,
- shared_dpll[i].crtc_mask,
+ shared_dpll[i].pipe_mask,
pll->active_mask);
return pll;
}
@@ -338,13 +340,13 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- if (shared_dpll[id].crtc_mask == 0)
+ if (shared_dpll[id].pipe_mask == 0)
shared_dpll[id].hw_state = *pll_state;
drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
pipe_name(crtc->pipe));
- shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
+ shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
}
static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
@@ -354,7 +356,7 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
struct intel_shared_dpll_state *shared_dpll;
shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
- shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
+ shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
}
static void intel_put_dpll(struct intel_atomic_state *state,
@@ -4597,19 +4599,19 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
POWER_DOMAIN_DPLL_DC_OFF);
}
- pll->state.crtc_mask = 0;
+ pll->state.pipe_mask = 0;
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
- pll->state.crtc_mask |= 1 << crtc->pipe;
+ pll->state.pipe_mask |= BIT(crtc->pipe);
}
- pll->active_mask = pll->state.crtc_mask;
+ pll->active_mask = pll->state.pipe_mask;
drm_dbg_kms(&i915->drm,
- "%s hw state readout: crtc_mask 0x%08x, on %i\n",
- pll->info->name, pll->state.crtc_mask, pll->on);
+ "%s hw state readout: pipe_mask 0x%x, on %i\n",
+ pll->info->name, pll->state.pipe_mask, pll->on);
}
void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2eb7618ef957..eb52e85022e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -241,9 +241,9 @@ struct intel_dpll_hw_state {
*/
struct intel_shared_dpll_state {
/**
- * @crtc_mask: mask of CRTC using this DPLL, active or not
+ * @pipe_mask: mask of pipes using this DPLL, active or not
*/
- unsigned crtc_mask;
+ u8 pipe_mask;
/**
* @hw_state: hardware configuration for the DPLL stored in
@@ -351,9 +351,9 @@ struct intel_shared_dpll {
struct intel_shared_dpll_state state;
/**
- * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
+ * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
*/
- unsigned active_mask;
+ u8 active_mask;
/**
* @on: is the PLL actually active? Disabled during modeset
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL state tracking
2021-02-24 14:42 ` [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL state tracking Ville Syrjala
@ 2021-03-04 10:52 ` Kahola, Mika
0 siblings, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-04 10:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL
> state tracking
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the other places we have use pipes instead of crtc indices when tracking
> resource usage. Life is easier when we do it the same way always, so switch
> the dpll mgr to using pipes as well. Looks like it was actually mixing these up
> in some cases so it would not even have worked correctly except when the
> device has a contiguous set of pipes starting from pipe A.
> Granted, that is the typical case but supposedly it may not always hold on
> modern hw.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++--------
> .../drm/i915/display/intel_display_debugfs.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 ++--
> 4 files changed, 51 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b34620545d3b..958c2a796bae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9653,7 +9653,7 @@ verify_single_dpll_state(struct drm_i915_private
> *dev_priv,
> struct intel_crtc_state *new_crtc_state) {
> struct intel_dpll_hw_state dpll_hw_state;
> - unsigned int crtc_mask;
> + u8 pipe_mask;
> bool active;
>
> memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); @@ -9666,34
> +9666,34 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
> I915_STATE_WARN(!pll->on && pll->active_mask,
> "pll in active use but not on in sw tracking\n");
> I915_STATE_WARN(pll->on && !pll->active_mask,
> - "pll is on but not used by any active crtc\n");
> + "pll is on but not used by any active pipe\n");
> I915_STATE_WARN(pll->on != active,
> "pll on state mismatch (expected %i, found %i)\n",
> pll->on, active);
> }
>
> if (!crtc) {
> - I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
> - "more active pll users than references: %x vs
> %x\n",
> - pll->active_mask, pll->state.crtc_mask);
> + I915_STATE_WARN(pll->active_mask & ~pll-
> >state.pipe_mask,
> + "more active pll users than references: 0x%x
> vs 0x%x\n",
> + pll->active_mask, pll->state.pipe_mask);
>
> return;
> }
>
> - crtc_mask = drm_crtc_mask(&crtc->base);
> + pipe_mask = BIT(crtc->pipe);
>
> if (new_crtc_state->hw.active)
> - I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> - "pll active mismatch (expected pipe %c in
> active mask 0x%02x)\n",
> + I915_STATE_WARN(!(pll->active_mask & pipe_mask),
> + "pll active mismatch (expected pipe %c in
> active mask 0x%x)\n",
> pipe_name(crtc->pipe), pll->active_mask);
> else
> - I915_STATE_WARN(pll->active_mask & crtc_mask,
> - "pll active mismatch (didn't expect pipe %c in
> active mask 0x%02x)\n",
> + I915_STATE_WARN(pll->active_mask & pipe_mask,
> + "pll active mismatch (didn't expect pipe %c in
> active mask
> +0x%x)\n",
> pipe_name(crtc->pipe), pll->active_mask);
>
> - I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
> - "pll enabled crtcs mismatch (expected 0x%x in
> 0x%02x)\n",
> - crtc_mask, pll->state.crtc_mask);
> + I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
> + "pll enabled crtcs mismatch (expected 0x%x in
> 0x%x)\n",
> + pipe_mask, pll->state.pipe_mask);
>
> I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
> &dpll_hw_state,
> @@ -9713,15 +9713,15 @@ verify_shared_dpll_state(struct intel_crtc *crtc,
>
> if (old_crtc_state->shared_dpll &&
> old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
> - unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> + u8 pipe_mask = BIT(crtc->pipe);
> struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
>
> - I915_STATE_WARN(pll->active_mask & crtc_mask,
> - "pll active mismatch (didn't expect pipe %c in
> active mask)\n",
> - pipe_name(crtc->pipe));
> - I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
> - "pll enabled crtcs mismatch (found %x in
> enabled mask)\n",
> - pipe_name(crtc->pipe));
> + I915_STATE_WARN(pll->active_mask & pipe_mask,
> + "pll active mismatch (didn't expect pipe %c in
> active mask (0x%x))\n",
> + pipe_name(crtc->pipe), pll->active_mask);
> + I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
> + "pll enabled crtcs mismatch (found %x in
> enabled mask (0x%x))\n",
> + pipe_name(crtc->pipe), pll-
> >state.pipe_mask);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 35f176ea8280..20194ccfec05 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1094,8 +1094,8 @@ static int i915_shared_dplls_info(struct seq_file
> *m, void *unused)
>
> seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
> pll->info->id);
> - seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
> - pll->state.crtc_mask, pll->active_mask, yesno(pll-
> >on));
> + seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
> + pll->state.pipe_mask, pll->active_mask, yesno(pll-
> >on));
> seq_printf(m, " tracked hardware state:\n");
> seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
> seq_printf(m, " dpll_md: 0x%08x\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 529b1d569af2..a68ae90b07e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -176,7 +176,7 @@ void intel_prepare_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> return;
>
> mutex_lock(&dev_priv->dpll.lock);
> - drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask);
> + drm_WARN_ON(&dev_priv->drm, !pll->state.pipe_mask);
> if (!pll->active_mask) {
> drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info-
> >name);
> drm_WARN_ON(&dev_priv->drm, pll->on); @@ -198,7
> +198,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state
> *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> - unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> + unsigned int pipe_mask = BIT(crtc->pipe);
> unsigned int old_mask;
>
> if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) @@ -207,16
> +207,16 @@ void intel_enable_shared_dpll(const struct intel_crtc_state
> *crtc_state)
> mutex_lock(&dev_priv->dpll.lock);
> old_mask = pll->active_mask;
>
> - if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask &
> crtc_mask)) ||
> - drm_WARN_ON(&dev_priv->drm, pll->active_mask & crtc_mask))
> + if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask &
> pipe_mask)) ||
> + drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask))
> goto out;
>
> - pll->active_mask |= crtc_mask;
> + pll->active_mask |= pipe_mask;
>
> drm_dbg_kms(&dev_priv->drm,
> - "enable %s (active %x, on? %d) for crtc %d\n",
> + "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
> pll->info->name, pll->active_mask, pll->on,
> - crtc->base.base.id);
> + crtc->base.base.id, crtc->base.name);
>
> if (old_mask) {
> drm_WARN_ON(&dev_priv->drm, !pll->on); @@ -244,7
> +244,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state
> *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> - unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
> + unsigned int pipe_mask = BIT(crtc->pipe);
>
> /* PCH only available on ILK+ */
> if (INTEL_GEN(dev_priv) < 5)
> @@ -254,18 +254,20 @@ void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state)
> return;
>
> mutex_lock(&dev_priv->dpll.lock);
> - if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask &
> crtc_mask)))
> + if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask),
> + "%s not used by [CRTC:%d:%s]\n", pll->info->name,
> + crtc->base.base.id, crtc->base.name))
> goto out;
>
> drm_dbg_kms(&dev_priv->drm,
> - "disable %s (active %x, on? %d) for crtc %d\n",
> + "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
> pll->info->name, pll->active_mask, pll->on,
> - crtc->base.base.id);
> + crtc->base.base.id, crtc->base.name);
>
> assert_shared_dpll_enabled(dev_priv, pll);
> drm_WARN_ON(&dev_priv->drm, !pll->on);
>
> - pll->active_mask &= ~crtc_mask;
> + pll->active_mask &= ~pipe_mask;
> if (pll->active_mask)
> goto out;
>
> @@ -296,7 +298,7 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> pll = &dev_priv->dpll.shared_dplls[i];
>
> /* Only want to check enabled timings first */
> - if (shared_dpll[i].crtc_mask == 0) {
> + if (shared_dpll[i].pipe_mask == 0) {
> if (!unused_pll)
> unused_pll = pll;
> continue;
> @@ -306,10 +308,10 @@ intel_find_shared_dpll(struct intel_atomic_state
> *state,
> &shared_dpll[i].hw_state,
> sizeof(*pll_state)) == 0) {
> drm_dbg_kms(&dev_priv->drm,
> - "[CRTC:%d:%s] sharing existing %s (crtc
> mask 0x%08x, active %x)\n",
> + "[CRTC:%d:%s] sharing existing %s (pipe
> mask 0x%x, active
> +0x%x)\n",
> crtc->base.base.id, crtc->base.name,
> pll->info->name,
> - shared_dpll[i].crtc_mask,
> + shared_dpll[i].pipe_mask,
> pll->active_mask);
> return pll;
> }
> @@ -338,13 +340,13 @@ intel_reference_shared_dpll(struct
> intel_atomic_state *state,
>
> shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
>
> - if (shared_dpll[id].crtc_mask == 0)
> + if (shared_dpll[id].pipe_mask == 0)
> shared_dpll[id].hw_state = *pll_state;
>
> drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,
> pipe_name(crtc->pipe));
>
> - shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
> + shared_dpll[id].pipe_mask |= BIT(crtc->pipe);
> }
>
> static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
> @@ -354,7 +356,7 @@ static void intel_unreference_shared_dpll(struct
> intel_atomic_state *state,
> struct intel_shared_dpll_state *shared_dpll;
>
> shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> - shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
> + shared_dpll[pll->info->id].pipe_mask &= ~BIT(crtc->pipe);
> }
>
> static void intel_put_dpll(struct intel_atomic_state *state, @@ -4597,19
> +4599,19 @@ static void readout_dpll_hw_state(struct drm_i915_private
> *i915,
>
> POWER_DOMAIN_DPLL_DC_OFF);
> }
>
> - pll->state.crtc_mask = 0;
> + pll->state.pipe_mask = 0;
> for_each_intel_crtc(&i915->drm, crtc) {
> struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
> - pll->state.crtc_mask |= 1 << crtc->pipe;
> + pll->state.pipe_mask |= BIT(crtc->pipe);
> }
> - pll->active_mask = pll->state.crtc_mask;
> + pll->active_mask = pll->state.pipe_mask;
>
> drm_dbg_kms(&i915->drm,
> - "%s hw state readout: crtc_mask 0x%08x, on %i\n",
> - pll->info->name, pll->state.crtc_mask, pll->on);
> + "%s hw state readout: pipe_mask 0x%x, on %i\n",
> + pll->info->name, pll->state.pipe_mask, pll->on);
> }
>
> void intel_dpll_readout_hw_state(struct drm_i915_private *i915) diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 2eb7618ef957..eb52e85022e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -241,9 +241,9 @@ struct intel_dpll_hw_state {
> */
> struct intel_shared_dpll_state {
> /**
> - * @crtc_mask: mask of CRTC using this DPLL, active or not
> + * @pipe_mask: mask of pipes using this DPLL, active or not
> */
> - unsigned crtc_mask;
> + u8 pipe_mask;
>
> /**
> * @hw_state: hardware configuration for the DPLL stored in @@ -
> 351,9 +351,9 @@ struct intel_shared_dpll {
> struct intel_shared_dpll_state state;
>
> /**
> - * @active_mask: mask of active CRTCs (i.e. DPMS on) using this DPLL
> + * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
> */
> - unsigned active_mask;
> + u8 active_mask;
>
> /**
> * @on: is the PLL actually active? Disabled during modeset
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config()
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (2 preceding siblings ...)
2021-02-24 14:42 ` [Intel-gfx] [PATCH 3/6] drm/i915: Use pipes instead crtc indices in PLL state tracking Ville Syrjala
@ 2021-02-24 14:42 ` Ville Syrjala
2021-03-08 13:11 ` Kahola, Mika
2021-02-24 14:42 ` [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled() Ville Syrjala
` (6 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2021-02-24 14:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the *_get_ddi_pll() stuff into the encodet->get_config() hook.
There it neatly sits next to the matching .{enable,disable}_clock()
functions.
In order to avoid excessive boilerplate I changed the behaviour
such that all platforms now do the readout via
crtc_state->port_dpll[].
ICL+ TC is still a bit special due to TBTPLL not having a functional
.get_freq(). Should probably change that by adopting the LCPLL
approach, but that would require a fairly substantial rework of the
DPLL ID handling. So leave it for later.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 321 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_ddi.h | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 219 -------------
5 files changed, 306 insertions(+), 250 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 05d5709ae537..29fe4919392a 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1490,14 +1490,10 @@ static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
- /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
- pipe_config->port_clock = intel_dpll_get_freq(i915,
- pipe_config->shared_dpll,
- &pipe_config->dpll_hw_state);
+ intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 91a8a42b4aa2..b03f74076f64 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -142,7 +142,7 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- intel_ddi_get_config(encoder, pipe_config);
+ hsw_ddi_get_config(encoder, pipe_config);
pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
DRM_MODE_FLAG_NHSYNC |
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index eeae78097a20..56f5f55a7c8f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -304,25 +304,6 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
}
-static void intel_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
- if (intel_phy_is_tc(dev_priv, phy) &&
- intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
- DPLL_ID_ICL_TBTPLL)
- pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
- encoder->port);
- else
- pipe_config->port_clock =
- intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll,
- &pipe_config->dpll_hw_state);
-
- ddi_dotclock_get(pipe_config);
-}
-
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
@@ -1608,6 +1589,17 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
mutex_unlock(&i915->dpll.lock);
}
+static struct intel_shared_dpll *
+_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
+ u32 clk_sel_mask, u32 clk_sel_shift)
+{
+ enum intel_dpll_id id;
+
+ id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
+
+ return intel_get_shared_dpll_by_id(i915, id);
+}
+
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1633,6 +1625,16 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
+ ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
+ ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
+}
+
static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1658,6 +1660,16 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+ RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+ RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
+}
+
static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1692,6 +1704,16 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_get_pll(i915, DG1_DPCLKA_CFGCR0(phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
+}
+
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1717,6 +1739,16 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
+}
+
static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1784,6 +1816,36 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
}
+static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
+ enum port port = encoder->port;
+ enum intel_dpll_id id;
+ u32 tmp;
+
+ tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+
+ switch (tmp & DDI_CLK_SEL_MASK) {
+ case DDI_CLK_SEL_TBT_162:
+ case DDI_CLK_SEL_TBT_270:
+ case DDI_CLK_SEL_TBT_540:
+ case DDI_CLK_SEL_TBT_810:
+ id = DPLL_ID_ICL_TBTPLL;
+ break;
+ case DDI_CLK_SEL_MG:
+ id = icl_tc_port_to_pll_id(tc_port);
+ break;
+ default:
+ MISSING_CASE(tmp);
+ fallthrough;
+ case DDI_CLK_SEL_NONE:
+ return NULL;
+ }
+
+ return intel_get_shared_dpll_by_id(i915, id);
+}
+
static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1809,6 +1871,39 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
}
+static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,
+ DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+ DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
+}
+
+static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum intel_dpll_id id;
+
+ switch (encoder->port) {
+ case PORT_A:
+ id = DPLL_ID_SKL_DPLL0;
+ break;
+ case PORT_B:
+ id = DPLL_ID_SKL_DPLL1;
+ break;
+ case PORT_C:
+ id = DPLL_ID_SKL_DPLL2;
+ break;
+ default:
+ MISSING_CASE(encoder->port);
+ return NULL;
+ }
+
+ return intel_get_shared_dpll_by_id(i915, id);
+}
+
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1843,6 +1938,28 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
mutex_unlock(&i915->dpll.lock);
}
+static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ enum intel_dpll_id id;
+ u32 tmp;
+
+ tmp = intel_de_read(i915, DPLL_CTRL2);
+
+ /*
+ * FIXME Not sure if the override affects both
+ * the PLL selection and the CLK_OFF bit.
+ */
+ if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
+ return NULL;
+
+ id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
+ DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
+
+ return intel_get_shared_dpll_by_id(i915, id);
+}
+
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1864,6 +1981,44 @@ void hsw_ddi_disable_clock(struct intel_encoder *encoder)
intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
+static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ enum intel_dpll_id id;
+ u32 tmp;
+
+ tmp = intel_de_read(i915, PORT_CLK_SEL(port));
+
+ switch (tmp & PORT_CLK_SEL_MASK) {
+ case PORT_CLK_SEL_WRPLL1:
+ id = DPLL_ID_WRPLL1;
+ break;
+ case PORT_CLK_SEL_WRPLL2:
+ id = DPLL_ID_WRPLL2;
+ break;
+ case PORT_CLK_SEL_SPLL:
+ id = DPLL_ID_SPLL;
+ break;
+ case PORT_CLK_SEL_LCPLL_810:
+ id = DPLL_ID_LCPLL_810;
+ break;
+ case PORT_CLK_SEL_LCPLL_1350:
+ id = DPLL_ID_LCPLL_1350;
+ break;
+ case PORT_CLK_SEL_LCPLL_2700:
+ id = DPLL_ID_LCPLL_2700;
+ break;
+ default:
+ MISSING_CASE(tmp);
+ fallthrough;
+ case PORT_CLK_SEL_NONE:
+ return NULL;
+ }
+
+ return intel_get_shared_dpll_by_id(i915, id);
+}
+
void intel_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3293,8 +3448,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
}
}
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static void intel_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
@@ -3341,7 +3496,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
}
if (!pipe_config->bigjoiner_slave)
- intel_ddi_clock_get(encoder, pipe_config);
+ ddi_dotclock_get(pipe_config);
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
@@ -3371,6 +3526,114 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+void intel_ddi_get_clock(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct intel_shared_dpll *pll)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+ struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
+ bool pll_active;
+
+ port_dpll->pll = pll;
+ pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
+ drm_WARN_ON(&i915->drm, !pll_active);
+
+ icl_set_active_port_dpll(crtc_state, port_dpll_id);
+
+ crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+ &crtc_state->dpll_hw_state);
+}
+
+static void adls_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void rkl_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void dg1_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum icl_port_dpll_id port_dpll_id;
+ struct icl_port_dpll *port_dpll;
+ struct intel_shared_dpll *pll;
+ bool pll_active;
+
+ pll = icl_ddi_tc_get_pll(encoder);
+
+ if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
+ port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+ else
+ port_dpll_id = ICL_PORT_DPLL_MG_PHY;
+
+ port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
+
+ port_dpll->pll = pll;
+ pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
+ drm_WARN_ON(&i915->drm, !pll_active);
+
+ icl_set_active_port_dpll(crtc_state, port_dpll_id);
+
+ if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
+ crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
+ else
+ crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+ &crtc_state->dpll_hw_state);
+
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void cnl_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void bxt_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+static void skl_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
+void hsw_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
static void intel_ddi_sync_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -4057,7 +4320,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->post_disable = intel_ddi_post_disable;
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
- encoder->get_config = intel_ddi_get_config;
encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
@@ -4073,37 +4335,50 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
if (IS_ALDERLAKE_S(dev_priv)) {
encoder->enable_clock = adls_ddi_enable_clock;
encoder->disable_clock = adls_ddi_disable_clock;
+ encoder->get_config = adls_ddi_get_config;
} else if (IS_ROCKETLAKE(dev_priv)) {
encoder->enable_clock = rkl_ddi_enable_clock;
encoder->disable_clock = rkl_ddi_disable_clock;
+ encoder->get_config = rkl_ddi_get_config;
} else if (IS_DG1(dev_priv)) {
encoder->enable_clock = dg1_ddi_enable_clock;
encoder->disable_clock = dg1_ddi_disable_clock;
+ encoder->get_config = dg1_ddi_get_config;
} else if (IS_JSL_EHL(dev_priv)) {
if (intel_ddi_is_tc(dev_priv, port)) {
encoder->enable_clock = jsl_ddi_tc_enable_clock;
encoder->disable_clock = jsl_ddi_tc_disable_clock;
+ encoder->get_config = icl_ddi_combo_get_config;
} else {
encoder->enable_clock = icl_ddi_combo_enable_clock;
encoder->disable_clock = icl_ddi_combo_disable_clock;
+ encoder->get_config = icl_ddi_combo_get_config;
}
} else if (INTEL_GEN(dev_priv) >= 11) {
if (intel_ddi_is_tc(dev_priv, port)) {
encoder->enable_clock = icl_ddi_tc_enable_clock;
encoder->disable_clock = icl_ddi_tc_disable_clock;
+ encoder->get_config = icl_ddi_tc_get_config;
} else {
encoder->enable_clock = icl_ddi_combo_enable_clock;
encoder->disable_clock = icl_ddi_combo_disable_clock;
+ encoder->get_config = icl_ddi_combo_get_config;
}
} else if (IS_CANNONLAKE(dev_priv)) {
encoder->enable_clock = cnl_ddi_enable_clock;
encoder->disable_clock = cnl_ddi_disable_clock;
+ encoder->get_config = cnl_ddi_get_config;
+ } else if (IS_GEN9_LP(dev_priv)) {
+ /* BXT/GLK have fixed PLL->port mapping */
+ encoder->get_config = bxt_ddi_get_config;
} else if (IS_GEN9_BC(dev_priv)) {
encoder->enable_clock = skl_ddi_enable_clock;
encoder->disable_clock = skl_ddi_disable_clock;
+ encoder->get_config = skl_ddi_get_config;
} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
encoder->enable_clock = hsw_ddi_enable_clock;
encoder->disable_clock = hsw_ddi_disable_clock;
+ encoder->get_config = hsw_ddi_get_config;
}
if (IS_DG1(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 4a0c1d5c85e7..0780c47efe0f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -30,9 +30,15 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
const struct drm_connector_state *old_conn_state);
void intel_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_ddi_get_clock(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct intel_shared_dpll *pll);
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_disable_clock(struct intel_encoder *encoder);
+void hsw_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
@@ -48,8 +54,6 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config);
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
bool state);
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 958c2a796bae..8b5cb814b679 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6523,212 +6523,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
return ret;
}
-static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- enum phy phy = intel_port_to_phy(dev_priv, port);
- struct icl_port_dpll *port_dpll;
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- u32 clk_sel;
-
- clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
-
- if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
- return;
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
- port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
-
- port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &port_dpll->hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
-
- icl_set_active_port_dpll(pipe_config, port_dpll_id);
-}
-
-static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- enum phy phy = intel_port_to_phy(dev_priv, port);
- enum icl_port_dpll_id port_dpll_id;
- struct icl_port_dpll *port_dpll;
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- i915_reg_t reg;
- u32 temp;
-
- if (intel_phy_is_combo(dev_priv, phy)) {
- u32 mask, shift;
-
- if (IS_ALDERLAKE_S(dev_priv)) {
- reg = ADLS_DPCLKA_CFGCR(phy);
- mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
- shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
- } else if (IS_ROCKETLAKE(dev_priv)) {
- reg = ICL_DPCLKA_CFGCR0;
- mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
- } else {
- reg = ICL_DPCLKA_CFGCR0;
- mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
- }
-
- temp = intel_de_read(dev_priv, reg) & mask;
- id = temp >> shift;
- port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- } else if (intel_phy_is_tc(dev_priv, phy)) {
- u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
-
- if (clk_sel == DDI_CLK_SEL_MG) {
- id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
- port));
- port_dpll_id = ICL_PORT_DPLL_MG_PHY;
- } else {
- drm_WARN_ON(&dev_priv->drm,
- clk_sel < DDI_CLK_SEL_TBT_162);
- id = DPLL_ID_ICL_TBTPLL;
- port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- }
- } else {
- drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
- return;
- }
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
- port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
-
- port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &port_dpll->hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
-
- icl_set_active_port_dpll(pipe_config, port_dpll_id);
-}
-
-static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- u32 temp;
-
- temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-
- if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
- return;
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
-
- pipe_config->shared_dpll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &pipe_config->dpll_hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
-}
-
-static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
- enum port port,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
-
- switch (port) {
- case PORT_A:
- id = DPLL_ID_SKL_DPLL0;
- break;
- case PORT_B:
- id = DPLL_ID_SKL_DPLL1;
- break;
- case PORT_C:
- id = DPLL_ID_SKL_DPLL2;
- break;
- default:
- drm_err(&dev_priv->drm, "Incorrect port type\n");
- return;
- }
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
-
- pipe_config->shared_dpll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &pipe_config->dpll_hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
-}
-
-static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- u32 temp;
-
- temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
- id = temp >> (port * 3 + 1);
-
- if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
- return;
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
-
- pipe_config->shared_dpll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &pipe_config->dpll_hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
-}
-
-static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
- bool pll_active;
-
- switch (ddi_pll_sel) {
- case PORT_CLK_SEL_WRPLL1:
- id = DPLL_ID_WRPLL1;
- break;
- case PORT_CLK_SEL_WRPLL2:
- id = DPLL_ID_WRPLL2;
- break;
- case PORT_CLK_SEL_SPLL:
- id = DPLL_ID_SPLL;
- break;
- case PORT_CLK_SEL_LCPLL_810:
- id = DPLL_ID_LCPLL_810;
- break;
- case PORT_CLK_SEL_LCPLL_1350:
- id = DPLL_ID_LCPLL_1350;
- break;
- case PORT_CLK_SEL_LCPLL_2700:
- id = DPLL_ID_LCPLL_2700;
- break;
- default:
- MISSING_CASE(ddi_pll_sel);
- fallthrough;
- case PORT_CLK_SEL_NONE:
- return;
- }
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
-
- pipe_config->shared_dpll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
- &pipe_config->dpll_hw_state);
- drm_WARN_ON(&dev_priv->drm, !pll_active);
-}
-
static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config,
struct intel_display_power_domain_set *power_domain_set)
@@ -6885,19 +6679,6 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
}
- if (IS_DG1(dev_priv))
- dg1_get_ddi_pll(dev_priv, port, pipe_config);
- else if (INTEL_GEN(dev_priv) >= 11)
- icl_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_CANNONLAKE(dev_priv))
- cnl_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_GEN9_LP(dev_priv))
- bxt_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_GEN9_BC(dev_priv))
- skl_get_ddi_pll(dev_priv, port, pipe_config);
- else
- hsw_get_ddi_pll(dev_priv, port, pipe_config);
-
/*
* Haswell has only FDI/PCH transcoder A. It is which is connected to
* DDI E. So just check whether this pipe is wired to DDI E and whether
--
2.26.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config()
2021-02-24 14:42 ` [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
@ 2021-03-08 13:11 ` Kahola, Mika
0 siblings, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-08 13:11 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to
> encoder->get_config()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the *_get_ddi_pll() stuff into the encodet->get_config() hook.
> There it neatly sits next to the matching .{enable,disable}_clock() functions.
>
> In order to avoid excessive boilerplate I changed the behaviour such that all
> platforms now do the readout via crtc_state->port_dpll[].
>
> ICL+ TC is still a bit special due to TBTPLL not having a functional
> .get_freq(). Should probably change that by adopting the LCPLL approach,
> but that would require a fairly substantial rework of the DPLL ID handling. So
> leave it for later.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 321 +++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_ddi.h | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 219 -------------
> 5 files changed, 306 insertions(+), 250 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 05d5709ae537..29fe4919392a 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1490,14 +1490,10 @@ static void
> gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, static void
> gen11_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>
> - /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> - pipe_config->port_clock = intel_dpll_get_freq(i915,
> - pipe_config->shared_dpll,
> - &pipe_config-
> >dpll_hw_state);
> + intel_ddi_get_clock(encoder, pipe_config,
> +icl_ddi_combo_get_pll(encoder));
>
> pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> if (intel_dsi->dual_link)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 91a8a42b4aa2..b03f74076f64 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -142,7 +142,7 @@ static void hsw_crt_get_config(struct intel_encoder
> *encoder, {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - intel_ddi_get_config(encoder, pipe_config);
> + hsw_ddi_get_config(encoder, pipe_config);
>
> pipe_config->hw.adjusted_mode.flags &=
> ~(DRM_MODE_FLAG_PHSYNC |
> DRM_MODE_FLAG_NHSYNC |
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index eeae78097a20..56f5f55a7c8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -304,25 +304,6 @@ static void ddi_dotclock_get(struct intel_crtc_state
> *pipe_config)
> pipe_config->hw.adjusted_mode.crtc_clock = dotclock; }
>
> -static void intel_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -
> - if (intel_phy_is_tc(dev_priv, phy) &&
> - intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
> - DPLL_ID_ICL_TBTPLL)
> - pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
> - encoder-
> >port);
> - else
> - pipe_config->port_clock =
> - intel_dpll_get_freq(dev_priv, pipe_config-
> >shared_dpll,
> - &pipe_config->dpll_hw_state);
> -
> - ddi_dotclock_get(pipe_config);
> -}
> -
> void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state) {
> @@ -1608,6 +1589,17 @@ static void _cnl_ddi_disable_clock(struct
> drm_i915_private *i915, i915_reg_t reg
> mutex_unlock(&i915->dpll.lock);
> }
>
> +static struct intel_shared_dpll *
> +_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
> + u32 clk_sel_mask, u32 clk_sel_shift) {
> + enum intel_dpll_id id;
> +
> + id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
> +
> + return intel_get_shared_dpll_by_id(i915, id); }
> +
> static void adls_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1633,6 +1625,16 @@ static void adls_ddi_disable_clock(struct
> intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
> +
> ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
> + ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
> +}
> +
> static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1658,6 +1660,16 @@ static void rkl_ddi_disable_clock(struct
> intel_encoder *encoder)
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
> +
> RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
> +
> RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
> +}
> +
> static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1692,6 +1704,16 @@ static void dg1_ddi_disable_clock(struct
> intel_encoder *encoder)
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_get_pll(i915, DG1_DPCLKA_CFGCR0(phy),
> +
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
> +
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
> +}
> +
> static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1717,6 +1739,16 @@ static void icl_ddi_combo_disable_clock(struct
> intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
> +
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
> +
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
> +}
> +
> static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1784,6 +1816,36 @@ static void icl_ddi_tc_disable_clock(struct
> intel_encoder *encoder)
> intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); }
>
> +static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct
> +intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
> + enum port port = encoder->port;
> + enum intel_dpll_id id;
> + u32 tmp;
> +
> + tmp = intel_de_read(i915, DDI_CLK_SEL(port));
> +
> + switch (tmp & DDI_CLK_SEL_MASK) {
> + case DDI_CLK_SEL_TBT_162:
> + case DDI_CLK_SEL_TBT_270:
> + case DDI_CLK_SEL_TBT_540:
> + case DDI_CLK_SEL_TBT_810:
> + id = DPLL_ID_ICL_TBTPLL;
> + break;
> + case DDI_CLK_SEL_MG:
> + id = icl_tc_port_to_pll_id(tc_port);
> + break;
> + default:
> + MISSING_CASE(tmp);
> + fallthrough;
> + case DDI_CLK_SEL_NONE:
> + return NULL;
> + }
> +
> + return intel_get_shared_dpll_by_id(i915, id); }
> +
> static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1809,6 +1871,39 @@ static void cnl_ddi_disable_clock(struct
> intel_encoder *encoder)
> DPCLKA_CFGCR0_DDI_CLK_OFF(port)); }
>
> +static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> +
> + return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,
> + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
> + DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
> +}
> +
> +static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum intel_dpll_id id;
> +
> + switch (encoder->port) {
> + case PORT_A:
> + id = DPLL_ID_SKL_DPLL0;
> + break;
> + case PORT_B:
> + id = DPLL_ID_SKL_DPLL1;
> + break;
> + case PORT_C:
> + id = DPLL_ID_SKL_DPLL2;
> + break;
> + default:
> + MISSING_CASE(encoder->port);
> + return NULL;
> + }
> +
> + return intel_get_shared_dpll_by_id(i915, id); }
> +
> static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1843,6 +1938,28 @@ static void skl_ddi_disable_clock(struct
> intel_encoder *encoder)
> mutex_unlock(&i915->dpll.lock);
> }
>
> +static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> + enum intel_dpll_id id;
> + u32 tmp;
> +
> + tmp = intel_de_read(i915, DPLL_CTRL2);
> +
> + /*
> + * FIXME Not sure if the override affects both
> + * the PLL selection and the CLK_OFF bit.
> + */
> + if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
> + return NULL;
> +
> + id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
> + DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
> +
> + return intel_get_shared_dpll_by_id(i915, id); }
> +
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) { @@ -
> 1864,6 +1981,44 @@ void hsw_ddi_disable_clock(struct intel_encoder
> *encoder)
> intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); }
>
> +static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> + enum intel_dpll_id id;
> + u32 tmp;
> +
> + tmp = intel_de_read(i915, PORT_CLK_SEL(port));
> +
> + switch (tmp & PORT_CLK_SEL_MASK) {
> + case PORT_CLK_SEL_WRPLL1:
> + id = DPLL_ID_WRPLL1;
> + break;
> + case PORT_CLK_SEL_WRPLL2:
> + id = DPLL_ID_WRPLL2;
> + break;
> + case PORT_CLK_SEL_SPLL:
> + id = DPLL_ID_SPLL;
> + break;
> + case PORT_CLK_SEL_LCPLL_810:
> + id = DPLL_ID_LCPLL_810;
> + break;
> + case PORT_CLK_SEL_LCPLL_1350:
> + id = DPLL_ID_LCPLL_1350;
> + break;
> + case PORT_CLK_SEL_LCPLL_2700:
> + id = DPLL_ID_LCPLL_2700;
> + break;
> + default:
> + MISSING_CASE(tmp);
> + fallthrough;
> + case PORT_CLK_SEL_NONE:
> + return NULL;
> + }
> +
> + return intel_get_shared_dpll_by_id(i915, id); }
> +
> void intel_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) { @@ -
> 3293,8 +3448,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder
> *encoder,
> }
> }
>
> -void intel_ddi_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> +static void intel_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> @@ -3341,7 +3496,7 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> }
>
> if (!pipe_config->bigjoiner_slave)
> - intel_ddi_clock_get(encoder, pipe_config);
> + ddi_dotclock_get(pipe_config);
>
> if (IS_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> @@ -3371,6 +3526,114 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); }
>
> +void intel_ddi_get_clock(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + struct intel_shared_dpll *pll)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> + struct icl_port_dpll *port_dpll = &crtc_state-
> >icl_port_dplls[port_dpll_id];
> + bool pll_active;
> +
> + port_dpll->pll = pll;
> + pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
> + drm_WARN_ON(&i915->drm, !pll_active);
> +
> + icl_set_active_port_dpll(crtc_state, port_dpll_id);
> +
> + crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state-
> >shared_dpll,
> + &crtc_state-
> >dpll_hw_state); }
> +
> +static void adls_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void rkl_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void dg1_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state,
> icl_ddi_combo_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum icl_port_dpll_id port_dpll_id;
> + struct icl_port_dpll *port_dpll;
> + struct intel_shared_dpll *pll;
> + bool pll_active;
> +
> + pll = icl_ddi_tc_get_pll(encoder);
> +
> + if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
> + port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> + else
> + port_dpll_id = ICL_PORT_DPLL_MG_PHY;
> +
> + port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
> +
> + port_dpll->pll = pll;
> + pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
> + drm_WARN_ON(&i915->drm, !pll_active);
> +
> + icl_set_active_port_dpll(crtc_state, port_dpll_id);
> +
> + if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) ==
> DPLL_ID_ICL_TBTPLL)
> + crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder-
> >port);
> + else
> + crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state-
> >shared_dpll,
> + &crtc_state-
> >dpll_hw_state);
> +
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void cnl_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void bxt_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +static void skl_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> +void hsw_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state) {
> + intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
> + intel_ddi_get_config(encoder, crtc_state); }
> +
> static void intel_ddi_sync_state(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -4057,7 +4320,6 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> encoder->post_disable = intel_ddi_post_disable;
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> - encoder->get_config = intel_ddi_get_config;
> encoder->sync_state = intel_ddi_sync_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend; @@ -4073,37
> +4335,50 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum
> port port)
> if (IS_ALDERLAKE_S(dev_priv)) {
> encoder->enable_clock = adls_ddi_enable_clock;
> encoder->disable_clock = adls_ddi_disable_clock;
> + encoder->get_config = adls_ddi_get_config;
> } else if (IS_ROCKETLAKE(dev_priv)) {
> encoder->enable_clock = rkl_ddi_enable_clock;
> encoder->disable_clock = rkl_ddi_disable_clock;
> + encoder->get_config = rkl_ddi_get_config;
> } else if (IS_DG1(dev_priv)) {
> encoder->enable_clock = dg1_ddi_enable_clock;
> encoder->disable_clock = dg1_ddi_disable_clock;
> + encoder->get_config = dg1_ddi_get_config;
> } else if (IS_JSL_EHL(dev_priv)) {
> if (intel_ddi_is_tc(dev_priv, port)) {
> encoder->enable_clock = jsl_ddi_tc_enable_clock;
> encoder->disable_clock = jsl_ddi_tc_disable_clock;
> + encoder->get_config = icl_ddi_combo_get_config;
> } else {
> encoder->enable_clock =
> icl_ddi_combo_enable_clock;
> encoder->disable_clock =
> icl_ddi_combo_disable_clock;
> + encoder->get_config = icl_ddi_combo_get_config;
> }
> } else if (INTEL_GEN(dev_priv) >= 11) {
> if (intel_ddi_is_tc(dev_priv, port)) {
> encoder->enable_clock = icl_ddi_tc_enable_clock;
> encoder->disable_clock = icl_ddi_tc_disable_clock;
> + encoder->get_config = icl_ddi_tc_get_config;
> } else {
> encoder->enable_clock =
> icl_ddi_combo_enable_clock;
> encoder->disable_clock =
> icl_ddi_combo_disable_clock;
> + encoder->get_config = icl_ddi_combo_get_config;
> }
> } else if (IS_CANNONLAKE(dev_priv)) {
> encoder->enable_clock = cnl_ddi_enable_clock;
> encoder->disable_clock = cnl_ddi_disable_clock;
> + encoder->get_config = cnl_ddi_get_config;
> + } else if (IS_GEN9_LP(dev_priv)) {
> + /* BXT/GLK have fixed PLL->port mapping */
> + encoder->get_config = bxt_ddi_get_config;
> } else if (IS_GEN9_BC(dev_priv)) {
> encoder->enable_clock = skl_ddi_enable_clock;
> encoder->disable_clock = skl_ddi_disable_clock;
> + encoder->get_config = skl_ddi_get_config;
> } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> encoder->enable_clock = hsw_ddi_enable_clock;
> encoder->disable_clock = hsw_ddi_disable_clock;
> + encoder->get_config = hsw_ddi_get_config;
> }
>
> if (IS_DG1(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 4a0c1d5c85e7..0780c47efe0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -30,9 +30,15 @@ void intel_ddi_fdi_post_disable(struct
> intel_atomic_state *state,
> const struct drm_connector_state
> *old_conn_state); void intel_ddi_enable_clock(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state);
> +void intel_ddi_get_clock(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state,
> + struct intel_shared_dpll *pll);
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state); void
> hsw_ddi_disable_clock(struct intel_encoder *encoder);
> +void hsw_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state); struct
> intel_shared_dpll
> +*icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -48,8
> +54,6 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
> *crtc_state); void intel_ddi_set_dp_msa(const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state *conn_state);
> bool intel_ddi_connector_get_hw_state(struct intel_connector
> *intel_connector); -void intel_ddi_get_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> bool state);
> void intel_ddi_compute_min_voltage_level(struct drm_i915_private
> *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 958c2a796bae..8b5cb814b679 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6523,212 +6523,6 @@ static bool ilk_get_pipe_config(struct intel_crtc
> *crtc,
> return ret;
> }
>
> -static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port
> port,
> - struct intel_crtc_state *pipe_config)
> -{
> - enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> - enum phy phy = intel_port_to_phy(dev_priv, port);
> - struct icl_port_dpll *port_dpll;
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - bool pll_active;
> - u32 clk_sel;
> -
> - clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) &
> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
> -
> - if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
> - return;
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> - port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
> -
> - port_dpll->pll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &port_dpll->hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -
> - icl_set_active_port_dpll(pipe_config, port_dpll_id);
> -}
> -
> -static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port
> port,
> - struct intel_crtc_state *pipe_config)
> -{
> - enum phy phy = intel_port_to_phy(dev_priv, port);
> - enum icl_port_dpll_id port_dpll_id;
> - struct icl_port_dpll *port_dpll;
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - bool pll_active;
> - i915_reg_t reg;
> - u32 temp;
> -
> - if (intel_phy_is_combo(dev_priv, phy)) {
> - u32 mask, shift;
> -
> - if (IS_ALDERLAKE_S(dev_priv)) {
> - reg = ADLS_DPCLKA_CFGCR(phy);
> - mask =
> ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
> - shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
> - } else if (IS_ROCKETLAKE(dev_priv)) {
> - reg = ICL_DPCLKA_CFGCR0;
> - mask =
> RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - shift =
> RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> - } else {
> - reg = ICL_DPCLKA_CFGCR0;
> - mask =
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - shift =
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> - }
> -
> - temp = intel_de_read(dev_priv, reg) & mask;
> - id = temp >> shift;
> - port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> - } else if (intel_phy_is_tc(dev_priv, phy)) {
> - u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) &
> DDI_CLK_SEL_MASK;
> -
> - if (clk_sel == DDI_CLK_SEL_MG) {
> - id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
> - port));
> - port_dpll_id = ICL_PORT_DPLL_MG_PHY;
> - } else {
> - drm_WARN_ON(&dev_priv->drm,
> - clk_sel < DDI_CLK_SEL_TBT_162);
> - id = DPLL_ID_ICL_TBTPLL;
> - port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> - }
> - } else {
> - drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
> - return;
> - }
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> - port_dpll = &pipe_config->icl_port_dplls[port_dpll_id];
> -
> - port_dpll->pll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &port_dpll->hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -
> - icl_set_active_port_dpll(pipe_config, port_dpll_id);
> -}
> -
> -static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port
> port,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - bool pll_active;
> - u32 temp;
> -
> - temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) &
> DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> -
> - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id >
> SKL_DPLL2))
> - return;
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> -
> - pipe_config->shared_dpll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &pipe_config->dpll_hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -}
> -
> -static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
> - enum port port,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - bool pll_active;
> -
> - switch (port) {
> - case PORT_A:
> - id = DPLL_ID_SKL_DPLL0;
> - break;
> - case PORT_B:
> - id = DPLL_ID_SKL_DPLL1;
> - break;
> - case PORT_C:
> - id = DPLL_ID_SKL_DPLL2;
> - break;
> - default:
> - drm_err(&dev_priv->drm, "Incorrect port type\n");
> - return;
> - }
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> -
> - pipe_config->shared_dpll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &pipe_config->dpll_hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -}
> -
> -static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port
> port,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - bool pll_active;
> - u32 temp;
> -
> - temp = intel_de_read(dev_priv, DPLL_CTRL2) &
> DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
> - id = temp >> (port * 3 + 1);
> -
> - if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id >
> SKL_DPLL3))
> - return;
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> -
> - pipe_config->shared_dpll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &pipe_config->dpll_hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -}
> -
> -static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port
> port,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct intel_shared_dpll *pll;
> - enum intel_dpll_id id;
> - u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
> - bool pll_active;
> -
> - switch (ddi_pll_sel) {
> - case PORT_CLK_SEL_WRPLL1:
> - id = DPLL_ID_WRPLL1;
> - break;
> - case PORT_CLK_SEL_WRPLL2:
> - id = DPLL_ID_WRPLL2;
> - break;
> - case PORT_CLK_SEL_SPLL:
> - id = DPLL_ID_SPLL;
> - break;
> - case PORT_CLK_SEL_LCPLL_810:
> - id = DPLL_ID_LCPLL_810;
> - break;
> - case PORT_CLK_SEL_LCPLL_1350:
> - id = DPLL_ID_LCPLL_1350;
> - break;
> - case PORT_CLK_SEL_LCPLL_2700:
> - id = DPLL_ID_LCPLL_2700;
> - break;
> - default:
> - MISSING_CASE(ddi_pll_sel);
> - fallthrough;
> - case PORT_CLK_SEL_NONE:
> - return;
> - }
> -
> - pll = intel_get_shared_dpll_by_id(dev_priv, id);
> -
> - pipe_config->shared_dpll = pll;
> - pll_active = intel_dpll_get_hw_state(dev_priv, pll,
> - &pipe_config->dpll_hw_state);
> - drm_WARN_ON(&dev_priv->drm, !pll_active);
> -}
> -
> static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config,
> struct intel_display_power_domain_set
> *power_domain_set) @@ -6885,19 +6679,6 @@ static void
> hsw_get_ddi_port_state(struct intel_crtc *crtc,
> port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
> }
>
> - if (IS_DG1(dev_priv))
> - dg1_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (INTEL_GEN(dev_priv) >= 11)
> - icl_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_CANNONLAKE(dev_priv))
> - cnl_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_GEN9_LP(dev_priv))
> - bxt_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_GEN9_BC(dev_priv))
> - skl_get_ddi_pll(dev_priv, port, pipe_config);
> - else
> - hsw_get_ddi_pll(dev_priv, port, pipe_config);
> -
> /*
> * Haswell has only FDI/PCH transcoder A. It is which is connected to
> * DDI E. So just check whether this pipe is wired to DDI E and
> whether
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled()
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (3 preceding siblings ...)
2021-02-24 14:42 ` [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
@ 2021-02-24 14:42 ` Ville Syrjala
2021-03-08 13:16 ` Kahola, Mika
2021-02-24 14:42 ` [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms Ville Syrjala
` (5 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2021-02-24 14:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Support reading out the current state of the DDI clock.
Not sure we really want this. Seems a bit excessive just to
restore the debug print to icl_sanitize_encoder_pll_mapping()?
But maybe there's more use for it?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 19 +++
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 123 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
.../drm/i915/display/intel_display_types.h | 4 +
5 files changed, 146 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 29fe4919392a..7f2abc088a66 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -655,6 +655,24 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
mutex_unlock(&dev_priv->dpll.lock);
}
+static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ bool clock_enabled = false;
+ enum phy phy;
+ u32 tmp;
+
+ tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
+ clock_enabled = true;
+ }
+
+ return clock_enabled;
+}
+
static void gen11_dsi_map_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1939,6 +1957,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->power_domain = POWER_DOMAIN_PORT_DSI;
encoder->get_power_domains = gen11_dsi_get_power_domains;
encoder->disable_clock = gen11_dsi_gate_clocks;
+ encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
/* register DSI connector with DRM subsystem */
drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index b03f74076f64..7f3d11c5ce3e 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1078,6 +1078,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
crt->base.post_disable = hsw_post_disable_crt;
crt->base.enable_clock = hsw_ddi_enable_clock;
crt->base.disable_clock = hsw_ddi_disable_clock;
+ crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
} else {
if (HAS_PCH_SPLIT(dev_priv)) {
crt->base.compute_config = pch_crt_compute_config;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 56f5f55a7c8f..7d477c4007c7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1589,6 +1589,12 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
mutex_unlock(&i915->dpll.lock);
}
+static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
+ u32 clk_off)
+{
+ return !(intel_de_read(i915, reg) & clk_off);
+}
+
static struct intel_shared_dpll *
_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel_shift)
@@ -1625,6 +1631,15 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
+ ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1660,6 +1675,15 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
+ RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1704,6 +1728,15 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1739,6 +1772,15 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
+static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
+ ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1778,6 +1820,20 @@ static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
}
+static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 tmp;
+
+ tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+
+ if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
+ return false;
+
+ return icl_ddi_combo_is_clock_enabled(encoder);
+}
+
static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -1816,6 +1872,23 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
}
+static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
+ enum port port = encoder->port;
+ u32 tmp;
+
+ tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+
+ if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
+ return false;
+
+ tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
+
+ return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
+}
+
static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1871,6 +1944,15 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
}
+static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,
+ DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+}
+
static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1938,6 +2020,18 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
mutex_unlock(&i915->dpll.lock);
}
+static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ /*
+ * FIXME Not sure if the override affects both
+ * the PLL selection and the CLK_OFF bit.
+ */
+ return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
+}
+
static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -1981,6 +2075,14 @@ void hsw_ddi_disable_clock(struct intel_encoder *encoder)
intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
}
+bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
+}
+
static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -2084,8 +2186,15 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
ddi_clk_needed = false;
}
- if (!ddi_clk_needed && encoder->disable_clock)
- encoder->disable_clock(encoder);
+ if (ddi_clk_needed || !encoder->disable_clock ||
+ !encoder->is_clock_enabled(encoder))
+ return;
+
+ drm_notice(&i915->drm,
+ "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+ encoder->base.base.id, encoder->base.name);
+
+ encoder->disable_clock(encoder);
}
static void
@@ -4335,38 +4444,46 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
if (IS_ALDERLAKE_S(dev_priv)) {
encoder->enable_clock = adls_ddi_enable_clock;
encoder->disable_clock = adls_ddi_disable_clock;
+ encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
encoder->get_config = adls_ddi_get_config;
} else if (IS_ROCKETLAKE(dev_priv)) {
encoder->enable_clock = rkl_ddi_enable_clock;
encoder->disable_clock = rkl_ddi_disable_clock;
+ encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
encoder->get_config = rkl_ddi_get_config;
} else if (IS_DG1(dev_priv)) {
encoder->enable_clock = dg1_ddi_enable_clock;
encoder->disable_clock = dg1_ddi_disable_clock;
+ encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
encoder->get_config = dg1_ddi_get_config;
} else if (IS_JSL_EHL(dev_priv)) {
if (intel_ddi_is_tc(dev_priv, port)) {
encoder->enable_clock = jsl_ddi_tc_enable_clock;
encoder->disable_clock = jsl_ddi_tc_disable_clock;
+ encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
encoder->get_config = icl_ddi_combo_get_config;
} else {
encoder->enable_clock = icl_ddi_combo_enable_clock;
encoder->disable_clock = icl_ddi_combo_disable_clock;
+ encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
encoder->get_config = icl_ddi_combo_get_config;
}
} else if (INTEL_GEN(dev_priv) >= 11) {
if (intel_ddi_is_tc(dev_priv, port)) {
encoder->enable_clock = icl_ddi_tc_enable_clock;
encoder->disable_clock = icl_ddi_tc_disable_clock;
+ encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
encoder->get_config = icl_ddi_tc_get_config;
} else {
encoder->enable_clock = icl_ddi_combo_enable_clock;
encoder->disable_clock = icl_ddi_combo_disable_clock;
+ encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
encoder->get_config = icl_ddi_combo_get_config;
}
} else if (IS_CANNONLAKE(dev_priv)) {
encoder->enable_clock = cnl_ddi_enable_clock;
encoder->disable_clock = cnl_ddi_disable_clock;
+ encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
encoder->get_config = cnl_ddi_get_config;
} else if (IS_GEN9_LP(dev_priv)) {
/* BXT/GLK have fixed PLL->port mapping */
@@ -4374,10 +4491,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
} else if (IS_GEN9_BC(dev_priv)) {
encoder->enable_clock = skl_ddi_enable_clock;
encoder->disable_clock = skl_ddi_disable_clock;
+ encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
encoder->get_config = skl_ddi_get_config;
} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
encoder->enable_clock = hsw_ddi_enable_clock;
encoder->disable_clock = hsw_ddi_disable_clock;
+ encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
encoder->get_config = hsw_ddi_get_config;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 0780c47efe0f..99cebbe6b586 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -36,6 +36,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_disable_clock(struct intel_encoder *encoder);
+bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder);
void hsw_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1a76e1d9de7a..5b2e81db0a20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -226,6 +226,10 @@ struct intel_encoder {
void (*enable_clock)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void (*disable_clock)(struct intel_encoder *encoder);
+ /*
+ * Returns whether the port clock is enabled or not.
+ */
+ bool (*is_clock_enabled)(struct intel_encoder *encoder);
enum hpd_pin hpd_pin;
enum intel_display_power_domain power_domain;
/* for communication with audio component; protected by av_mutex */
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled()
2021-02-24 14:42 ` [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled() Ville Syrjala
@ 2021-03-08 13:16 ` Kahola, Mika
0 siblings, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-08 13:16 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled()
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Support reading out the current state of the DDI clock.
>
> Not sure we really want this. Seems a bit excessive just to restore the debug
> print to icl_sanitize_encoder_pll_mapping()?
> But maybe there's more use for it?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I guess there is no harm done if we have the state of the DDI clock in store.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 19 +++
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 123 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
> .../drm/i915/display/intel_display_types.h | 4 +
> 5 files changed, 146 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 29fe4919392a..7f2abc088a66 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -655,6 +655,24 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
> mutex_unlock(&dev_priv->dpll.lock);
> }
>
> +static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + bool clock_enabled = false;
> + enum phy phy;
> + u32 tmp;
> +
> + tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
> + clock_enabled = true;
> + }
> +
> + return clock_enabled;
> +}
> +
> static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) { @@ -
> 1939,6 +1957,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->power_domain = POWER_DOMAIN_PORT_DSI;
> encoder->get_power_domains = gen11_dsi_get_power_domains;
> encoder->disable_clock = gen11_dsi_gate_clocks;
> + encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
>
> /* register DSI connector with DRM subsystem */
> drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index b03f74076f64..7f3d11c5ce3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -1078,6 +1078,7 @@ void intel_crt_init(struct drm_i915_private
> *dev_priv)
> crt->base.post_disable = hsw_post_disable_crt;
> crt->base.enable_clock = hsw_ddi_enable_clock;
> crt->base.disable_clock = hsw_ddi_disable_clock;
> + crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
> } else {
> if (HAS_PCH_SPLIT(dev_priv)) {
> crt->base.compute_config =
> pch_crt_compute_config; diff --git
> a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 56f5f55a7c8f..7d477c4007c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1589,6 +1589,12 @@ static void _cnl_ddi_disable_clock(struct
> drm_i915_private *i915, i915_reg_t reg
> mutex_unlock(&i915->dpll.lock);
> }
>
> +static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915,
> i915_reg_t reg,
> + u32 clk_off)
> +{
> + return !(intel_de_read(i915, reg) & clk_off); }
> +
> static struct intel_shared_dpll *
> _cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
> u32 clk_sel_mask, u32 clk_sel_shift) @@ -1625,6 +1631,15
> @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
> +
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +}
> +
> static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1660,6 +1675,15 @@ static void rkl_ddi_disable_clock(struct intel_encoder
> *encoder)
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
> +
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +}
> +
> static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1704,6 +1728,15 @@ static void dg1_ddi_disable_clock(struct intel_encoder
> *encoder)
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
> +
> DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +}
> +
> static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1739,6 +1772,15 @@ static void icl_ddi_combo_disable_clock(struct
> intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder
> +*encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
> +
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +}
> +
> struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1778,6 +1820,20 @@ static void jsl_ddi_tc_disable_clock(struct intel_encoder
> *encoder)
> intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); }
>
> +static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> + u32 tmp;
> +
> + tmp = intel_de_read(i915, DDI_CLK_SEL(port));
> +
> + if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
> + return false;
> +
> + return icl_ddi_combo_is_clock_enabled(encoder);
> +}
> +
> static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> @@ -1816,6 +1872,23 @@ static void icl_ddi_tc_disable_clock(struct
> intel_encoder *encoder)
> intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); }
>
> +static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
> + enum port port = encoder->port;
> + u32 tmp;
> +
> + tmp = intel_de_read(i915, DDI_CLK_SEL(port));
> +
> + if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
> + return false;
> +
> + tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
> +
> + return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
> +}
> +
> static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1871,6 +1944,15 @@ static void cnl_ddi_disable_clock(struct intel_encoder
> *encoder)
> DPCLKA_CFGCR0_DDI_CLK_OFF(port)); }
>
> +static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> +
> + return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,
> +
> DPCLKA_CFGCR0_DDI_CLK_OFF(port)); }
> +
> static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1938,6 +2020,18 @@ static void skl_ddi_disable_clock(struct intel_encoder
> *encoder)
> mutex_unlock(&i915->dpll.lock);
> }
>
> +static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> +
> + /*
> + * FIXME Not sure if the override affects both
> + * the PLL selection and the CLK_OFF bit.
> + */
> + return !(intel_de_read(i915, DPLL_CTRL2) &
> +DPLL_CTRL2_DDI_CLK_OFF(port)); }
> +
> static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1981,6 +2075,14 @@ void hsw_ddi_disable_clock(struct intel_encoder
> *encoder)
> intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); }
>
> +bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum port port = encoder->port;
> +
> + return intel_de_read(i915, PORT_CLK_SEL(port)) !=
> PORT_CLK_SEL_NONE; }
> +
> static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 2084,8 +2186,15 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
> ddi_clk_needed = false;
> }
>
> - if (!ddi_clk_needed && encoder->disable_clock)
> - encoder->disable_clock(encoder);
> + if (ddi_clk_needed || !encoder->disable_clock ||
> + !encoder->is_clock_enabled(encoder))
> + return;
> +
> + drm_notice(&i915->drm,
> + "[ENCODER:%d:%s] is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> + encoder->base.base.id, encoder->base.name);
> +
> + encoder->disable_clock(encoder);
> }
>
> static void
> @@ -4335,38 +4444,46 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> if (IS_ALDERLAKE_S(dev_priv)) {
> encoder->enable_clock = adls_ddi_enable_clock;
> encoder->disable_clock = adls_ddi_disable_clock;
> + encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
> encoder->get_config = adls_ddi_get_config;
> } else if (IS_ROCKETLAKE(dev_priv)) {
> encoder->enable_clock = rkl_ddi_enable_clock;
> encoder->disable_clock = rkl_ddi_disable_clock;
> + encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
> encoder->get_config = rkl_ddi_get_config;
> } else if (IS_DG1(dev_priv)) {
> encoder->enable_clock = dg1_ddi_enable_clock;
> encoder->disable_clock = dg1_ddi_disable_clock;
> + encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
> encoder->get_config = dg1_ddi_get_config;
> } else if (IS_JSL_EHL(dev_priv)) {
> if (intel_ddi_is_tc(dev_priv, port)) {
> encoder->enable_clock = jsl_ddi_tc_enable_clock;
> encoder->disable_clock = jsl_ddi_tc_disable_clock;
> + encoder->is_clock_enabled =
> jsl_ddi_tc_is_clock_enabled;
> encoder->get_config = icl_ddi_combo_get_config;
> } else {
> encoder->enable_clock =
> icl_ddi_combo_enable_clock;
> encoder->disable_clock =
> icl_ddi_combo_disable_clock;
> + encoder->is_clock_enabled =
> icl_ddi_combo_is_clock_enabled;
> encoder->get_config = icl_ddi_combo_get_config;
> }
> } else if (INTEL_GEN(dev_priv) >= 11) {
> if (intel_ddi_is_tc(dev_priv, port)) {
> encoder->enable_clock = icl_ddi_tc_enable_clock;
> encoder->disable_clock = icl_ddi_tc_disable_clock;
> + encoder->is_clock_enabled =
> icl_ddi_tc_is_clock_enabled;
> encoder->get_config = icl_ddi_tc_get_config;
> } else {
> encoder->enable_clock =
> icl_ddi_combo_enable_clock;
> encoder->disable_clock =
> icl_ddi_combo_disable_clock;
> + encoder->is_clock_enabled =
> icl_ddi_combo_is_clock_enabled;
> encoder->get_config = icl_ddi_combo_get_config;
> }
> } else if (IS_CANNONLAKE(dev_priv)) {
> encoder->enable_clock = cnl_ddi_enable_clock;
> encoder->disable_clock = cnl_ddi_disable_clock;
> + encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
> encoder->get_config = cnl_ddi_get_config;
> } else if (IS_GEN9_LP(dev_priv)) {
> /* BXT/GLK have fixed PLL->port mapping */ @@ -4374,10
> +4491,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum
> port port)
> } else if (IS_GEN9_BC(dev_priv)) {
> encoder->enable_clock = skl_ddi_enable_clock;
> encoder->disable_clock = skl_ddi_disable_clock;
> + encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
> encoder->get_config = skl_ddi_get_config;
> } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> encoder->enable_clock = hsw_ddi_enable_clock;
> encoder->disable_clock = hsw_ddi_disable_clock;
> + encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
> encoder->get_config = hsw_ddi_get_config;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 0780c47efe0f..99cebbe6b586 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -36,6 +36,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
> void hsw_ddi_enable_clock(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state); void
> hsw_ddi_disable_clock(struct intel_encoder *encoder);
> +bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder);
> void hsw_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state); struct
> intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1a76e1d9de7a..5b2e81db0a20 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -226,6 +226,10 @@ struct intel_encoder {
> void (*enable_clock)(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> void (*disable_clock)(struct intel_encoder *encoder);
> + /*
> + * Returns whether the port clock is enabled or not.
> + */
> + bool (*is_clock_enabled)(struct intel_encoder *encoder);
> enum hpd_pin hpd_pin;
> enum intel_display_power_domain power_domain;
> /* for communication with audio component; protected by av_mutex
> */
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (4 preceding siblings ...)
2021-02-24 14:42 ` [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled() Ville Syrjala
@ 2021-02-24 14:42 ` Ville Syrjala
2021-03-08 13:17 ` Kahola, Mika
2021-02-24 18:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move DDI clock readout to encoder->get_config() Patchwork
` (4 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Ville Syrjala @ 2021-02-24 14:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Now that all the encoder clock stuff is uniformly abstracted
for all hsw+ platforms, let's extend icl_sanitize_encoder_pll_mapping()
to cover all of them.
Not sure there is a particular benefit in doing so, but less special
cases always makes me happy.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.h | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7d477c4007c7..dd2203f87078 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2134,7 +2134,7 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder)
encoder->disable_clock(encoder);
}
-void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
+void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 port_mask;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 99cebbe6b586..59c6b01d4199 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -66,6 +66,6 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp,
int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
enum transcoder cpu_transcoder,
bool enable, u32 hdcp_mask);
-void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
+void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8b5cb814b679..87db5331176b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13144,8 +13144,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
/* notify opregion of the sanitized encoder state */
intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
- if (INTEL_GEN(dev_priv) >= 11)
- icl_sanitize_encoder_pll_mapping(encoder);
+ if (HAS_DDI(dev_priv))
+ intel_ddi_sanitize_encoder_pll_mapping(encoder);
}
/* FIXME read out full plane state for all planes */
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms
2021-02-24 14:42 ` [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms Ville Syrjala
@ 2021-03-08 13:17 ` Kahola, Mika
0 siblings, 0 replies; 20+ messages in thread
From: Kahola, Mika @ 2021-03-08 13:17 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Extend
> icl_sanitize_encoder_pll_mapping() to all DDI platforms
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that all the encoder clock stuff is uniformly abstracted for all hsw+
> platforms, let's extend icl_sanitize_encoder_pll_mapping()
> to cover all of them.
>
> Not sure there is a particular benefit in doing so, but less special cases always
> makes me happy.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.h | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 7d477c4007c7..dd2203f87078 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2134,7 +2134,7 @@ static void intel_ddi_disable_clock(struct
> intel_encoder *encoder)
> encoder->disable_clock(encoder);
> }
>
> -void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> +void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder
> +*encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u32 port_mask;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 99cebbe6b586..59c6b01d4199 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -66,6 +66,6 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp, int
> intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> enum transcoder cpu_transcoder,
> bool enable, u32 hdcp_mask);
> -void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> +void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder
> +*encoder);
>
> #endif /* __INTEL_DDI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8b5cb814b679..87db5331176b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13144,8 +13144,8 @@ static void intel_sanitize_encoder(struct
> intel_encoder *encoder)
> /* notify opregion of the sanitized encoder state */
> intel_opregion_notify_encoder(encoder, connector &&
> has_active_crtc);
>
> - if (INTEL_GEN(dev_priv) >= 11)
> - icl_sanitize_encoder_pll_mapping(encoder);
> + if (HAS_DDI(dev_priv))
> + intel_ddi_sanitize_encoder_pll_mapping(encoder);
> }
>
> /* FIXME read out full plane state for all planes */
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move DDI clock readout to encoder->get_config()
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (5 preceding siblings ...)
2021-02-24 14:42 ` [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms Ville Syrjala
@ 2021-02-24 18:59 ` Patchwork
2021-02-24 19:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-02-24 18:59 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move DDI clock readout to encoder->get_config()
URL : https://patchwork.freedesktop.org/series/87351/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1437:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1491:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move DDI clock readout to encoder->get_config()
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (6 preceding siblings ...)
2021-02-24 18:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move DDI clock readout to encoder->get_config() Patchwork
@ 2021-02-24 19:28 ` Patchwork
2021-02-25 16:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move DDI clock readout to encoder->get_config() (rev2) Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-02-24 19:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5877 bytes --]
== Series Details ==
Series: drm/i915: Move DDI clock readout to encoder->get_config()
URL : https://patchwork.freedesktop.org/series/87351/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9798 -> Patchwork_19726
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19726 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19726, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19726:
### CI changes ###
#### Possible regressions ####
* boot:
- fi-apl-guc: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-apl-guc/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-apl-guc/boot.html
- fi-cfl-8700k: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-cfl-8700k/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-cfl-8700k/boot.html
- fi-skl-6700k2: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-skl-6700k2/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-skl-6700k2/boot.html
- fi-cfl-guc: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-cfl-guc/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-cfl-guc/boot.html
- fi-skl-guc: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-skl-guc/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-skl-guc/boot.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* boot:
- {fi-rkl-11500t}: [PASS][11] -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-rkl-11500t/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-rkl-11500t/boot.html
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- fi-tgl-y: NOTRUN -> [FAIL][13]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-tgl-y/igt@runner@aborted.html
- fi-cml-s: NOTRUN -> [FAIL][14]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-cml-s/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][15]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-tgl-u2/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-jsl-1}: NOTRUN -> [FAIL][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-jsl-1/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_19726 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][17] -> [FAIL][18] ([i915#1372])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@runner@aborted:
- fi-icl-y: NOTRUN -> [FAIL][19] ([i915#1569])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-icl-y/igt@runner@aborted.html
#### Warnings ####
* igt@runner@aborted:
- fi-icl-u2: [FAIL][20] ([i915#1814]) -> [FAIL][21] ([i915#1569] / [k.org#202973])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9798/fi-icl-u2/igt@runner@aborted.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/fi-icl-u2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[k.org#202973]: https://bugzilla.kernel.org/show_bug.cgi?id=202973
Participating hosts (45 -> 38)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-ehl-2 fi-bdw-samus fi-snb-2600
Build changes
-------------
* Linux: CI_DRM_9798 -> Patchwork_19726
CI-20190529: 20190529
CI_DRM_9798: 70e2e79cd772b97799f4cecd823539f452063562 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6013: a6c7181747850161377dae5161d33c0675ab273e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19726: 9fa8dca29b2de607f4b6678569cbef11f2e8897c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9fa8dca29b2d drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms
cf9d399b8223 drm/i915: Add encoder->is_clock_enabled()
7ec7b96ba2c0 drm/i915: Move DDI clock readout to encoder->get_config()
adcf89a394ab drm/i915: Use pipes instead crtc indices in PLL state tracking
9611bc1a6ab1 drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
a544fe9b32f6 drm/i915: Call primary encoder's .get_config() from MST .get_config()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19726/index.html
[-- Attachment #1.2: Type: text/html, Size: 6829 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move DDI clock readout to encoder->get_config() (rev2)
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (7 preceding siblings ...)
2021-02-24 19:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-02-25 16:37 ` Patchwork
2021-02-25 17:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-25 18:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-02-25 16:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move DDI clock readout to encoder->get_config() (rev2)
URL : https://patchwork.freedesktop.org/series/87351/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1437:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1491:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move DDI clock readout to encoder->get_config() (rev2)
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (8 preceding siblings ...)
2021-02-25 16:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move DDI clock readout to encoder->get_config() (rev2) Patchwork
@ 2021-02-25 17:04 ` Patchwork
2021-02-25 18:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-02-25 17:04 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5383 bytes --]
== Series Details ==
Series: drm/i915: Move DDI clock readout to encoder->get_config() (rev2)
URL : https://patchwork.freedesktop.org/series/87351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9804 -> Patchwork_19729
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/index.html
Known issues
------------
Here are the changes found in Patchwork_19729 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-compute0:
- fi-kbl-r: NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-kbl-r/igt@amdgpu/amd_cs_nop@sync-compute0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-r: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-kbl-r/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][3] -> [INCOMPLETE][4] ([i915#142] / [i915#2405])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-r: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-kbl-r/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-r: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-kbl-r/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
* igt@runner@aborted:
- fi-byt-j1900: NOTRUN -> [FAIL][9] ([i915#1814] / [i915#2505])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-byt-j1900/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-soraka: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-kbl-soraka/igt@i915_pm_rpm@module-reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (42 -> 38)
------------------------------
Additional (1): fi-ehl-2
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9804 -> Patchwork_19729
CI-20190529: 20190529
CI_DRM_9804: 0ed1d18cdc37ecf5e07f009a9788ea9ad74677a8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6015: aa44cddf4ef689f8a3726fcbeedc03f08b12bd82 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19729: 80a910e388958d3943d65661cd19781a4c75e74f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
80a910e38895 drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms
f83943e75f3f drm/i915: Add encoder->is_clock_enabled()
48c569d9a71f drm/i915: Move DDI clock readout to encoder->get_config()
cfc935b506b1 drm/i915: Use pipes instead crtc indices in PLL state tracking
77cda7d22e7d drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
28adc57734fc drm/i915: Call primary encoder's .get_config() from MST .get_config()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move DDI clock readout to encoder->get_config() (rev2)
2021-02-24 14:42 [Intel-gfx] [PATCH 0/6] drm/i915: Move DDI clock readout to encoder->get_config() Ville Syrjala
` (9 preceding siblings ...)
2021-02-25 17:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-02-25 18:24 ` Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-02-25 18:24 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30287 bytes --]
== Series Details ==
Series: drm/i915: Move DDI clock readout to encoder->get_config() (rev2)
URL : https://patchwork.freedesktop.org/series/87351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9804_full -> Patchwork_19729_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_19729_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19729_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19729_full:
### IGT changes ###
#### Warnings ####
* igt@runner@aborted:
- shard-kbl: ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4]) ([i915#180] / [i915#2724] / [i915#3002]) -> ([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl3/igt@runner@aborted.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl2/igt@runner@aborted.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl2/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl7/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl2/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl4/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_19729_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-snb2/igt@gem_ctx_persistence@idempotent.html
* igt@gem_exec_balancer@hang:
- shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([i915#1895])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb7/igt@gem_exec_balancer@hang.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb4/igt@gem_exec_balancer@hang.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb7/igt@gem_exec_fair@basic-none@vcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][22] -> [SKIP][23] ([fdo#109271])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][24] -> [FAIL][25] ([i915#2842]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs1:
- shard-tglb: [PASS][26] -> [DMESG-WARN][27] ([i915#2803])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb1/igt@gem_exec_schedule@u-fairslice@vcs1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb6/igt@gem_exec_schedule@u-fairslice@vcs1.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][28] ([i915#3002])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gen3_render_tiledx_blits:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109289])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@gen3_render_tiledx_blits.html
* igt@gen9_exec_parse@bb-start-far:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#112306])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@gen9_exec_parse@bb-start-far.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#1937])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109293] / [fdo#109506])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][33] -> [FAIL][34] ([i915#2521])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#110725] / [fdo#111614])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111304])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl2/igt@kms_ccs@pipe-c-crc-primary-basic.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@kms_ccs@pipe-d-ccs-on-another-bo.html
* igt@kms_chamelium@dp-crc-fast:
- shard-snb: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +10 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-snb7/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +9 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl6/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@vga-frame-dump:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl1/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color@pipe-c-ctm-0-75:
- shard-skl: [PASS][41] -> [DMESG-WARN][42] ([i915#1982])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl10/igt@kms_color@pipe-c-ctm-0-75.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl5/igt@kms_color@pipe-c-ctm-0-75.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-skl: NOTRUN -> [FAIL][43] ([i915#54])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109278] / [fdo#109279]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen:
- shard-kbl: [PASS][45] -> [FAIL][46] ([i915#54])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
- shard-apl: [PASS][47] -> [FAIL][48] ([i915#54])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-apl2/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-64x64-random:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#54]) +5 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-64x64-random.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: [PASS][52] -> [INCOMPLETE][53] ([i915#198])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][54] ([i915#180]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#2122]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2672])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
- shard-snb: NOTRUN -> [SKIP][58] ([fdo#109271]) +185 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-snb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109280]) +5 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271]) +121 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#1188])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][67] -> [FAIL][68] ([fdo#108145] / [i915#265]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][70] -> [SKIP][71] ([fdo#109441]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][72] -> [DMESG-WARN][73] ([i915#180])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-apl8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@perf@blocking:
- shard-skl: [PASS][74] -> [FAIL][75] ([i915#1542])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl6/igt@perf@blocking.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl8/igt@perf@blocking.html
* igt@perf@polling-parameterized:
- shard-apl: NOTRUN -> [FAIL][76] ([i915#1542])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl6/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_self_import:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +45 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl2/igt@prime_nv_api@i915_self_import.html
* igt@prime_nv_pcopy@test3_2:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109291])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@prime_nv_pcopy@test3_2.html
* igt@sysfs_clients@recycle-many:
- shard-hsw: [PASS][79] -> [FAIL][80] ([i915#3028])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-hsw1/igt@sysfs_clients@recycle-many.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-hsw8/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [FAIL][81] ([i915#2842]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][83] ([i915#2842]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb4/igt@gem_exec_fair@basic-pace@vecs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [DMESG-WARN][85] ([i915#2803]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb1/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][87] ([i915#644]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][89] ([i915#2597]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb1/igt@kms_async_flips@test-time-stamp.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb8/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen:
- shard-skl: [FAIL][91] ([i915#54]) -> [PASS][92] +9 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-left-edge:
- shard-skl: [DMESG-WARN][93] ([i915#1982]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl2/igt@kms_cursor_edge_walk@pipe-a-64x64-left-edge.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl2/igt@kms_cursor_edge_walk@pipe-a-64x64-left-edge.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [FAIL][95] ([i915#2598]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][97] ([i915#1188]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl1/igt@kms_hdr@bpc-switch.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [INCOMPLETE][99] ([i915#198]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][101] ([fdo#109441]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb6/igt@kms_psr@psr2_dpms.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@sysfs_clients@busy@vcs1:
- shard-kbl: [FAIL][103] ([i915#3009]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl4/igt@sysfs_clients@busy@vcs1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl3/igt@sysfs_clients@busy@vcs1.html
* igt@sysfs_clients@busy@vecs0:
- shard-skl: [FAIL][105] ([i915#3019]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl7/igt@sysfs_clients@busy@vecs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl10/igt@sysfs_clients@busy@vecs0.html
- shard-tglb: [FAIL][107] ([i915#3019]) -> [PASS][108] +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb5/igt@sysfs_clients@busy@vecs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb1/igt@sysfs_clients@busy@vecs0.html
* igt@sysfs_clients@recycle:
- shard-kbl: [FAIL][109] ([i915#3028]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl2/igt@sysfs_clients@recycle.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl4/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@recycle-many:
- shard-glk: [FAIL][111] ([i915#3028]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-glk9/igt@sysfs_clients@recycle-many.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-glk8/igt@sysfs_clients@recycle-many.html
- shard-tglb: [FAIL][113] ([i915#3028]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb8/igt@sysfs_clients@recycle-many.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb2/igt@sysfs_clients@recycle-many.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][115] ([i915#2842]) -> [FAIL][116] ([i915#2876])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][117] ([i915#2849]) -> [FAIL][118] ([i915#2842])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [DMESG-WARN][119] ([i915#1610] / [i915#2803]) -> [DMESG-WARN][120] ([i915#2803])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl9/igt@gem_exec_schedule@u-fairslice@rcs0.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][121] ([i915#1804] / [i915#2684]) -> [WARN][122] ([i915#2681] / [i915#2684])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [INCOMPLETE][123] ([i915#155]) -> [DMESG-WARN][124] ([i915#180])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][125] ([i915#658]) -> [SKIP][126] ([i915#2920])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-iclb: [SKIP][127] ([i915#2920]) -> [SKIP][128] ([i915#658])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-iclb: ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][133], [FAIL][134], [FAIL][135]) ([i915#2724] / [i915#3002])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb3/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-iclb6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb4/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb7/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-iclb5/igt@runner@aborted.html
- shard-apl: [FAIL][136] ([i915#2724]) -> ([FAIL][137], [FAIL][138], [FAIL][139]) ([i915#180] / [i915#1814] / [i915#3002])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-apl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl8/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-apl1/igt@runner@aborted.html
- shard-tglb: ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#1602] / [i915#1814] / [i915#2667] / [i915#3002]) -> ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([i915#1602] / [i915#1814] / [i915#2426] / [i915#2667] / [i915#2803] / [i915#3002])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb2/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb1/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-tglb2/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb5/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb6/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb1/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-tglb8/igt@runner@aborted.html
- shard-skl: ([FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([i915#1814] / [i915#2029] / [i915#2426] / [i915#3002]) -> ([FAIL][153], [FAIL][154], [FAIL][155]) ([i915#2426] / [i915#3002])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl2/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl10/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl9/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9804/shard-skl3/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl2/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl10/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/shard-skl5/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112306]: https://bugs.freedesktop.org/show_bug.cgi?id=112306
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#180]: https://gitlab.freedesktop.org
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19729/index.html
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