[igt-dev] [PATCH i-g-t 00/14] tools/intel_display_poller: async flip and vrr

[igt-dev] [PATCH i-g-t 00/14] tools/intel_display_poller: async flip and vrr

[Manasi Navare]

Add VRR and async flips support to display poller

Ville Syrjälä (14):
  tools/intel_display_poller: Fix TILEOFF vs. LINOFF for skl+
  tools/intel_display_poller: Unify ilk+ and bdw+ codepaths
  tools/intel_display_poller: Use intel_gen()
  tools/intel_display_poller: Add pipe D support
  tools/intel_display_poller: Add flipdone tests
  tools/intel_display_poller: Add async flip test mode
  lib: Add transcoder VRR registers
  lib: Add timestmap registers
  tools/intel_display_poller: Extract wait_scanline()
  tools/intel_display_poller: Add frame timestamp tests
  tools/intel_display_poller: Rework some loops
  tools/intel_display_poller: Add VRR push support
  tools/intel_display_poller: Add vrr-wrap test
  tools/intel_display_poller: Add vrr-push test

 lib/intel_reg.h              |  43 +++
 tools/intel_display_poller.c | 719 ++++++++++++++++++++++++++++-------
 2 files changed, 635 insertions(+), 127 deletions(-)

-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 01/14] tools/intel_display_poller: Fix TILEOFF vs. LINOFF for skl+

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

skl+ (like hsw/bdw) always use the TILEOFF register, and never
the LINOFF register. Let's respect that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index f4797a20..15da8e76 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -128,9 +128,9 @@ static uint32_t dspoffset_reg(uint32_t devid, int pipe)
 	bool use_tileoff;
 	int plane = pipe_to_plane(devid, pipe);
 
-	if (IS_GEN2(devid) || IS_GEN3(devid))
+	if (intel_gen(devid) < 4)
 		use_tileoff = false;
-	else if (IS_HASWELL(devid) || IS_BROADWELL(devid))
+	else if (IS_HASWELL(devid) || IS_BROADWELL(devid) || intel_gen(devid) >= 9)
 		use_tileoff = true;
 	else
 		use_tileoff = read_reg(PIPE_REG(plane, DSPACNTR)) & DISPLAY_PLANE_TILED;
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 02/14] tools/intel_display_poller: Unify ilk+ and bdw+ codepaths

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The ilk+ and bdw+ codepaths are identical, except for the ilk/snb
pipe C check. Unify them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 26 +-------------------------
 1 file changed, 1 insertion(+), 25 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 15da8e76..bb115598 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -1128,8 +1128,7 @@ int main(int argc, char *argv[])
 		default:
 			usage(argv[0]);
 		}
-	} else if (HAS_PCH_SPLIT(devid) &&
-		   (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))) {
+	} else {
 		if (pipe > 1 &&
 		    (IS_GEN5(devid) || IS_GEN6(devid)))
 			usage(argv[0]);
@@ -1154,29 +1153,6 @@ int main(int argc, char *argv[])
 		default:
 			usage(argv[0]);
 		}
-	} else if (intel_gen(devid) >= 8) {
-		if (test_pixelcount)
-			usage(argv[0]);
-
-		switch (test) {
-		case TEST_IIR:
-			test = TEST_DEIIR;
-			break;
-		case TEST_FRAMECOUNT:
-			test = TEST_FRAMECOUNT_G4X;
-			break;
-		case TEST_FLIPCOUNT:
-		case TEST_PAN:
-		case TEST_FLIP:
-		case TEST_SURFLIVE:
-		case TEST_WRAP:
-		case TEST_FIELD:
-			break;
-		default:
-			usage(argv[0]);
-		}
-	} else {
-		usage(argv[0]);
 	}
 
 	switch (test) {
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 03/14] tools/intel_display_poller: Use intel_gen()

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use intel_gen() to simplify some of the conditions. And for
the same of consistency we'll replace all the IS_GEN*()s.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index bb115598..0594e918 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -96,7 +96,7 @@ static char pipe_name(int pipe)
 
 static int pipe_to_plane(uint32_t devid, int pipe)
 {
-	if (!IS_GEN2(devid) && !IS_GEN3(devid))
+	if (intel_gen(devid) >= 4)
 		return pipe;
 
 	switch (pipe) {
@@ -145,7 +145,7 @@ static uint32_t dspsurf_reg(uint32_t devid, int pipe)
 {
 	int plane = pipe_to_plane(devid, pipe);
 
-	if (IS_GEN2(devid) || IS_GEN3(devid))
+	if (intel_gen(devid) < 4)
 		return PIPE_REG(plane, DSPABASE);
 	else
 		return PIPE_REG(plane, DSPASURF);
@@ -1053,7 +1053,7 @@ int main(int argc, char *argv[])
 	 * check if the requires registers are
 	 * avilable on the current platform.
 	 */
-	if (IS_GEN2(devid)) {
+	if (intel_gen(devid) == 2) {
 		if (pipe > 1)
 			usage(argv[0]);
 
@@ -1073,8 +1073,7 @@ int main(int argc, char *argv[])
 		default:
 			usage(argv[0]);
 		}
-	} else if (IS_GEN3(devid) ||
-		   (IS_GEN4(devid) && !IS_G4X(devid))) {
+	} else if (intel_gen(devid) < 5 && !IS_G4X(devid)) {
 		if (pipe > 1)
 			usage(argv[0]);
 
@@ -1091,14 +1090,13 @@ int main(int argc, char *argv[])
 		case TEST_FIELD:
 			break;
 		case TEST_FLIP:
-			if (IS_GEN3(devid))
+			if (intel_gen(devid) == 3)
 				test = TEST_PAN;
 			break;
 		default:
 			usage(argv[0]);
 		}
-	} else if (IS_G4X(devid) ||
-		   IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) {
+	} else if (IS_G4X(devid) || IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) {
 		if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
 			vlv_offset = 0x180000;
 		if (IS_CHERRYVIEW(devid))
@@ -1129,8 +1127,7 @@ int main(int argc, char *argv[])
 			usage(argv[0]);
 		}
 	} else {
-		if (pipe > 1 &&
-		    (IS_GEN5(devid) || IS_GEN6(devid)))
+		if (pipe > 1 && intel_gen(devid) < 7)
 			usage(argv[0]);
 
 		if (test_pixelcount)
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 04/14] tools/intel_display_poller: Add pipe D support

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's support 4 pipes for tgl+.

v2: Fix up pipe_offsets[] as well

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 0594e918..826833b3 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -58,7 +58,7 @@ enum test {
 };
 
 static uint32_t vlv_offset;
-static uint16_t pipe_offset[3] = { 0, 0x1000, 0x2000, };
+static uint16_t pipe_offset[4] = { 0, 0x1000, 0x2000, 0x3000, };
 
 #define PIPE_REG(pipe, reg_a) (pipe_offset[(pipe)] + (reg_a))
 
@@ -1023,7 +1023,7 @@ int main(int argc, char *argv[])
 				pipe -= '0';
 			else
 				usage(argv[0]);
-			if (pipe < 0 || pipe > 2)
+			if (pipe < 0 || pipe > 3)
 				usage(argv[0]);
 			break;
 		case 'b':
@@ -1104,6 +1104,8 @@ int main(int argc, char *argv[])
 
 		if (pipe > 1 && !IS_CHERRYVIEW(devid))
 			usage(argv[0]);
+		if (pipe > 2)
+			usage(argv[0]);
 
 		if (test_pixelcount)
 			usage(argv[0]);
@@ -1129,6 +1131,10 @@ int main(int argc, char *argv[])
 	} else {
 		if (pipe > 1 && intel_gen(devid) < 7)
 			usage(argv[0]);
+		if (pipe > 2 && intel_gen(devid) < 12)
+			usage(argv[0]);
+		if (pipe > 3)
+			usage(argv[0]);
 
 		if (test_pixelcount)
 			usage(argv[0]);
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 05/14] tools/intel_display_poller: Add flipdone tests

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add test for determining on which scanline the flipdone interrupt
is signalled. ilk+ and vlv/chv have this. Earlier platforms had
a "flip pending" bit instead which only seems to respond to CS flips
so not relevant for MMIO based flips.

v2: Rework the loops a bit to ease VRR in the future

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 187 ++++++++++++++++++++++++++++++++++-
 1 file changed, 186 insertions(+), 1 deletion(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 826833b3..be237221 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -52,6 +52,9 @@ enum test {
 	TEST_FLIPCOUNT,
 	TEST_PAN,
 	TEST_FLIP,
+	TEST_FLIPDONE,
+	TEST_FLIPDONE_PIPESTAT,
+	TEST_FLIPDONE_DEIIR,
 	TEST_SURFLIVE,
 	TEST_WRAP,
 	TEST_FIELD,
@@ -789,6 +792,158 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
 	write_reg(surf, saved);
 }
 
+static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
+				       uint32_t *min, uint32_t *max, const int count)
+{
+	uint32_t dsl, dsl1 = 0, dsl2 = 0;
+	uint32_t pipestat, pipestat1, pipestat2, pipestat_save;
+	bool field1 = false, field2 = false;
+	uint32_t saved, next, surf = 0, bit;
+	int i[2] = {};
+
+	dsl = PIPE_REG(pipe, PIPEA_DSL);
+	pipestat = PIPE_REG(pipe, PIPEASTAT);
+	surf = dspsurf_reg(devid, pipe);
+
+	bit = 1 << 10;
+
+	saved = read_reg(surf);
+	next = saved;
+
+	pipestat_save = read_reg(pipestat) & 0x7fff0000;
+	pipestat1 = pipestat_save & ~(1 << (bit<<16));
+	write_reg(pipestat, pipestat1 | bit);
+
+	while (!quit) {
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			field1 = dsl1 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			if (dsl1 == target_scanline)
+				break;
+		}
+
+		write_reg(pipestat, pipestat1 | bit);
+		if (next == saved)
+			next = saved+256*1024;
+		else
+			next = saved;
+		write_reg(surf, next);
+
+		while (!quit) {
+			pipestat2 = read_reg(pipestat);
+			dsl2 = read_reg(dsl);
+
+			field2 = dsl2 & 0x80000000;
+			dsl2 &= ~0x80000000;
+
+			if (pipestat2 & bit)
+				break;
+		}
+
+		write_reg(pipestat, pipestat1 | bit);
+
+		if (field1 != field2)
+			printf("fields are different (%u:%u -> %u:%u)\n",
+			       field1, dsl1, field2, dsl2);
+
+		min[field1*count+i[field1]] = dsl1;
+		max[field1*count+i[field1]] = dsl2;
+		if (++i[field1] >= count)
+			break;
+	}
+
+	write_reg(surf, saved);
+	write_reg(pipestat, pipestat_save);
+}
+
+static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
+				    uint32_t *min, uint32_t *max, const int count)
+{
+	uint32_t dsl, dsl1 = 0, dsl2 = 0;
+	uint32_t iir, iir2, ier, imr;
+	uint32_t ier_save, imr_save;
+	bool field1 = false, field2 = false;
+	uint32_t saved, next, surf = 0, bit;
+	int i[2] = {};
+
+	dsl = PIPE_REG(pipe, PIPEA_DSL);
+	surf = dspsurf_reg(devid, pipe);
+
+	if (intel_gen(devid) >= 9)
+		bit = 3;
+	else if (intel_gen(devid) >= 8)
+		bit = 4;
+	else if (intel_gen(devid) >= 7)
+		bit = 3 + 5 * pipe;
+	else if (intel_gen(devid) >= 5)
+		bit = 26 + pipe;
+	else
+		abort();
+	bit = 1 << bit;
+
+	if (intel_gen(devid) >= 8) {
+		iir = GEN8_DE_PIPE_IIR(pipe);
+		ier = GEN8_DE_PIPE_IER(pipe);
+		imr = GEN8_DE_PIPE_IMR(pipe);
+	} else {
+		iir = DEIIR;
+		ier = DEIER;
+		imr = DEIMR;
+	}
+
+	saved = read_reg(surf);
+	next = saved;
+
+	imr_save = read_reg(imr);
+	ier_save = read_reg(ier);
+	write_reg(ier, ier_save & ~bit);
+	write_reg(imr, imr_save & ~bit);
+
+	while (!quit) {
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			field1 = dsl1 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			if (dsl1 == target_scanline)
+				break;
+		}
+
+		write_reg(iir, bit);
+		if (next == saved)
+			next = saved+256*1024;
+		else
+			next = saved;
+		write_reg(surf, next);
+
+		while (!quit) {
+			iir2 = read_reg(iir);
+			dsl2 = read_reg(dsl);
+
+			field2 = dsl2 & 0x80000000;
+			dsl2 &= ~0x80000000;
+
+			if (iir2 & bit)
+				break;
+		}
+
+		write_reg(iir, bit);
+
+		if (field1 != field2)
+			printf("fields are different (%u:%u -> %u:%u)\n",
+			       field1, dsl1, field2, dsl2);
+
+		min[field1*count+i[field1]] = dsl1;
+		max[field1*count+i[field1]] = dsl2;
+		if (++i[field1] >= count)
+			break;
+	}
+
+	write_reg(surf, saved);
+	write_reg(imr, imr_save);
+	write_reg(ier, ier_save);
+}
+
 static void poll_dsl_surflive(uint32_t devid, int pipe,
 			      uint32_t *min, uint32_t *max, const int count)
 {
@@ -933,6 +1088,12 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 	case TEST_FLIP:
 		snprintf(str, sizeof str, "%s / pipe %c / Flip", type, pipe_name(pipe));
 		return str;
+	case TEST_FLIPDONE_PIPESTAT:
+		snprintf(str, sizeof str, "%s / pipe %c / Flip done (vlv/chv)", type, pipe_name(pipe));
+		return str;
+	case TEST_FLIPDONE_DEIIR:
+		snprintf(str, sizeof str, "%s / pipe %c / Flip done (pch)", type, pipe_name(pipe));
+		return str;
 	case TEST_SURFLIVE:
 		snprintf(str, sizeof str, "%s / pipe %c / Surflive", type, pipe_name(pipe));
 		return str;
@@ -950,7 +1111,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 static void __attribute__((noreturn)) usage(const char *name)
 {
 	fprintf(stderr, "Usage: %s [options]\n"
-		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|surflive|wrap|field>\n"
+		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|flipdone|surflive|wrap|field>\n"
 		" -p,--pipe <pipe>\n"
 		" -b,--bit <bit>\n"
 		" -l,--line <target scanline/pixel>\n"
@@ -1002,6 +1163,8 @@ int main(int argc, char *argv[])
 				test = TEST_PAN;
 			else if (!strcmp(optarg, "flip"))
 				test = TEST_FLIP;
+			else if (!strcmp(optarg, "flipdone"))
+				test = TEST_FLIPDONE;
 			else if (!strcmp(optarg, "surflive"))
 				test = TEST_SURFLIVE;
 			else if (!strcmp(optarg, "wrap"))
@@ -1117,6 +1280,16 @@ int main(int argc, char *argv[])
 		case TEST_FRAMECOUNT:
 			test = TEST_FRAMECOUNT_G4X;
 			break;
+		case TEST_FLIPDONE:
+			/*
+			 * g4x has no apparent "flip done" interrupt,
+			 * and the "flip pending" interrupt does not
+			 * seem to do anything with mmio flips.
+			 */
+			if (IS_G4X(devid))
+				usage(argv[0]);
+			test = TEST_FLIPDONE_PIPESTAT;
+			break;
 		case TEST_FLIPCOUNT:
 		case TEST_PIPESTAT:
 		case TEST_PAN:
@@ -1146,6 +1319,9 @@ int main(int argc, char *argv[])
 		case TEST_FRAMECOUNT:
 			test = TEST_FRAMECOUNT_G4X;
 			break;
+		case TEST_FLIPDONE:
+			test = TEST_FLIPDONE_DEIIR;
+			break;
 		case TEST_FLIPCOUNT:
 		case TEST_PAN:
 		case TEST_FLIP:
@@ -1161,6 +1337,7 @@ int main(int argc, char *argv[])
 	switch (test) {
 	case TEST_IIR:
 	case TEST_FRAMECOUNT:
+	case TEST_FLIPDONE:
 		/* should no longer have the generic tests here */
 		assert(0);
 	default:
@@ -1226,6 +1403,14 @@ int main(int argc, char *argv[])
 			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
 				      min, max, count);
 		break;
+	case TEST_FLIPDONE_PIPESTAT:
+		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
+					   min, max, count);
+		break;
+	case TEST_FLIPDONE_DEIIR:
+		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
+					min, max, count);
+		break;
 	case TEST_SURFLIVE:
 		poll_dsl_surflive(devid, pipe, min, max, count);
 		break;
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 06/14] tools/intel_display_poller: Add async flip test mode

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Test various things using mmio async flips. These are present since
g4x, except g4x does not seem to have a working flipdone interrupt.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 lib/intel_reg.h              |  3 ++
 tools/intel_display_poller.c | 83 +++++++++++++++++++++++++++---------
 2 files changed, 66 insertions(+), 20 deletions(-)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cb..7b543109 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2330,6 +2330,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define PIPEEDPCONF		0x7F008
 
+#define DSPAADDR_VLV		0x7017C /* vlv/chv */
+#define DSPBADDR_VLV		0x7117C /* vlv/chv */
+#define DSPCADDR_CHV		0x7417C /* chv */
 #define DSPACNTR		0x70180
 #define DSPBCNTR		0x71180
 #define DSPCCNTR		0x72180
diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index be237221..d6a77d35 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -144,16 +144,35 @@ static uint32_t dspoffset_reg(uint32_t devid, int pipe)
 		return PIPE_REG(plane, DSPABASE);
 }
 
-static uint32_t dspsurf_reg(uint32_t devid, int pipe)
+static uint32_t dspsurf_reg(uint32_t devid, int pipe, bool async)
 {
 	int plane = pipe_to_plane(devid, pipe);
 
+	if (async && (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)))
+		return PIPE_REG(plane, DSPAADDR_VLV);
+
 	if (intel_gen(devid) < 4)
 		return PIPE_REG(plane, DSPABASE);
 	else
 		return PIPE_REG(plane, DSPASURF);
 }
 
+static void enable_async_flip(uint32_t devid, int pipe, bool enable)
+{
+	int plane = pipe_to_plane(devid, pipe);
+	uint32_t tmp;
+
+	if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
+		return;
+
+	tmp = read_reg(PIPE_REG(plane, DSPACNTR));
+	if (enable)
+		tmp |= 1 << 9;
+	else
+		tmp &= ~(1 << 9);
+	write_reg(PIPE_REG(plane, DSPACNTR), tmp);
+}
+
 static void poll_pixel_pipestat(int pipe, int bit, uint32_t *min, uint32_t *max, const int count)
 {
 	uint32_t pix, pix1, pix2, iir, iir1, iir2, iir_bit, iir_mask;
@@ -307,7 +326,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ
 	int i = 0;
 
 	pix = PIPE_REG(pipe, PIPEAFRAMEPIXEL);
-	surf = dspsurf_reg(devid, pipe);
+	surf = dspsurf_reg(devid, pipe, false);
 
 	saved = read_reg(surf);
 
@@ -318,7 +337,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ
 				break;
 		}
 
-		write_reg(surf, saved+128*1024);
+		write_reg(surf, saved+256*1024);
 
 		while (!quit){
 			pix2 = read_reg(pix) & PIPE_PIXEL_MASK;
@@ -613,7 +632,7 @@ static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
 
 	flp = PIPE_REG(pipe, PIPEAFLIPCOUNT_G4X);
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
-	surf = dspsurf_reg(devid, pipe);
+	surf = dspsurf_reg(devid, pipe, false);
 
 	while (!quit) {
 		usleep(10);
@@ -746,7 +765,7 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
 }
 
 static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
-			  uint32_t *min, uint32_t *max, const int count)
+			  uint32_t *min, uint32_t *max, const int count, bool async)
 {
 	uint32_t dsl, dsl1 = 0, dsl2 = 0;
 	bool field1 = false, field2 = false;
@@ -754,10 +773,12 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
 	int i[2] = {};
 
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
-	surf = dspsurf_reg(devid, pipe);
+	surf = dspsurf_reg(devid, pipe, async);
 
 	saved = read_reg(surf);
 
+	enable_async_flip(devid, pipe, async);
+
 	while (!quit) {
 		while (!quit) {
 			dsl1 = read_reg(dsl);
@@ -767,7 +788,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
 				break;
 		}
 
-		write_reg(surf, saved+128*1024);
+		write_reg(surf, saved+256*1024);
 
 		while (!quit) {
 			dsl2 = read_reg(dsl);
@@ -789,11 +810,12 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
 			break;
 	}
 
+	enable_async_flip(devid, pipe, false);
 	write_reg(surf, saved);
 }
 
 static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
-				       uint32_t *min, uint32_t *max, const int count)
+				       uint32_t *min, uint32_t *max, const int count, bool async)
 {
 	uint32_t dsl, dsl1 = 0, dsl2 = 0;
 	uint32_t pipestat, pipestat1, pipestat2, pipestat_save;
@@ -803,7 +825,7 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
 
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
 	pipestat = PIPE_REG(pipe, PIPEASTAT);
-	surf = dspsurf_reg(devid, pipe);
+	surf = dspsurf_reg(devid, pipe, async);
 
 	bit = 1 << 10;
 
@@ -814,6 +836,8 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
 	pipestat1 = pipestat_save & ~(1 << (bit<<16));
 	write_reg(pipestat, pipestat1 | bit);
 
+	enable_async_flip(devid, pipe, async);
+
 	while (!quit) {
 		while (!quit) {
 			dsl1 = read_reg(dsl);
@@ -853,12 +877,13 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
 			break;
 	}
 
+	enable_async_flip(devid, pipe, false);
 	write_reg(surf, saved);
 	write_reg(pipestat, pipestat_save);
 }
 
 static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
-				    uint32_t *min, uint32_t *max, const int count)
+				    uint32_t *min, uint32_t *max, const int count, bool async)
 {
 	uint32_t dsl, dsl1 = 0, dsl2 = 0;
 	uint32_t iir, iir2, ier, imr;
@@ -868,7 +893,7 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
 	int i[2] = {};
 
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
-	surf = dspsurf_reg(devid, pipe);
+	surf = dspsurf_reg(devid, pipe, async);
 
 	if (intel_gen(devid) >= 9)
 		bit = 3;
@@ -900,6 +925,8 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
 	write_reg(ier, ier_save & ~bit);
 	write_reg(imr, imr_save & ~bit);
 
+	enable_async_flip(devid, pipe, async);
+
 	while (!quit) {
 		while (!quit) {
 			dsl1 = read_reg(dsl);
@@ -939,13 +966,14 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
 			break;
 	}
 
+	enable_async_flip(devid, pipe, false);
 	write_reg(surf, saved);
 	write_reg(imr, imr_save);
 	write_reg(ier, ier_save);
 }
 
 static void poll_dsl_surflive(uint32_t devid, int pipe,
-			      uint32_t *min, uint32_t *max, const int count)
+			      uint32_t *min, uint32_t *max, const int count, bool async)
 {
 	uint32_t dsl, dsl1 = 0, dsl2 = 0, surf, surf1, surf2, surflive, surfl1 = 0, surfl2, saved, tmp;
 	bool field1 = false, field2 = false;
@@ -953,12 +981,14 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
 
 	surflive = PIPE_REG(pipe, DSPASURFLIVE);
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
-	surf = dspsurf_reg(devid, pipe);
+	surf = dspsurf_reg(devid, pipe, async);
 
 	saved = read_reg(surf);
 
 	surf1 = saved & ~0xfff;
-	surf2 = surf1 + 128*1024;
+	surf2 = surf1 + 256*1024;
+
+	enable_async_flip(devid, pipe, async);
 
 	while (!quit) {
 		write_reg(surf, surf2);
@@ -994,6 +1024,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
 		surf2 = tmp;
 	}
 
+	enable_async_flip(devid, pipe, false);
 	write_reg(surf, saved);
 }
 
@@ -1116,7 +1147,8 @@ static void __attribute__((noreturn)) usage(const char *name)
 		" -b,--bit <bit>\n"
 		" -l,--line <target scanline/pixel>\n"
 		" -f,--fuzz <target fuzz>\n"
-		" -x,--pixel\n",
+		" -x,--pixel\n"
+		" -a,--async\n",
 		name);
 	exit(1);
 }
@@ -1127,6 +1159,7 @@ int main(int argc, char *argv[])
 	int i;
 	int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1;
 	bool test_pixelcount = false;
+	bool test_async_flip = false;
 	uint32_t devid;
 	uint32_t min[2*128] = {};
 	uint32_t max[2*128] = {};
@@ -1142,10 +1175,11 @@ int main(int argc, char *argv[])
 			{ .name = "line", .has_arg = required_argument, },
 			{ .name = "fuzz", .has_arg = required_argument, },
 			{ .name = "pixel", .has_arg = no_argument, },
+			{ .name = "async", .has_arg = no_argument, },
 			{ },
 		};
 
-		int opt = getopt_long(argc, argv, "t:p:b:l:f:x", long_options, NULL);
+		int opt = getopt_long(argc, argv, "t:p:b:l:f:xa", long_options, NULL);
 		if (opt == -1)
 			break;
 
@@ -1207,6 +1241,9 @@ int main(int argc, char *argv[])
 		case 'x':
 			test_pixelcount = true;
 			break;
+		case 'a':
+			test_async_flip = true;
+			break;
 		}
 	}
 
@@ -1223,6 +1260,9 @@ int main(int argc, char *argv[])
 		if (test_pixelcount)
 			usage(argv[0]);
 
+		if (test_async_flip)
+			usage(argv[0]);
+
 		switch (test) {
 		case TEST_IIR:
 			test = TEST_IIR_GEN2;
@@ -1240,6 +1280,9 @@ int main(int argc, char *argv[])
 		if (pipe > 1)
 			usage(argv[0]);
 
+		if (test_async_flip)
+			usage(argv[0]);
+
 		switch (test) {
 		case TEST_IIR:
 			test = TEST_IIR_GEN3;
@@ -1401,18 +1444,18 @@ int main(int argc, char *argv[])
 					min, max, count);
 		else
 			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
-				      min, max, count);
+				      min, max, count, test_async_flip);
 		break;
 	case TEST_FLIPDONE_PIPESTAT:
 		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
-					   min, max, count);
+					   min, max, count, test_async_flip);
 		break;
 	case TEST_FLIPDONE_DEIIR:
 		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
-					min, max, count);
+					min, max, count, test_async_flip);
 		break;
 	case TEST_SURFLIVE:
-		poll_dsl_surflive(devid, pipe, min, max, count);
+		poll_dsl_surflive(devid, pipe, min, max, count, test_async_flip);
 		break;
 	case TEST_WRAP:
 		if (test_pixelcount)
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 07/14] lib: Add transcoder VRR registers

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add definitions for the transcoder VRR registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 lib/intel_reg.h | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 7b543109..d5017f3d 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -880,6 +880,43 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define VSYNC_EDP	0x6F014
 #define VSYNCSHIFT_EDP	0x6F028
 
+#define TRANS_VRR_CTL_A                0x60420
+#define TRANS_VRR_CTL_B                0x61420
+#define TRANS_VRR_CTL_C                0x62420
+#define TRANS_VRR_CTL_D                0x63420
+#define TRANS_VRR_VMAX_A               0x60424
+#define TRANS_VRR_VMAX_B               0x61424
+#define TRANS_VRR_VMAX_C               0x62424
+#define TRANS_VRR_VMAX_D               0x63424
+#define TRANS_VRR_VMIN_A               0x60434
+#define TRANS_VRR_VMIN_B               0x61434
+#define TRANS_VRR_VMIN_C               0x62434
+#define TRANS_VRR_VMIN_D               0x63434
+#define TRANS_VRR_VMAXSHIFT_A          0x60428
+#define TRANS_VRR_VMAXSHIFT_B          0x61428
+#define TRANS_VRR_VMAXSHIFT_C          0x62428
+#define TRANS_VRR_VMAXSHIFT_D          0x63428
+#define TRANS_VRR_STATUS_A             0x6042C
+#define TRANS_VRR_STATUS_B             0x6142C
+#define TRANS_VRR_STATUS_C             0x6242C
+#define TRANS_VRR_STATUS_D             0x6342C
+#define TRANS_VRR_VTOTAL_PREV_A        0x60480
+#define TRANS_VRR_VTOTAL_PREV_B        0x61480
+#define TRANS_VRR_VTOTAL_PREV_C        0x62480
+#define TRANS_VRR_VTOTAL_PREV_D        0x63480
+#define TRANS_VRR_FLIPLINE_A           0x60438
+#define TRANS_VRR_FLIPLINE_B           0x61438
+#define TRANS_VRR_FLIPLINE_C           0x62438
+#define TRANS_VRR_FLIPLINE_D           0x63438
+#define TRANS_VRR_STATUS2_A            0x6043C
+#define TRANS_VRR_STATUS2_B            0x6143C
+#define TRANS_VRR_STATUS2_C            0x6243C
+#define TRANS_VRR_STATUS2_D            0x6343C
+#define TRANS_PUSH_A                   0x60A70
+#define TRANS_PUSH_B                   0x61A70
+#define TRANS_PUSH_C                   0x62A70
+#define TRANS_PUSH_D                   0x63A70
+
 #define PP_STATUS	0x61200
 # define PP_ON					(1 << 31)
 /*
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 08/14] lib: Add timestmap registers

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add definitions for the timestamp registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 lib/intel_reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index d5017f3d..d4045c36 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2294,6 +2294,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define PIPEAFRMCOUNT_G4X	0x70040
 #define PIPEAFLIPCOUNT_G4X	0x70044
+#define PIPEAFRMTMSMTP		0x70048
 /*
  * Computing GMCH M and N values.
  *
@@ -2801,6 +2802,8 @@ typedef enum {
 #define MCHBAR_RENDER_STANDBY	0x111B8
 #define RENDER_STANDBY_ENABLE	(1 << 30)
 
+#define ILK_TIMESTAMP_HI        0x70070
+#define IVB_TIMESTAMP_CTR       0x44070
 
 /* Ironlake */
 
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 09/14] tools/intel_display_poller: Extract wait_scanline()

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the code to wait for a specific scanline to a helper.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 69 ++++++++++++------------------------
 1 file changed, 23 insertions(+), 46 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index d6a77d35..260818db 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -173,6 +173,21 @@ static void enable_async_flip(uint32_t devid, int pipe, bool enable)
 	write_reg(PIPE_REG(plane, DSPACNTR), tmp);
 }
 
+static int wait_scanline(int pipe, int target_scanline, bool *field)
+{
+	uint32_t dsl_reg = PIPE_REG(pipe, PIPEA_DSL);
+
+	while (!quit) {
+		uint32_t dsl = read_reg(dsl_reg);
+		*field = dsl & 0x80000000;
+		dsl &= ~0x80000000;
+		if (dsl == target_scanline)
+			return dsl;
+	}
+
+	return 0;
+}
+
 static void poll_pixel_pipestat(int pipe, int bit, uint32_t *min, uint32_t *max, const int count)
 {
 	uint32_t pix, pix1, pix2, iir, iir1, iir2, iir_bit, iir_mask;
@@ -720,34 +735,21 @@ static void poll_dsl_framecount_gen3(int pipe, uint32_t *min, uint32_t *max, con
 static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
 			 uint32_t *min, uint32_t *max, const int count)
 {
-	uint32_t dsl, dsl1 = 0, dsl2 = 0;
+	uint32_t dsl1 = 0, dsl2 = 0;
 	bool field1 = false, field2 = false;
 	uint32_t saved, surf = 0;
 	int i[2] = {};
 
-	dsl = PIPE_REG(pipe, PIPEA_DSL);
 	surf = dspoffset_reg(devid, pipe);
 
 	saved = read_reg(surf);
 
 	while (!quit) {
-		while (!quit) {
-			dsl1 = read_reg(dsl);
-			field1 = dsl1 & 0x80000000;
-			dsl1 &= ~0x80000000;
-			if (dsl1 == target_scanline)
-				break;
-		}
+		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		write_reg(surf, saved+256);
 
-		while (!quit) {
-			dsl2 = read_reg(dsl);
-			field2 = dsl1 & 0x80000000;
-			dsl2 &= ~0x80000000;
-			if (dsl2 == target_scanline + target_fuzz)
-				break;
-		}
+		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
 
 		write_reg(surf, saved);
 
@@ -767,12 +769,11 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
 static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
 			  uint32_t *min, uint32_t *max, const int count, bool async)
 {
-	uint32_t dsl, dsl1 = 0, dsl2 = 0;
+	uint32_t dsl1 = 0, dsl2 = 0;
 	bool field1 = false, field2 = false;
 	uint32_t saved, surf = 0;
 	int i[2] = {};
 
-	dsl = PIPE_REG(pipe, PIPEA_DSL);
 	surf = dspsurf_reg(devid, pipe, async);
 
 	saved = read_reg(surf);
@@ -780,23 +781,11 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
 	enable_async_flip(devid, pipe, async);
 
 	while (!quit) {
-		while (!quit) {
-			dsl1 = read_reg(dsl);
-			field1 = dsl1 & 0x80000000;
-			dsl1 &= ~0x80000000;
-			if (dsl1 == target_scanline)
-				break;
-		}
+		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		write_reg(surf, saved+256*1024);
 
-		while (!quit) {
-			dsl2 = read_reg(dsl);
-			field2 = dsl1 & 0x80000000;
-			dsl2 &= ~0x80000000;
-			if (dsl2 == target_scanline + target_fuzz)
-				break;
-		}
+		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
 
 		write_reg(surf, saved);
 
@@ -839,13 +828,7 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
 	enable_async_flip(devid, pipe, async);
 
 	while (!quit) {
-		while (!quit) {
-			dsl1 = read_reg(dsl);
-			field1 = dsl1 & 0x80000000;
-			dsl1 &= ~0x80000000;
-			if (dsl1 == target_scanline)
-				break;
-		}
+		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		write_reg(pipestat, pipestat1 | bit);
 		if (next == saved)
@@ -928,13 +911,7 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
 	enable_async_flip(devid, pipe, async);
 
 	while (!quit) {
-		while (!quit) {
-			dsl1 = read_reg(dsl);
-			field1 = dsl1 & 0x80000000;
-			dsl1 &= ~0x80000000;
-			if (dsl1 == target_scanline)
-				break;
-		}
+		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		write_reg(iir, bit);
 		if (next == saved)
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 10/14] tools/intel_display_poller: Add frame timestamp tests

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a couple of new test modes to verify how frame timestamps
work.
* frametimestamp determines on which scanline the frame
  timestamp is sampled
* timestamp returns the difference between the current timestamp
  on a specific scanline from the last sampled frame timestamp.
  This can be used to determine if the timestamp ticks at the
  expected rate.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 103 ++++++++++++++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 260818db..ae3f993f 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -49,6 +49,8 @@ enum test {
 	TEST_FRAMECOUNT,
 	TEST_FRAMECOUNT_GEN3,
 	TEST_FRAMECOUNT_G4X,
+	TEST_FRAMETIMESTAMP,
+	TEST_TIMESTAMP,
 	TEST_FLIPCOUNT,
 	TEST_PAN,
 	TEST_FLIP,
@@ -732,6 +734,80 @@ static void poll_dsl_framecount_gen3(int pipe, uint32_t *min, uint32_t *max, con
 	}
 }
 
+
+static void poll_dsl_frametimestamp(uint32_t devid, int pipe,
+				    uint32_t *min, uint32_t *max, const int count)
+{
+	uint32_t dsl, dsl1, dsl2, frm, frm1, frm2;
+	bool field1, field2;
+	int i[2] = {};
+
+	frm = PIPE_REG(pipe, PIPEAFRMTMSMTP);
+	dsl = PIPE_REG(pipe, PIPEA_DSL);
+
+	while (!quit) {
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			frm1 = read_reg(frm);
+			frm2 = read_reg(frm);
+			dsl2 = read_reg(dsl);
+
+			field1 = dsl1 & 0x80000000;
+			field2 = dsl2 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			dsl2 &= ~0x80000000;
+
+			if (frm1 != frm2)
+				break;
+		}
+
+		if (field1 != field2)
+			printf("fields are different (%u:%u -> %u:%u)\n",
+			       field1, dsl1, field2, dsl2);
+
+		min[field1*count+i[field1]] = dsl1;
+		max[field1*count+i[field1]] = dsl2;
+		if (++i[field1] >= count)
+			break;
+	}
+}
+
+static uint32_t timestamp_reg(uint32_t devid)
+{
+	if (intel_gen(devid) >= 7)
+		return IVB_TIMESTAMP_CTR;
+	else if (intel_gen(devid) >= 5)
+		return ILK_TIMESTAMP_HI;
+	else
+		return TIMESTAMP_QW + 4;
+}
+
+static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
+			       uint32_t *min, uint32_t *max, const int count)
+{
+	uint32_t dsl1, frm, frm1, ts, ts1;
+	bool field1;
+	int i[2] = {};
+
+	ts = timestamp_reg(devid);
+	frm = PIPE_REG(pipe, PIPEAFRMTMSMTP);
+
+	while (!quit) {
+		dsl1 = wait_scanline(pipe, target_scanline, &field1);
+
+		frm1 = read_reg(frm);
+		ts1 = read_reg(ts);
+
+		field1 = dsl1 & 0x80000000;
+		dsl1 &= ~0x80000000;
+
+		min[field1*count+i[field1]] = dsl1;
+		max[field1*count+i[field1]] = ts1 - frm1;
+		if (++i[field1] >= count)
+			break;
+	}
+}
+
 static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
 			 uint32_t *min, uint32_t *max, const int count)
 {
@@ -1087,6 +1163,12 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 	case TEST_FRAMECOUNT_G4X:
 		snprintf(str, sizeof str, "%s / pipe %c / Frame count (g4x+)", type, pipe_name(pipe));
 		return str;
+	case TEST_FRAMETIMESTAMP:
+		snprintf(str, sizeof str, "%s / pipe %c / Frame timestamp", type, pipe_name(pipe));
+		return str;
+	case TEST_TIMESTAMP:
+		snprintf(str, sizeof str, "%s / pipe %c / Timestamp", type, pipe_name(pipe));
+		return str;
 	case TEST_FLIPCOUNT:
 		snprintf(str, sizeof str, "%s / pipe %c / Flip count (g4x+)", type, pipe_name(pipe));
 		return str;
@@ -1119,7 +1201,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 static void __attribute__((noreturn)) usage(const char *name)
 {
 	fprintf(stderr, "Usage: %s [options]\n"
-		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|flipdone|surflive|wrap|field>\n"
+		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field>\n"
 		" -p,--pipe <pipe>\n"
 		" -b,--bit <bit>\n"
 		" -l,--line <target scanline/pixel>\n"
@@ -1170,6 +1252,10 @@ int main(int argc, char *argv[])
 				test = TEST_FRAMECOUNT;
 			else if (!strcmp(optarg, "flipcount"))
 				test = TEST_FLIPCOUNT;
+			else if (!strcmp(optarg, "frametimestamp"))
+				test = TEST_FRAMETIMESTAMP;
+			else if (!strcmp(optarg, "timestamp"))
+				test = TEST_TIMESTAMP;
 			else if (!strcmp(optarg, "pan"))
 				test = TEST_PAN;
 			else if (!strcmp(optarg, "flip"))
@@ -1318,6 +1404,11 @@ int main(int argc, char *argv[])
 		case TEST_WRAP:
 		case TEST_FIELD:
 			break;
+		case TEST_FRAMETIMESTAMP:
+		case TEST_TIMESTAMP:
+			if (!IS_G4X(devid))
+				usage(argv[0]);
+			break;
 		default:
 			usage(argv[0]);
 		}
@@ -1348,6 +1439,8 @@ int main(int argc, char *argv[])
 		case TEST_SURFLIVE:
 		case TEST_WRAP:
 		case TEST_FIELD:
+		case TEST_TIMESTAMP:
+		case TEST_FRAMETIMESTAMP:
 			break;
 		default:
 			usage(argv[0]);
@@ -1403,6 +1496,14 @@ int main(int argc, char *argv[])
 		assert(!test_pixelcount);
 		poll_dsl_framecount_g4x(pipe, min, max, count);
 		break;
+	case TEST_FRAMETIMESTAMP:
+		assert(!test_pixelcount);
+		poll_dsl_frametimestamp(devid, pipe, min, max, count);
+		break;
+	case TEST_TIMESTAMP:
+		assert(!test_pixelcount);
+		poll_dsl_timestamp(devid, pipe, target_scanline, min, max, count);
+		break;
 	case TEST_FLIPCOUNT:
 		assert(!test_pixelcount);
 		poll_dsl_flipcount_g4x(devid, pipe, min, max, count);
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 11/14] tools/intel_display_poller: Rework some loops

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rework the structure of some of the loops a bit. This is
going to help slide VRR support into the tests.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 82 +++++++++++++++++++-----------------
 1 file changed, 43 insertions(+), 39 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index ae3f993f..3b3375ec 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -574,18 +574,20 @@ static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
 	write_reg(iir, bit);
 
 	while (!quit) {
-		dsl1 = read_reg(dsl);
-		iir1 = read_reg(iir);
-		iir2 = read_reg(iir);
-		dsl2 = read_reg(dsl);
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			iir1 = read_reg(iir);
+			iir2 = read_reg(iir);
+			dsl2 = read_reg(dsl);
 
-		field1 = dsl1 & 0x80000000;
-		field2 = dsl2 & 0x80000000;
-		dsl1 &= ~0x80000000;
-		dsl2 &= ~0x80000000;
+			field1 = dsl1 & 0x80000000;
+			field2 = dsl2 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			dsl2 &= ~0x80000000;
 
-		if (!(iir2 & bit))
-			continue;
+			if (iir2 & bit)
+				break;
+		}
 
 		write_reg(iir, bit);
 
@@ -616,18 +618,20 @@ static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, cons
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
 
 	while (!quit) {
-		dsl1 = read_reg(dsl);
-		frm1 = read_reg(frm);
-		frm2 = read_reg(frm);
-		dsl2 = read_reg(dsl);
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			frm1 = read_reg(frm);
+			frm2 = read_reg(frm);
+			dsl2 = read_reg(dsl);
 
-		field1 = dsl1 & 0x80000000;
-		field2 = dsl2 & 0x80000000;
-		dsl1 &= ~0x80000000;
-		dsl2 &= ~0x80000000;
+			field1 = dsl1 & 0x80000000;
+			field2 = dsl2 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			dsl2 &= ~0x80000000;
 
-		if (frm1 + 1 != frm2)
-			continue;
+			if (frm1 + 1 == frm2)
+				break;
+		}
 
 		if (field1 != field2)
 			printf("fields are different (%u:%u -> %u:%u)\n",
@@ -683,19 +687,17 @@ static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
 			dsl1 &= ~0x80000000;
 			dsl2 &= ~0x80000000;
 
-			if (flp1 == flp2)
-				continue;
-
-			if (field1 != field2)
-				printf("fields are different (%u:%u -> %u:%u)\n",
-				       field1, dsl1, field2, dsl2);
-
-			min[field1*count+i[field1]] = dsl1;
-			max[field1*count+i[field1]] = dsl2;
-			if (++i[field1] >= count)
+			if (flp1 != flp2)
 				break;
 		}
-		if (i[field1] >= count)
+
+		if (field1 != field2)
+			printf("fields are different (%u:%u -> %u:%u)\n",
+			       field1, dsl1, field2, dsl2);
+
+		min[field1*count+i[field1]] = dsl1;
+		max[field1*count+i[field1]] = dsl2;
+		if (++i[field1] >= count)
 			break;
 	}
 }
@@ -1090,16 +1092,18 @@ static void poll_dsl_wrap(int pipe, uint32_t *min, uint32_t *max, const int coun
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
 
 	while (!quit) {
-		dsl1 = read_reg(dsl);
-		dsl2 = read_reg(dsl);
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			dsl2 = read_reg(dsl);
 
-		field1 = dsl1 & 0x80000000;
-		field2 = dsl2 & 0x80000000;
-		dsl1 &= ~0x80000000;
-		dsl2 &= ~0x80000000;
+			field1 = dsl1 & 0x80000000;
+			field2 = dsl2 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			dsl2 &= ~0x80000000;
 
-		if (dsl2 >= dsl1)
-			continue;
+			if (dsl2 < dsl1)
+				break;
+		}
 
 		if (field1 != field2)
 			printf("fields are different (%u:%u -> %u:%u)\n",
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 12/14] tools/intel_display_poller: Add VRR push support

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a new command line knob to specify the scanline on which we
should send the VRR push. This allows many of the test modes
to probe the hardware behaviour in the presence of VRR pushes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 134 +++++++++++++++++++++++++++++------
 1 file changed, 112 insertions(+), 22 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 3b3375ec..37383dc8 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -159,6 +159,29 @@ static uint32_t dspsurf_reg(uint32_t devid, int pipe, bool async)
 		return PIPE_REG(plane, DSPASURF);
 }
 
+static int pipe_to_transcoder(uint32_t devid, int pipe)
+{
+	int gen = intel_gen(devid);
+
+	if (IS_HASWELL(devid) || IS_BROADWELL(devid) ||
+	    gen == 9 || gen == 10 || gen == 11) {
+		/* FIXME not 100% robust */
+		if (read_reg(PIPE_REG(pipe, PIPEACONF)) & PIPEACONF_ENABLE)
+			return pipe;
+		else
+			return 0xf; /* EDP */
+	} else {
+		return pipe;
+	}
+}
+
+static uint32_t trans_reg(uint32_t devid, int pipe, uint32_t reg)
+{
+	int trans = pipe_to_transcoder(devid, pipe);
+
+	return PIPE_REG(trans, reg);
+}
+
 static void enable_async_flip(uint32_t devid, int pipe, bool enable)
 {
 	int plane = pipe_to_plane(devid, pipe);
@@ -175,6 +198,26 @@ static void enable_async_flip(uint32_t devid, int pipe, bool enable)
 	write_reg(PIPE_REG(plane, DSPACNTR), tmp);
 }
 
+static void push_vrr(uint32_t devid, int pipe, int vrr_push_scanline)
+{
+	uint32_t dsl = PIPE_REG(pipe, PIPEA_DSL);
+	uint32_t push = trans_reg(devid, pipe, TRANS_PUSH_A);
+
+	if (vrr_push_scanline < 0)
+		return;
+
+	if (read_reg(push) & 0x40000000)
+		return;
+
+	while (!quit) {
+		uint32_t dsl1 = read_reg(dsl) & ~0x80000000;
+		if (dsl1 == vrr_push_scanline)
+			break;
+	}
+
+	write_reg(push, 0xc0000000);
+}
+
 static int wait_scanline(int pipe, int target_scanline, bool *field)
 {
 	uint32_t dsl_reg = PIPE_REG(pipe, PIPEA_DSL);
@@ -545,7 +588,8 @@ static void poll_dsl_iir_gen3(int pipe, int bit,
 }
 
 static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
-			   uint32_t *min, uint32_t *max, const int count)
+			   uint32_t *min, uint32_t *max, const int count,
+			   int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1, dsl2, iir1, iir2, imr_save, ier_save;
 	bool field1, field2;
@@ -574,6 +618,8 @@ static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
 	write_reg(iir, bit);
 
 	while (!quit) {
+		push_vrr(devid, pipe, vrr_push_scanline);
+
 		while (!quit) {
 			dsl1 = read_reg(dsl);
 			iir1 = read_reg(iir);
@@ -608,7 +654,9 @@ static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
 	write_reg(ier, ier_save);
 }
 
-static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, const int count)
+static void poll_dsl_framecount_g4x(uint32_t devid, int pipe,
+				    uint32_t *min, uint32_t *max, const int count,
+				    int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1, dsl2, frm, frm1, frm2;
 	bool field1, field2;
@@ -618,6 +666,8 @@ static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, cons
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
 
 	while (!quit) {
+		push_vrr(devid, pipe, vrr_push_scanline);
+
 		while (!quit) {
 			dsl1 = read_reg(dsl);
 			frm1 = read_reg(frm);
@@ -645,7 +695,8 @@ static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, cons
 }
 
 static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
-				   uint32_t *min, uint32_t *max, const int count)
+				   uint32_t *min, uint32_t *max, const int count,
+				   int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1, dsl2, flp, flp1, flp2, surf;
 	bool field1, field2;
@@ -676,6 +727,7 @@ static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
 			return;
 
 		write_reg(surf, read_reg(surf));
+		push_vrr(devid, pipe, vrr_push_scanline);
 
 		while (!quit) {
 			dsl1 = read_reg(dsl);
@@ -738,7 +790,8 @@ static void poll_dsl_framecount_gen3(int pipe, uint32_t *min, uint32_t *max, con
 
 
 static void poll_dsl_frametimestamp(uint32_t devid, int pipe,
-				    uint32_t *min, uint32_t *max, const int count)
+				    uint32_t *min, uint32_t *max, const int count,
+				    int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1, dsl2, frm, frm1, frm2;
 	bool field1, field2;
@@ -748,6 +801,8 @@ static void poll_dsl_frametimestamp(uint32_t devid, int pipe,
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
 
 	while (!quit) {
+		push_vrr(devid, pipe, vrr_push_scanline);
+
 		while (!quit) {
 			dsl1 = read_reg(dsl);
 			frm1 = read_reg(frm);
@@ -785,7 +840,8 @@ static uint32_t timestamp_reg(uint32_t devid)
 }
 
 static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
-			       uint32_t *min, uint32_t *max, const int count)
+			       uint32_t *min, uint32_t *max, const int count,
+			       int vrr_push_scanline)
 {
 	uint32_t dsl1, frm, frm1, ts, ts1;
 	bool field1;
@@ -795,6 +851,8 @@ static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
 	frm = PIPE_REG(pipe, PIPEAFRMTMSMTP);
 
 	while (!quit) {
+		push_vrr(devid, pipe, vrr_push_scanline);
+
 		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		frm1 = read_reg(frm);
@@ -811,7 +869,8 @@ static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
 }
 
 static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
-			 uint32_t *min, uint32_t *max, const int count)
+			 uint32_t *min, uint32_t *max, const int count,
+			 int vrr_push_scanline)
 {
 	uint32_t dsl1 = 0, dsl2 = 0;
 	bool field1 = false, field2 = false;
@@ -826,6 +885,7 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
 		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		write_reg(surf, saved+256);
+		push_vrr(devid, pipe, vrr_push_scanline);
 
 		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
 
@@ -845,7 +905,8 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
 }
 
 static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
-			  uint32_t *min, uint32_t *max, const int count, bool async)
+			  uint32_t *min, uint32_t *max, const int count, bool async,
+			  int vrr_push_scanline)
 {
 	uint32_t dsl1 = 0, dsl2 = 0;
 	bool field1 = false, field2 = false;
@@ -862,6 +923,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
 		dsl1 = wait_scanline(pipe, target_scanline, &field1);
 
 		write_reg(surf, saved+256*1024);
+		push_vrr(devid, pipe, vrr_push_scanline);
 
 		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
 
@@ -944,7 +1006,8 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
 }
 
 static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
-				    uint32_t *min, uint32_t *max, const int count, bool async)
+				    uint32_t *min, uint32_t *max, const int count, bool async,
+				    int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1 = 0, dsl2 = 0;
 	uint32_t iir, iir2, ier, imr;
@@ -997,6 +1060,7 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
 		else
 			next = saved;
 		write_reg(surf, next);
+		push_vrr(devid, pipe, vrr_push_scanline);
 
 		while (!quit) {
 			iir2 = read_reg(iir);
@@ -1028,7 +1092,8 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
 }
 
 static void poll_dsl_surflive(uint32_t devid, int pipe,
-			      uint32_t *min, uint32_t *max, const int count, bool async)
+			      uint32_t *min, uint32_t *max, const int count, bool async,
+			      int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1 = 0, dsl2 = 0, surf, surf1, surf2, surflive, surfl1 = 0, surfl2, saved, tmp;
 	bool field1 = false, field2 = false;
@@ -1047,6 +1112,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
 
 	while (!quit) {
 		write_reg(surf, surf2);
+		push_vrr(devid, pipe, vrr_push_scanline);
 
 		while (!quit) {
 			dsl1 = read_reg(dsl);
@@ -1083,7 +1149,9 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
 	write_reg(surf, saved);
 }
 
-static void poll_dsl_wrap(int pipe, uint32_t *min, uint32_t *max, const int count)
+static void poll_dsl_wrap(uint32_t devid, int pipe,
+			  uint32_t *min, uint32_t *max, const int count,
+			  int vrr_push_scanline)
 {
 	uint32_t dsl, dsl1, dsl2;
 	bool field1, field2;
@@ -1092,6 +1160,8 @@ static void poll_dsl_wrap(int pipe, uint32_t *min, uint32_t *max, const int coun
 	dsl = PIPE_REG(pipe, PIPEA_DSL);
 
 	while (!quit) {
+		push_vrr(devid, pipe, vrr_push_scanline);
+
 		while (!quit) {
 			dsl1 = read_reg(dsl);
 			dsl2 = read_reg(dsl);
@@ -1211,7 +1281,8 @@ static void __attribute__((noreturn)) usage(const char *name)
 		" -l,--line <target scanline/pixel>\n"
 		" -f,--fuzz <target fuzz>\n"
 		" -x,--pixel\n"
-		" -a,--async\n",
+		" -a,--async\n"
+		" -v,--vrr-push <push scanline>\n",
 		name);
 	exit(1);
 }
@@ -1223,6 +1294,7 @@ int main(int argc, char *argv[])
 	int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1;
 	bool test_pixelcount = false;
 	bool test_async_flip = false;
+	int vrr_push_scanline = -1;
 	uint32_t devid;
 	uint32_t min[2*128] = {};
 	uint32_t max[2*128] = {};
@@ -1239,10 +1311,11 @@ int main(int argc, char *argv[])
 			{ .name = "fuzz", .has_arg = required_argument, },
 			{ .name = "pixel", .has_arg = no_argument, },
 			{ .name = "async", .has_arg = no_argument, },
+			{ .name = "vrr-push", .has_arg = required_argument, },
 			{ },
 		};
 
-		int opt = getopt_long(argc, argv, "t:p:b:l:f:xa", long_options, NULL);
+		int opt = getopt_long(argc, argv, "t:p:b:l:f:xav:", long_options, NULL);
 		if (opt == -1)
 			break;
 
@@ -1311,6 +1384,11 @@ int main(int argc, char *argv[])
 		case 'a':
 			test_async_flip = true;
 			break;
+		case 'v':
+			vrr_push_scanline = atoi(optarg);
+			if (vrr_push_scanline < 0)
+				usage(argv[0]);
+			break;
 		}
 	}
 
@@ -1330,6 +1408,9 @@ int main(int argc, char *argv[])
 		if (test_async_flip)
 			usage(argv[0]);
 
+		if (vrr_push_scanline >= 0)
+			usage(argv[0]);
+
 		switch (test) {
 		case TEST_IIR:
 			test = TEST_IIR_GEN2;
@@ -1350,6 +1431,9 @@ int main(int argc, char *argv[])
 		if (test_async_flip)
 			usage(argv[0]);
 
+		if (vrr_push_scanline >= 0)
+			usage(argv[0]);
+
 		switch (test) {
 		case TEST_IIR:
 			test = TEST_IIR_GEN3;
@@ -1383,6 +1467,9 @@ int main(int argc, char *argv[])
 		if (test_pixelcount)
 			usage(argv[0]);
 
+		if (vrr_push_scanline >= 0)
+			usage(argv[0]);
+
 		switch (test) {
 		case TEST_IIR:
 			test = TEST_IIR_GEN3;
@@ -1427,6 +1514,9 @@ int main(int argc, char *argv[])
 		if (test_pixelcount)
 			usage(argv[0]);
 
+		if (vrr_push_scanline >= 0 && intel_gen(devid) < 11)
+			usage(argv[0]);
+
 		switch (test) {
 		case TEST_IIR:
 			test = TEST_DEIIR;
@@ -1488,7 +1578,7 @@ int main(int argc, char *argv[])
 		break;
 	case TEST_DEIIR:
 		assert(!test_pixelcount);
-		poll_dsl_deiir(devid, pipe, bit, min, max, count);
+		poll_dsl_deiir(devid, pipe, bit, min, max, count, vrr_push_scanline);
 		break;
 	case TEST_FRAMECOUNT_GEN3:
 		if (test_pixelcount)
@@ -1498,19 +1588,19 @@ int main(int argc, char *argv[])
 		break;
 	case TEST_FRAMECOUNT_G4X:
 		assert(!test_pixelcount);
-		poll_dsl_framecount_g4x(pipe, min, max, count);
+		poll_dsl_framecount_g4x(devid, pipe, min, max, count, vrr_push_scanline);
 		break;
 	case TEST_FRAMETIMESTAMP:
 		assert(!test_pixelcount);
-		poll_dsl_frametimestamp(devid, pipe, min, max, count);
+		poll_dsl_frametimestamp(devid, pipe, min, max, count, vrr_push_scanline);
 		break;
 	case TEST_TIMESTAMP:
 		assert(!test_pixelcount);
-		poll_dsl_timestamp(devid, pipe, target_scanline, min, max, count);
+		poll_dsl_timestamp(devid, pipe, target_scanline, min, max, count, vrr_push_scanline);
 		break;
 	case TEST_FLIPCOUNT:
 		assert(!test_pixelcount);
-		poll_dsl_flipcount_g4x(devid, pipe, min, max, count);
+		poll_dsl_flipcount_g4x(devid, pipe, min, max, count, vrr_push_scanline);
 		break;
 	case TEST_PAN:
 		if (test_pixelcount)
@@ -1518,7 +1608,7 @@ int main(int argc, char *argv[])
 				       min, max, count);
 		else
 			poll_dsl_pan(devid, pipe, target_scanline, target_fuzz,
-				     min, max, count);
+				     min, max, count, vrr_push_scanline);
 		break;
 	case TEST_FLIP:
 		if (test_pixelcount)
@@ -1526,7 +1616,7 @@ int main(int argc, char *argv[])
 					min, max, count);
 		else
 			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
-				      min, max, count, test_async_flip);
+				      min, max, count, test_async_flip, vrr_push_scanline);
 		break;
 	case TEST_FLIPDONE_PIPESTAT:
 		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
@@ -1534,16 +1624,16 @@ int main(int argc, char *argv[])
 		break;
 	case TEST_FLIPDONE_DEIIR:
 		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
-					min, max, count, test_async_flip);
+					min, max, count, test_async_flip, vrr_push_scanline);
 		break;
 	case TEST_SURFLIVE:
-		poll_dsl_surflive(devid, pipe, min, max, count, test_async_flip);
+		poll_dsl_surflive(devid, pipe, min, max, count, test_async_flip, vrr_push_scanline);
 		break;
 	case TEST_WRAP:
 		if (test_pixelcount)
 			poll_pixel_wrap(pipe, min, max, count);
 		else
-			poll_dsl_wrap(pipe, min, max, count);
+			poll_dsl_wrap(devid, pipe, min, max, count, vrr_push_scanline);
 		break;
 	case TEST_FIELD:
 		poll_dsl_field(pipe, min, max, count);
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 13/14] tools/intel_display_poller: Add vrr-wrap test

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The VRR_STATUS2 registers contains yet anoher scanline counter.
Let's add a test to check when it wraps.

Not sure this is actually useful. A better way might be to
allow wholesale replacement of the normal scanline counter
register with the VRR STATUS2? Not sure we care about this
register at all actually.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 43 ++++++++++++++++++++++++++++++------
 1 file changed, 36 insertions(+), 7 deletions(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 37383dc8..6c417050 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -59,6 +59,7 @@ enum test {
 	TEST_FLIPDONE_DEIIR,
 	TEST_SURFLIVE,
 	TEST_WRAP,
+	TEST_VRR_WRAP,
 	TEST_FIELD,
 };
 
@@ -1149,16 +1150,14 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
 	write_reg(surf, saved);
 }
 
-static void poll_dsl_wrap(uint32_t devid, int pipe,
-			  uint32_t *min, uint32_t *max, const int count,
-			  int vrr_push_scanline)
+static void _poll_dsl_wrap(uint32_t devid, int pipe,
+			   uint32_t *min, uint32_t *max, const int count,
+			   int vrr_push_scanline, uint32_t dsl)
 {
-	uint32_t dsl, dsl1, dsl2;
+	uint32_t dsl1, dsl2;
 	bool field1, field2;
 	int i[2] = {};
 
-	dsl = PIPE_REG(pipe, PIPEA_DSL);
-
 	while (!quit) {
 		push_vrr(devid, pipe, vrr_push_scanline);
 
@@ -1186,6 +1185,24 @@ static void poll_dsl_wrap(uint32_t devid, int pipe,
 	}
 }
 
+static void poll_dsl_wrap(uint32_t devid,
+			  int pipe, uint32_t *min, uint32_t *max, const int count,
+			  int vrr_push_scanline)
+{
+	return _poll_dsl_wrap(devid, pipe, min, max, count,
+			      vrr_push_scanline,
+			      PIPE_REG(pipe, PIPEA_DSL));
+}
+
+static void poll_vrr_wrap(uint32_t devid,
+			  int pipe, uint32_t *min, uint32_t *max, const int count,
+			  int vrr_push_scanline)
+{
+	return _poll_dsl_wrap(devid, pipe, min, max, count,
+			      vrr_push_scanline,
+			      trans_reg(devid, pipe, TRANS_VRR_STATUS2_A));
+}
+
 static void poll_dsl_field(int pipe, uint32_t *min, uint32_t *max, const int count)
 {
 	uint32_t dsl, dsl1, dsl2;
@@ -1267,6 +1284,9 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 	case TEST_FIELD:
 		snprintf(str, sizeof str, "%s / pipe %c / Field", type, pipe_name(pipe));
 		return str;
+	case TEST_VRR_WRAP:
+		snprintf(str, sizeof str, "%s / pipe %c / VRR wrap", type, pipe_name(pipe));
+		return str;
 	default:
 		return "";
 	}
@@ -1275,7 +1295,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 static void __attribute__((noreturn)) usage(const char *name)
 {
 	fprintf(stderr, "Usage: %s [options]\n"
-		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field>\n"
+		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field|vrr-wrap>\n"
 		" -p,--pipe <pipe>\n"
 		" -b,--bit <bit>\n"
 		" -l,--line <target scanline/pixel>\n"
@@ -1345,6 +1365,8 @@ int main(int argc, char *argv[])
 				test = TEST_WRAP;
 			else if (!strcmp(optarg, "field"))
 				test = TEST_FIELD;
+			else if (!strcmp(optarg, "vrr-wrap"))
+				test = TEST_VRR_WRAP;
 			else
 				usage(argv[0]);
 			break;
@@ -1527,6 +1549,10 @@ int main(int argc, char *argv[])
 		case TEST_FLIPDONE:
 			test = TEST_FLIPDONE_DEIIR;
 			break;
+		case TEST_VRR_WRAP:
+			if (intel_gen(devid) < 11)
+				usage(argv[0]);
+			break;
 		case TEST_FLIPCOUNT:
 		case TEST_PAN:
 		case TEST_FLIP:
@@ -1638,6 +1664,9 @@ int main(int argc, char *argv[])
 	case TEST_FIELD:
 		poll_dsl_field(pipe, min, max, count);
 		break;
+	case TEST_VRR_WRAP:
+		poll_vrr_wrap(devid, pipe, min, max, count, vrr_push_scanline);
+		break;
 	default:
 		assert(0);
 	}
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] [PATCH i-g-t 14/14] tools/intel_display_poller: Add vrr-push test

[Manasi Navare]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add another VRR test, this time to dermine on which scanline
the hardware will clear the push bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tools/intel_display_poller.c | 59 +++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 6c417050..fa77f9ea 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -61,6 +61,7 @@ enum test {
 	TEST_WRAP,
 	TEST_VRR_WRAP,
 	TEST_FIELD,
+	TEST_VRR_PUSH,
 };
 
 static uint32_t vlv_offset;
@@ -1230,6 +1231,50 @@ static void poll_dsl_field(int pipe, uint32_t *min, uint32_t *max, const int cou
 	}
 }
 
+static void poll_dsl_vrr_push(uint32_t devid, int pipe,
+			      uint32_t *min, uint32_t *max, const int count,
+			      int vrr_push_scanline)
+{
+	uint32_t dsl, dsl1, dsl2;
+	uint32_t vrr, vrr1, vrr2;
+	bool field1, field2;
+	int i[2] = {};
+
+	dsl = PIPE_REG(pipe, PIPEA_DSL);
+	vrr = trans_reg(devid, pipe, TRANS_PUSH_A);
+
+	while (!quit) {
+		push_vrr(devid, pipe, vrr_push_scanline);
+
+		while (!quit) {
+			dsl1 = read_reg(dsl);
+			vrr1 = read_reg(vrr);
+			vrr2 = read_reg(vrr);
+			dsl2 = read_reg(dsl);
+
+			field1 = dsl1 & 0x80000000;
+			field2 = dsl2 & 0x80000000;
+			dsl1 &= ~0x80000000;
+			dsl2 &= ~0x80000000;
+
+			if (!(vrr2 & 0x40000000))
+				break;
+		}
+
+		if (!(vrr1 & 0x40000000))
+			continue;
+
+		if (field1 != field2)
+			printf("fields are different (%u:%u -> %u:%u)\n",
+			       field1, dsl1, field2, dsl2);
+
+		min[field1*count+i[field1]] = dsl1;
+		max[field1*count+i[field1]] = dsl2;
+		if (++i[field1] >= count)
+			break;
+	}
+}
+
 static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_count)
 {
 	static char str[64];
@@ -1287,6 +1332,9 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 	case TEST_VRR_WRAP:
 		snprintf(str, sizeof str, "%s / pipe %c / VRR wrap", type, pipe_name(pipe));
 		return str;
+	case TEST_VRR_PUSH:
+		snprintf(str, sizeof str, "%s / pipe %c / VRR push", type, pipe_name(pipe));
+		return str;
 	default:
 		return "";
 	}
@@ -1295,7 +1343,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
 static void __attribute__((noreturn)) usage(const char *name)
 {
 	fprintf(stderr, "Usage: %s [options]\n"
-		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field|vrr-wrap>\n"
+		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field|vrr-wrap|vrr-push>\n"
 		" -p,--pipe <pipe>\n"
 		" -b,--bit <bit>\n"
 		" -l,--line <target scanline/pixel>\n"
@@ -1365,6 +1413,8 @@ int main(int argc, char *argv[])
 				test = TEST_WRAP;
 			else if (!strcmp(optarg, "field"))
 				test = TEST_FIELD;
+			else if (!strcmp(optarg, "vrr-push"))
+				test = TEST_VRR_PUSH;
 			else if (!strcmp(optarg, "vrr-wrap"))
 				test = TEST_VRR_WRAP;
 			else
@@ -1549,6 +1599,10 @@ int main(int argc, char *argv[])
 		case TEST_FLIPDONE:
 			test = TEST_FLIPDONE_DEIIR;
 			break;
+		case TEST_VRR_PUSH:
+			if (vrr_push_scanline < 0)
+				usage(argv[0]);
+			/* fallthrough */
 		case TEST_VRR_WRAP:
 			if (intel_gen(devid) < 11)
 				usage(argv[0]);
@@ -1664,6 +1718,9 @@ int main(int argc, char *argv[])
 	case TEST_FIELD:
 		poll_dsl_field(pipe, min, max, count);
 		break;
+	case TEST_VRR_PUSH:
+		poll_dsl_vrr_push(devid, pipe, min, max, count, vrr_push_scanline);
+		break;
 	case TEST_VRR_WRAP:
 		poll_vrr_wrap(devid, pipe, min, max, count, vrr_push_scanline);
 		break;
-- 
2.19.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.BAT: failure for tools/intel_display_poller: async flip and vrr (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 6694 bytes --]

== Series Details ==

Series: tools/intel_display_poller: async flip and vrr (rev2)
URL   : https://patchwork.freedesktop.org/series/85042/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9818 -> IGTPW_5560
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5560 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5560, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5560:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_tiled_fence_blits@basic:
    - fi-kbl-8809g:       [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-8809g/igt@gem_tiled_fence_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-kbl-8809g/igt@gem_tiled_fence_blits@basic.html

  
Known issues
------------

  Here are the changes found in IGTPW_5560 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-icl-y:           NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-apl-guc:         NOTRUN -> [SKIP][4] ([fdo#109271]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-apl-guc/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-y:           NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-icl-y/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@basic:
    - fi-tgl-y:           [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@gem_mmap_gtt@basic.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-tgl-y/igt@gem_mmap_gtt@basic.html

  * igt@i915_hangman@error-state-basic:
    - fi-apl-guc:         NOTRUN -> [DMESG-WARN][8] ([i915#1610])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-apl-guc/igt@i915_hangman@error-state-basic.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-y:           NOTRUN -> [SKIP][9] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-icl-y/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-bsw-n3050/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-y:           NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-icl-y/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-icl-y:           NOTRUN -> [SKIP][12] ([fdo#109278])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-icl-y/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][13] ([fdo#109271]) +39 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-bsw-n3050/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-icl-y:           NOTRUN -> [SKIP][14] ([fdo#110189]) +3 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html

  * igt@runner@aborted:
    - fi-apl-guc:         NOTRUN -> [FAIL][15] ([i915#2426])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-apl-guc/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - fi-kbl-8809g:       [TIMEOUT][16] -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [FAIL][18] ([i915#2128]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
    - fi-tgl-y:           [DMESG-WARN][20] ([i915#402]) -> [PASS][21] +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9818/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#2128]: https://gitlab.freedesktop.org/drm/intel/issues/2128
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (42 -> 40)
------------------------------

  Additional (3): fi-icl-y fi-apl-guc fi-bsw-n3050 
  Missing    (5): fi-ilk-m540 fi-bsw-cyan fi-ctg-p8600 fi-dg1-1 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6016 -> IGTPW_5560

  CI-20190529: 20190529
  CI_DRM_9818: fb3b93df7979b1cf6b69ac801d1703c0bf1dde66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5560: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/index.html
  IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/index.html

[-- Attachment #1.2: Type: text/html, Size: 7970 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.IGT: success for tools/intel_display_poller: async flip and vrr (rev2)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 1202 bytes --]

== Series Details ==

Series: tools/intel_display_poller: async flip and vrr (rev2)
URL   : https://patchwork.freedesktop.org/series/85042/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9818_full -> IGTPW_5560_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/index.html


Changes
-------

  No changes found


Participating hosts (10 -> 8)
------------------------------

  Missing    (2): pig-kbl-iris pig-icl-1065g7 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6016 -> IGTPW_5560
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_9818: fb3b93df7979b1cf6b69ac801d1703c0bf1dde66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5560: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/index.html
  IGT_6016: 2107b0a53692fb329175bc16169c3699712187aa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5560/index.html

[-- Attachment #1.2: Type: text/html, Size: 1779 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 03/14] tools/intel_display_poller: Use intel_gen()

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:36PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use intel_gen() to simplify some of the conditions. And for
> the same of consistency we'll replace all the IS_GEN*()s.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index bb115598..0594e918 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -96,7 +96,7 @@ static char pipe_name(int pipe)
>  
>  static int pipe_to_plane(uint32_t devid, int pipe)
>  {
> -	if (!IS_GEN2(devid) && !IS_GEN3(devid))
> +	if (intel_gen(devid) >= 4)
>  		return pipe;
>  
>  	switch (pipe) {
> @@ -145,7 +145,7 @@ static uint32_t dspsurf_reg(uint32_t devid, int pipe)
>  {
>  	int plane = pipe_to_plane(devid, pipe);
>  
> -	if (IS_GEN2(devid) || IS_GEN3(devid))
> +	if (intel_gen(devid) < 4)
>  		return PIPE_REG(plane, DSPABASE);
>  	else
>  		return PIPE_REG(plane, DSPASURF);
> @@ -1053,7 +1053,7 @@ int main(int argc, char *argv[])
>  	 * check if the requires registers are
>  	 * avilable on the current platform.
>  	 */
> -	if (IS_GEN2(devid)) {
> +	if (intel_gen(devid) == 2) {
>  		if (pipe > 1)
>  			usage(argv[0]);
>  
> @@ -1073,8 +1073,7 @@ int main(int argc, char *argv[])
>  		default:
>  			usage(argv[0]);
>  		}
> -	} else if (IS_GEN3(devid) ||
> -		   (IS_GEN4(devid) && !IS_G4X(devid))) {
> +	} else if (intel_gen(devid) < 5 && !IS_G4X(devid)) {
>  		if (pipe > 1)
>  			usage(argv[0]);
>  
> @@ -1091,14 +1090,13 @@ int main(int argc, char *argv[])
>  		case TEST_FIELD:
>  			break;
>  		case TEST_FLIP:
> -			if (IS_GEN3(devid))
> +			if (intel_gen(devid) == 3)
>  				test = TEST_PAN;
>  			break;
>  		default:
>  			usage(argv[0]);
>  		}
> -	} else if (IS_G4X(devid) ||
> -		   IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) {
> +	} else if (IS_G4X(devid) || IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)) {
>  		if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
>  			vlv_offset = 0x180000;
>  		if (IS_CHERRYVIEW(devid))
> @@ -1129,8 +1127,7 @@ int main(int argc, char *argv[])
>  			usage(argv[0]);
>  		}
>  	} else {
> -		if (pipe > 1 &&
> -		    (IS_GEN5(devid) || IS_GEN6(devid)))
> +		if (pipe > 1 && intel_gen(devid) < 7)
>  			usage(argv[0]);
>  
>  		if (test_pixelcount)
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 04/14] tools/intel_display_poller: Add pipe D support

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:37PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's support 4 pipes for tgl+.
> 
> v2: Fix up pipe_offsets[] as well
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 0594e918..826833b3 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -58,7 +58,7 @@ enum test {
>  };
>  
>  static uint32_t vlv_offset;
> -static uint16_t pipe_offset[3] = { 0, 0x1000, 0x2000, };
> +static uint16_t pipe_offset[4] = { 0, 0x1000, 0x2000, 0x3000, };
>  
>  #define PIPE_REG(pipe, reg_a) (pipe_offset[(pipe)] + (reg_a))
>  
> @@ -1023,7 +1023,7 @@ int main(int argc, char *argv[])
>  				pipe -= '0';
>  			else
>  				usage(argv[0]);
> -			if (pipe < 0 || pipe > 2)
> +			if (pipe < 0 || pipe > 3)
>  				usage(argv[0]);
>  			break;
>  		case 'b':
> @@ -1104,6 +1104,8 @@ int main(int argc, char *argv[])
>  
>  		if (pipe > 1 && !IS_CHERRYVIEW(devid))
>  			usage(argv[0]);
> +		if (pipe > 2)
> +			usage(argv[0]);
>  
>  		if (test_pixelcount)
>  			usage(argv[0]);
> @@ -1129,6 +1131,10 @@ int main(int argc, char *argv[])
>  	} else {
>  		if (pipe > 1 && intel_gen(devid) < 7)
>  			usage(argv[0]);
> +		if (pipe > 2 && intel_gen(devid) < 12)
> +			usage(argv[0]);
> +		if (pipe > 3)
> +			usage(argv[0]);
>  
>  		if (test_pixelcount)
>  			usage(argv[0]);
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 05/14] tools/intel_display_poller: Add flipdone tests

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:38PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add test for determining on which scanline the flipdone interrupt
> is signalled. ilk+ and vlv/chv have this. Earlier platforms had
> a "flip pending" bit instead which only seems to respond to CS flips
> so not relevant for MMIO based flips.
> 
> v2: Rework the loops a bit to ease VRR in the future
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Looks good to me in general for checking the flipdone interrupt.
So for the changes here:

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Quick question here:
How do we test this TEST_FLIPDONE with vrr enabled, we need to add setting vrr prop etc here?

Manasi

> ---
>  tools/intel_display_poller.c | 187 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 186 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 826833b3..be237221 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -52,6 +52,9 @@ enum test {
>  	TEST_FLIPCOUNT,
>  	TEST_PAN,
>  	TEST_FLIP,
> +	TEST_FLIPDONE,
> +	TEST_FLIPDONE_PIPESTAT,
> +	TEST_FLIPDONE_DEIIR,
>  	TEST_SURFLIVE,
>  	TEST_WRAP,
>  	TEST_FIELD,
> @@ -789,6 +792,158 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
>  	write_reg(surf, saved);
>  }
>  
> +static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> +				       uint32_t *min, uint32_t *max, const int count)
> +{
> +	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> +	uint32_t pipestat, pipestat1, pipestat2, pipestat_save;
> +	bool field1 = false, field2 = false;
> +	uint32_t saved, next, surf = 0, bit;
> +	int i[2] = {};
> +
> +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> +	pipestat = PIPE_REG(pipe, PIPEASTAT);
> +	surf = dspsurf_reg(devid, pipe);
> +
> +	bit = 1 << 10;
> +
> +	saved = read_reg(surf);
> +	next = saved;
> +
> +	pipestat_save = read_reg(pipestat) & 0x7fff0000;
> +	pipestat1 = pipestat_save & ~(1 << (bit<<16));
> +	write_reg(pipestat, pipestat1 | bit);
> +
> +	while (!quit) {
> +		while (!quit) {
> +			dsl1 = read_reg(dsl);
> +			field1 = dsl1 & 0x80000000;
> +			dsl1 &= ~0x80000000;
> +			if (dsl1 == target_scanline)
> +				break;
> +		}
> +
> +		write_reg(pipestat, pipestat1 | bit);
> +		if (next == saved)
> +			next = saved+256*1024;
> +		else
> +			next = saved;
> +		write_reg(surf, next);
> +
> +		while (!quit) {
> +			pipestat2 = read_reg(pipestat);
> +			dsl2 = read_reg(dsl);
> +
> +			field2 = dsl2 & 0x80000000;
> +			dsl2 &= ~0x80000000;
> +
> +			if (pipestat2 & bit)
> +				break;
> +		}
> +
> +		write_reg(pipestat, pipestat1 | bit);
> +
> +		if (field1 != field2)
> +			printf("fields are different (%u:%u -> %u:%u)\n",
> +			       field1, dsl1, field2, dsl2);
> +
> +		min[field1*count+i[field1]] = dsl1;
> +		max[field1*count+i[field1]] = dsl2;
> +		if (++i[field1] >= count)
> +			break;
> +	}
> +
> +	write_reg(surf, saved);
> +	write_reg(pipestat, pipestat_save);
> +}
> +
> +static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> +				    uint32_t *min, uint32_t *max, const int count)
> +{
> +	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> +	uint32_t iir, iir2, ier, imr;
> +	uint32_t ier_save, imr_save;
> +	bool field1 = false, field2 = false;
> +	uint32_t saved, next, surf = 0, bit;
> +	int i[2] = {};
> +
> +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> +	surf = dspsurf_reg(devid, pipe);
> +
> +	if (intel_gen(devid) >= 9)
> +		bit = 3;
> +	else if (intel_gen(devid) >= 8)
> +		bit = 4;
> +	else if (intel_gen(devid) >= 7)
> +		bit = 3 + 5 * pipe;
> +	else if (intel_gen(devid) >= 5)
> +		bit = 26 + pipe;
> +	else
> +		abort();
> +	bit = 1 << bit;
> +
> +	if (intel_gen(devid) >= 8) {
> +		iir = GEN8_DE_PIPE_IIR(pipe);
> +		ier = GEN8_DE_PIPE_IER(pipe);
> +		imr = GEN8_DE_PIPE_IMR(pipe);
> +	} else {
> +		iir = DEIIR;
> +		ier = DEIER;
> +		imr = DEIMR;
> +	}
> +
> +	saved = read_reg(surf);
> +	next = saved;
> +
> +	imr_save = read_reg(imr);
> +	ier_save = read_reg(ier);
> +	write_reg(ier, ier_save & ~bit);
> +	write_reg(imr, imr_save & ~bit);
> +
> +	while (!quit) {
> +		while (!quit) {
> +			dsl1 = read_reg(dsl);
> +			field1 = dsl1 & 0x80000000;
> +			dsl1 &= ~0x80000000;
> +			if (dsl1 == target_scanline)
> +				break;
> +		}
> +
> +		write_reg(iir, bit);
> +		if (next == saved)
> +			next = saved+256*1024;
> +		else
> +			next = saved;
> +		write_reg(surf, next);
> +
> +		while (!quit) {
> +			iir2 = read_reg(iir);
> +			dsl2 = read_reg(dsl);
> +
> +			field2 = dsl2 & 0x80000000;
> +			dsl2 &= ~0x80000000;
> +
> +			if (iir2 & bit)
> +				break;
> +		}
> +
> +		write_reg(iir, bit);
> +
> +		if (field1 != field2)
> +			printf("fields are different (%u:%u -> %u:%u)\n",
> +			       field1, dsl1, field2, dsl2);
> +
> +		min[field1*count+i[field1]] = dsl1;
> +		max[field1*count+i[field1]] = dsl2;
> +		if (++i[field1] >= count)
> +			break;
> +	}
> +
> +	write_reg(surf, saved);
> +	write_reg(imr, imr_save);
> +	write_reg(ier, ier_save);
> +}
> +
>  static void poll_dsl_surflive(uint32_t devid, int pipe,
>  			      uint32_t *min, uint32_t *max, const int count)
>  {
> @@ -933,6 +1088,12 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  	case TEST_FLIP:
>  		snprintf(str, sizeof str, "%s / pipe %c / Flip", type, pipe_name(pipe));
>  		return str;
> +	case TEST_FLIPDONE_PIPESTAT:
> +		snprintf(str, sizeof str, "%s / pipe %c / Flip done (vlv/chv)", type, pipe_name(pipe));
> +		return str;
> +	case TEST_FLIPDONE_DEIIR:
> +		snprintf(str, sizeof str, "%s / pipe %c / Flip done (pch)", type, pipe_name(pipe));
> +		return str;
>  	case TEST_SURFLIVE:
>  		snprintf(str, sizeof str, "%s / pipe %c / Surflive", type, pipe_name(pipe));
>  		return str;
> @@ -950,7 +1111,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  static void __attribute__((noreturn)) usage(const char *name)
>  {
>  	fprintf(stderr, "Usage: %s [options]\n"
> -		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|surflive|wrap|field>\n"
> +		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|flipdone|surflive|wrap|field>\n"
>  		" -p,--pipe <pipe>\n"
>  		" -b,--bit <bit>\n"
>  		" -l,--line <target scanline/pixel>\n"
> @@ -1002,6 +1163,8 @@ int main(int argc, char *argv[])
>  				test = TEST_PAN;
>  			else if (!strcmp(optarg, "flip"))
>  				test = TEST_FLIP;
> +			else if (!strcmp(optarg, "flipdone"))
> +				test = TEST_FLIPDONE;
>  			else if (!strcmp(optarg, "surflive"))
>  				test = TEST_SURFLIVE;
>  			else if (!strcmp(optarg, "wrap"))
> @@ -1117,6 +1280,16 @@ int main(int argc, char *argv[])
>  		case TEST_FRAMECOUNT:
>  			test = TEST_FRAMECOUNT_G4X;
>  			break;
> +		case TEST_FLIPDONE:
> +			/*
> +			 * g4x has no apparent "flip done" interrupt,
> +			 * and the "flip pending" interrupt does not
> +			 * seem to do anything with mmio flips.
> +			 */
> +			if (IS_G4X(devid))
> +				usage(argv[0]);
> +			test = TEST_FLIPDONE_PIPESTAT;
> +			break;
>  		case TEST_FLIPCOUNT:
>  		case TEST_PIPESTAT:
>  		case TEST_PAN:
> @@ -1146,6 +1319,9 @@ int main(int argc, char *argv[])
>  		case TEST_FRAMECOUNT:
>  			test = TEST_FRAMECOUNT_G4X;
>  			break;
> +		case TEST_FLIPDONE:
> +			test = TEST_FLIPDONE_DEIIR;
> +			break;
>  		case TEST_FLIPCOUNT:
>  		case TEST_PAN:
>  		case TEST_FLIP:
> @@ -1161,6 +1337,7 @@ int main(int argc, char *argv[])
>  	switch (test) {
>  	case TEST_IIR:
>  	case TEST_FRAMECOUNT:
> +	case TEST_FLIPDONE:
>  		/* should no longer have the generic tests here */
>  		assert(0);
>  	default:
> @@ -1226,6 +1403,14 @@ int main(int argc, char *argv[])
>  			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
>  				      min, max, count);
>  		break;
> +	case TEST_FLIPDONE_PIPESTAT:
> +		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
> +					   min, max, count);
> +		break;
> +	case TEST_FLIPDONE_DEIIR:
> +		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
> +					min, max, count);
> +		break;
>  	case TEST_SURFLIVE:
>  		poll_dsl_surflive(devid, pipe, min, max, count);
>  		break;
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 07/14] lib: Add transcoder VRR registers

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:40PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add definitions for the transcoder VRR registers.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Registers look good,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  lib/intel_reg.h | 37 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index 7b543109..d5017f3d 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -880,6 +880,43 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define VSYNC_EDP	0x6F014
>  #define VSYNCSHIFT_EDP	0x6F028
>  
> +#define TRANS_VRR_CTL_A                0x60420
> +#define TRANS_VRR_CTL_B                0x61420
> +#define TRANS_VRR_CTL_C                0x62420
> +#define TRANS_VRR_CTL_D                0x63420
> +#define TRANS_VRR_VMAX_A               0x60424
> +#define TRANS_VRR_VMAX_B               0x61424
> +#define TRANS_VRR_VMAX_C               0x62424
> +#define TRANS_VRR_VMAX_D               0x63424
> +#define TRANS_VRR_VMIN_A               0x60434
> +#define TRANS_VRR_VMIN_B               0x61434
> +#define TRANS_VRR_VMIN_C               0x62434
> +#define TRANS_VRR_VMIN_D               0x63434
> +#define TRANS_VRR_VMAXSHIFT_A          0x60428
> +#define TRANS_VRR_VMAXSHIFT_B          0x61428
> +#define TRANS_VRR_VMAXSHIFT_C          0x62428
> +#define TRANS_VRR_VMAXSHIFT_D          0x63428
> +#define TRANS_VRR_STATUS_A             0x6042C
> +#define TRANS_VRR_STATUS_B             0x6142C
> +#define TRANS_VRR_STATUS_C             0x6242C
> +#define TRANS_VRR_STATUS_D             0x6342C
> +#define TRANS_VRR_VTOTAL_PREV_A        0x60480
> +#define TRANS_VRR_VTOTAL_PREV_B        0x61480
> +#define TRANS_VRR_VTOTAL_PREV_C        0x62480
> +#define TRANS_VRR_VTOTAL_PREV_D        0x63480
> +#define TRANS_VRR_FLIPLINE_A           0x60438
> +#define TRANS_VRR_FLIPLINE_B           0x61438
> +#define TRANS_VRR_FLIPLINE_C           0x62438
> +#define TRANS_VRR_FLIPLINE_D           0x63438
> +#define TRANS_VRR_STATUS2_A            0x6043C
> +#define TRANS_VRR_STATUS2_B            0x6143C
> +#define TRANS_VRR_STATUS2_C            0x6243C
> +#define TRANS_VRR_STATUS2_D            0x6343C
> +#define TRANS_PUSH_A                   0x60A70
> +#define TRANS_PUSH_B                   0x61A70
> +#define TRANS_PUSH_C                   0x62A70
> +#define TRANS_PUSH_D                   0x63A70
> +
>  #define PP_STATUS	0x61200
>  # define PP_ON					(1 << 31)
>  /*
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 12/14] tools/intel_display_poller: Add VRR push support

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:45PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a new command line knob to specify the scanline on which we
> should send the VRR push. This allows many of the test modes
> to probe the hardware behaviour in the presence of VRR pushes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 134 +++++++++++++++++++++++++++++------
>  1 file changed, 112 insertions(+), 22 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 3b3375ec..37383dc8 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -159,6 +159,29 @@ static uint32_t dspsurf_reg(uint32_t devid, int pipe, bool async)
>  		return PIPE_REG(plane, DSPASURF);
>  }
>  
> +static int pipe_to_transcoder(uint32_t devid, int pipe)
> +{
> +	int gen = intel_gen(devid);
> +
> +	if (IS_HASWELL(devid) || IS_BROADWELL(devid) ||
> +	    gen == 9 || gen == 10 || gen == 11) {
> +		/* FIXME not 100% robust */
> +		if (read_reg(PIPE_REG(pipe, PIPEACONF)) & PIPEACONF_ENABLE)
> +			return pipe;
> +		else
> +			return 0xf; /* EDP */
> +	} else {
> +		return pipe;
> +	}
> +}
> +
> +static uint32_t trans_reg(uint32_t devid, int pipe, uint32_t reg)
> +{
> +	int trans = pipe_to_transcoder(devid, pipe);
> +
> +	return PIPE_REG(trans, reg);
> +}
> +
>  static void enable_async_flip(uint32_t devid, int pipe, bool enable)
>  {
>  	int plane = pipe_to_plane(devid, pipe);
> @@ -175,6 +198,26 @@ static void enable_async_flip(uint32_t devid, int pipe, bool enable)
>  	write_reg(PIPE_REG(plane, DSPACNTR), tmp);
>  }
>  
> +static void push_vrr(uint32_t devid, int pipe, int vrr_push_scanline)
> +{
> +	uint32_t dsl = PIPE_REG(pipe, PIPEA_DSL);
> +	uint32_t push = trans_reg(devid, pipe, TRANS_PUSH_A);
> +
> +	if (vrr_push_scanline < 0)
> +		return;
> +
> +	if (read_reg(push) & 0x40000000)
> +		return;
> +
> +	while (!quit) {
> +		uint32_t dsl1 = read_reg(dsl) & ~0x80000000;
> +		if (dsl1 == vrr_push_scanline)
> +			break;
> +	}
> +
> +	write_reg(push, 0xc0000000);
> +}
> +
>  static int wait_scanline(int pipe, int target_scanline, bool *field)
>  {
>  	uint32_t dsl_reg = PIPE_REG(pipe, PIPEA_DSL);
> @@ -545,7 +588,8 @@ static void poll_dsl_iir_gen3(int pipe, int bit,
>  }
>  
>  static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
> -			   uint32_t *min, uint32_t *max, const int count)
> +			   uint32_t *min, uint32_t *max, const int count,
> +			   int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1, dsl2, iir1, iir2, imr_save, ier_save;
>  	bool field1, field2;
> @@ -574,6 +618,8 @@ static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
>  	write_reg(iir, bit);
>  
>  	while (!quit) {
> +		push_vrr(devid, pipe, vrr_push_scanline);
> +
>  		while (!quit) {
>  			dsl1 = read_reg(dsl);
>  			iir1 = read_reg(iir);
> @@ -608,7 +654,9 @@ static void poll_dsl_deiir(uint32_t devid, int pipe, int bit,
>  	write_reg(ier, ier_save);
>  }
>  
> -static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, const int count)
> +static void poll_dsl_framecount_g4x(uint32_t devid, int pipe,
> +				    uint32_t *min, uint32_t *max, const int count,
> +				    int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1, dsl2, frm, frm1, frm2;
>  	bool field1, field2;
> @@ -618,6 +666,8 @@ static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, cons
>  	dsl = PIPE_REG(pipe, PIPEA_DSL);
>  
>  	while (!quit) {
> +		push_vrr(devid, pipe, vrr_push_scanline);
> +
>  		while (!quit) {
>  			dsl1 = read_reg(dsl);
>  			frm1 = read_reg(frm);
> @@ -645,7 +695,8 @@ static void poll_dsl_framecount_g4x(int pipe, uint32_t *min, uint32_t *max, cons
>  }
>  
>  static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
> -				   uint32_t *min, uint32_t *max, const int count)
> +				   uint32_t *min, uint32_t *max, const int count,
> +				   int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1, dsl2, flp, flp1, flp2, surf;
>  	bool field1, field2;
> @@ -676,6 +727,7 @@ static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
>  			return;
>  
>  		write_reg(surf, read_reg(surf));
> +		push_vrr(devid, pipe, vrr_push_scanline);
>  
>  		while (!quit) {
>  			dsl1 = read_reg(dsl);
> @@ -738,7 +790,8 @@ static void poll_dsl_framecount_gen3(int pipe, uint32_t *min, uint32_t *max, con
>  
>  
>  static void poll_dsl_frametimestamp(uint32_t devid, int pipe,
> -				    uint32_t *min, uint32_t *max, const int count)
> +				    uint32_t *min, uint32_t *max, const int count,
> +				    int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1, dsl2, frm, frm1, frm2;
>  	bool field1, field2;
> @@ -748,6 +801,8 @@ static void poll_dsl_frametimestamp(uint32_t devid, int pipe,
>  	dsl = PIPE_REG(pipe, PIPEA_DSL);
>  
>  	while (!quit) {
> +		push_vrr(devid, pipe, vrr_push_scanline);
> +
>  		while (!quit) {
>  			dsl1 = read_reg(dsl);
>  			frm1 = read_reg(frm);
> @@ -785,7 +840,8 @@ static uint32_t timestamp_reg(uint32_t devid)
>  }
>  
>  static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
> -			       uint32_t *min, uint32_t *max, const int count)
> +			       uint32_t *min, uint32_t *max, const int count,
> +			       int vrr_push_scanline)
>  {
>  	uint32_t dsl1, frm, frm1, ts, ts1;
>  	bool field1;
> @@ -795,6 +851,8 @@ static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
>  	frm = PIPE_REG(pipe, PIPEAFRMTMSMTP);
>  
>  	while (!quit) {
> +		push_vrr(devid, pipe, vrr_push_scanline);
> +
>  		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		frm1 = read_reg(frm);
> @@ -811,7 +869,8 @@ static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
>  }
>  
>  static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> -			 uint32_t *min, uint32_t *max, const int count)
> +			 uint32_t *min, uint32_t *max, const int count,
> +			 int vrr_push_scanline)
>  {
>  	uint32_t dsl1 = 0, dsl2 = 0;
>  	bool field1 = false, field2 = false;
> @@ -826,6 +885,7 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
>  		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		write_reg(surf, saved+256);
> +		push_vrr(devid, pipe, vrr_push_scanline);
>  
>  		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
>  
> @@ -845,7 +905,8 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
>  }
>  
>  static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> -			  uint32_t *min, uint32_t *max, const int count, bool async)
> +			  uint32_t *min, uint32_t *max, const int count, bool async,
> +			  int vrr_push_scanline)
>  {
>  	uint32_t dsl1 = 0, dsl2 = 0;
>  	bool field1 = false, field2 = false;
> @@ -862,6 +923,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
>  		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		write_reg(surf, saved+256*1024);
> +		push_vrr(devid, pipe, vrr_push_scanline);
>  
>  		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
>  
> @@ -944,7 +1006,8 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
>  }
>  
>  static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> -				    uint32_t *min, uint32_t *max, const int count, bool async)
> +				    uint32_t *min, uint32_t *max, const int count, bool async,
> +				    int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1 = 0, dsl2 = 0;
>  	uint32_t iir, iir2, ier, imr;
> @@ -997,6 +1060,7 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
>  		else
>  			next = saved;
>  		write_reg(surf, next);
> +		push_vrr(devid, pipe, vrr_push_scanline);
>  
>  		while (!quit) {
>  			iir2 = read_reg(iir);
> @@ -1028,7 +1092,8 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
>  }
>  
>  static void poll_dsl_surflive(uint32_t devid, int pipe,
> -			      uint32_t *min, uint32_t *max, const int count, bool async)
> +			      uint32_t *min, uint32_t *max, const int count, bool async,
> +			      int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1 = 0, dsl2 = 0, surf, surf1, surf2, surflive, surfl1 = 0, surfl2, saved, tmp;
>  	bool field1 = false, field2 = false;
> @@ -1047,6 +1112,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
>  
>  	while (!quit) {
>  		write_reg(surf, surf2);
> +		push_vrr(devid, pipe, vrr_push_scanline);
>  
>  		while (!quit) {
>  			dsl1 = read_reg(dsl);
> @@ -1083,7 +1149,9 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
>  	write_reg(surf, saved);
>  }
>  
> -static void poll_dsl_wrap(int pipe, uint32_t *min, uint32_t *max, const int count)
> +static void poll_dsl_wrap(uint32_t devid, int pipe,
> +			  uint32_t *min, uint32_t *max, const int count,
> +			  int vrr_push_scanline)
>  {
>  	uint32_t dsl, dsl1, dsl2;
>  	bool field1, field2;
> @@ -1092,6 +1160,8 @@ static void poll_dsl_wrap(int pipe, uint32_t *min, uint32_t *max, const int coun
>  	dsl = PIPE_REG(pipe, PIPEA_DSL);
>  
>  	while (!quit) {
> +		push_vrr(devid, pipe, vrr_push_scanline);
> +
>  		while (!quit) {
>  			dsl1 = read_reg(dsl);
>  			dsl2 = read_reg(dsl);
> @@ -1211,7 +1281,8 @@ static void __attribute__((noreturn)) usage(const char *name)
>  		" -l,--line <target scanline/pixel>\n"
>  		" -f,--fuzz <target fuzz>\n"
>  		" -x,--pixel\n"
> -		" -a,--async\n",
> +		" -a,--async\n"
> +		" -v,--vrr-push <push scanline>\n",
>  		name);
>  	exit(1);
>  }
> @@ -1223,6 +1294,7 @@ int main(int argc, char *argv[])
>  	int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1;
>  	bool test_pixelcount = false;
>  	bool test_async_flip = false;
> +	int vrr_push_scanline = -1;
>  	uint32_t devid;
>  	uint32_t min[2*128] = {};
>  	uint32_t max[2*128] = {};
> @@ -1239,10 +1311,11 @@ int main(int argc, char *argv[])
>  			{ .name = "fuzz", .has_arg = required_argument, },
>  			{ .name = "pixel", .has_arg = no_argument, },
>  			{ .name = "async", .has_arg = no_argument, },
> +			{ .name = "vrr-push", .has_arg = required_argument, },
>  			{ },
>  		};
>  
> -		int opt = getopt_long(argc, argv, "t:p:b:l:f:xa", long_options, NULL);
> +		int opt = getopt_long(argc, argv, "t:p:b:l:f:xav:", long_options, NULL);
>  		if (opt == -1)
>  			break;
>  
> @@ -1311,6 +1384,11 @@ int main(int argc, char *argv[])
>  		case 'a':
>  			test_async_flip = true;
>  			break;
> +		case 'v':
> +			vrr_push_scanline = atoi(optarg);
> +			if (vrr_push_scanline < 0)
> +				usage(argv[0]);
> +			break;
>  		}
>  	}
>  
> @@ -1330,6 +1408,9 @@ int main(int argc, char *argv[])
>  		if (test_async_flip)
>  			usage(argv[0]);
>  
> +		if (vrr_push_scanline >= 0)
> +			usage(argv[0]);
> +
>  		switch (test) {
>  		case TEST_IIR:
>  			test = TEST_IIR_GEN2;
> @@ -1350,6 +1431,9 @@ int main(int argc, char *argv[])
>  		if (test_async_flip)
>  			usage(argv[0]);
>  
> +		if (vrr_push_scanline >= 0)
> +			usage(argv[0]);
> +
>  		switch (test) {
>  		case TEST_IIR:
>  			test = TEST_IIR_GEN3;
> @@ -1383,6 +1467,9 @@ int main(int argc, char *argv[])
>  		if (test_pixelcount)
>  			usage(argv[0]);
>  
> +		if (vrr_push_scanline >= 0)
> +			usage(argv[0]);
> +
>  		switch (test) {
>  		case TEST_IIR:
>  			test = TEST_IIR_GEN3;
> @@ -1427,6 +1514,9 @@ int main(int argc, char *argv[])
>  		if (test_pixelcount)
>  			usage(argv[0]);
>  
> +		if (vrr_push_scanline >= 0 && intel_gen(devid) < 11)
> +			usage(argv[0]);
> +
>  		switch (test) {
>  		case TEST_IIR:
>  			test = TEST_DEIIR;
> @@ -1488,7 +1578,7 @@ int main(int argc, char *argv[])
>  		break;
>  	case TEST_DEIIR:
>  		assert(!test_pixelcount);
> -		poll_dsl_deiir(devid, pipe, bit, min, max, count);
> +		poll_dsl_deiir(devid, pipe, bit, min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_FRAMECOUNT_GEN3:
>  		if (test_pixelcount)
> @@ -1498,19 +1588,19 @@ int main(int argc, char *argv[])
>  		break;
>  	case TEST_FRAMECOUNT_G4X:
>  		assert(!test_pixelcount);
> -		poll_dsl_framecount_g4x(pipe, min, max, count);
> +		poll_dsl_framecount_g4x(devid, pipe, min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_FRAMETIMESTAMP:
>  		assert(!test_pixelcount);
> -		poll_dsl_frametimestamp(devid, pipe, min, max, count);
> +		poll_dsl_frametimestamp(devid, pipe, min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_TIMESTAMP:
>  		assert(!test_pixelcount);
> -		poll_dsl_timestamp(devid, pipe, target_scanline, min, max, count);
> +		poll_dsl_timestamp(devid, pipe, target_scanline, min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_FLIPCOUNT:
>  		assert(!test_pixelcount);
> -		poll_dsl_flipcount_g4x(devid, pipe, min, max, count);
> +		poll_dsl_flipcount_g4x(devid, pipe, min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_PAN:
>  		if (test_pixelcount)
> @@ -1518,7 +1608,7 @@ int main(int argc, char *argv[])
>  				       min, max, count);
>  		else
>  			poll_dsl_pan(devid, pipe, target_scanline, target_fuzz,
> -				     min, max, count);
> +				     min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_FLIP:
>  		if (test_pixelcount)
> @@ -1526,7 +1616,7 @@ int main(int argc, char *argv[])
>  					min, max, count);
>  		else
>  			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
> -				      min, max, count, test_async_flip);
> +				      min, max, count, test_async_flip, vrr_push_scanline);
>  		break;
>  	case TEST_FLIPDONE_PIPESTAT:
>  		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
> @@ -1534,16 +1624,16 @@ int main(int argc, char *argv[])
>  		break;
>  	case TEST_FLIPDONE_DEIIR:
>  		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
> -					min, max, count, test_async_flip);
> +					min, max, count, test_async_flip, vrr_push_scanline);
>  		break;
>  	case TEST_SURFLIVE:
> -		poll_dsl_surflive(devid, pipe, min, max, count, test_async_flip);
> +		poll_dsl_surflive(devid, pipe, min, max, count, test_async_flip, vrr_push_scanline);
>  		break;
>  	case TEST_WRAP:
>  		if (test_pixelcount)
>  			poll_pixel_wrap(pipe, min, max, count);
>  		else
> -			poll_dsl_wrap(pipe, min, max, count);
> +			poll_dsl_wrap(devid, pipe, min, max, count, vrr_push_scanline);
>  		break;
>  	case TEST_FIELD:
>  		poll_dsl_field(pipe, min, max, count);
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 14/14] tools/intel_display_poller: Add vrr-push test

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:47PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add another VRR test, this time to dermine on which scanline
> the hardware will clear the push bit.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 59 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 58 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 6c417050..fa77f9ea 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -61,6 +61,7 @@ enum test {
>  	TEST_WRAP,
>  	TEST_VRR_WRAP,
>  	TEST_FIELD,
> +	TEST_VRR_PUSH,
>  };
>  
>  static uint32_t vlv_offset;
> @@ -1230,6 +1231,50 @@ static void poll_dsl_field(int pipe, uint32_t *min, uint32_t *max, const int cou
>  	}
>  }
>  
> +static void poll_dsl_vrr_push(uint32_t devid, int pipe,
> +			      uint32_t *min, uint32_t *max, const int count,
> +			      int vrr_push_scanline)
> +{
> +	uint32_t dsl, dsl1, dsl2;
> +	uint32_t vrr, vrr1, vrr2;
> +	bool field1, field2;
> +	int i[2] = {};
> +
> +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> +	vrr = trans_reg(devid, pipe, TRANS_PUSH_A);
> +
> +	while (!quit) {
> +		push_vrr(devid, pipe, vrr_push_scanline);
> +
> +		while (!quit) {
> +			dsl1 = read_reg(dsl);
> +			vrr1 = read_reg(vrr);
> +			vrr2 = read_reg(vrr);
> +			dsl2 = read_reg(dsl);
> +
> +			field1 = dsl1 & 0x80000000;
> +			field2 = dsl2 & 0x80000000;
> +			dsl1 &= ~0x80000000;
> +			dsl2 &= ~0x80000000;
> +
> +			if (!(vrr2 & 0x40000000))
> +				break;
> +		}
> +
> +		if (!(vrr1 & 0x40000000))
> +			continue;
> +
> +		if (field1 != field2)
> +			printf("fields are different (%u:%u -> %u:%u)\n",
> +			       field1, dsl1, field2, dsl2);
> +
> +		min[field1*count+i[field1]] = dsl1;
> +		max[field1*count+i[field1]] = dsl2;
> +		if (++i[field1] >= count)
> +			break;
> +	}
> +}
> +
>  static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_count)
>  {
>  	static char str[64];
> @@ -1287,6 +1332,9 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  	case TEST_VRR_WRAP:
>  		snprintf(str, sizeof str, "%s / pipe %c / VRR wrap", type, pipe_name(pipe));
>  		return str;
> +	case TEST_VRR_PUSH:
> +		snprintf(str, sizeof str, "%s / pipe %c / VRR push", type, pipe_name(pipe));
> +		return str;
>  	default:
>  		return "";
>  	}
> @@ -1295,7 +1343,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  static void __attribute__((noreturn)) usage(const char *name)
>  {
>  	fprintf(stderr, "Usage: %s [options]\n"
> -		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field|vrr-wrap>\n"
> +		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field|vrr-wrap|vrr-push>\n"
>  		" -p,--pipe <pipe>\n"
>  		" -b,--bit <bit>\n"
>  		" -l,--line <target scanline/pixel>\n"
> @@ -1365,6 +1413,8 @@ int main(int argc, char *argv[])
>  				test = TEST_WRAP;
>  			else if (!strcmp(optarg, "field"))
>  				test = TEST_FIELD;
> +			else if (!strcmp(optarg, "vrr-push"))
> +				test = TEST_VRR_PUSH;
>  			else if (!strcmp(optarg, "vrr-wrap"))
>  				test = TEST_VRR_WRAP;
>  			else
> @@ -1549,6 +1599,10 @@ int main(int argc, char *argv[])
>  		case TEST_FLIPDONE:
>  			test = TEST_FLIPDONE_DEIIR;
>  			break;
> +		case TEST_VRR_PUSH:
> +			if (vrr_push_scanline < 0)
> +				usage(argv[0]);
> +			/* fallthrough */
>  		case TEST_VRR_WRAP:
>  			if (intel_gen(devid) < 11)
>  				usage(argv[0]);
> @@ -1664,6 +1718,9 @@ int main(int argc, char *argv[])
>  	case TEST_FIELD:
>  		poll_dsl_field(pipe, min, max, count);
>  		break;
> +	case TEST_VRR_PUSH:
> +		poll_dsl_vrr_push(devid, pipe, min, max, count, vrr_push_scanline);
> +		break;
>  	case TEST_VRR_WRAP:
>  		poll_vrr_wrap(devid, pipe, min, max, count, vrr_push_scanline);
>  		break;
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 05/14] tools/intel_display_poller: Add flipdone tests

[Ville Syrjälä]

On Mon, Mar 01, 2021 at 03:54:25PM -0800, Navare, Manasi wrote:
> On Mon, Mar 01, 2021 at 12:37:38PM -0800, Manasi Navare wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Add test for determining on which scanline the flipdone interrupt
> > is signalled. ilk+ and vlv/chv have this. Earlier platforms had
> > a "flip pending" bit instead which only seems to respond to CS flips
> > so not relevant for MMIO based flips.
> > 
> > v2: Rework the loops a bit to ease VRR in the future
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Looks good to me in general for checking the flipdone interrupt.
> So for the changes here:
> 
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> 
> Quick question here:
> How do we test this TEST_FLIPDONE with vrr enabled, we need to add setting vrr prop etc here?

Just enable vrr whatever way you feel like it. I did it by forcing it on
always in the kernel. But I guess we could add a knob to eg. testdisplay
to turn it on. Then you could easily test any mode you want with or
without vrr.

> 
> Manasi
> 
> > ---
> >  tools/intel_display_poller.c | 187 ++++++++++++++++++++++++++++++++++-
> >  1 file changed, 186 insertions(+), 1 deletion(-)
> > 
> > diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> > index 826833b3..be237221 100644
> > --- a/tools/intel_display_poller.c
> > +++ b/tools/intel_display_poller.c
> > @@ -52,6 +52,9 @@ enum test {
> >  	TEST_FLIPCOUNT,
> >  	TEST_PAN,
> >  	TEST_FLIP,
> > +	TEST_FLIPDONE,
> > +	TEST_FLIPDONE_PIPESTAT,
> > +	TEST_FLIPDONE_DEIIR,
> >  	TEST_SURFLIVE,
> >  	TEST_WRAP,
> >  	TEST_FIELD,
> > @@ -789,6 +792,158 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
> >  	write_reg(surf, saved);
> >  }
> >  
> > +static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> > +				       uint32_t *min, uint32_t *max, const int count)
> > +{
> > +	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> > +	uint32_t pipestat, pipestat1, pipestat2, pipestat_save;
> > +	bool field1 = false, field2 = false;
> > +	uint32_t saved, next, surf = 0, bit;
> > +	int i[2] = {};
> > +
> > +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> > +	pipestat = PIPE_REG(pipe, PIPEASTAT);
> > +	surf = dspsurf_reg(devid, pipe);
> > +
> > +	bit = 1 << 10;
> > +
> > +	saved = read_reg(surf);
> > +	next = saved;
> > +
> > +	pipestat_save = read_reg(pipestat) & 0x7fff0000;
> > +	pipestat1 = pipestat_save & ~(1 << (bit<<16));
> > +	write_reg(pipestat, pipestat1 | bit);
> > +
> > +	while (!quit) {
> > +		while (!quit) {
> > +			dsl1 = read_reg(dsl);
> > +			field1 = dsl1 & 0x80000000;
> > +			dsl1 &= ~0x80000000;
> > +			if (dsl1 == target_scanline)
> > +				break;
> > +		}
> > +
> > +		write_reg(pipestat, pipestat1 | bit);
> > +		if (next == saved)
> > +			next = saved+256*1024;
> > +		else
> > +			next = saved;
> > +		write_reg(surf, next);
> > +
> > +		while (!quit) {
> > +			pipestat2 = read_reg(pipestat);
> > +			dsl2 = read_reg(dsl);
> > +
> > +			field2 = dsl2 & 0x80000000;
> > +			dsl2 &= ~0x80000000;
> > +
> > +			if (pipestat2 & bit)
> > +				break;
> > +		}
> > +
> > +		write_reg(pipestat, pipestat1 | bit);
> > +
> > +		if (field1 != field2)
> > +			printf("fields are different (%u:%u -> %u:%u)\n",
> > +			       field1, dsl1, field2, dsl2);
> > +
> > +		min[field1*count+i[field1]] = dsl1;
> > +		max[field1*count+i[field1]] = dsl2;
> > +		if (++i[field1] >= count)
> > +			break;
> > +	}
> > +
> > +	write_reg(surf, saved);
> > +	write_reg(pipestat, pipestat_save);
> > +}
> > +
> > +static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> > +				    uint32_t *min, uint32_t *max, const int count)
> > +{
> > +	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> > +	uint32_t iir, iir2, ier, imr;
> > +	uint32_t ier_save, imr_save;
> > +	bool field1 = false, field2 = false;
> > +	uint32_t saved, next, surf = 0, bit;
> > +	int i[2] = {};
> > +
> > +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> > +	surf = dspsurf_reg(devid, pipe);
> > +
> > +	if (intel_gen(devid) >= 9)
> > +		bit = 3;
> > +	else if (intel_gen(devid) >= 8)
> > +		bit = 4;
> > +	else if (intel_gen(devid) >= 7)
> > +		bit = 3 + 5 * pipe;
> > +	else if (intel_gen(devid) >= 5)
> > +		bit = 26 + pipe;
> > +	else
> > +		abort();
> > +	bit = 1 << bit;
> > +
> > +	if (intel_gen(devid) >= 8) {
> > +		iir = GEN8_DE_PIPE_IIR(pipe);
> > +		ier = GEN8_DE_PIPE_IER(pipe);
> > +		imr = GEN8_DE_PIPE_IMR(pipe);
> > +	} else {
> > +		iir = DEIIR;
> > +		ier = DEIER;
> > +		imr = DEIMR;
> > +	}
> > +
> > +	saved = read_reg(surf);
> > +	next = saved;
> > +
> > +	imr_save = read_reg(imr);
> > +	ier_save = read_reg(ier);
> > +	write_reg(ier, ier_save & ~bit);
> > +	write_reg(imr, imr_save & ~bit);
> > +
> > +	while (!quit) {
> > +		while (!quit) {
> > +			dsl1 = read_reg(dsl);
> > +			field1 = dsl1 & 0x80000000;
> > +			dsl1 &= ~0x80000000;
> > +			if (dsl1 == target_scanline)
> > +				break;
> > +		}
> > +
> > +		write_reg(iir, bit);
> > +		if (next == saved)
> > +			next = saved+256*1024;
> > +		else
> > +			next = saved;
> > +		write_reg(surf, next);
> > +
> > +		while (!quit) {
> > +			iir2 = read_reg(iir);
> > +			dsl2 = read_reg(dsl);
> > +
> > +			field2 = dsl2 & 0x80000000;
> > +			dsl2 &= ~0x80000000;
> > +
> > +			if (iir2 & bit)
> > +				break;
> > +		}
> > +
> > +		write_reg(iir, bit);
> > +
> > +		if (field1 != field2)
> > +			printf("fields are different (%u:%u -> %u:%u)\n",
> > +			       field1, dsl1, field2, dsl2);
> > +
> > +		min[field1*count+i[field1]] = dsl1;
> > +		max[field1*count+i[field1]] = dsl2;
> > +		if (++i[field1] >= count)
> > +			break;
> > +	}
> > +
> > +	write_reg(surf, saved);
> > +	write_reg(imr, imr_save);
> > +	write_reg(ier, ier_save);
> > +}
> > +
> >  static void poll_dsl_surflive(uint32_t devid, int pipe,
> >  			      uint32_t *min, uint32_t *max, const int count)
> >  {
> > @@ -933,6 +1088,12 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
> >  	case TEST_FLIP:
> >  		snprintf(str, sizeof str, "%s / pipe %c / Flip", type, pipe_name(pipe));
> >  		return str;
> > +	case TEST_FLIPDONE_PIPESTAT:
> > +		snprintf(str, sizeof str, "%s / pipe %c / Flip done (vlv/chv)", type, pipe_name(pipe));
> > +		return str;
> > +	case TEST_FLIPDONE_DEIIR:
> > +		snprintf(str, sizeof str, "%s / pipe %c / Flip done (pch)", type, pipe_name(pipe));
> > +		return str;
> >  	case TEST_SURFLIVE:
> >  		snprintf(str, sizeof str, "%s / pipe %c / Surflive", type, pipe_name(pipe));
> >  		return str;
> > @@ -950,7 +1111,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
> >  static void __attribute__((noreturn)) usage(const char *name)
> >  {
> >  	fprintf(stderr, "Usage: %s [options]\n"
> > -		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|surflive|wrap|field>\n"
> > +		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|flipdone|surflive|wrap|field>\n"
> >  		" -p,--pipe <pipe>\n"
> >  		" -b,--bit <bit>\n"
> >  		" -l,--line <target scanline/pixel>\n"
> > @@ -1002,6 +1163,8 @@ int main(int argc, char *argv[])
> >  				test = TEST_PAN;
> >  			else if (!strcmp(optarg, "flip"))
> >  				test = TEST_FLIP;
> > +			else if (!strcmp(optarg, "flipdone"))
> > +				test = TEST_FLIPDONE;
> >  			else if (!strcmp(optarg, "surflive"))
> >  				test = TEST_SURFLIVE;
> >  			else if (!strcmp(optarg, "wrap"))
> > @@ -1117,6 +1280,16 @@ int main(int argc, char *argv[])
> >  		case TEST_FRAMECOUNT:
> >  			test = TEST_FRAMECOUNT_G4X;
> >  			break;
> > +		case TEST_FLIPDONE:
> > +			/*
> > +			 * g4x has no apparent "flip done" interrupt,
> > +			 * and the "flip pending" interrupt does not
> > +			 * seem to do anything with mmio flips.
> > +			 */
> > +			if (IS_G4X(devid))
> > +				usage(argv[0]);
> > +			test = TEST_FLIPDONE_PIPESTAT;
> > +			break;
> >  		case TEST_FLIPCOUNT:
> >  		case TEST_PIPESTAT:
> >  		case TEST_PAN:
> > @@ -1146,6 +1319,9 @@ int main(int argc, char *argv[])
> >  		case TEST_FRAMECOUNT:
> >  			test = TEST_FRAMECOUNT_G4X;
> >  			break;
> > +		case TEST_FLIPDONE:
> > +			test = TEST_FLIPDONE_DEIIR;
> > +			break;
> >  		case TEST_FLIPCOUNT:
> >  		case TEST_PAN:
> >  		case TEST_FLIP:
> > @@ -1161,6 +1337,7 @@ int main(int argc, char *argv[])
> >  	switch (test) {
> >  	case TEST_IIR:
> >  	case TEST_FRAMECOUNT:
> > +	case TEST_FLIPDONE:
> >  		/* should no longer have the generic tests here */
> >  		assert(0);
> >  	default:
> > @@ -1226,6 +1403,14 @@ int main(int argc, char *argv[])
> >  			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
> >  				      min, max, count);
> >  		break;
> > +	case TEST_FLIPDONE_PIPESTAT:
> > +		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
> > +					   min, max, count);
> > +		break;
> > +	case TEST_FLIPDONE_DEIIR:
> > +		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
> > +					min, max, count);
> > +		break;
> >  	case TEST_SURFLIVE:
> >  		poll_dsl_surflive(devid, pipe, min, max, count);
> >  		break;
> > -- 
> > 2.19.1
> > 
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev

-- 
Ville Syrjälä
Intel
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 05/14] tools/intel_display_poller: Add flipdone tests

[Navare, Manasi]

On Tue, Mar 02, 2021 at 02:17:25AM +0200, Ville Syrjälä wrote:
> On Mon, Mar 01, 2021 at 03:54:25PM -0800, Navare, Manasi wrote:
> > On Mon, Mar 01, 2021 at 12:37:38PM -0800, Manasi Navare wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Add test for determining on which scanline the flipdone interrupt
> > > is signalled. ilk+ and vlv/chv have this. Earlier platforms had
> > > a "flip pending" bit instead which only seems to respond to CS flips
> > > so not relevant for MMIO based flips.
> > > 
> > > v2: Rework the loops a bit to ease VRR in the future
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Looks good to me in general for checking the flipdone interrupt.
> > So for the changes here:
> > 
> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > 
> > Quick question here:
> > How do we test this TEST_FLIPDONE with vrr enabled, we need to add setting vrr prop etc here?
> 
> Just enable vrr whatever way you feel like it. I did it by forcing it on
> always in the kernel. But I guess we could add a knob to eg. testdisplay
> to turn it on. Then you could easily test any mode you want with or
> without vrr.
>

Yes adding that knob will be good so we can start using testdisplay to test vrr.
Are you going to add that as a separate series?
Also for running the test_flipdone in this poller tool we would also need a similar knowb right?

Manasi
 
> > 
> > Manasi
> > 
> > > ---
> > >  tools/intel_display_poller.c | 187 ++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 186 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> > > index 826833b3..be237221 100644
> > > --- a/tools/intel_display_poller.c
> > > +++ b/tools/intel_display_poller.c
> > > @@ -52,6 +52,9 @@ enum test {
> > >  	TEST_FLIPCOUNT,
> > >  	TEST_PAN,
> > >  	TEST_FLIP,
> > > +	TEST_FLIPDONE,
> > > +	TEST_FLIPDONE_PIPESTAT,
> > > +	TEST_FLIPDONE_DEIIR,
> > >  	TEST_SURFLIVE,
> > >  	TEST_WRAP,
> > >  	TEST_FIELD,
> > > @@ -789,6 +792,158 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
> > >  	write_reg(surf, saved);
> > >  }
> > >  
> > > +static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> > > +				       uint32_t *min, uint32_t *max, const int count)
> > > +{
> > > +	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> > > +	uint32_t pipestat, pipestat1, pipestat2, pipestat_save;
> > > +	bool field1 = false, field2 = false;
> > > +	uint32_t saved, next, surf = 0, bit;
> > > +	int i[2] = {};
> > > +
> > > +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> > > +	pipestat = PIPE_REG(pipe, PIPEASTAT);
> > > +	surf = dspsurf_reg(devid, pipe);
> > > +
> > > +	bit = 1 << 10;
> > > +
> > > +	saved = read_reg(surf);
> > > +	next = saved;
> > > +
> > > +	pipestat_save = read_reg(pipestat) & 0x7fff0000;
> > > +	pipestat1 = pipestat_save & ~(1 << (bit<<16));
> > > +	write_reg(pipestat, pipestat1 | bit);
> > > +
> > > +	while (!quit) {
> > > +		while (!quit) {
> > > +			dsl1 = read_reg(dsl);
> > > +			field1 = dsl1 & 0x80000000;
> > > +			dsl1 &= ~0x80000000;
> > > +			if (dsl1 == target_scanline)
> > > +				break;
> > > +		}
> > > +
> > > +		write_reg(pipestat, pipestat1 | bit);
> > > +		if (next == saved)
> > > +			next = saved+256*1024;
> > > +		else
> > > +			next = saved;
> > > +		write_reg(surf, next);
> > > +
> > > +		while (!quit) {
> > > +			pipestat2 = read_reg(pipestat);
> > > +			dsl2 = read_reg(dsl);
> > > +
> > > +			field2 = dsl2 & 0x80000000;
> > > +			dsl2 &= ~0x80000000;
> > > +
> > > +			if (pipestat2 & bit)
> > > +				break;
> > > +		}
> > > +
> > > +		write_reg(pipestat, pipestat1 | bit);
> > > +
> > > +		if (field1 != field2)
> > > +			printf("fields are different (%u:%u -> %u:%u)\n",
> > > +			       field1, dsl1, field2, dsl2);
> > > +
> > > +		min[field1*count+i[field1]] = dsl1;
> > > +		max[field1*count+i[field1]] = dsl2;
> > > +		if (++i[field1] >= count)
> > > +			break;
> > > +	}
> > > +
> > > +	write_reg(surf, saved);
> > > +	write_reg(pipestat, pipestat_save);
> > > +}
> > > +
> > > +static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> > > +				    uint32_t *min, uint32_t *max, const int count)
> > > +{
> > > +	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> > > +	uint32_t iir, iir2, ier, imr;
> > > +	uint32_t ier_save, imr_save;
> > > +	bool field1 = false, field2 = false;
> > > +	uint32_t saved, next, surf = 0, bit;
> > > +	int i[2] = {};
> > > +
> > > +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> > > +	surf = dspsurf_reg(devid, pipe);
> > > +
> > > +	if (intel_gen(devid) >= 9)
> > > +		bit = 3;
> > > +	else if (intel_gen(devid) >= 8)
> > > +		bit = 4;
> > > +	else if (intel_gen(devid) >= 7)
> > > +		bit = 3 + 5 * pipe;
> > > +	else if (intel_gen(devid) >= 5)
> > > +		bit = 26 + pipe;
> > > +	else
> > > +		abort();
> > > +	bit = 1 << bit;
> > > +
> > > +	if (intel_gen(devid) >= 8) {
> > > +		iir = GEN8_DE_PIPE_IIR(pipe);
> > > +		ier = GEN8_DE_PIPE_IER(pipe);
> > > +		imr = GEN8_DE_PIPE_IMR(pipe);
> > > +	} else {
> > > +		iir = DEIIR;
> > > +		ier = DEIER;
> > > +		imr = DEIMR;
> > > +	}
> > > +
> > > +	saved = read_reg(surf);
> > > +	next = saved;
> > > +
> > > +	imr_save = read_reg(imr);
> > > +	ier_save = read_reg(ier);
> > > +	write_reg(ier, ier_save & ~bit);
> > > +	write_reg(imr, imr_save & ~bit);
> > > +
> > > +	while (!quit) {
> > > +		while (!quit) {
> > > +			dsl1 = read_reg(dsl);
> > > +			field1 = dsl1 & 0x80000000;
> > > +			dsl1 &= ~0x80000000;
> > > +			if (dsl1 == target_scanline)
> > > +				break;
> > > +		}
> > > +
> > > +		write_reg(iir, bit);
> > > +		if (next == saved)
> > > +			next = saved+256*1024;
> > > +		else
> > > +			next = saved;
> > > +		write_reg(surf, next);
> > > +
> > > +		while (!quit) {
> > > +			iir2 = read_reg(iir);
> > > +			dsl2 = read_reg(dsl);
> > > +
> > > +			field2 = dsl2 & 0x80000000;
> > > +			dsl2 &= ~0x80000000;
> > > +
> > > +			if (iir2 & bit)
> > > +				break;
> > > +		}
> > > +
> > > +		write_reg(iir, bit);
> > > +
> > > +		if (field1 != field2)
> > > +			printf("fields are different (%u:%u -> %u:%u)\n",
> > > +			       field1, dsl1, field2, dsl2);
> > > +
> > > +		min[field1*count+i[field1]] = dsl1;
> > > +		max[field1*count+i[field1]] = dsl2;
> > > +		if (++i[field1] >= count)
> > > +			break;
> > > +	}
> > > +
> > > +	write_reg(surf, saved);
> > > +	write_reg(imr, imr_save);
> > > +	write_reg(ier, ier_save);
> > > +}
> > > +
> > >  static void poll_dsl_surflive(uint32_t devid, int pipe,
> > >  			      uint32_t *min, uint32_t *max, const int count)
> > >  {
> > > @@ -933,6 +1088,12 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
> > >  	case TEST_FLIP:
> > >  		snprintf(str, sizeof str, "%s / pipe %c / Flip", type, pipe_name(pipe));
> > >  		return str;
> > > +	case TEST_FLIPDONE_PIPESTAT:
> > > +		snprintf(str, sizeof str, "%s / pipe %c / Flip done (vlv/chv)", type, pipe_name(pipe));
> > > +		return str;
> > > +	case TEST_FLIPDONE_DEIIR:
> > > +		snprintf(str, sizeof str, "%s / pipe %c / Flip done (pch)", type, pipe_name(pipe));
> > > +		return str;
> > >  	case TEST_SURFLIVE:
> > >  		snprintf(str, sizeof str, "%s / pipe %c / Surflive", type, pipe_name(pipe));
> > >  		return str;
> > > @@ -950,7 +1111,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
> > >  static void __attribute__((noreturn)) usage(const char *name)
> > >  {
> > >  	fprintf(stderr, "Usage: %s [options]\n"
> > > -		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|surflive|wrap|field>\n"
> > > +		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|flipdone|surflive|wrap|field>\n"
> > >  		" -p,--pipe <pipe>\n"
> > >  		" -b,--bit <bit>\n"
> > >  		" -l,--line <target scanline/pixel>\n"
> > > @@ -1002,6 +1163,8 @@ int main(int argc, char *argv[])
> > >  				test = TEST_PAN;
> > >  			else if (!strcmp(optarg, "flip"))
> > >  				test = TEST_FLIP;
> > > +			else if (!strcmp(optarg, "flipdone"))
> > > +				test = TEST_FLIPDONE;
> > >  			else if (!strcmp(optarg, "surflive"))
> > >  				test = TEST_SURFLIVE;
> > >  			else if (!strcmp(optarg, "wrap"))
> > > @@ -1117,6 +1280,16 @@ int main(int argc, char *argv[])
> > >  		case TEST_FRAMECOUNT:
> > >  			test = TEST_FRAMECOUNT_G4X;
> > >  			break;
> > > +		case TEST_FLIPDONE:
> > > +			/*
> > > +			 * g4x has no apparent "flip done" interrupt,
> > > +			 * and the "flip pending" interrupt does not
> > > +			 * seem to do anything with mmio flips.
> > > +			 */
> > > +			if (IS_G4X(devid))
> > > +				usage(argv[0]);
> > > +			test = TEST_FLIPDONE_PIPESTAT;
> > > +			break;
> > >  		case TEST_FLIPCOUNT:
> > >  		case TEST_PIPESTAT:
> > >  		case TEST_PAN:
> > > @@ -1146,6 +1319,9 @@ int main(int argc, char *argv[])
> > >  		case TEST_FRAMECOUNT:
> > >  			test = TEST_FRAMECOUNT_G4X;
> > >  			break;
> > > +		case TEST_FLIPDONE:
> > > +			test = TEST_FLIPDONE_DEIIR;
> > > +			break;
> > >  		case TEST_FLIPCOUNT:
> > >  		case TEST_PAN:
> > >  		case TEST_FLIP:
> > > @@ -1161,6 +1337,7 @@ int main(int argc, char *argv[])
> > >  	switch (test) {
> > >  	case TEST_IIR:
> > >  	case TEST_FRAMECOUNT:
> > > +	case TEST_FLIPDONE:
> > >  		/* should no longer have the generic tests here */
> > >  		assert(0);
> > >  	default:
> > > @@ -1226,6 +1403,14 @@ int main(int argc, char *argv[])
> > >  			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
> > >  				      min, max, count);
> > >  		break;
> > > +	case TEST_FLIPDONE_PIPESTAT:
> > > +		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
> > > +					   min, max, count);
> > > +		break;
> > > +	case TEST_FLIPDONE_DEIIR:
> > > +		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
> > > +					min, max, count);
> > > +		break;
> > >  	case TEST_SURFLIVE:
> > >  		poll_dsl_surflive(devid, pipe, min, max, count);
> > >  		break;
> > > -- 
> > > 2.19.1
> > > 
> > > _______________________________________________
> > > igt-dev mailing list
> > > igt-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/igt-dev
> > _______________________________________________
> > igt-dev mailing list
> > igt-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/igt-dev
> 
> -- 
> Ville Syrjälä
> Intel
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 13/14] tools/intel_display_poller: Add vrr-wrap test

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:46PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The VRR_STATUS2 registers contains yet anoher scanline counter.
> Let's add a test to check when it wraps.
> 
> Not sure this is actually useful. A better way might be to
> allow wholesale replacement of the normal scanline counter
> register with the VRR STATUS2? Not sure we care about this
> register at all actually.

Why do we need this test? This vertical scanline counter is just used
to issue flip on a particular scanline mostly used for HW debug.
How did you use the wrap test for testing VRR?

Manasi

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  tools/intel_display_poller.c | 43 ++++++++++++++++++++++++++++++------
>  1 file changed, 36 insertions(+), 7 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 37383dc8..6c417050 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -59,6 +59,7 @@ enum test {
>  	TEST_FLIPDONE_DEIIR,
>  	TEST_SURFLIVE,
>  	TEST_WRAP,
> +	TEST_VRR_WRAP,
>  	TEST_FIELD,
>  };
>  
> @@ -1149,16 +1150,14 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
>  	write_reg(surf, saved);
>  }
>  
> -static void poll_dsl_wrap(uint32_t devid, int pipe,
> -			  uint32_t *min, uint32_t *max, const int count,
> -			  int vrr_push_scanline)
> +static void _poll_dsl_wrap(uint32_t devid, int pipe,
> +			   uint32_t *min, uint32_t *max, const int count,
> +			   int vrr_push_scanline, uint32_t dsl)
>  {
> -	uint32_t dsl, dsl1, dsl2;
> +	uint32_t dsl1, dsl2;
>  	bool field1, field2;
>  	int i[2] = {};
>  
> -	dsl = PIPE_REG(pipe, PIPEA_DSL);
> -
>  	while (!quit) {
>  		push_vrr(devid, pipe, vrr_push_scanline);
>  
> @@ -1186,6 +1185,24 @@ static void poll_dsl_wrap(uint32_t devid, int pipe,
>  	}
>  }
>  
> +static void poll_dsl_wrap(uint32_t devid,
> +			  int pipe, uint32_t *min, uint32_t *max, const int count,
> +			  int vrr_push_scanline)
> +{
> +	return _poll_dsl_wrap(devid, pipe, min, max, count,
> +			      vrr_push_scanline,
> +			      PIPE_REG(pipe, PIPEA_DSL));
> +}
> +
> +static void poll_vrr_wrap(uint32_t devid,
> +			  int pipe, uint32_t *min, uint32_t *max, const int count,
> +			  int vrr_push_scanline)
> +{
> +	return _poll_dsl_wrap(devid, pipe, min, max, count,
> +			      vrr_push_scanline,
> +			      trans_reg(devid, pipe, TRANS_VRR_STATUS2_A));
> +}
> +
>  static void poll_dsl_field(int pipe, uint32_t *min, uint32_t *max, const int count)
>  {
>  	uint32_t dsl, dsl1, dsl2;
> @@ -1267,6 +1284,9 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  	case TEST_FIELD:
>  		snprintf(str, sizeof str, "%s / pipe %c / Field", type, pipe_name(pipe));
>  		return str;
> +	case TEST_VRR_WRAP:
> +		snprintf(str, sizeof str, "%s / pipe %c / VRR wrap", type, pipe_name(pipe));
> +		return str;
>  	default:
>  		return "";
>  	}
> @@ -1275,7 +1295,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  static void __attribute__((noreturn)) usage(const char *name)
>  {
>  	fprintf(stderr, "Usage: %s [options]\n"
> -		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field>\n"
> +		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field|vrr-wrap>\n"
>  		" -p,--pipe <pipe>\n"
>  		" -b,--bit <bit>\n"
>  		" -l,--line <target scanline/pixel>\n"
> @@ -1345,6 +1365,8 @@ int main(int argc, char *argv[])
>  				test = TEST_WRAP;
>  			else if (!strcmp(optarg, "field"))
>  				test = TEST_FIELD;
> +			else if (!strcmp(optarg, "vrr-wrap"))
> +				test = TEST_VRR_WRAP;
>  			else
>  				usage(argv[0]);
>  			break;
> @@ -1527,6 +1549,10 @@ int main(int argc, char *argv[])
>  		case TEST_FLIPDONE:
>  			test = TEST_FLIPDONE_DEIIR;
>  			break;
> +		case TEST_VRR_WRAP:
> +			if (intel_gen(devid) < 11)
> +				usage(argv[0]);
> +			break;
>  		case TEST_FLIPCOUNT:
>  		case TEST_PAN:
>  		case TEST_FLIP:
> @@ -1638,6 +1664,9 @@ int main(int argc, char *argv[])
>  	case TEST_FIELD:
>  		poll_dsl_field(pipe, min, max, count);
>  		break;
> +	case TEST_VRR_WRAP:
> +		poll_vrr_wrap(devid, pipe, min, max, count, vrr_push_scanline);
> +		break;
>  	default:
>  		assert(0);
>  	}
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 01/14] tools/intel_display_poller: Fix TILEOFF vs. LINOFF for skl+

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:34PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> skl+ (like hsw/bdw) always use the TILEOFF register, and never
> the LINOFF register. Let's respect that.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index f4797a20..15da8e76 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -128,9 +128,9 @@ static uint32_t dspoffset_reg(uint32_t devid, int pipe)
>  	bool use_tileoff;
>  	int plane = pipe_to_plane(devid, pipe);
>  
> -	if (IS_GEN2(devid) || IS_GEN3(devid))
> +	if (intel_gen(devid) < 4)
>  		use_tileoff = false;
> -	else if (IS_HASWELL(devid) || IS_BROADWELL(devid))
> +	else if (IS_HASWELL(devid) || IS_BROADWELL(devid) || intel_gen(devid) >= 9)
>  		use_tileoff = true;
>  	else
>  		use_tileoff = read_reg(PIPE_REG(plane, DSPACNTR)) & DISPLAY_PLANE_TILED;
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 02/14] tools/intel_display_poller: Unify ilk+ and bdw+ codepaths

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:35PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The ilk+ and bdw+ codepaths are identical, except for the ilk/snb
> pipe C check. Unify them.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Cleanup looks good to me

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 26 +-------------------------
>  1 file changed, 1 insertion(+), 25 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 15da8e76..bb115598 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -1128,8 +1128,7 @@ int main(int argc, char *argv[])
>  		default:
>  			usage(argv[0]);
>  		}
> -	} else if (HAS_PCH_SPLIT(devid) &&
> -		   (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))) {
> +	} else {
>  		if (pipe > 1 &&
>  		    (IS_GEN5(devid) || IS_GEN6(devid)))
>  			usage(argv[0]);
> @@ -1154,29 +1153,6 @@ int main(int argc, char *argv[])
>  		default:
>  			usage(argv[0]);
>  		}
> -	} else if (intel_gen(devid) >= 8) {
> -		if (test_pixelcount)
> -			usage(argv[0]);
> -
> -		switch (test) {
> -		case TEST_IIR:
> -			test = TEST_DEIIR;
> -			break;
> -		case TEST_FRAMECOUNT:
> -			test = TEST_FRAMECOUNT_G4X;
> -			break;
> -		case TEST_FLIPCOUNT:
> -		case TEST_PAN:
> -		case TEST_FLIP:
> -		case TEST_SURFLIVE:
> -		case TEST_WRAP:
> -		case TEST_FIELD:
> -			break;
> -		default:
> -			usage(argv[0]);
> -		}
> -	} else {
> -		usage(argv[0]);
>  	}
>  
>  	switch (test) {
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 09/14] tools/intel_display_poller: Extract wait_scanline()

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:42PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pull the code to wait for a specific scanline to a helper.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 69 ++++++++++++------------------------
>  1 file changed, 23 insertions(+), 46 deletions(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index d6a77d35..260818db 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -173,6 +173,21 @@ static void enable_async_flip(uint32_t devid, int pipe, bool enable)
>  	write_reg(PIPE_REG(plane, DSPACNTR), tmp);
>  }
>  
> +static int wait_scanline(int pipe, int target_scanline, bool *field)
> +{
> +	uint32_t dsl_reg = PIPE_REG(pipe, PIPEA_DSL);
> +
> +	while (!quit) {
> +		uint32_t dsl = read_reg(dsl_reg);
> +		*field = dsl & 0x80000000;
> +		dsl &= ~0x80000000;
> +		if (dsl == target_scanline)
> +			return dsl;
> +	}
> +
> +	return 0;
> +}
> +
>  static void poll_pixel_pipestat(int pipe, int bit, uint32_t *min, uint32_t *max, const int count)
>  {
>  	uint32_t pix, pix1, pix2, iir, iir1, iir2, iir_bit, iir_mask;
> @@ -720,34 +735,21 @@ static void poll_dsl_framecount_gen3(int pipe, uint32_t *min, uint32_t *max, con
>  static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
>  			 uint32_t *min, uint32_t *max, const int count)
>  {
> -	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> +	uint32_t dsl1 = 0, dsl2 = 0;
>  	bool field1 = false, field2 = false;
>  	uint32_t saved, surf = 0;
>  	int i[2] = {};
>  
> -	dsl = PIPE_REG(pipe, PIPEA_DSL);
>  	surf = dspoffset_reg(devid, pipe);
>  
>  	saved = read_reg(surf);
>  
>  	while (!quit) {
> -		while (!quit) {
> -			dsl1 = read_reg(dsl);
> -			field1 = dsl1 & 0x80000000;
> -			dsl1 &= ~0x80000000;
> -			if (dsl1 == target_scanline)
> -				break;
> -		}
> +		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		write_reg(surf, saved+256);
>  
> -		while (!quit) {
> -			dsl2 = read_reg(dsl);
> -			field2 = dsl1 & 0x80000000;
> -			dsl2 &= ~0x80000000;
> -			if (dsl2 == target_scanline + target_fuzz)
> -				break;
> -		}
> +		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
>  
>  		write_reg(surf, saved);
>  
> @@ -767,12 +769,11 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
>  static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
>  			  uint32_t *min, uint32_t *max, const int count, bool async)
>  {
> -	uint32_t dsl, dsl1 = 0, dsl2 = 0;
> +	uint32_t dsl1 = 0, dsl2 = 0;
>  	bool field1 = false, field2 = false;
>  	uint32_t saved, surf = 0;
>  	int i[2] = {};
>  
> -	dsl = PIPE_REG(pipe, PIPEA_DSL);
>  	surf = dspsurf_reg(devid, pipe, async);
>  
>  	saved = read_reg(surf);
> @@ -780,23 +781,11 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
>  	enable_async_flip(devid, pipe, async);
>  
>  	while (!quit) {
> -		while (!quit) {
> -			dsl1 = read_reg(dsl);
> -			field1 = dsl1 & 0x80000000;
> -			dsl1 &= ~0x80000000;
> -			if (dsl1 == target_scanline)
> -				break;
> -		}
> +		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		write_reg(surf, saved+256*1024);
>  
> -		while (!quit) {
> -			dsl2 = read_reg(dsl);
> -			field2 = dsl1 & 0x80000000;
> -			dsl2 &= ~0x80000000;
> -			if (dsl2 == target_scanline + target_fuzz)
> -				break;
> -		}
> +		dsl2 = wait_scanline(pipe, target_scanline + target_fuzz, &field2);
>  
>  		write_reg(surf, saved);
>  
> @@ -839,13 +828,7 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
>  	enable_async_flip(devid, pipe, async);
>  
>  	while (!quit) {
> -		while (!quit) {
> -			dsl1 = read_reg(dsl);
> -			field1 = dsl1 & 0x80000000;
> -			dsl1 &= ~0x80000000;
> -			if (dsl1 == target_scanline)
> -				break;
> -		}
> +		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		write_reg(pipestat, pipestat1 | bit);
>  		if (next == saved)
> @@ -928,13 +911,7 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
>  	enable_async_flip(devid, pipe, async);
>  
>  	while (!quit) {
> -		while (!quit) {
> -			dsl1 = read_reg(dsl);
> -			field1 = dsl1 & 0x80000000;
> -			dsl1 &= ~0x80000000;
> -			if (dsl1 == target_scanline)
> -				break;
> -		}
> +		dsl1 = wait_scanline(pipe, target_scanline, &field1);
>  
>  		write_reg(iir, bit);
>  		if (next == saved)
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 08/14] lib: Add timestmap registers

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:41PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add definitions for the timestamp registers.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  lib/intel_reg.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index d5017f3d..d4045c36 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2294,6 +2294,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>   */
>  #define PIPEAFRMCOUNT_G4X	0x70040
>  #define PIPEAFLIPCOUNT_G4X	0x70044
> +#define PIPEAFRMTMSMTP		0x70048
>  /*
>   * Computing GMCH M and N values.
>   *
> @@ -2801,6 +2802,8 @@ typedef enum {
>  #define MCHBAR_RENDER_STANDBY	0x111B8
>  #define RENDER_STANDBY_ENABLE	(1 << 30)
>  
> +#define ILK_TIMESTAMP_HI        0x70070
> +#define IVB_TIMESTAMP_CTR       0x44070
>  
>  /* Ironlake */
>  
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 10/14] tools/intel_display_poller: Add frame timestamp tests

[Navare, Manasi]

On Mon, Mar 01, 2021 at 12:37:43PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a couple of new test modes to verify how frame timestamps
> work.
> * frametimestamp determines on which scanline the frame
>   timestamp is sampled
> * timestamp returns the difference between the current timestamp
>   on a specific scanline from the last sampled frame timestamp.
>   This can be used to determine if the timestamp ticks at the
>   expected rate.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  tools/intel_display_poller.c | 103 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 102 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index 260818db..ae3f993f 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -49,6 +49,8 @@ enum test {
>  	TEST_FRAMECOUNT,
>  	TEST_FRAMECOUNT_GEN3,
>  	TEST_FRAMECOUNT_G4X,
> +	TEST_FRAMETIMESTAMP,
> +	TEST_TIMESTAMP,
>  	TEST_FLIPCOUNT,
>  	TEST_PAN,
>  	TEST_FLIP,
> @@ -732,6 +734,80 @@ static void poll_dsl_framecount_gen3(int pipe, uint32_t *min, uint32_t *max, con
>  	}
>  }
>  
> +
> +static void poll_dsl_frametimestamp(uint32_t devid, int pipe,
> +				    uint32_t *min, uint32_t *max, const int count)
> +{
> +	uint32_t dsl, dsl1, dsl2, frm, frm1, frm2;
> +	bool field1, field2;
> +	int i[2] = {};
> +
> +	frm = PIPE_REG(pipe, PIPEAFRMTMSMTP);
> +	dsl = PIPE_REG(pipe, PIPEA_DSL);
> +
> +	while (!quit) {
> +		while (!quit) {
> +			dsl1 = read_reg(dsl);
> +			frm1 = read_reg(frm);
> +			frm2 = read_reg(frm);
> +			dsl2 = read_reg(dsl);
> +
> +			field1 = dsl1 & 0x80000000;
> +			field2 = dsl2 & 0x80000000;
> +			dsl1 &= ~0x80000000;
> +			dsl2 &= ~0x80000000;
> +
> +			if (frm1 != frm2)
> +				break;
> +		}
> +
> +		if (field1 != field2)
> +			printf("fields are different (%u:%u -> %u:%u)\n",
> +			       field1, dsl1, field2, dsl2);
> +
> +		min[field1*count+i[field1]] = dsl1;
> +		max[field1*count+i[field1]] = dsl2;
> +		if (++i[field1] >= count)
> +			break;
> +	}
> +}
> +
> +static uint32_t timestamp_reg(uint32_t devid)
> +{
> +	if (intel_gen(devid) >= 7)
> +		return IVB_TIMESTAMP_CTR;
> +	else if (intel_gen(devid) >= 5)
> +		return ILK_TIMESTAMP_HI;
> +	else
> +		return TIMESTAMP_QW + 4;
> +}
> +
> +static void poll_dsl_timestamp(uint32_t devid, int pipe, int target_scanline,
> +			       uint32_t *min, uint32_t *max, const int count)
> +{
> +	uint32_t dsl1, frm, frm1, ts, ts1;
> +	bool field1;
> +	int i[2] = {};
> +
> +	ts = timestamp_reg(devid);
> +	frm = PIPE_REG(pipe, PIPEAFRMTMSMTP);
> +
> +	while (!quit) {
> +		dsl1 = wait_scanline(pipe, target_scanline, &field1);
> +
> +		frm1 = read_reg(frm);
> +		ts1 = read_reg(ts);
> +
> +		field1 = dsl1 & 0x80000000;
> +		dsl1 &= ~0x80000000;
> +
> +		min[field1*count+i[field1]] = dsl1;
> +		max[field1*count+i[field1]] = ts1 - frm1;
> +		if (++i[field1] >= count)
> +			break;
> +	}
> +}
> +
>  static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
>  			 uint32_t *min, uint32_t *max, const int count)
>  {
> @@ -1087,6 +1163,12 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  	case TEST_FRAMECOUNT_G4X:
>  		snprintf(str, sizeof str, "%s / pipe %c / Frame count (g4x+)", type, pipe_name(pipe));
>  		return str;
> +	case TEST_FRAMETIMESTAMP:
> +		snprintf(str, sizeof str, "%s / pipe %c / Frame timestamp", type, pipe_name(pipe));
> +		return str;
> +	case TEST_TIMESTAMP:
> +		snprintf(str, sizeof str, "%s / pipe %c / Timestamp", type, pipe_name(pipe));
> +		return str;
>  	case TEST_FLIPCOUNT:
>  		snprintf(str, sizeof str, "%s / pipe %c / Flip count (g4x+)", type, pipe_name(pipe));
>  		return str;
> @@ -1119,7 +1201,7 @@ static const char *test_name(enum test test, int pipe, int bit, bool test_pixel_
>  static void __attribute__((noreturn)) usage(const char *name)
>  {
>  	fprintf(stderr, "Usage: %s [options]\n"
> -		" -t,--test <pipestat|iir|framecount|flipcount|pan|flip|flipdone|surflive|wrap|field>\n"
> +		" -t,--test <pipestat|iir|framecount|flipcount|frametimestamp|timestamp|pan|flip|flipdone|surflive|wrap|field>\n"
>  		" -p,--pipe <pipe>\n"
>  		" -b,--bit <bit>\n"
>  		" -l,--line <target scanline/pixel>\n"
> @@ -1170,6 +1252,10 @@ int main(int argc, char *argv[])
>  				test = TEST_FRAMECOUNT;
>  			else if (!strcmp(optarg, "flipcount"))
>  				test = TEST_FLIPCOUNT;
> +			else if (!strcmp(optarg, "frametimestamp"))
> +				test = TEST_FRAMETIMESTAMP;
> +			else if (!strcmp(optarg, "timestamp"))
> +				test = TEST_TIMESTAMP;
>  			else if (!strcmp(optarg, "pan"))
>  				test = TEST_PAN;
>  			else if (!strcmp(optarg, "flip"))
> @@ -1318,6 +1404,11 @@ int main(int argc, char *argv[])
>  		case TEST_WRAP:
>  		case TEST_FIELD:
>  			break;
> +		case TEST_FRAMETIMESTAMP:
> +		case TEST_TIMESTAMP:
> +			if (!IS_G4X(devid))
> +				usage(argv[0]);
> +			break;
>  		default:
>  			usage(argv[0]);
>  		}
> @@ -1348,6 +1439,8 @@ int main(int argc, char *argv[])
>  		case TEST_SURFLIVE:
>  		case TEST_WRAP:
>  		case TEST_FIELD:
> +		case TEST_TIMESTAMP:
> +		case TEST_FRAMETIMESTAMP:
>  			break;
>  		default:
>  			usage(argv[0]);
> @@ -1403,6 +1496,14 @@ int main(int argc, char *argv[])
>  		assert(!test_pixelcount);
>  		poll_dsl_framecount_g4x(pipe, min, max, count);
>  		break;
> +	case TEST_FRAMETIMESTAMP:
> +		assert(!test_pixelcount);
> +		poll_dsl_frametimestamp(devid, pipe, min, max, count);
> +		break;
> +	case TEST_TIMESTAMP:
> +		assert(!test_pixelcount);
> +		poll_dsl_timestamp(devid, pipe, target_scanline, min, max, count);
> +		break;
>  	case TEST_FLIPCOUNT:
>  		assert(!test_pixelcount);
>  		poll_dsl_flipcount_g4x(devid, pipe, min, max, count);
> -- 
> 2.19.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 06/14] tools/intel_display_poller: Add async flip test mode

[Karthik B S]

On 3/2/2021 2:07 AM, Navare, Manasi D wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Test various things using mmio async flips. These are present since
> g4x, except g4x does not seem to have a working flipdone interrupt.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   lib/intel_reg.h              |  3 ++
>   tools/intel_display_poller.c | 83 +++++++++++++++++++++++++++---------
>   2 files changed, 66 insertions(+), 20 deletions(-)
>
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index ac1fc6cb..7b543109 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2330,6 +2330,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>   
>   #define PIPEEDPCONF		0x7F008
>   
> +#define DSPAADDR_VLV		0x7017C /* vlv/chv */
> +#define DSPBADDR_VLV		0x7117C /* vlv/chv */
> +#define DSPCADDR_CHV		0x7417C /* chv */
>   #define DSPACNTR		0x70180
>   #define DSPBCNTR		0x71180
>   #define DSPCCNTR		0x72180
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index be237221..d6a77d35 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -144,16 +144,35 @@ static uint32_t dspoffset_reg(uint32_t devid, int pipe)
>   		return PIPE_REG(plane, DSPABASE);
>   }
>   
> -static uint32_t dspsurf_reg(uint32_t devid, int pipe)
> +static uint32_t dspsurf_reg(uint32_t devid, int pipe, bool async)
>   {
>   	int plane = pipe_to_plane(devid, pipe);
>   
> +	if (async && (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)))
> +		return PIPE_REG(plane, DSPAADDR_VLV);
> +

Hi,

Would this be correct when we try async flip on Pipe C on CHV? It would 
return 0x7217C whereas the required return is 0x7417C? Please correct me 
if I'm missing something here.

Other than the above mentioned open, the patch looks good to me.

Thanks,
Karthik.B.S
>   	if (intel_gen(devid) < 4)
>   		return PIPE_REG(plane, DSPABASE);
>   	else
>   		return PIPE_REG(plane, DSPASURF);
>   }
>   
> +static void enable_async_flip(uint32_t devid, int pipe, bool enable)
> +{
> +	int plane = pipe_to_plane(devid, pipe);
> +	uint32_t tmp;
> +
> +	if (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid))
> +		return;
> +
> +	tmp = read_reg(PIPE_REG(plane, DSPACNTR));
> +	if (enable)
> +		tmp |= 1 << 9;
> +	else
> +		tmp &= ~(1 << 9);
> +	write_reg(PIPE_REG(plane, DSPACNTR), tmp);
> +}
> +
>   static void poll_pixel_pipestat(int pipe, int bit, uint32_t *min, uint32_t *max, const int count)
>   {
>   	uint32_t pix, pix1, pix2, iir, iir1, iir2, iir_bit, iir_mask;
> @@ -307,7 +326,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ
>   	int i = 0;
>   
>   	pix = PIPE_REG(pipe, PIPEAFRAMEPIXEL);
> -	surf = dspsurf_reg(devid, pipe);
> +	surf = dspsurf_reg(devid, pipe, false);
>   
>   	saved = read_reg(surf);
>   
> @@ -318,7 +337,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ
>   				break;
>   		}
>   
> -		write_reg(surf, saved+128*1024);
> +		write_reg(surf, saved+256*1024);
>   
>   		while (!quit){
>   			pix2 = read_reg(pix) & PIPE_PIXEL_MASK;
> @@ -613,7 +632,7 @@ static void poll_dsl_flipcount_g4x(uint32_t devid, int pipe,
>   
>   	flp = PIPE_REG(pipe, PIPEAFLIPCOUNT_G4X);
>   	dsl = PIPE_REG(pipe, PIPEA_DSL);
> -	surf = dspsurf_reg(devid, pipe);
> +	surf = dspsurf_reg(devid, pipe, false);
>   
>   	while (!quit) {
>   		usleep(10);
> @@ -746,7 +765,7 @@ static void poll_dsl_pan(uint32_t devid, int pipe, int target_scanline, int targ
>   }
>   
>   static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> -			  uint32_t *min, uint32_t *max, const int count)
> +			  uint32_t *min, uint32_t *max, const int count, bool async)
>   {
>   	uint32_t dsl, dsl1 = 0, dsl2 = 0;
>   	bool field1 = false, field2 = false;
> @@ -754,10 +773,12 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
>   	int i[2] = {};
>   
>   	dsl = PIPE_REG(pipe, PIPEA_DSL);
> -	surf = dspsurf_reg(devid, pipe);
> +	surf = dspsurf_reg(devid, pipe, async);
>   
>   	saved = read_reg(surf);
>   
> +	enable_async_flip(devid, pipe, async);
> +
>   	while (!quit) {
>   		while (!quit) {
>   			dsl1 = read_reg(dsl);
> @@ -767,7 +788,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
>   				break;
>   		}
>   
> -		write_reg(surf, saved+128*1024);
> +		write_reg(surf, saved+256*1024);
>   
>   		while (!quit) {
>   			dsl2 = read_reg(dsl);
> @@ -789,11 +810,12 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar
>   			break;
>   	}
>   
> +	enable_async_flip(devid, pipe, false);
>   	write_reg(surf, saved);
>   }
>   
>   static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> -				       uint32_t *min, uint32_t *max, const int count)
> +				       uint32_t *min, uint32_t *max, const int count, bool async)
>   {
>   	uint32_t dsl, dsl1 = 0, dsl2 = 0;
>   	uint32_t pipestat, pipestat1, pipestat2, pipestat_save;
> @@ -803,7 +825,7 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
>   
>   	dsl = PIPE_REG(pipe, PIPEA_DSL);
>   	pipestat = PIPE_REG(pipe, PIPEASTAT);
> -	surf = dspsurf_reg(devid, pipe);
> +	surf = dspsurf_reg(devid, pipe, async);
>   
>   	bit = 1 << 10;
>   
> @@ -814,6 +836,8 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
>   	pipestat1 = pipestat_save & ~(1 << (bit<<16));
>   	write_reg(pipestat, pipestat1 | bit);
>   
> +	enable_async_flip(devid, pipe, async);
> +
>   	while (!quit) {
>   		while (!quit) {
>   			dsl1 = read_reg(dsl);
> @@ -853,12 +877,13 @@ static void poll_dsl_flipdone_pipestat(uint32_t devid, int pipe, int target_scan
>   			break;
>   	}
>   
> +	enable_async_flip(devid, pipe, false);
>   	write_reg(surf, saved);
>   	write_reg(pipestat, pipestat_save);
>   }
>   
>   static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanline, int target_fuzz,
> -				    uint32_t *min, uint32_t *max, const int count)
> +				    uint32_t *min, uint32_t *max, const int count, bool async)
>   {
>   	uint32_t dsl, dsl1 = 0, dsl2 = 0;
>   	uint32_t iir, iir2, ier, imr;
> @@ -868,7 +893,7 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
>   	int i[2] = {};
>   
>   	dsl = PIPE_REG(pipe, PIPEA_DSL);
> -	surf = dspsurf_reg(devid, pipe);
> +	surf = dspsurf_reg(devid, pipe, async);
>   
>   	if (intel_gen(devid) >= 9)
>   		bit = 3;
> @@ -900,6 +925,8 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
>   	write_reg(ier, ier_save & ~bit);
>   	write_reg(imr, imr_save & ~bit);
>   
> +	enable_async_flip(devid, pipe, async);
> +
>   	while (!quit) {
>   		while (!quit) {
>   			dsl1 = read_reg(dsl);
> @@ -939,13 +966,14 @@ static void poll_dsl_flipdone_deiir(uint32_t devid, int pipe, int target_scanlin
>   			break;
>   	}
>   
> +	enable_async_flip(devid, pipe, false);
>   	write_reg(surf, saved);
>   	write_reg(imr, imr_save);
>   	write_reg(ier, ier_save);
>   }
>   
>   static void poll_dsl_surflive(uint32_t devid, int pipe,
> -			      uint32_t *min, uint32_t *max, const int count)
> +			      uint32_t *min, uint32_t *max, const int count, bool async)
>   {
>   	uint32_t dsl, dsl1 = 0, dsl2 = 0, surf, surf1, surf2, surflive, surfl1 = 0, surfl2, saved, tmp;
>   	bool field1 = false, field2 = false;
> @@ -953,12 +981,14 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
>   
>   	surflive = PIPE_REG(pipe, DSPASURFLIVE);
>   	dsl = PIPE_REG(pipe, PIPEA_DSL);
> -	surf = dspsurf_reg(devid, pipe);
> +	surf = dspsurf_reg(devid, pipe, async);
>   
>   	saved = read_reg(surf);
>   
>   	surf1 = saved & ~0xfff;
> -	surf2 = surf1 + 128*1024;
> +	surf2 = surf1 + 256*1024;
> +
> +	enable_async_flip(devid, pipe, async);
>   
>   	while (!quit) {
>   		write_reg(surf, surf2);
> @@ -994,6 +1024,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe,
>   		surf2 = tmp;
>   	}
>   
> +	enable_async_flip(devid, pipe, false);
>   	write_reg(surf, saved);
>   }
>   
> @@ -1116,7 +1147,8 @@ static void __attribute__((noreturn)) usage(const char *name)
>   		" -b,--bit <bit>\n"
>   		" -l,--line <target scanline/pixel>\n"
>   		" -f,--fuzz <target fuzz>\n"
> -		" -x,--pixel\n",
> +		" -x,--pixel\n"
> +		" -a,--async\n",
>   		name);
>   	exit(1);
>   }
> @@ -1127,6 +1159,7 @@ int main(int argc, char *argv[])
>   	int i;
>   	int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1;
>   	bool test_pixelcount = false;
> +	bool test_async_flip = false;
>   	uint32_t devid;
>   	uint32_t min[2*128] = {};
>   	uint32_t max[2*128] = {};
> @@ -1142,10 +1175,11 @@ int main(int argc, char *argv[])
>   			{ .name = "line", .has_arg = required_argument, },
>   			{ .name = "fuzz", .has_arg = required_argument, },
>   			{ .name = "pixel", .has_arg = no_argument, },
> +			{ .name = "async", .has_arg = no_argument, },
>   			{ },
>   		};
>   
> -		int opt = getopt_long(argc, argv, "t:p:b:l:f:x", long_options, NULL);
> +		int opt = getopt_long(argc, argv, "t:p:b:l:f:xa", long_options, NULL);
>   		if (opt == -1)
>   			break;
>   
> @@ -1207,6 +1241,9 @@ int main(int argc, char *argv[])
>   		case 'x':
>   			test_pixelcount = true;
>   			break;
> +		case 'a':
> +			test_async_flip = true;
> +			break;
>   		}
>   	}
>   
> @@ -1223,6 +1260,9 @@ int main(int argc, char *argv[])
>   		if (test_pixelcount)
>   			usage(argv[0]);
>   
> +		if (test_async_flip)
> +			usage(argv[0]);
> +
>   		switch (test) {
>   		case TEST_IIR:
>   			test = TEST_IIR_GEN2;
> @@ -1240,6 +1280,9 @@ int main(int argc, char *argv[])
>   		if (pipe > 1)
>   			usage(argv[0]);
>   
> +		if (test_async_flip)
> +			usage(argv[0]);
> +
>   		switch (test) {
>   		case TEST_IIR:
>   			test = TEST_IIR_GEN3;
> @@ -1401,18 +1444,18 @@ int main(int argc, char *argv[])
>   					min, max, count);
>   		else
>   			poll_dsl_flip(devid, pipe, target_scanline, target_fuzz,
> -				      min, max, count);
> +				      min, max, count, test_async_flip);
>   		break;
>   	case TEST_FLIPDONE_PIPESTAT:
>   		poll_dsl_flipdone_pipestat(devid, pipe, target_scanline, target_fuzz,
> -					   min, max, count);
> +					   min, max, count, test_async_flip);
>   		break;
>   	case TEST_FLIPDONE_DEIIR:
>   		poll_dsl_flipdone_deiir(devid, pipe, target_scanline, target_fuzz,
> -					min, max, count);
> +					min, max, count, test_async_flip);
>   		break;
>   	case TEST_SURFLIVE:
> -		poll_dsl_surflive(devid, pipe, min, max, count);
> +		poll_dsl_surflive(devid, pipe, min, max, count, test_async_flip);
>   		break;
>   	case TEST_WRAP:
>   		if (test_pixelcount)


_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH i-g-t 06/14] tools/intel_display_poller: Add async flip test mode

[Ville Syrjälä]

On Mon, May 17, 2021 at 12:28:00PM +0530, Karthik B S wrote:
> On 3/2/2021 2:07 AM, Navare, Manasi D wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Test various things using mmio async flips. These are present since
> > g4x, except g4x does not seem to have a working flipdone interrupt.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   lib/intel_reg.h              |  3 ++
> >   tools/intel_display_poller.c | 83 +++++++++++++++++++++++++++---------
> >   2 files changed, 66 insertions(+), 20 deletions(-)
> >
> > diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> > index ac1fc6cb..7b543109 100644
> > --- a/lib/intel_reg.h
> > +++ b/lib/intel_reg.h
> > @@ -2330,6 +2330,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> >   
> >   #define PIPEEDPCONF		0x7F008
> >   
> > +#define DSPAADDR_VLV		0x7017C /* vlv/chv */
> > +#define DSPBADDR_VLV		0x7117C /* vlv/chv */
> > +#define DSPCADDR_CHV		0x7417C /* chv */
> >   #define DSPACNTR		0x70180
> >   #define DSPBCNTR		0x71180
> >   #define DSPCCNTR		0x72180
> > diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> > index be237221..d6a77d35 100644
> > --- a/tools/intel_display_poller.c
> > +++ b/tools/intel_display_poller.c
> > @@ -144,16 +144,35 @@ static uint32_t dspoffset_reg(uint32_t devid, int pipe)
> >   		return PIPE_REG(plane, DSPABASE);
> >   }
> >   
> > -static uint32_t dspsurf_reg(uint32_t devid, int pipe)
> > +static uint32_t dspsurf_reg(uint32_t devid, int pipe, bool async)
> >   {
> >   	int plane = pipe_to_plane(devid, pipe);
> >   
> > +	if (async && (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)))
> > +		return PIPE_REG(plane, DSPAADDR_VLV);
> > +
> 
> Hi,
> 
> Would this be correct when we try async flip on Pipe C on CHV? It would 
> return 0x7217C whereas the required return is 0x7417C? Please correct me 
> if I'm missing something here.

Sorry, forgot to reply to this. This handled through pipe_offset[].

#define PIPE_REG(pipe, reg_a) (pipe_offset[(pipe)] + (reg_a))
...
if (IS_CHERRYVIEW(devid))
	pipe_offset[2] = 0x4000;

-- 
Ville Syrjälä
Intel

Re: [igt-dev] [PATCH i-g-t 06/14] tools/intel_display_poller: Add async flip test mode

[Karthik B S]

On 10/8/2021 7:20 PM, Ville Syrjälä wrote:
> On Mon, May 17, 2021 at 12:28:00PM +0530, Karthik B S wrote:
>> On 3/2/2021 2:07 AM, Navare, Manasi D wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Test various things using mmio async flips. These are present since
>>> g4x, except g4x does not seem to have a working flipdone interrupt.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>>    lib/intel_reg.h              |  3 ++
>>>    tools/intel_display_poller.c | 83 +++++++++++++++++++++++++++---------
>>>    2 files changed, 66 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
>>> index ac1fc6cb..7b543109 100644
>>> --- a/lib/intel_reg.h
>>> +++ b/lib/intel_reg.h
>>> @@ -2330,6 +2330,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>>>    
>>>    #define PIPEEDPCONF		0x7F008
>>>    
>>> +#define DSPAADDR_VLV		0x7017C /* vlv/chv */
>>> +#define DSPBADDR_VLV		0x7117C /* vlv/chv */
>>> +#define DSPCADDR_CHV		0x7417C /* chv */
>>>    #define DSPACNTR		0x70180
>>>    #define DSPBCNTR		0x71180
>>>    #define DSPCCNTR		0x72180
>>> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
>>> index be237221..d6a77d35 100644
>>> --- a/tools/intel_display_poller.c
>>> +++ b/tools/intel_display_poller.c
>>> @@ -144,16 +144,35 @@ static uint32_t dspoffset_reg(uint32_t devid, int pipe)
>>>    		return PIPE_REG(plane, DSPABASE);
>>>    }
>>>    
>>> -static uint32_t dspsurf_reg(uint32_t devid, int pipe)
>>> +static uint32_t dspsurf_reg(uint32_t devid, int pipe, bool async)
>>>    {
>>>    	int plane = pipe_to_plane(devid, pipe);
>>>    
>>> +	if (async && (IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid)))
>>> +		return PIPE_REG(plane, DSPAADDR_VLV);
>>> +
>> Hi,
>>
>> Would this be correct when we try async flip on Pipe C on CHV? It would
>> return 0x7217C whereas the required return is 0x7417C? Please correct me
>> if I'm missing something here.
> Sorry, forgot to reply to this. This handled through pipe_offset[].
>
> #define PIPE_REG(pipe, reg_a) (pipe_offset[(pipe)] + (reg_a))
> ...
> if (IS_CHERRYVIEW(devid))
> 	pipe_offset[2] = 0x4000;
>
Thank you for the clarification. I had missed this condition and only 
checked the definition.

Reviewed-by: Karthik B S <karthik.b.s@intel.com>

Re: [igt-dev] [PATCH i-g-t 13/14] tools/intel_display_poller: Add vrr-wrap test

[Ville Syrjälä]

On Thu, Apr 08, 2021 at 11:03:29AM -0700, Navare, Manasi wrote:
> On Mon, Mar 01, 2021 at 12:37:46PM -0800, Manasi Navare wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The VRR_STATUS2 registers contains yet anoher scanline counter.
> > Let's add a test to check when it wraps.
> > 
> > Not sure this is actually useful. A better way might be to
> > allow wholesale replacement of the normal scanline counter
> > register with the VRR STATUS2? Not sure we care about this
> > register at all actually.
> 
> Why do we need this test? This vertical scanline counter is just used
> to issue flip on a particular scanline mostly used for HW debug.
> How did you use the wrap test for testing VRR?

Hmm. Neglected to answer this one too. The only reason I added this
was to confirm how the VRR_STATUS2 scanline works. IIRC it worked
exactly like the normal DSL register, so we probably don't need this
test.

-- 
Ville Syrjälä
Intel

Re: [igt-dev] [PATCH i-g-t 11/14] tools/intel_display_poller: Rework some loops

[Ville Syrjälä]

On Mon, Mar 01, 2021 at 12:37:44PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rework the structure of some of the loops a bit. This is
> going to help slide VRR support into the tests.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Could someone rb/ack this one so I push the rest?

-- 
Ville Syrjälä
Intel