* [igt-dev] [PATCH i-g-t] i915/perf: Add test to query CS timestamp
@ 2021-03-02 18:30 Umesh Nerlige Ramappa
2021-03-02 19:03 ` [igt-dev] ✗ Fi.CI.BAT: failure for " Patchwork
0 siblings, 1 reply; 2+ messages in thread
From: Umesh Nerlige Ramappa @ 2021-03-02 18:30 UTC (permalink / raw)
To: igt-dev, Lionel G Landwerlin, Tvrtko Ursulin, Chris Wilson
Add tests to query CS timestamps for different engines.
v2:
- remove flag parameter
- assert for minimum usable values rather than maximum
v3:
- use clock id for cpu timestamps (Lionel)
- check if query is supported (Ashutosh)
- test bad queries
v4: (Chris, Tvrtko)
- cs_timestamp is a misnomer, use cs_cycles instead
- use cs cycle frequency returned in the query
- omit size parameter
v5:
- use __for_each_physical_engine (Lionel)
- check for ENODEV (Umesh)
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
include/drm-uapi/i915_drm.h | 43 +++++++++
tests/i915/i915_query.c | 186 ++++++++++++++++++++++++++++++++++++
2 files changed, 229 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index bf9ea471..a29f8578 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2176,6 +2176,10 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
+ /**
+ * Query Command Streamer timestamp register.
+ */
+#define DRM_I915_QUERY_CS_CYCLES 4
/* Must be kept compact -- no holes and well documented */
/*
@@ -2309,6 +2313,45 @@ struct drm_i915_engine_info {
__u64 rsvd1[4];
};
+/**
+ * struct drm_i915_query_cs_cycles
+ *
+ * The query returns the command streamer cycles and the frequency that can be
+ * used to calculate the command streamer timestamp. In addition the query
+ * returns the cpu timestamp that indicates when the command streamer cycle
+ * count was captured.
+ */
+struct drm_i915_query_cs_cycles {
+ /** Engine for which command streamer cycles is queried. */
+ struct i915_engine_class_instance engine;
+
+ /** Must be zero. */
+ __u32 flags;
+
+ /**
+ * Command streamer cycles as read from the command streamer
+ * register at 0x358 offset.
+ */
+ __u64 cs_cycles;
+
+ /** Frequency of the cs cycles in Hz. */
+ __u64 cs_frequency;
+
+ /** CPU timestamp in nanoseconds. */
+ __u64 cpu_timestamp;
+
+ /**
+ * Reference clock id for CPU timestamp. For definition, see
+ * clock_gettime(2) and perf_event_open(2). Supported clock ids are
+ * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME,
+ * CLOCK_TAI.
+ */
+ __s32 clockid;
+
+ /** Must be zero. */
+ __u32 rsvd;
+};
+
/**
* struct drm_i915_query_engine_info
*
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 29b938e9..0d7f3256 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -267,6 +267,179 @@ eu_available(const struct drm_i915_query_topology_info *topo_info,
eu / 8] >> (eu % 8)) & 1;
}
+static bool query_cs_cycles_supported(int fd)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_CS_CYCLES,
+ };
+
+ return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
+}
+
+static void __query_cs_cycles(int i915, void *data, int err)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_CS_CYCLES,
+ .data_ptr = to_user_pointer(data),
+ .length = sizeof(struct drm_i915_query_cs_cycles),
+ };
+
+ i915_query_items(i915, &item, 1);
+
+ if (err)
+ igt_assert(item.length == -err);
+}
+
+static bool engine_has_cs_cycles(int i915, uint16_t class, uint16_t instance)
+{
+ struct drm_i915_query_cs_cycles ts = {};
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_CS_CYCLES,
+ .data_ptr = to_user_pointer(&ts),
+ .length = sizeof(struct drm_i915_query_cs_cycles),
+ };
+
+ ts.engine.engine_class = class;
+ ts.engine.engine_instance = instance;
+
+ i915_query_items(i915, &item, 1);
+
+ return item.length != -ENODEV;
+}
+
+static void
+__cs_cycles(int i915, struct i915_engine_class_instance *engine)
+{
+ struct drm_i915_query_cs_cycles ts1 = {};
+ struct drm_i915_query_cs_cycles ts2 = {};
+ uint64_t delta_cpu, delta_cs, delta_delta;
+ int i, usable = 0;
+ struct {
+ int32_t id;
+ const char *name;
+ } clock[] = {
+ { CLOCK_MONOTONIC, "CLOCK_MONOTONIC" },
+ { CLOCK_MONOTONIC_RAW, "CLOCK_MONOTONIC_RAW" },
+ { CLOCK_REALTIME, "CLOCK_REALTIME" },
+ { CLOCK_BOOTTIME, "CLOCK_BOOTTIME" },
+ { CLOCK_TAI, "CLOCK_TAI" },
+ };
+
+ igt_debug("engine[%u:%u]\n",
+ engine->engine_class,
+ engine->engine_instance);
+
+ /* Try a new clock every 10 iterations. */
+#define NUM_SNAPSHOTS 10
+ for (i = 0; i < NUM_SNAPSHOTS * ARRAY_SIZE(clock); i++) {
+ int index = i / NUM_SNAPSHOTS;
+
+ ts1.engine = *engine;
+ ts1.clockid = clock[index].id;
+
+ ts2.engine = *engine;
+ ts2.clockid = clock[index].id;
+
+ __query_cs_cycles(i915, &ts1, 0);
+ __query_cs_cycles(i915, &ts2, 0);
+
+ igt_debug("cpu_ts1[%llu], cs_ts1[%llu], freq %llu Hz\n",
+ ts1.cpu_timestamp,
+ ts1.cs_cycles,
+ ts1.cs_frequency);
+ igt_debug("cpu_ts2[%llu], cs_ts2[%llu], freq %llu Hz\n",
+ ts2.cpu_timestamp,
+ ts2.cs_cycles,
+ ts2.cs_frequency);
+
+ delta_cpu = ts2.cpu_timestamp - ts1.cpu_timestamp;
+ delta_cs = (ts2.cs_cycles - ts1.cs_cycles) *
+ NSEC_PER_SEC / ts1.cs_frequency;
+
+ igt_debug("delta_cpu[%lu], delta_cs[%lu]\n",
+ delta_cpu, delta_cs);
+
+ delta_delta = delta_cpu > delta_cs ?
+ delta_cpu - delta_cs :
+ delta_cs - delta_cpu;
+ igt_debug("delta_delta %lu\n", delta_delta);
+
+ if (delta_delta < 5000)
+ usable++;
+
+ /*
+ * User needs few good snapshots of the timestamps to
+ * synchronize cpu time with cs time. Check if we have enough
+ * usable values before moving to the next clockid.
+ */
+ if (!((i + 1) % NUM_SNAPSHOTS)) {
+ igt_debug("clock %s\n", clock[index].name);
+ igt_debug("usable %d\n", usable);
+ igt_assert(usable > 2);
+ usable = 0;
+ }
+ }
+}
+
+static void test_cs_cycles(int i915)
+{
+ const struct intel_execution_engine2 *e;
+ struct i915_engine_class_instance engine;
+
+ __for_each_physical_engine(i915, e) {
+ if (engine_has_cs_cycles(i915, e->class, e->instance)) {
+ engine.engine_class = e->class;
+ engine.engine_instance = e->instance;
+ __cs_cycles(i915, &engine);
+ }
+ }
+}
+
+static void test_cs_cycles_invalid(int i915)
+{
+ struct i915_engine_class_instance engine;
+ const struct intel_execution_engine2 *e;
+ struct drm_i915_query_cs_cycles ts = {};
+
+ /* get one engine */
+ __for_each_physical_engine(i915, e)
+ break;
+
+ /* bad engines */
+ ts.engine.engine_class = e->class;
+ ts.engine.engine_instance = -1;
+ __query_cs_cycles(i915, &ts, EINVAL);
+
+ ts.engine.engine_class = -1;
+ ts.engine.engine_instance = e->instance;
+ __query_cs_cycles(i915, &ts, EINVAL);
+
+ ts.engine.engine_class = -1;
+ ts.engine.engine_instance = -1;
+ __query_cs_cycles(i915, &ts, EINVAL);
+
+ /* non zero flags */
+ ts.flags = 1;
+ ts.engine.engine_class = e->class;
+ ts.engine.engine_instance = e->instance;
+ __query_cs_cycles(i915, &ts, EINVAL);
+
+ /* non zero rsvd field */
+ ts.flags = 0;
+ ts.rsvd = 1;
+ __query_cs_cycles(i915, &ts, EINVAL);
+
+ /* bad clockid */
+ ts.rsvd = 0;
+ ts.clockid = -1;
+ __query_cs_cycles(i915, &ts, EINVAL);
+
+ /* sanity check */
+ engine.engine_class = e->class;
+ engine.engine_instance = e->instance;
+ __cs_cycles(i915, &engine);
+}
+
/*
* Verify that we get coherent values between the legacy getparam slice/subslice
* masks and the new topology query.
@@ -783,6 +956,19 @@ igt_main
engines(fd);
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(intel_gen(devid) >= 6);
+ igt_require(query_cs_cycles_supported(fd));
+ }
+
+ igt_subtest("cs-cycles")
+ test_cs_cycles(fd);
+
+ igt_subtest("cs-cycles-invalid")
+ test_cs_cycles_invalid(fd);
+ }
+
igt_fixture {
close(fd);
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for i915/perf: Add test to query CS timestamp
2021-03-02 18:30 [igt-dev] [PATCH i-g-t] i915/perf: Add test to query CS timestamp Umesh Nerlige Ramappa
@ 2021-03-02 19:03 ` Patchwork
0 siblings, 0 replies; 2+ messages in thread
From: Patchwork @ 2021-03-02 19:03 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: igt-dev
[-- Attachment #1.1: Type: text/plain, Size: 2745 bytes --]
== Series Details ==
Series: i915/perf: Add test to query CS timestamp
URL : https://patchwork.freedesktop.org/series/87553/
State : failure
== Summary ==
CI Bug Log - changes from IGT_6019 -> IGTPW_5564
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_5564 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_5564, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5564/index.html
Known issues
------------
Here are the changes found in IGTPW_5564 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_linear_blits@basic:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2] ([i915#2502])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6019/fi-kbl-8809g/igt@gem_linear_blits@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5564/fi-kbl-8809g/igt@gem_linear_blits@basic.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [TIMEOUT][3] ([i915#3145]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6019/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5564/fi-kbl-8809g/igt@gem_exec_gttfill@basic.html
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
Participating hosts (45 -> 14)
------------------------------
ERROR: It appears as if the changes made in IGTPW_5564 prevented too many machines from booting.
Missing (31): fi-kbl-soraka fi-icl-y fi-skl-6600u fi-cml-u2 fi-cml-s fi-bsw-n3050 fi-byt-j1900 fi-tgl-u2 fi-glk-dsi fi-ctg-p8600 fi-hsw-4770 fi-elk-e7500 fi-tgl-y fi-bsw-nick fi-ilk-m540 fi-ehl-1 fi-tgl-dsi fi-skl-guc fi-cfl-8700k fi-dg1-1 fi-ehl-2 fi-hsw-gt1 fi-jsl-1 fi-rkl-11500t fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u fi-bsw-kefka fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6019 -> IGTPW_5564
CI-20190529: 20190529
CI_DRM_9821: 2eaa470f08c2bc15cc2c17da08c232ac46721e54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_5564: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5564/index.html
IGT_6019: 970aae7166c50851b62ed94f02964f402fa4b701 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@i915_query@cs-cycles
+igt@i915_query@cs-cycles-invalid
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5564/index.html
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
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