* [PATCH v2 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Convert to yaml file
@ 2021-03-05 1:54 ` Shawn Lin
0 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2021-03-05 1:54 UTC (permalink / raw)
To: Rob Herring, Ulf Hansson
Cc: linux-mmc, Adrian Hunter, devicetree, linux-rockchip, Shawn Lin
This patch converts sdhci-of-dwcmshc.txt to sdhci-of-dwcmshc.yaml
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.txt | 20 -------
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 63 ++++++++++++++++++++++
2 files changed, 63 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
create mode 100755 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
deleted file mode 100644
index ee4253b..0000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Synopsys DesignWare Cores Mobile Storage Host Controller
-
-Required properties:
-- compatible: should be one of the following:
- "snps,dwcmshc-sdhci"
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: Array of clocks required for SDHCI; requires at least one for
- core clock.
-- clock-names: Array of names corresponding to clocks property; shall be
- "core" for core clock and "bus" for optional bus clock.
-
-Example:
- sdhci2: sdhci@aa0000 {
- compatible = "snps,dwcmshc-sdhci";
- reg = <0xaa0000 0x1000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&emmcclk>;
- bus-width = <8>;
- }
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
new file mode 100755
index 0000000..9d717a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/sdhci-of-dwcmshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys Designware Mobile Storage Host Controller Binding
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+ - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - snps,dwcmshc-sdhci
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+ description:
+ Handle to "core" for core clock and "bus" for optional bus clock.
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: core
+ - const: bus
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@aa0000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xaa000 0x1000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>;
+ clock-names = "core", "bus";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+...
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Convert to yaml file
@ 2021-03-05 1:54 ` Shawn Lin
0 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2021-03-05 1:54 UTC (permalink / raw)
To: Rob Herring, Ulf Hansson
Cc: linux-mmc, Adrian Hunter, devicetree, linux-rockchip, Shawn Lin
This patch converts sdhci-of-dwcmshc.txt to sdhci-of-dwcmshc.yaml
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.txt | 20 -------
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 63 ++++++++++++++++++++++
2 files changed, 63 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
create mode 100755 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
deleted file mode 100644
index ee4253b..0000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Synopsys DesignWare Cores Mobile Storage Host Controller
-
-Required properties:
-- compatible: should be one of the following:
- "snps,dwcmshc-sdhci"
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: Array of clocks required for SDHCI; requires at least one for
- core clock.
-- clock-names: Array of names corresponding to clocks property; shall be
- "core" for core clock and "bus" for optional bus clock.
-
-Example:
- sdhci2: sdhci@aa0000 {
- compatible = "snps,dwcmshc-sdhci";
- reg = <0xaa0000 0x1000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&emmcclk>;
- bus-width = <8>;
- }
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
new file mode 100755
index 0000000..9d717a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/sdhci-of-dwcmshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys Designware Mobile Storage Host Controller Binding
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+ - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - snps,dwcmshc-sdhci
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+ description:
+ Handle to "core" for core clock and "bus" for optional bus clock.
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: core
+ - const: bus
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@aa0000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xaa000 0x1000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>;
+ clock-names = "core", "bus";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+...
--
2.7.4
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add rockchip support
2021-03-05 1:54 ` Shawn Lin
@ 2021-03-05 1:54 ` Shawn Lin
-1 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2021-03-05 1:54 UTC (permalink / raw)
To: Rob Herring, Ulf Hansson
Cc: linux-mmc, Adrian Hunter, devicetree, linux-rockchip, Shawn Lin
This patch adds rockchip support in sdhci-of-dwcmhsc.yaml
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 26 ++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
index 9d717a8..efec5d5 100755
--- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
@@ -16,6 +16,7 @@ allOf:
properties:
compatible:
enum:
+ - rockchip,dwcmshc-sdhci
- snps,dwcmshc-sdhci
reg:
@@ -27,16 +28,26 @@ properties:
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 5
description:
Handle to "core" for core clock and "bus" for optional bus clock.
+ "axi", "block" and "timer" are for Rockchip specified which aims for
+ DMA, pipe and internal timer respectively.
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 5
items:
- const: core
- const: bus
+ - const: axi
+ - const: block
+ - const: timer
+
+ rockchip,txclk-tapnum:
+ description: Specify the number of delay for tx sampling.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
required:
- compatible
@@ -49,6 +60,17 @@ unevaluatedProperties: false
examples:
- |
+ mmc@fe310000 {
+ compatible = "rockchip,dwcmshc-sdhci";
+ reg = <0xfe310000 0x10000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - |
mmc@aa0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xaa000 0x1000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add rockchip support
@ 2021-03-05 1:54 ` Shawn Lin
0 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2021-03-05 1:54 UTC (permalink / raw)
To: Rob Herring, Ulf Hansson
Cc: linux-mmc, Adrian Hunter, devicetree, linux-rockchip, Shawn Lin
This patch adds rockchip support in sdhci-of-dwcmhsc.yaml
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 26 ++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
index 9d717a8..efec5d5 100755
--- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
@@ -16,6 +16,7 @@ allOf:
properties:
compatible:
enum:
+ - rockchip,dwcmshc-sdhci
- snps,dwcmshc-sdhci
reg:
@@ -27,16 +28,26 @@ properties:
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 5
description:
Handle to "core" for core clock and "bus" for optional bus clock.
+ "axi", "block" and "timer" are for Rockchip specified which aims for
+ DMA, pipe and internal timer respectively.
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 5
items:
- const: core
- const: bus
+ - const: axi
+ - const: block
+ - const: timer
+
+ rockchip,txclk-tapnum:
+ description: Specify the number of delay for tx sampling.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
required:
- compatible
@@ -49,6 +60,17 @@ unevaluatedProperties: false
examples:
- |
+ mmc@fe310000 {
+ compatible = "rockchip,dwcmshc-sdhci";
+ reg = <0xfe310000 0x10000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - |
mmc@aa0000 {
compatible = "snps,dwcmshc-sdhci";
reg = <0xaa000 0x1000>;
--
2.7.4
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] mmc: sdhci-of-dwcmshc: add rockchip platform support
2021-03-05 1:54 ` Shawn Lin
@ 2021-03-05 1:54 ` Shawn Lin
-1 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2021-03-05 1:54 UTC (permalink / raw)
To: Rob Herring, Ulf Hansson
Cc: linux-mmc, Adrian Hunter, devicetree, linux-rockchip, Shawn Lin
sdhci based synopsys MMC IP is also used on some rockchip platforms,
so add a basic support here.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/sdhci-of-dwcmshc.c | 220 ++++++++++++++++++++++++++++++++++--
1 file changed, 213 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 59d8d96..959084c 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -9,9 +9,11 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/sizes.h>
#include "sdhci-pltfm.h"
@@ -21,11 +23,43 @@
/* DWCMSHC specific Mode Select value */
#define DWCMSHC_CTRL_HS400 0x7
+/* Rockchip specific Registers */
+#define DWCMSHC_HOST_CTRL3 0x508
+#define DWCMSHC_EMMC_CONTROL 0x52c
+#define DWCMSHC_EMMC_ATCTRL 0x540
+#define DWCMSHC_EMMC_DLL_CTRL 0x800
+#define DWCMSHC_EMMC_DLL_RXCLK 0x804
+#define DWCMSHC_EMMC_DLL_TXCLK 0x808
+#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
+#define DWCMSHC_EMMC_DLL_STATUS0 0x840
+#define DWCMSHC_EMMC_DLL_START BIT(0)
+#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
+#define DWCMSHC_EMMC_DLL_START_POINT 16
+#define DWCMSHC_EMMC_DLL_INC 8
+#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
+#define DLL_TXCLK_TAPNUM_DEFAULT 0x8
+#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
+#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
+#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
+#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
+#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
+#define DLL_RXCLK_NO_INVERTER 1
+#define DLL_RXCLK_INVERTER 0
+#define DWCMSHC_ENHANCED_STROBE BIT(8)
+#define DLL_LOCK_WO_TMOUT(x) \
+ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
+ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
+#define ROCKCHIP_MAX_CLKS 3
+
#define BOUNDARY_OK(addr, len) \
((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
struct dwcmshc_priv {
struct clk *bus_clk;
+
+ /* Rockchip specified optional clocks */
+ struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS];
+ int txclk_tapnum;
};
/*
@@ -100,6 +134,97 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}
+static void dwcmshc_rk_hs400_enhanced_strobe(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ u32 vendor;
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
+ if (ios->enhanced_strobe)
+ vendor |= DWCMSHC_ENHANCED_STROBE;
+ else
+ vendor &= ~DWCMSHC_ENHANCED_STROBE;
+
+ sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
+}
+
+static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, extra;
+ int err;
+
+ host->mmc->actual_clock = 0;
+
+ /* DO NOT TOUCH THIS SETTING */
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+
+ if (clock == 0)
+ return;
+
+ /* Rockchip platform only support 375KHz for identify mode */
+ if (clock <= 400000)
+ clock = 375000;
+
+ err = clk_set_rate(pltfm_host->clk, clock);
+ if (err)
+ dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
+
+ sdhci_set_clock(host, clock);
+
+ /* Disable cmd conflict check */
+ extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
+ extra &= ~BIT(0);
+ sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
+
+ if (clock <= 400000) {
+ /* Disable DLL to reset sample clock */
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+ return;
+ }
+
+ /* Reset DLL */
+ sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
+ udelay(1);
+ sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
+
+ /* Init DLL settings */
+ extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
+ 0x2 << DWCMSHC_EMMC_DLL_INC |
+ DWCMSHC_EMMC_DLL_START;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
+ err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
+ extra, DLL_LOCK_WO_TMOUT(extra), 1,
+ 500 * USEC_PER_MSEC);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
+ return;
+ }
+
+ extra = 0x1 << 16 | /* tune clock stop en */
+ 0x2 << 17 | /* pre-change delay */
+ 0x3 << 19; /* post-change delay */
+ sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);
+
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ txclk_tapnum = priv->txclk_tapnum;
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_TXCLK_TAPNUM_FROM_SW |
+ txclk_tapnum;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_STRBIN_TAPNUM_DEFAULT |
+ DLL_STRBIN_TAPNUM_FROM_SW;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
+}
+
static const struct sdhci_ops sdhci_dwcmshc_ops = {
.set_clock = sdhci_set_clock,
.set_bus_width = sdhci_set_bus_width,
@@ -109,21 +234,91 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = {
.adma_write_desc = dwcmshc_adma_write_desc,
};
+static const struct sdhci_ops sdhci_dwcmshc_rk_ops = {
+ .set_clock = dwcmshc_rk_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .reset = sdhci_reset,
+ .adma_write_desc = dwcmshc_adma_write_desc,
+};
+
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
.ops = &sdhci_dwcmshc_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};
+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk_pdata = {
+ .ops = &sdhci_dwcmshc_rk_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+};
+
+static int rockchip_pltf_init(struct sdhci_host *host, struct dwcmshc_priv *priv)
+{
+ int err;
+
+ priv->rockchip_clks[0].id = "axi";
+ priv->rockchip_clks[1].id = "block";
+ priv->rockchip_clks[2].id = "timer";
+ err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), ROCKCHIP_MAX_CLKS,
+ priv->rockchip_clks);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
+ return err;
+ }
+
+ err = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
+ return err;
+ }
+
+ if (of_property_read_u32(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
+ &priv->txclk_tapnum))
+ priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
+
+ /* Disable cmd conflict check */
+ sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3);
+ /* Reset previous settings */
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
+
+ return 0;
+}
+
+static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
+ {
+ .compatible = "snps,dwcmshc-sdhci",
+ .data = &sdhci_dwcmshc_pdata,
+ },
+ {
+ .compatible = "rockchip,dwcmshc-sdhci",
+ .data = &sdhci_dwcmshc_rk_pdata,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
+
static int dwcmshc_probe(struct platform_device *pdev)
{
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_host *host;
struct dwcmshc_priv *priv;
+ const struct sdhci_pltfm_data *pltfm_data;
int err;
u32 extra;
- host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata,
+ pltfm_data = of_device_get_match_data(&pdev->dev);
+ if (!pltfm_data) {
+ dev_err(&pdev->dev, "Error: No device match data found\n");
+ return -ENODEV;
+ }
+
+ host = sdhci_pltfm_init(pdev, pltfm_data,
sizeof(struct dwcmshc_priv));
if (IS_ERR(host))
return PTR_ERR(host);
@@ -161,6 +356,15 @@ static int dwcmshc_probe(struct platform_device *pdev)
host->mmc_host_ops.request = dwcmshc_request;
+ if (pltfm_data == &sdhci_dwcmshc_rk_pdata) {
+ host->mmc_host_ops.hs400_enhanced_strobe =
+ dwcmshc_rk_hs400_enhanced_strobe;
+
+ err = rockchip_pltf_init(host, priv);
+ if (err)
+ goto err_clk;
+ }
+
err = sdhci_add_host(host);
if (err)
goto err_clk;
@@ -170,6 +374,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
err_clk:
clk_disable_unprepare(pltfm_host->clk);
clk_disable_unprepare(priv->bus_clk);
+ clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
free_pltfm:
sdhci_pltfm_free(pdev);
return err;
@@ -185,6 +390,7 @@ static int dwcmshc_remove(struct platform_device *pdev)
clk_disable_unprepare(pltfm_host->clk);
clk_disable_unprepare(priv->bus_clk);
+ clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
sdhci_pltfm_free(pdev);
@@ -207,6 +413,8 @@ static int dwcmshc_suspend(struct device *dev)
if (!IS_ERR(priv->bus_clk))
clk_disable_unprepare(priv->bus_clk);
+ clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
+
return ret;
}
@@ -227,18 +435,16 @@ static int dwcmshc_resume(struct device *dev)
return ret;
}
+ ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
+ if (ret)
+ return ret;
+
return sdhci_resume_host(host);
}
#endif
static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
-static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
- { .compatible = "snps,dwcmshc-sdhci" },
- {}
-};
-MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
-
static struct platform_driver sdhci_dwcmshc_driver = {
.driver = {
.name = "sdhci-dwcmshc",
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] mmc: sdhci-of-dwcmshc: add rockchip platform support
@ 2021-03-05 1:54 ` Shawn Lin
0 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2021-03-05 1:54 UTC (permalink / raw)
To: Rob Herring, Ulf Hansson
Cc: linux-mmc, Adrian Hunter, devicetree, linux-rockchip, Shawn Lin
sdhci based synopsys MMC IP is also used on some rockchip platforms,
so add a basic support here.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/sdhci-of-dwcmshc.c | 220 ++++++++++++++++++++++++++++++++++--
1 file changed, 213 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 59d8d96..959084c 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -9,9 +9,11 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/sizes.h>
#include "sdhci-pltfm.h"
@@ -21,11 +23,43 @@
/* DWCMSHC specific Mode Select value */
#define DWCMSHC_CTRL_HS400 0x7
+/* Rockchip specific Registers */
+#define DWCMSHC_HOST_CTRL3 0x508
+#define DWCMSHC_EMMC_CONTROL 0x52c
+#define DWCMSHC_EMMC_ATCTRL 0x540
+#define DWCMSHC_EMMC_DLL_CTRL 0x800
+#define DWCMSHC_EMMC_DLL_RXCLK 0x804
+#define DWCMSHC_EMMC_DLL_TXCLK 0x808
+#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
+#define DWCMSHC_EMMC_DLL_STATUS0 0x840
+#define DWCMSHC_EMMC_DLL_START BIT(0)
+#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
+#define DWCMSHC_EMMC_DLL_START_POINT 16
+#define DWCMSHC_EMMC_DLL_INC 8
+#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
+#define DLL_TXCLK_TAPNUM_DEFAULT 0x8
+#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
+#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
+#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
+#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
+#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
+#define DLL_RXCLK_NO_INVERTER 1
+#define DLL_RXCLK_INVERTER 0
+#define DWCMSHC_ENHANCED_STROBE BIT(8)
+#define DLL_LOCK_WO_TMOUT(x) \
+ ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
+ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
+#define ROCKCHIP_MAX_CLKS 3
+
#define BOUNDARY_OK(addr, len) \
((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
struct dwcmshc_priv {
struct clk *bus_clk;
+
+ /* Rockchip specified optional clocks */
+ struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS];
+ int txclk_tapnum;
};
/*
@@ -100,6 +134,97 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}
+static void dwcmshc_rk_hs400_enhanced_strobe(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ u32 vendor;
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
+ if (ios->enhanced_strobe)
+ vendor |= DWCMSHC_ENHANCED_STROBE;
+ else
+ vendor &= ~DWCMSHC_ENHANCED_STROBE;
+
+ sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
+}
+
+static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, extra;
+ int err;
+
+ host->mmc->actual_clock = 0;
+
+ /* DO NOT TOUCH THIS SETTING */
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+
+ if (clock == 0)
+ return;
+
+ /* Rockchip platform only support 375KHz for identify mode */
+ if (clock <= 400000)
+ clock = 375000;
+
+ err = clk_set_rate(pltfm_host->clk, clock);
+ if (err)
+ dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
+
+ sdhci_set_clock(host, clock);
+
+ /* Disable cmd conflict check */
+ extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
+ extra &= ~BIT(0);
+ sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
+
+ if (clock <= 400000) {
+ /* Disable DLL to reset sample clock */
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+ return;
+ }
+
+ /* Reset DLL */
+ sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
+ udelay(1);
+ sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
+
+ /* Init DLL settings */
+ extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
+ 0x2 << DWCMSHC_EMMC_DLL_INC |
+ DWCMSHC_EMMC_DLL_START;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
+ err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
+ extra, DLL_LOCK_WO_TMOUT(extra), 1,
+ 500 * USEC_PER_MSEC);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
+ return;
+ }
+
+ extra = 0x1 << 16 | /* tune clock stop en */
+ 0x2 << 17 | /* pre-change delay */
+ 0x3 << 19; /* post-change delay */
+ sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);
+
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
+ host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ txclk_tapnum = priv->txclk_tapnum;
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_TXCLK_TAPNUM_FROM_SW |
+ txclk_tapnum;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
+
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_STRBIN_TAPNUM_DEFAULT |
+ DLL_STRBIN_TAPNUM_FROM_SW;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
+}
+
static const struct sdhci_ops sdhci_dwcmshc_ops = {
.set_clock = sdhci_set_clock,
.set_bus_width = sdhci_set_bus_width,
@@ -109,21 +234,91 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = {
.adma_write_desc = dwcmshc_adma_write_desc,
};
+static const struct sdhci_ops sdhci_dwcmshc_rk_ops = {
+ .set_clock = dwcmshc_rk_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = dwcmshc_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .reset = sdhci_reset,
+ .adma_write_desc = dwcmshc_adma_write_desc,
+};
+
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
.ops = &sdhci_dwcmshc_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};
+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk_pdata = {
+ .ops = &sdhci_dwcmshc_rk_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+};
+
+static int rockchip_pltf_init(struct sdhci_host *host, struct dwcmshc_priv *priv)
+{
+ int err;
+
+ priv->rockchip_clks[0].id = "axi";
+ priv->rockchip_clks[1].id = "block";
+ priv->rockchip_clks[2].id = "timer";
+ err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), ROCKCHIP_MAX_CLKS,
+ priv->rockchip_clks);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
+ return err;
+ }
+
+ err = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
+ if (err) {
+ dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
+ return err;
+ }
+
+ if (of_property_read_u32(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
+ &priv->txclk_tapnum))
+ priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
+
+ /* Disable cmd conflict check */
+ sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3);
+ /* Reset previous settings */
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
+
+ return 0;
+}
+
+static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
+ {
+ .compatible = "snps,dwcmshc-sdhci",
+ .data = &sdhci_dwcmshc_pdata,
+ },
+ {
+ .compatible = "rockchip,dwcmshc-sdhci",
+ .data = &sdhci_dwcmshc_rk_pdata,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
+
static int dwcmshc_probe(struct platform_device *pdev)
{
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_host *host;
struct dwcmshc_priv *priv;
+ const struct sdhci_pltfm_data *pltfm_data;
int err;
u32 extra;
- host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata,
+ pltfm_data = of_device_get_match_data(&pdev->dev);
+ if (!pltfm_data) {
+ dev_err(&pdev->dev, "Error: No device match data found\n");
+ return -ENODEV;
+ }
+
+ host = sdhci_pltfm_init(pdev, pltfm_data,
sizeof(struct dwcmshc_priv));
if (IS_ERR(host))
return PTR_ERR(host);
@@ -161,6 +356,15 @@ static int dwcmshc_probe(struct platform_device *pdev)
host->mmc_host_ops.request = dwcmshc_request;
+ if (pltfm_data == &sdhci_dwcmshc_rk_pdata) {
+ host->mmc_host_ops.hs400_enhanced_strobe =
+ dwcmshc_rk_hs400_enhanced_strobe;
+
+ err = rockchip_pltf_init(host, priv);
+ if (err)
+ goto err_clk;
+ }
+
err = sdhci_add_host(host);
if (err)
goto err_clk;
@@ -170,6 +374,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
err_clk:
clk_disable_unprepare(pltfm_host->clk);
clk_disable_unprepare(priv->bus_clk);
+ clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
free_pltfm:
sdhci_pltfm_free(pdev);
return err;
@@ -185,6 +390,7 @@ static int dwcmshc_remove(struct platform_device *pdev)
clk_disable_unprepare(pltfm_host->clk);
clk_disable_unprepare(priv->bus_clk);
+ clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
sdhci_pltfm_free(pdev);
@@ -207,6 +413,8 @@ static int dwcmshc_suspend(struct device *dev)
if (!IS_ERR(priv->bus_clk))
clk_disable_unprepare(priv->bus_clk);
+ clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
+
return ret;
}
@@ -227,18 +435,16 @@ static int dwcmshc_resume(struct device *dev)
return ret;
}
+ ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
+ if (ret)
+ return ret;
+
return sdhci_resume_host(host);
}
#endif
static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
-static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
- { .compatible = "snps,dwcmshc-sdhci" },
- {}
-};
-MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
-
static struct platform_driver sdhci_dwcmshc_driver = {
.driver = {
.name = "sdhci-dwcmshc",
--
2.7.4
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Convert to yaml file
2021-03-05 1:54 ` Shawn Lin
@ 2021-03-08 21:42 ` Rob Herring
-1 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2021-03-08 21:42 UTC (permalink / raw)
To: Shawn Lin
Cc: Ulf Hansson, linux-mmc, Adrian Hunter, devicetree, linux-rockchip
On Fri, Mar 05, 2021 at 09:54:20AM +0800, Shawn Lin wrote:
> This patch converts sdhci-of-dwcmshc.txt to sdhci-of-dwcmshc.yaml
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> .../devicetree/bindings/mmc/sdhci-of-dwcmshc.txt | 20 -------
> .../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 63 ++++++++++++++++++++++
Use the compatible string for filename.
> 2 files changed, 63 insertions(+), 20 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> create mode 100755 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> deleted file mode 100644
> index ee4253b..0000000
> --- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -* Synopsys DesignWare Cores Mobile Storage Host Controller
> -
> -Required properties:
> -- compatible: should be one of the following:
> - "snps,dwcmshc-sdhci"
> -- reg: offset and length of the register set for the device.
> -- interrupts: a single interrupt specifier.
> -- clocks: Array of clocks required for SDHCI; requires at least one for
> - core clock.
> -- clock-names: Array of names corresponding to clocks property; shall be
> - "core" for core clock and "bus" for optional bus clock.
> -
> -Example:
> - sdhci2: sdhci@aa0000 {
> - compatible = "snps,dwcmshc-sdhci";
> - reg = <0xaa0000 0x1000>;
> - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&emmcclk>;
> - bus-width = <8>;
> - }
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
> new file mode 100755
> index 0000000..9d717a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/sdhci-of-dwcmshc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys Designware Mobile Storage Host Controller Binding
> +
> +maintainers:
> + - Ulf Hansson <ulf.hansson@linaro.org>
> + - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> +
> +allOf:
> + - $ref: mmc-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - snps,dwcmshc-sdhci
> +
> + reg:
> + minItems: 1
> + maxItems: 3
You need to define what each entry is.
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> + description:
> + Handle to "core" for core clock and "bus" for optional bus clock.
minItems: 1
items:
- description: core clock
- description: bus clock
> +
> + clock-names:
> + minItems: 1
> + maxItems: 2
Don't need maxItems here (implied by 'items' length).
> + items:
> + - const: core
> + - const: bus
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + mmc@aa0000 {
> + compatible = "snps,dwcmshc-sdhci";
> + reg = <0xaa000 0x1000>;
> + interrupts = <0 25 0x4>;
> + clocks = <&cru 17>, <&cru 18>;
> + clock-names = "core", "bus";
> + bus-width = <8>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> +...
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Convert to yaml file
@ 2021-03-08 21:42 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2021-03-08 21:42 UTC (permalink / raw)
To: Shawn Lin
Cc: Ulf Hansson, linux-mmc, Adrian Hunter, devicetree, linux-rockchip
On Fri, Mar 05, 2021 at 09:54:20AM +0800, Shawn Lin wrote:
> This patch converts sdhci-of-dwcmshc.txt to sdhci-of-dwcmshc.yaml
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> .../devicetree/bindings/mmc/sdhci-of-dwcmshc.txt | 20 -------
> .../devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml | 63 ++++++++++++++++++++++
Use the compatible string for filename.
> 2 files changed, 63 insertions(+), 20 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> create mode 100755 Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> deleted file mode 100644
> index ee4253b..0000000
> --- a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -* Synopsys DesignWare Cores Mobile Storage Host Controller
> -
> -Required properties:
> -- compatible: should be one of the following:
> - "snps,dwcmshc-sdhci"
> -- reg: offset and length of the register set for the device.
> -- interrupts: a single interrupt specifier.
> -- clocks: Array of clocks required for SDHCI; requires at least one for
> - core clock.
> -- clock-names: Array of names corresponding to clocks property; shall be
> - "core" for core clock and "bus" for optional bus clock.
> -
> -Example:
> - sdhci2: sdhci@aa0000 {
> - compatible = "snps,dwcmshc-sdhci";
> - reg = <0xaa0000 0x1000>;
> - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&emmcclk>;
> - bus-width = <8>;
> - }
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
> new file mode 100755
> index 0000000..9d717a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/sdhci-of-dwcmshc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys Designware Mobile Storage Host Controller Binding
> +
> +maintainers:
> + - Ulf Hansson <ulf.hansson@linaro.org>
> + - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
> +
> +allOf:
> + - $ref: mmc-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - snps,dwcmshc-sdhci
> +
> + reg:
> + minItems: 1
> + maxItems: 3
You need to define what each entry is.
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> + description:
> + Handle to "core" for core clock and "bus" for optional bus clock.
minItems: 1
items:
- description: core clock
- description: bus clock
> +
> + clock-names:
> + minItems: 1
> + maxItems: 2
Don't need maxItems here (implied by 'items' length).
> + items:
> + - const: core
> + - const: bus
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + mmc@aa0000 {
> + compatible = "snps,dwcmshc-sdhci";
> + reg = <0xaa000 0x1000>;
> + interrupts = <0 25 0x4>;
> + clocks = <&cru 17>, <&cru 18>;
> + clock-names = "core", "bus";
> + bus-width = <8>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> +...
> --
> 2.7.4
>
>
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-03-08 21:43 UTC | newest]
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-- links below jump to the message on this page --
2021-03-05 1:54 [PATCH v2 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Convert to yaml file Shawn Lin
2021-03-05 1:54 ` Shawn Lin
2021-03-05 1:54 ` [PATCH v2 2/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add rockchip support Shawn Lin
2021-03-05 1:54 ` Shawn Lin
2021-03-05 1:54 ` [PATCH v2 3/3] mmc: sdhci-of-dwcmshc: add rockchip platform support Shawn Lin
2021-03-05 1:54 ` Shawn Lin
2021-03-08 21:42 ` [PATCH v2 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Convert to yaml file Rob Herring
2021-03-08 21:42 ` Rob Herring
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