All of lore.kernel.org
 help / color / mirror / Atom feed
From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org
Cc: acme@kernel.org, tglx@linutronix.de, bp@alien8.de,
	namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com,
	yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 18/25] perf/x86/intel: Add attr_update for Hybrid PMUs
Date: Wed, 10 Mar 2021 08:37:54 -0800	[thread overview]
Message-ID: <1615394281-68214-19-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1615394281-68214-1-git-send-email-kan.liang@linux.intel.com>

From: Kan Liang <kan.liang@linux.intel.com>

The attribute_group for Hybrid PMUs should be different from the previous
cpu PMU. For example, cpumask is required for a Hybrid PMU. The PMU type
should be included in the event and format attribute.

Add hybrid_attr_update for the Hybrid PMU.
Check the PMU type in is_visible() function. Only display the event or
format for the matched Hybrid PMU.

Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/intel/core.c | 120 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 114 insertions(+), 6 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 0026a54..8ac948a 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5266,6 +5266,106 @@ static const struct attribute_group *attr_update[] = {
 	NULL,
 };
 
+static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct x86_hybrid_pmu *pmu =
+		container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
+	struct perf_pmu_events_hybrid_attr *pmu_attr =
+		container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
+
+	return pmu->cpu_type & pmu_attr->pmu_type;
+}
+
+static umode_t hybrid_events_is_visible(struct kobject *kobj,
+					struct attribute *attr, int i)
+{
+	return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
+}
+
+static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
+{
+	int cpu = cpumask_first(&pmu->supported_cpus);
+
+	return (cpu >= nr_cpu_ids) ? -1 : cpu;
+}
+
+static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
+				     struct attribute *attr, int i)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct x86_hybrid_pmu *pmu =
+		 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
+	int cpu = hybrid_find_supported_cpu(pmu);
+
+	return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
+}
+
+static umode_t hybrid_format_is_visible(struct kobject *kobj,
+					struct attribute *attr, int i)
+{
+	struct device *dev = kobj_to_dev(kobj);
+	struct x86_hybrid_pmu *pmu =
+		container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
+	struct perf_pmu_format_hybrid_attr *pmu_attr =
+		container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
+	int cpu = hybrid_find_supported_cpu(pmu);
+
+	return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0;
+}
+
+static struct attribute_group hybrid_group_events_td  = {
+	.name		= "events",
+	.is_visible	= hybrid_events_is_visible,
+};
+
+static struct attribute_group hybrid_group_events_mem = {
+	.name		= "events",
+	.is_visible	= hybrid_events_is_visible,
+};
+
+static struct attribute_group hybrid_group_events_tsx = {
+	.name		= "events",
+	.is_visible	= hybrid_tsx_is_visible,
+};
+
+static struct attribute_group hybrid_group_format_extra = {
+	.name		= "format",
+	.is_visible	= hybrid_format_is_visible,
+};
+
+static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
+					  struct device_attribute *attr,
+					  char *buf)
+{
+	struct x86_hybrid_pmu *pmu =
+		container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
+
+	return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
+}
+
+static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
+static struct attribute *intel_hybrid_cpus_attrs[] = {
+	&dev_attr_cpus.attr,
+	NULL,
+};
+
+static struct attribute_group hybrid_group_cpus = {
+	.attrs		= intel_hybrid_cpus_attrs,
+};
+
+static const struct attribute_group *hybrid_attr_update[] = {
+	&hybrid_group_events_td,
+	&hybrid_group_events_mem,
+	&hybrid_group_events_tsx,
+	&group_caps_gen,
+	&group_caps_lbr,
+	&hybrid_group_format_extra,
+	&group_default,
+	&hybrid_group_cpus,
+	NULL,
+};
+
 static struct attribute *empty_attrs;
 
 __init int intel_pmu_init(void)
@@ -5896,14 +5996,22 @@ __init int intel_pmu_init(void)
 
 	snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
 
+	if (!is_hybrid()) {
+		group_events_td.attrs  = td_attr;
+		group_events_mem.attrs = mem_attr;
+		group_events_tsx.attrs = tsx_attr;
+		group_format_extra.attrs = extra_attr;
+		group_format_extra_skl.attrs = extra_skl_attr;
 
-	group_events_td.attrs  = td_attr;
-	group_events_mem.attrs = mem_attr;
-	group_events_tsx.attrs = tsx_attr;
-	group_format_extra.attrs = extra_attr;
-	group_format_extra_skl.attrs = extra_skl_attr;
+		x86_pmu.attr_update = attr_update;
+	} else {
+		hybrid_group_events_td.attrs  = td_attr;
+		hybrid_group_events_mem.attrs = mem_attr;
+		hybrid_group_events_tsx.attrs = tsx_attr;
+		hybrid_group_format_extra.attrs = extra_attr;
 
-	x86_pmu.attr_update = attr_update;
+		x86_pmu.attr_update = hybrid_attr_update;
+	}
 
 	intel_pmu_check_num_counters(&x86_pmu.num_counters,
 				     &x86_pmu.num_counters_fixed,
-- 
2.7.4


  parent reply	other threads:[~2021-03-10 16:44 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-10 16:37 [PATCH V2 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-03-10 16:37 ` [PATCH V2 1/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-03-10 16:53   ` Borislav Petkov
2021-03-10 19:33     ` Srinivas Pandruvada
2021-03-10 19:46     ` Ricardo Neri
2021-03-10 20:01       ` Borislav Petkov
2021-03-10 22:25         ` Ricardo Neri
2021-03-10 22:32           ` Liang, Kan
2021-03-10 22:42           ` Srinivas Pandruvada
2021-03-10 16:37 ` [PATCH V2 2/25] x86/cpu: Add helper functions to get parameters of hybrid CPUs kan.liang
2021-03-11 11:48   ` Borislav Petkov
2021-03-10 16:37 ` [PATCH V2 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-03-10 16:37 ` [PATCH V2 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-03-10 16:37 ` [PATCH V2 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-03-10 16:37 ` [PATCH V2 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-03-10 16:37 ` [PATCH V2 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-03-10 16:37 ` [PATCH V2 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-03-11 11:07   ` Peter Zijlstra
2021-03-11 15:09     ` Liang, Kan
2021-03-10 16:37 ` [PATCH V2 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-03-10 16:37 ` [PATCH V2 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-03-10 16:37 ` [PATCH V2 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-03-10 16:37 ` [PATCH V2 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-03-10 16:37 ` [PATCH V2 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-03-10 16:37 ` [PATCH V2 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-03-10 16:37 ` [PATCH V2 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-03-10 16:37 ` [PATCH V2 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-03-10 16:50   ` Dave Hansen
2021-03-10 17:38     ` Liang, Kan
2021-03-11 11:56   ` Peter Zijlstra
2021-03-11 12:17   ` Peter Zijlstra
2021-03-11 12:30     ` Peter Zijlstra
2021-03-11 12:19   ` Peter Zijlstra
2021-03-11 12:34   ` Peter Zijlstra
2021-03-11 15:41     ` Liang, Kan
2021-03-11 16:13       ` Peter Zijlstra
2021-03-11 17:53     ` Andi Kleen
2021-03-11 19:54       ` Peter Zijlstra
2021-03-10 16:37 ` [PATCH V2 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-03-10 16:37 ` kan.liang [this message]
2021-03-10 16:37 ` [PATCH V2 19/25] perf/x86: Support filter_match callback kan.liang
2021-03-10 16:37 ` [PATCH V2 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-03-11 12:51   ` Peter Zijlstra
2021-03-11 16:09   ` Peter Zijlstra
2021-03-11 16:32     ` Peter Zijlstra
2021-03-11 17:31       ` Liang, Kan
2021-03-11 16:53     ` Liang, Kan
2021-03-11 17:25       ` Liang, Kan
2021-03-11 19:58       ` Peter Zijlstra
2021-03-11 20:30         ` Andi Kleen
2021-03-11 20:37           ` Peter Zijlstra
2021-03-11 20:32         ` Liang, Kan
2021-03-11 20:47           ` Peter Zijlstra
2021-03-11 21:09             ` Luck, Tony
2021-03-11 21:43               ` Peter Zijlstra
2021-03-12  0:00               ` Andi Kleen
2021-03-10 16:37 ` [PATCH V2 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-03-10 16:37 ` [PATCH V2 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-03-10 16:37 ` [PATCH V2 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-03-10 16:38 ` [PATCH V2 24/25] perf/x86/cstate: " kan.liang
2021-03-10 16:38 ` [PATCH V2 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1615394281-68214-19-git-send-email-kan.liang@linux.intel.com \
    --to=kan.liang@linux.intel.com \
    --cc=acme@kernel.org \
    --cc=adrian.hunter@intel.com \
    --cc=ak@linux.intel.com \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=bp@alien8.de \
    --cc=jolsa@redhat.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@kernel.org \
    --cc=namhyung@kernel.org \
    --cc=peterz@infradead.org \
    --cc=tglx@linutronix.de \
    --cc=yao.jin@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.