All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Dave Hansen <dave.hansen@intel.com>,
	peterz@infradead.org, mingo@kernel.org,
	linux-kernel@vger.kernel.org
Cc: acme@kernel.org, tglx@linutronix.de, bp@alien8.de,
	namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com,
	yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com
Subject: Re: [PATCH V2 16/25] perf/x86: Register hybrid PMUs
Date: Wed, 10 Mar 2021 12:38:35 -0500	[thread overview]
Message-ID: <e8dd446f-f57c-dfbd-d923-b313411b74a0@linux.intel.com> (raw)
In-Reply-To: <a1adb737-f126-ecec-9bca-a1b5bdb76156@intel.com>



On 3/10/2021 11:50 AM, Dave Hansen wrote:
> On 3/10/21 8:37 AM, kan.liang@linux.intel.com wrote:
>> -	err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
>> -	if (err)
>> -		goto out2;
>> +	if (!is_hybrid()) {
>> +		err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
>> +		if (err)
>> +			goto out2;
>> +	} else {
>> +		u8 cpu_type = get_hybrid_cpu_type(smp_processor_id());
>> +		struct x86_hybrid_pmu *hybrid_pmu;
>> +		int i;
> 
> Where's the preempt_disable()?
> 
>> +static void init_hybrid_pmu(int cpu)
>> +{
>> +	unsigned int fixed_mask, unused_eax, unused_ebx, unused_edx;
>> +	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
>> +	u8 cpu_type = get_hybrid_cpu_type(cpu);
>> +	struct x86_hybrid_pmu *pmu = NULL;
>> +	struct perf_cpu_context *cpuctx;
>> +	int i;
> 
> Ditto.
> 
> Are we really sure the IPIs are worth the trouble?  Why don't we just
> cache the leaf when we bring the CPU up like just about every other
> thing we read from CPUID?

Simple answer: You are right. We don't need it. A simple 
get_this_hybrid_cpu_type() should be fine for perf.

Here is the complete story.
I need the CPU type of the dead CPU in the cpu_dead. In the previous 
patch set, we can read it from the cached CPU type in the struct 
cpuinfo_x86.

In the V2 patch, I tried to do a similar thing (but I have to read it at 
runtime). Since the CPU is offlined, I asked Ricardo to provide the 
function get_hybrid_cpu_type() which can read the CPU type of a specific 
CPU. But I'm wrong. We cannot retrieve the valid CPU type from an 
offlined CPU. So I dropped the method and used another method to 
retrieve the information, but I didn't let Ricardo update the function. 
My bad.

Now, we only need to read the CPU type of the current CPU. A 
get_this_hybrid_cpu_type() function is enough for me.

I think we can get rid of the IPIs trouble with the new 
get_this_hybrid_cpu_type() in the next version. We shouldn't need the 
preempt_disable() either.

Thanks for pointing that out.

Kan


  reply	other threads:[~2021-03-10 17:39 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-10 16:37 [PATCH V2 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-03-10 16:37 ` [PATCH V2 1/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-03-10 16:53   ` Borislav Petkov
2021-03-10 19:33     ` Srinivas Pandruvada
2021-03-10 19:46     ` Ricardo Neri
2021-03-10 20:01       ` Borislav Petkov
2021-03-10 22:25         ` Ricardo Neri
2021-03-10 22:32           ` Liang, Kan
2021-03-10 22:42           ` Srinivas Pandruvada
2021-03-10 16:37 ` [PATCH V2 2/25] x86/cpu: Add helper functions to get parameters of hybrid CPUs kan.liang
2021-03-11 11:48   ` Borislav Petkov
2021-03-10 16:37 ` [PATCH V2 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-03-10 16:37 ` [PATCH V2 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-03-10 16:37 ` [PATCH V2 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-03-10 16:37 ` [PATCH V2 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-03-10 16:37 ` [PATCH V2 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-03-10 16:37 ` [PATCH V2 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-03-11 11:07   ` Peter Zijlstra
2021-03-11 15:09     ` Liang, Kan
2021-03-10 16:37 ` [PATCH V2 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-03-10 16:37 ` [PATCH V2 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-03-10 16:37 ` [PATCH V2 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-03-10 16:37 ` [PATCH V2 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-03-10 16:37 ` [PATCH V2 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-03-10 16:37 ` [PATCH V2 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-03-10 16:37 ` [PATCH V2 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-03-10 16:37 ` [PATCH V2 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-03-10 16:50   ` Dave Hansen
2021-03-10 17:38     ` Liang, Kan [this message]
2021-03-11 11:56   ` Peter Zijlstra
2021-03-11 12:17   ` Peter Zijlstra
2021-03-11 12:30     ` Peter Zijlstra
2021-03-11 12:19   ` Peter Zijlstra
2021-03-11 12:34   ` Peter Zijlstra
2021-03-11 15:41     ` Liang, Kan
2021-03-11 16:13       ` Peter Zijlstra
2021-03-11 17:53     ` Andi Kleen
2021-03-11 19:54       ` Peter Zijlstra
2021-03-10 16:37 ` [PATCH V2 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-03-10 16:37 ` [PATCH V2 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-03-10 16:37 ` [PATCH V2 19/25] perf/x86: Support filter_match callback kan.liang
2021-03-10 16:37 ` [PATCH V2 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-03-11 12:51   ` Peter Zijlstra
2021-03-11 16:09   ` Peter Zijlstra
2021-03-11 16:32     ` Peter Zijlstra
2021-03-11 17:31       ` Liang, Kan
2021-03-11 16:53     ` Liang, Kan
2021-03-11 17:25       ` Liang, Kan
2021-03-11 19:58       ` Peter Zijlstra
2021-03-11 20:30         ` Andi Kleen
2021-03-11 20:37           ` Peter Zijlstra
2021-03-11 20:32         ` Liang, Kan
2021-03-11 20:47           ` Peter Zijlstra
2021-03-11 21:09             ` Luck, Tony
2021-03-11 21:43               ` Peter Zijlstra
2021-03-12  0:00               ` Andi Kleen
2021-03-10 16:37 ` [PATCH V2 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-03-10 16:37 ` [PATCH V2 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-03-10 16:37 ` [PATCH V2 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-03-10 16:38 ` [PATCH V2 24/25] perf/x86/cstate: " kan.liang
2021-03-10 16:38 ` [PATCH V2 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e8dd446f-f57c-dfbd-d923-b313411b74a0@linux.intel.com \
    --to=kan.liang@linux.intel.com \
    --cc=acme@kernel.org \
    --cc=adrian.hunter@intel.com \
    --cc=ak@linux.intel.com \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=bp@alien8.de \
    --cc=dave.hansen@intel.com \
    --cc=jolsa@redhat.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@kernel.org \
    --cc=namhyung@kernel.org \
    --cc=peterz@infradead.org \
    --cc=tglx@linutronix.de \
    --cc=yao.jin@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.