[PATCH 0/6] Enable miscellaneous hardware blocks to boot WPSS

[PATCH 0/6] Enable miscellaneous hardware blocks to boot WPSS

[Sibi Sankar]

This series enables miscellaneous hardware blocks to boot Wireless
Processor Subsystem (WPSS) on SC7280 SoC.

[1] https://lore.kernel.org/patchwork/cover/1389010/
The series depends on ^^

Sibi Sankar (6):
  soc: qcom: smem: Update max processor count
  dt-bindings: mailbox: Add WPSS client index to IPCC
  dt-bindings: reset: aoss: Add AOSS reset controller binding
  dt-bindings: reset: pdc: Add PDC Global bindings
  reset: qcom: Add PDC Global reset signals for WPSS
  arm64: dts: qcom: sc7280: Add nodes to boot WPSS

 .../devicetree/bindings/reset/qcom,aoss-reset.yaml |   5 +
 .../devicetree/bindings/reset/qcom,pdc-global.yaml |   4 +
 arch/arm64/boot/dts/qcom/sc7280.dtsi               | 143 +++++++++++++++++++++
 drivers/reset/reset-qcom-pdc.c                     |  62 +++++++--
 drivers/soc/qcom/smem.c                            |   2 +-
 include/dt-bindings/mailbox/qcom-ipcc.h            |   1 +
 include/dt-bindings/reset/qcom,sdm845-pdc.h        |   2 +
 7 files changed, 207 insertions(+), 12 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 1/6] soc: qcom: smem: Update max processor count

[Sibi Sankar]

Update max processor count to reflect the number of co-processors on
SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/soc/qcom/smem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index cc4e0655a47b..4fb5aeeb0843 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -84,7 +84,7 @@
 #define SMEM_GLOBAL_HOST	0xfffe
 
 /* Max number of processors/hosts in a system */
-#define SMEM_HOST_COUNT		11
+#define SMEM_HOST_COUNT		14
 
 /**
   * struct smem_proc_comm - proc_comm communication struct (legacy)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/6] dt-bindings: mailbox: Add WPSS client index to IPCC

[Sibi Sankar]

Add WPSS remote processor client index to Inter-Processor Communication
Controller (IPCC) block.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 include/dt-bindings/mailbox/qcom-ipcc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h
index 4c23eefed5f3..eb91a6c05b71 100644
--- a/include/dt-bindings/mailbox/qcom-ipcc.h
+++ b/include/dt-bindings/mailbox/qcom-ipcc.h
@@ -29,5 +29,6 @@
 #define IPCC_CLIENT_PCIE1		14
 #define IPCC_CLIENT_PCIE2		15
 #define IPCC_CLIENT_SPSS		16
+#define IPCC_CLIENT_WPSS		24
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 3/6] dt-bindings: reset: aoss: Add AOSS reset controller binding

[Sibi Sankar]

Add AOSS reset controller bindings for SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
index e2d85a1e1d63..a054757f4d9f 100644
--- a/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml
@@ -21,6 +21,11 @@ properties:
           - const: "qcom,sc7180-aoss-cc"
           - const: "qcom,sdm845-aoss-cc"
 
+      - description: on SC7280 SoCs the following compatibles must be specified
+        items:
+          - const: "qcom,sc7280-aoss-cc"
+          - const: "qcom,sdm845-aoss-cc"
+
       - description: on SDM845 SoCs the following compatibles must be specified
         items:
           - const: "qcom,sdm845-aoss-cc"
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings

[Sibi Sankar]

Add PDC Global reset controller bindings for SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++
 include/dt-bindings/reset/qcom,sdm845-pdc.h                  | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
index d7d8cec9419f..831ea8d5d83f 100644
--- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
@@ -21,6 +21,10 @@ properties:
           - const: "qcom,sc7180-pdc-global"
           - const: "qcom,sdm845-pdc-global"
 
+      - description: on SC7280 SoCs the following compatibles must be specified
+        items:
+          - const: "qcom,sc7280-pdc-global"
+
       - description: on SDM845 SoCs the following compatibles must be specified
         items:
           - const: "qcom,sdm845-pdc-global"
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
index 53c37f9c319a..03a0c0eb8147 100644
--- a/include/dt-bindings/reset/qcom,sdm845-pdc.h
+++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
@@ -16,5 +16,7 @@
 #define PDC_DISPLAY_SYNC_RESET	7
 #define PDC_COMPUTE_SYNC_RESET	8
 #define PDC_MODEM_SYNC_RESET	9
+#define PDC_WLAN_RF_SYNC_RESET	10
+#define PDC_WPSS_SYNC_RESET	11
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 5/6] reset: qcom: Add PDC Global reset signals for WPSS

[Sibi Sankar]

Add PDC Global reset signals for Wireless Processor Subsystem (WPSS)
on SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/reset/reset-qcom-pdc.c | 62 ++++++++++++++++++++++++++++++++++--------
 1 file changed, 51 insertions(+), 11 deletions(-)

diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
index ab74bccd4a5b..bb7113ae6232 100644
--- a/drivers/reset/reset-qcom-pdc.c
+++ b/drivers/reset/reset-qcom-pdc.c
@@ -11,18 +11,26 @@
 
 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
 
-#define RPMH_PDC_SYNC_RESET	0x100
+#define RPMH_SDM845_PDC_SYNC_RESET	0x100
+#define RPMH_SC7280_PDC_SYNC_RESET	0x1000
 
 struct qcom_pdc_reset_map {
 	u8 bit;
 };
 
+struct qcom_pdc_reset_desc {
+	const struct qcom_pdc_reset_map *resets;
+	unsigned int offset;
+	size_t num_resets;
+};
+
 struct qcom_pdc_reset_data {
 	struct reset_controller_dev rcdev;
 	struct regmap *regmap;
+	const struct qcom_pdc_reset_desc *desc;
 };
 
-static const struct regmap_config sdm845_pdc_regmap_config = {
+static const struct regmap_config pdc_regmap_config = {
 	.name		= "pdc-reset",
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -44,6 +52,33 @@ static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
 	[PDC_MODEM_SYNC_RESET] = {9},
 };
 
+static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
+	.resets = sdm845_pdc_resets,
+	.offset = RPMH_SDM845_PDC_SYNC_RESET,
+	.num_resets = ARRAY_SIZE(sdm845_pdc_resets),
+};
+
+static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
+	[PDC_APPS_SYNC_RESET] = {0},
+	[PDC_SP_SYNC_RESET] = {1},
+	[PDC_AUDIO_SYNC_RESET] = {2},
+	[PDC_SENSORS_SYNC_RESET] = {3},
+	[PDC_AOP_SYNC_RESET] = {4},
+	[PDC_DEBUG_SYNC_RESET] = {5},
+	[PDC_GPU_SYNC_RESET] = {6},
+	[PDC_DISPLAY_SYNC_RESET] = {7},
+	[PDC_COMPUTE_SYNC_RESET] = {8},
+	[PDC_MODEM_SYNC_RESET] = {9},
+	[PDC_WLAN_RF_SYNC_RESET] = {10},
+	[PDC_WPSS_SYNC_RESET] = {11},
+};
+
+static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
+	.resets = sc7280_pdc_resets,
+	.offset = RPMH_SC7280_PDC_SYNC_RESET,
+	.num_resets = ARRAY_SIZE(sc7280_pdc_resets),
+};
+
 static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
 				struct reset_controller_dev *rcdev)
 {
@@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
 					unsigned long idx)
 {
 	struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+	const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
 
-	return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
-				  BIT(sdm845_pdc_resets[idx].bit),
-				  BIT(sdm845_pdc_resets[idx].bit));
+	return regmap_update_bits(data->regmap, data->desc->offset, BIT(map->bit), BIT(map->bit));
 }
 
 static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
 					unsigned long idx)
 {
 	struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+	const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
 
-	return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
-				  BIT(sdm845_pdc_resets[idx].bit), 0);
+	return regmap_update_bits(data->regmap, data->desc->offset, BIT(map->bit), 0);
 }
 
 static const struct reset_control_ops qcom_pdc_reset_ops = {
@@ -76,22 +110,27 @@ static const struct reset_control_ops qcom_pdc_reset_ops = {
 
 static int qcom_pdc_reset_probe(struct platform_device *pdev)
 {
+	const struct qcom_pdc_reset_desc *desc;
 	struct qcom_pdc_reset_data *data;
 	struct device *dev = &pdev->dev;
 	void __iomem *base;
 	struct resource *res;
 
+	desc = device_get_match_data(&pdev->dev);
+	if (!desc)
+		return -EINVAL;
+
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 
+	data->desc = desc;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
-	data->regmap = devm_regmap_init_mmio(dev, base,
-					     &sdm845_pdc_regmap_config);
+	data->regmap = devm_regmap_init_mmio(dev, base, &pdc_regmap_config);
 	if (IS_ERR(data->regmap)) {
 		dev_err(dev, "Unable to initialize regmap\n");
 		return PTR_ERR(data->regmap);
@@ -99,14 +138,15 @@ static int qcom_pdc_reset_probe(struct platform_device *pdev)
 
 	data->rcdev.owner = THIS_MODULE;
 	data->rcdev.ops = &qcom_pdc_reset_ops;
-	data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
+	data->rcdev.nr_resets = desc->num_resets;
 	data->rcdev.of_node = dev->of_node;
 
 	return devm_reset_controller_register(dev, &data->rcdev);
 }
 
 static const struct of_device_id qcom_pdc_reset_of_match[] = {
-	{ .compatible = "qcom,sdm845-pdc-global" },
+	{ .compatible = "qcom,sc7280-pdc-global", .data = &sc7280_pdc_reset_desc },
+	{ .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_reset_desc },
 	{}
 };
 MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

[Sibi Sankar]

Add miscellaneous nodes to boot the Wireless Processor Subsystem on
SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---

https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
Depends on ipcc dt node enablement from ^^ 

 arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++
 1 file changed, 143 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 18637c369c1d..4f03c468df51 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -10,6 +10,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
@@ -50,6 +52,11 @@
 			no-map;
 		};
 
+		smem_mem: memory@80900000 {
+			reg = <0x0 0x80900000 0x0 0x200000>;
+			no-map;
+		};
+
 		cpucp_mem: memory@80b00000 {
 			no-map;
 			reg = <0x0 0x80b00000 0x0 0x100000>;
@@ -244,12 +251,131 @@
 		reg = <0 0x80000000 0 0>;
 	};
 
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_regs 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
 	firmware {
 		scm {
 			compatible = "qcom,scm-sc7280", "qcom,scm";
 		};
 	};
 
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-mpss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_MPSS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		ipa_smp2p_out: ipa-ap-to-modem {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		ipa_smp2p_in: ipa-modem-to-ap {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wpss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <617>, <616>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_WPSS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <13>;
+
+		wpss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wpss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -315,6 +441,11 @@
 			};
 		};
 
+		tcsr_mutex_regs: syscon@1f40000 {
+			compatible = "syscon";
+			reg = <0 0x01f40000 0 0x40000>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sc7280-pdc", "qcom,pdc";
 			reg = <0 0x0b220000 0 0x30000>;
@@ -328,6 +459,18 @@
 			interrupt-controller;
 		};
 
+		pdc_reset: reset-controller@b5e0000 {
+			compatible = "qcom,sc7280-pdc-global";
+			reg = <0 0x0b5e0000 0 0x20000>;
+			#reset-cells = <1>;
+		};
+
+		aoss_reset: reset-controller@c2a0000 {
+			compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
+			reg = <0 0x0c2a0000 0 0x31000>;
+			#reset-cells = <1>;
+		};
+
 		spmi_bus: spmi@c440000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0 0x0c440000 0 0x1100>,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/6] soc: qcom: smem: Update max processor count

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:51:46)
> Update max processor count to reflect the number of co-processors on
> SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH 2/6] dt-bindings: mailbox: Add WPSS client index to IPCC

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:51:47)
> Add WPSS remote processor client index to Inter-Processor Communication
> Controller (IPCC) block.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH 3/6] dt-bindings: reset: aoss: Add AOSS reset controller binding

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:51:48)
> Add AOSS reset controller bindings for SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:51:49)
> Add PDC Global reset controller bindings for SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++
>  include/dt-bindings/reset/qcom,sdm845-pdc.h                  | 2 ++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
> index d7d8cec9419f..831ea8d5d83f 100644
> --- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
> @@ -21,6 +21,10 @@ properties:
>            - const: "qcom,sc7180-pdc-global"
>            - const: "qcom,sdm845-pdc-global"
>  
> +      - description: on SC7280 SoCs the following compatibles must be specified
> +        items:
> +          - const: "qcom,sc7280-pdc-global"

Somehow this one can drop sdm845-pdc-global but aoss-cc can't?

> +
>        - description: on SDM845 SoCs the following compatibles must be specified
>          items:
>            - const: "qcom,sdm845-pdc-global"

Re: [PATCH 5/6] reset: qcom: Add PDC Global reset signals for WPSS

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:51:50)
> Add PDC Global reset signals for Wireless Processor Subsystem (WPSS)
> on SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  drivers/reset/reset-qcom-pdc.c | 62 ++++++++++++++++++++++++++++++++++--------
>  1 file changed, 51 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
> index ab74bccd4a5b..bb7113ae6232 100644
> --- a/drivers/reset/reset-qcom-pdc.c
> +++ b/drivers/reset/reset-qcom-pdc.c
> @@ -11,18 +11,26 @@
>  
>  #include <dt-bindings/reset/qcom,sdm845-pdc.h>
>  
> -#define RPMH_PDC_SYNC_RESET    0x100
> +#define RPMH_SDM845_PDC_SYNC_RESET     0x100
> +#define RPMH_SC7280_PDC_SYNC_RESET     0x1000
>  
>  struct qcom_pdc_reset_map {
>         u8 bit;
>  };
>  
> +struct qcom_pdc_reset_desc {
> +       const struct qcom_pdc_reset_map *resets;
> +       unsigned int offset;
> +       size_t num_resets;

Please put num_resets next to resets and move offset before or after the
block. That way we know that resets and num_resets are related because
they're right next to each other.

> +};
> +
>  struct qcom_pdc_reset_data {
>         struct reset_controller_dev rcdev;
>         struct regmap *regmap;
> +       const struct qcom_pdc_reset_desc *desc;
>  };
>  
> -static const struct regmap_config sdm845_pdc_regmap_config = {
> +static const struct regmap_config pdc_regmap_config = {
>         .name           = "pdc-reset",
>         .reg_bits       = 32,
>         .reg_stride     = 4,

Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

[Stephen Boyd]

Quoting Sibi Sankar (2021-03-08 21:51:51)
> Add miscellaneous nodes to boot the Wireless Processor Subsystem on

Maybe add (WPSS) after the name so we know they're related.

> SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> 
> https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
> Depends on ipcc dt node enablement from ^^ 
> 
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++
>  1 file changed, 143 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 18637c369c1d..4f03c468df51 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -244,12 +251,131 @@
>                 reg = <0 0x80000000 0 0>;
>         };
>  
> +       tcsr_mutex: hwlock {
> +               compatible = "qcom,tcsr-mutex";
> +               syscon = <&tcsr_mutex_regs 0 0x1000>;
> +               #hwlock-cells = <1>;
> +       };

Is this node in the right place? I think the node above it is 'memory'?
In which case 'hwlock' comes before 'memory' alphabetically.

> +
> +       smem {
> +               compatible = "qcom,smem";
> +               memory-region = <&smem_mem>;
> +               hwlocks = <&tcsr_mutex 3>;
> +       };
> +
>         firmware {
>                 scm {
>                         compatible = "qcom,scm-sc7280", "qcom,scm";
>                 };
>         };
>  
> +       smp2p-adsp {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <443>, <429>;
> +               interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
> +                                            IPCC_MPROC_SIGNAL_SMP2P
> +                                            IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&ipcc IPCC_CLIENT_LPASS
> +                               IPCC_MPROC_SIGNAL_SMP2P>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <2>;
> +
> +               adsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               adsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-cdsp {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <94>, <432>;
> +               interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
> +                                            IPCC_MPROC_SIGNAL_SMP2P
> +                                            IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&ipcc IPCC_CLIENT_CDSP
> +                               IPCC_MPROC_SIGNAL_SMP2P>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <5>;
> +
> +               cdsp_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               cdsp_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +
> +       smp2p-mpss {
> +               compatible = "qcom,smp2p";
> +               qcom,smem = <435>, <428>;
> +               interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> +                                            IPCC_MPROC_SIGNAL_SMP2P
> +                                            IRQ_TYPE_EDGE_RISING>;
> +               mboxes = <&ipcc IPCC_CLIENT_MPSS
> +                               IPCC_MPROC_SIGNAL_SMP2P>;
> +
> +               qcom,local-pid = <0>;
> +               qcom,remote-pid = <1>;
> +
> +               modem_smp2p_out: master-kernel {
> +                       qcom,entry-name = "master-kernel";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               modem_smp2p_in: slave-kernel {
> +                       qcom,entry-name = "slave-kernel";

Do these names need to have 'master' and 'slave' in them? We're trying
to avoid these terms. See Documentation/process/coding-style.rst Section
4 naming.

> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +
> +               ipa_smp2p_out: ipa-ap-to-modem {
> +                       qcom,entry-name = "ipa";
> +                       #qcom,smem-state-cells = <1>;
> +               };
> +
> +               ipa_smp2p_in: ipa-modem-to-ap {
> +                       qcom,entry-name = "ipa";
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +

Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

[Bjorn Andersson]

On Sat 13 Mar 15:46 CST 2021, Stephen Boyd wrote:

> Quoting Sibi Sankar (2021-03-08 21:51:51)
> > Add miscellaneous nodes to boot the Wireless Processor Subsystem on
> 
> Maybe add (WPSS) after the name so we know they're related.
> 
> > SC7280 SoCs.
> > 
> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > ---
> > 
> > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
> > Depends on ipcc dt node enablement from ^^ 
> > 
> >  arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 143 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 18637c369c1d..4f03c468df51 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -244,12 +251,131 @@
> >                 reg = <0 0x80000000 0 0>;
> >         };
> >  
> > +       tcsr_mutex: hwlock {
> > +               compatible = "qcom,tcsr-mutex";
> > +               syscon = <&tcsr_mutex_regs 0 0x1000>;
> > +               #hwlock-cells = <1>;
> > +       };
> 
> Is this node in the right place? I think the node above it is 'memory'?
> In which case 'hwlock' comes before 'memory' alphabetically.
> 

Thanks for spotting this, as it's no longer acceptable to have a
standalone "syscon" node I was asked to rewrite the binding for this a
few months ago. So the tcsr_mutex should now be represented with a reg
under /soc.

> > +
> > +       smem {
> > +               compatible = "qcom,smem";
> > +               memory-region = <&smem_mem>;
> > +               hwlocks = <&tcsr_mutex 3>;
> > +       };
> > +
> >         firmware {
> >                 scm {
> >                         compatible = "qcom,scm-sc7280", "qcom,scm";
> >                 };
> >         };
> >  
> > +       smp2p-adsp {
> > +               compatible = "qcom,smp2p";
> > +               qcom,smem = <443>, <429>;
> > +               interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
> > +                                            IPCC_MPROC_SIGNAL_SMP2P
> > +                                            IRQ_TYPE_EDGE_RISING>;
> > +               mboxes = <&ipcc IPCC_CLIENT_LPASS
> > +                               IPCC_MPROC_SIGNAL_SMP2P>;
> > +
> > +               qcom,local-pid = <0>;
> > +               qcom,remote-pid = <2>;
> > +
> > +               adsp_smp2p_out: master-kernel {
> > +                       qcom,entry-name = "master-kernel";
> > +                       #qcom,smem-state-cells = <1>;
> > +               };
> > +
> > +               adsp_smp2p_in: slave-kernel {
> > +                       qcom,entry-name = "slave-kernel";
> > +                       interrupt-controller;
> > +                       #interrupt-cells = <2>;
> > +               };
> > +       };
> > +
> > +       smp2p-cdsp {
> > +               compatible = "qcom,smp2p";
> > +               qcom,smem = <94>, <432>;
> > +               interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
> > +                                            IPCC_MPROC_SIGNAL_SMP2P
> > +                                            IRQ_TYPE_EDGE_RISING>;
> > +               mboxes = <&ipcc IPCC_CLIENT_CDSP
> > +                               IPCC_MPROC_SIGNAL_SMP2P>;
> > +
> > +               qcom,local-pid = <0>;
> > +               qcom,remote-pid = <5>;
> > +
> > +               cdsp_smp2p_out: master-kernel {
> > +                       qcom,entry-name = "master-kernel";
> > +                       #qcom,smem-state-cells = <1>;
> > +               };
> > +
> > +               cdsp_smp2p_in: slave-kernel {
> > +                       qcom,entry-name = "slave-kernel";
> > +                       interrupt-controller;
> > +                       #interrupt-cells = <2>;
> > +               };
> > +       };
> > +
> > +       smp2p-mpss {
> > +               compatible = "qcom,smp2p";
> > +               qcom,smem = <435>, <428>;
> > +               interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> > +                                            IPCC_MPROC_SIGNAL_SMP2P
> > +                                            IRQ_TYPE_EDGE_RISING>;
> > +               mboxes = <&ipcc IPCC_CLIENT_MPSS
> > +                               IPCC_MPROC_SIGNAL_SMP2P>;
> > +
> > +               qcom,local-pid = <0>;
> > +               qcom,remote-pid = <1>;
> > +
> > +               modem_smp2p_out: master-kernel {
> > +                       qcom,entry-name = "master-kernel";
> > +                       #qcom,smem-state-cells = <1>;
> > +               };
> > +
> > +               modem_smp2p_in: slave-kernel {
> > +                       qcom,entry-name = "slave-kernel";
> 
> Do these names need to have 'master' and 'slave' in them? We're trying
> to avoid these terms. See Documentation/process/coding-style.rst Section
> 4 naming.
> 

They need to match the naming in the firmware, but I would welcome a
future change to something in line with the coding style and simply more
descriptive.

Regards,
Bjorn

> > +                       interrupt-controller;
> > +                       #interrupt-cells = <2>;
> > +               };
> > +
> > +               ipa_smp2p_out: ipa-ap-to-modem {
> > +                       qcom,entry-name = "ipa";
> > +                       #qcom,smem-state-cells = <1>;
> > +               };
> > +
> > +               ipa_smp2p_in: ipa-modem-to-ap {
> > +                       qcom,entry-name = "ipa";
> > +                       interrupt-controller;
> > +                       #interrupt-cells = <2>;
> > +               };
> > +       };
> > +

Re: [PATCH 2/6] dt-bindings: mailbox: Add WPSS client index to IPCC

[Rob Herring]

On Tue, 09 Mar 2021 11:21:47 +0530, Sibi Sankar wrote:
> Add WPSS remote processor client index to Inter-Processor Communication
> Controller (IPCC) block.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  include/dt-bindings/mailbox/qcom-ipcc.h | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 3/6] dt-bindings: reset: aoss: Add AOSS reset controller binding

[Rob Herring]

On Tue, 09 Mar 2021 11:21:48 +0530, Sibi Sankar wrote:
> Add AOSS reset controller bindings for SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings

[Rob Herring]

On Tue, 09 Mar 2021 11:21:49 +0530, Sibi Sankar wrote:
> Add PDC Global reset controller bindings for SC7280 SoCs.
> 
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++
>  include/dt-bindings/reset/qcom,sdm845-pdc.h                  | 2 ++
>  2 files changed, 6 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

[Stephen Boyd]

Quoting Bjorn Andersson (2021-03-13 20:16:39)
> On Sat 13 Mar 15:46 CST 2021, Stephen Boyd wrote:
> 
> > Quoting Sibi Sankar (2021-03-08 21:51:51)
> > > Add miscellaneous nodes to boot the Wireless Processor Subsystem on
> > 
> > Maybe add (WPSS) after the name so we know they're related.
> > 
> > > SC7280 SoCs.
> > > 
> > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> > > ---
> > > 
> > > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
> > > Depends on ipcc dt node enablement from ^^ 
> > > 
> > >  arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 143 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index 18637c369c1d..4f03c468df51 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > @@ -244,12 +251,131 @@
> > >                 reg = <0 0x80000000 0 0>;
> > >         };
> > >  
> > > +       tcsr_mutex: hwlock {
> > > +               compatible = "qcom,tcsr-mutex";
> > > +               syscon = <&tcsr_mutex_regs 0 0x1000>;
> > > +               #hwlock-cells = <1>;
> > > +       };
> > 
> > Is this node in the right place? I think the node above it is 'memory'?
> > In which case 'hwlock' comes before 'memory' alphabetically.
> > 
> 
> Thanks for spotting this, as it's no longer acceptable to have a
> standalone "syscon" node I was asked to rewrite the binding for this a
> few months ago. So the tcsr_mutex should now be represented with a reg
> under /soc.

Oh nice, I wasn't aware.

> > > +                       #interrupt-cells = <2>;
> > > +               };
> > > +       };
> > > +
> > > +       smp2p-mpss {
> > > +               compatible = "qcom,smp2p";
> > > +               qcom,smem = <435>, <428>;
> > > +               interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> > > +                                            IPCC_MPROC_SIGNAL_SMP2P
> > > +                                            IRQ_TYPE_EDGE_RISING>;
> > > +               mboxes = <&ipcc IPCC_CLIENT_MPSS
> > > +                               IPCC_MPROC_SIGNAL_SMP2P>;
> > > +
> > > +               qcom,local-pid = <0>;
> > > +               qcom,remote-pid = <1>;
> > > +
> > > +               modem_smp2p_out: master-kernel {
> > > +                       qcom,entry-name = "master-kernel";
> > > +                       #qcom,smem-state-cells = <1>;
> > > +               };
> > > +
> > > +               modem_smp2p_in: slave-kernel {
> > > +                       qcom,entry-name = "slave-kernel";
> > 
> > Do these names need to have 'master' and 'slave' in them? We're trying
> > to avoid these terms. See Documentation/process/coding-style.rst Section
> > 4 naming.
> > 
> 
> They need to match the naming in the firmware, but I would welcome a
> future change to something in line with the coding style and simply more
> descriptive.
> 

Sibi can this be done? I think it's still pretty early days for the
firmware so hopefully the terms can be replaced with something
different.

Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

[Sibi Sankar]

On 2021-03-24 03:36, Stephen Boyd wrote:
> Quoting Bjorn Andersson (2021-03-13 20:16:39)
>> On Sat 13 Mar 15:46 CST 2021, Stephen Boyd wrote:
>> 
>> > Quoting Sibi Sankar (2021-03-08 21:51:51)
>> > > Add miscellaneous nodes to boot the Wireless Processor Subsystem on
>> >
>> > Maybe add (WPSS) after the name so we know they're related.
>> >
>> > > SC7280 SoCs.
>> > >
>> > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> > > ---
>> > >
>> > > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
>> > > Depends on ipcc dt node enablement from ^^
>> > >
>> > >  arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++
>> > >  1 file changed, 143 insertions(+)
>> > >
>> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > index 18637c369c1d..4f03c468df51 100644
>> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > @@ -244,12 +251,131 @@
>> > >                 reg = <0 0x80000000 0 0>;
>> > >         };
>> > >
>> > > +       tcsr_mutex: hwlock {
>> > > +               compatible = "qcom,tcsr-mutex";
>> > > +               syscon = <&tcsr_mutex_regs 0 0x1000>;
>> > > +               #hwlock-cells = <1>;
>> > > +       };
>> >
>> > Is this node in the right place? I think the node above it is 'memory'?
>> > In which case 'hwlock' comes before 'memory' alphabetically.
>> >
>> 
>> Thanks for spotting this, as it's no longer acceptable to have a
>> standalone "syscon" node I was asked to rewrite the binding for this a
>> few months ago. So the tcsr_mutex should now be represented with a reg
>> under /soc.
> 
> Oh nice, I wasn't aware.
> 
>> > > +                       #interrupt-cells = <2>;
>> > > +               };
>> > > +       };
>> > > +
>> > > +       smp2p-mpss {
>> > > +               compatible = "qcom,smp2p";
>> > > +               qcom,smem = <435>, <428>;
>> > > +               interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
>> > > +                                            IPCC_MPROC_SIGNAL_SMP2P
>> > > +                                            IRQ_TYPE_EDGE_RISING>;
>> > > +               mboxes = <&ipcc IPCC_CLIENT_MPSS
>> > > +                               IPCC_MPROC_SIGNAL_SMP2P>;
>> > > +
>> > > +               qcom,local-pid = <0>;
>> > > +               qcom,remote-pid = <1>;
>> > > +
>> > > +               modem_smp2p_out: master-kernel {
>> > > +                       qcom,entry-name = "master-kernel";
>> > > +                       #qcom,smem-state-cells = <1>;
>> > > +               };
>> > > +
>> > > +               modem_smp2p_in: slave-kernel {
>> > > +                       qcom,entry-name = "slave-kernel";
>> >
>> > Do these names need to have 'master' and 'slave' in them? We're trying
>> > to avoid these terms. See Documentation/process/coding-style.rst Section
>> > 4 naming.
>> >
>> 
>> They need to match the naming in the firmware, but I would welcome a
>> future change to something in line with the coding style and simply 
>> more
>> descriptive.
>> 
> 
> Sibi can this be done? I think it's still pretty early days for the
> firmware so hopefully the terms can be replaced with something
> different.

I'll discuss the ask with the modem fw team and
get back.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

[Sibi Sankar]

On 2021-03-24 12:19, Sibi Sankar wrote:
> On 2021-03-24 03:36, Stephen Boyd wrote:
>> Quoting Bjorn Andersson (2021-03-13 20:16:39)
>>> On Sat 13 Mar 15:46 CST 2021, Stephen Boyd wrote:
>>> 
>>> > Quoting Sibi Sankar (2021-03-08 21:51:51)
>>> > > Add miscellaneous nodes to boot the Wireless Processor Subsystem on
>>> >
>>> > Maybe add (WPSS) after the name so we know they're related.
>>> >
>>> > > SC7280 SoCs.
>>> > >
>>> > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>>> > > ---
>>> > >
>>> > > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
>>> > > Depends on ipcc dt node enablement from ^^
>>> > >
>>> > >  arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 +++++++++++++++++++++++++++++++++++
>>> > >  1 file changed, 143 insertions(+)
>>> > >
>>> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> > > index 18637c369c1d..4f03c468df51 100644
>>> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> > > @@ -244,12 +251,131 @@
>>> > >                 reg = <0 0x80000000 0 0>;
>>> > >         };
>>> > >
>>> > > +       tcsr_mutex: hwlock {
>>> > > +               compatible = "qcom,tcsr-mutex";
>>> > > +               syscon = <&tcsr_mutex_regs 0 0x1000>;
>>> > > +               #hwlock-cells = <1>;
>>> > > +       };
>>> >
>>> > Is this node in the right place? I think the node above it is 'memory'?
>>> > In which case 'hwlock' comes before 'memory' alphabetically.
>>> >
>>> 
>>> Thanks for spotting this, as it's no longer acceptable to have a
>>> standalone "syscon" node I was asked to rewrite the binding for this 
>>> a
>>> few months ago. So the tcsr_mutex should now be represented with a 
>>> reg
>>> under /soc.
>> 
>> Oh nice, I wasn't aware.
>> 
>>> > > +                       #interrupt-cells = <2>;
>>> > > +               };
>>> > > +       };
>>> > > +
>>> > > +       smp2p-mpss {
>>> > > +               compatible = "qcom,smp2p";
>>> > > +               qcom,smem = <435>, <428>;
>>> > > +               interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
>>> > > +                                            IPCC_MPROC_SIGNAL_SMP2P
>>> > > +                                            IRQ_TYPE_EDGE_RISING>;
>>> > > +               mboxes = <&ipcc IPCC_CLIENT_MPSS
>>> > > +                               IPCC_MPROC_SIGNAL_SMP2P>;
>>> > > +
>>> > > +               qcom,local-pid = <0>;
>>> > > +               qcom,remote-pid = <1>;
>>> > > +
>>> > > +               modem_smp2p_out: master-kernel {
>>> > > +                       qcom,entry-name = "master-kernel";
>>> > > +                       #qcom,smem-state-cells = <1>;
>>> > > +               };
>>> > > +
>>> > > +               modem_smp2p_in: slave-kernel {
>>> > > +                       qcom,entry-name = "slave-kernel";
>>> >
>>> > Do these names need to have 'master' and 'slave' in them? We're trying
>>> > to avoid these terms. See Documentation/process/coding-style.rst Section
>>> > 4 naming.
>>> >
>>> 
>>> They need to match the naming in the firmware, but I would welcome a
>>> future change to something in line with the coding style and simply 
>>> more
>>> descriptive.
>>> 
>> 
>> Sibi can this be done? I think it's still pretty early days for the
>> firmware so hopefully the terms can be replaced with something
>> different.
> 
> I'll discuss the ask with the modem fw team and
> get back.

Sorry for the delayed response. Looks
like it's something Qualcomm wouldn't
want to do mid-project since a number
of the fw images are re-used across
platforms. But this is something that
will be taken up on newer SoCs.

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a Linux Foundation Collaborative Project.

Re: [PATCH 4/6] dt-bindings: reset: pdc: Add PDC Global bindings

[Sibi Sankar]

On 2021-03-14 03:07, Stephen Boyd wrote:
> Quoting Sibi Sankar (2021-03-08 21:51:49)
>> Add PDC Global reset controller bindings for SC7280 SoCs.
>> 
>> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
>> ---
>>  Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++
>>  include/dt-bindings/reset/qcom,sdm845-pdc.h                  | 2 ++
>>  2 files changed, 6 insertions(+)
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml 
>> b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
>> index d7d8cec9419f..831ea8d5d83f 100644
>> --- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
>> +++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
>> @@ -21,6 +21,10 @@ properties:
>>            - const: "qcom,sc7180-pdc-global"
>>            - const: "qcom,sdm845-pdc-global"
>> 
>> +      - description: on SC7280 SoCs the following compatibles must be 
>> specified
>> +        items:
>> +          - const: "qcom,sc7280-pdc-global"
> 
> Somehow this one can drop sdm845-pdc-global but aoss-cc can't?

I missed replying to ^^. aoss-cc
reset is identical to that found
on SDM845 SoC but the pdc-reset
differs in the number of resets
and offset within the pdc register
space.

> 
>> +
>>        - description: on SDM845 SoCs the following compatibles must be 
>> specified
>>          items:
>>            - const: "qcom,sdm845-pdc-global"

-- 
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a Linux Foundation Collaborative Project.

[PATCH 1/6] soc: qcom: smem: Update max processor count

[Sibi Sankar]

Update max processor count to reflect the number of
co-processors on SC7180 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/soc/qcom/smem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index f27c00d82ae49..bef8502625f96 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -84,7 +84,7 @@
 #define SMEM_GLOBAL_HOST	0xfffe
 
 /* Max number of processors/hosts in a system */
-#define SMEM_HOST_COUNT		10
+#define SMEM_HOST_COUNT		11
 
 /**
   * struct smem_proc_comm - proc_comm communication struct (legacy)
-- 
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