From: Manish Narani <manish.narani@xilinx.com> To: <gregkh@linuxfoundation.org>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>, <balbi@kernel.org>, <p.zabel@pengutronix.de> Cc: <git@xilinx.com>, <linux-usb@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Manish Narani <manish.narani@xilinx.com> Subject: [PATCH v4 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller Date: Wed, 17 Mar 2021 12:22:28 +0530 [thread overview] Message-ID: <1615963949-75320-2-git-send-email-manish.narani@xilinx.com> (raw) In-Reply-To: <1615963949-75320-1-git-send-email-manish.narani@xilinx.com> Add documentation for Versal DWC3 controller. Add required property 'reg' for the same. Also add optional properties for snps,dwc3. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/usb/dwc3-xilinx.txt | 28 ++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt index a668f43..04813a4 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt @@ -1,32 +1,56 @@ Xilinx SuperSpeed DWC3 USB SoC controller Required properties: -- compatible: Should contain "xlnx,zynqmp-dwc3" +- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3" +- reg: Base address and length of the register control block - clocks: A list of phandles for the clocks listed in clock-names - clock-names: Should contain the following: "bus_clk" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation "ref_clk" Clock source to core during PHY power down +- resets: A list of phandles for resets listed in reset-names +- reset-names: + "usb_crst" USB core reset + "usb_hibrst" USB hibernation reset + "usb_apbrst" USB APB reset Required child node: A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. +Optional properties for snps,dwc3: +- dma-coherent: Enable this flag if CCI is enabled in design. Adding this + flag configures Global SoC bus Configuration Register and + Xilinx USB 3.0 IP - USB coherency register to enable CCI. +- interrupt-names: Should contain the following: + "dwc_usb3" USB gadget mode interrupts + "otg" USB OTG mode interrupts + "hiber" USB hibernation interrupts + Example device node: usb@0 { #address-cells = <0x2>; #size-cells = <0x1>; compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3@fe200000 { compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x40000>; - interrupts = <0x0 0x41 0x4>; + interrupt-names = "dwc_usb3", "otg", "hiber"; + interrupts = <0 65 4>, <0 69 4>, <0 75 4>; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + phy-names = "usb3-phy"; dr_mode = "host"; + dma-coherent; }; }; -- 2.1.1
WARNING: multiple messages have this Message-ID (diff)
From: Manish Narani <manish.narani@xilinx.com> To: <gregkh@linuxfoundation.org>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>, <balbi@kernel.org>, <p.zabel@pengutronix.de> Cc: <git@xilinx.com>, <linux-usb@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, Manish Narani <manish.narani@xilinx.com> Subject: [PATCH v4 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller Date: Wed, 17 Mar 2021 12:22:28 +0530 [thread overview] Message-ID: <1615963949-75320-2-git-send-email-manish.narani@xilinx.com> (raw) In-Reply-To: <1615963949-75320-1-git-send-email-manish.narani@xilinx.com> Add documentation for Versal DWC3 controller. Add required property 'reg' for the same. Also add optional properties for snps,dwc3. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/usb/dwc3-xilinx.txt | 28 ++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt index a668f43..04813a4 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt @@ -1,32 +1,56 @@ Xilinx SuperSpeed DWC3 USB SoC controller Required properties: -- compatible: Should contain "xlnx,zynqmp-dwc3" +- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3" +- reg: Base address and length of the register control block - clocks: A list of phandles for the clocks listed in clock-names - clock-names: Should contain the following: "bus_clk" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation "ref_clk" Clock source to core during PHY power down +- resets: A list of phandles for resets listed in reset-names +- reset-names: + "usb_crst" USB core reset + "usb_hibrst" USB hibernation reset + "usb_apbrst" USB APB reset Required child node: A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. +Optional properties for snps,dwc3: +- dma-coherent: Enable this flag if CCI is enabled in design. Adding this + flag configures Global SoC bus Configuration Register and + Xilinx USB 3.0 IP - USB coherency register to enable CCI. +- interrupt-names: Should contain the following: + "dwc_usb3" USB gadget mode interrupts + "otg" USB OTG mode interrupts + "hiber" USB hibernation interrupts + Example device node: usb@0 { #address-cells = <0x2>; #size-cells = <0x1>; compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; + resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; + reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3@fe200000 { compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x40000>; - interrupts = <0x0 0x41 0x4>; + interrupt-names = "dwc_usb3", "otg", "hiber"; + interrupts = <0 65 4>, <0 69 4>, <0 75 4>; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + phy-names = "usb3-phy"; dr_mode = "host"; + dma-coherent; }; }; -- 2.1.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-03-17 6:54 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-17 6:52 [PATCH v4 0/2] Add a separate DWC3 OF driver for Xilinx platforms Manish Narani 2021-03-17 6:52 ` Manish Narani 2021-03-17 6:52 ` Manish Narani [this message] 2021-03-17 6:52 ` [PATCH v4 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller Manish Narani 2021-03-17 6:52 ` [PATCH v4 2/2] usb: dwc3: Add driver for Xilinx platforms Manish Narani 2021-03-17 6:52 ` Manish Narani 2021-03-17 9:50 ` kernel test robot 2021-03-17 9:50 ` kernel test robot 2021-03-23 11:47 ` Greg KH 2021-03-23 11:47 ` Greg KH 2021-03-23 11:47 ` Greg KH 2021-03-24 9:16 ` Rong Chen 2021-03-24 9:16 ` Rong Chen 2021-03-24 9:16 ` Rong Chen 2021-04-07 21:48 ` Guenter Roeck 2021-04-07 21:48 ` Guenter Roeck 2021-04-08 6:08 ` Michal Simek 2021-04-08 6:08 ` Michal Simek [not found] ` <a7bbf265-a771-2c2e-b5e7-a189692ca280@hoefle.co> 2021-04-08 19:11 ` Marco Hoefle 2021-04-11 14:02 ` Guenter Roeck 2021-04-11 14:02 ` Guenter Roeck 2021-04-12 8:01 ` Michal Simek 2021-04-12 8:01 ` Michal Simek
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1615963949-75320-2-git-send-email-manish.narani@xilinx.com \ --to=manish.narani@xilinx.com \ --cc=balbi@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=git@xilinx.com \ --cc=gregkh@linuxfoundation.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-usb@vger.kernel.org \ --cc=michal.simek@xilinx.com \ --cc=p.zabel@pengutronix.de \ --cc=robh+dt@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.