* [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3
@ 2021-03-10 6:24 Min Hu (Connor)
2021-03-10 6:24 ` [dpdk-dev] [PATCH 1/9] net/hns3: support runtime config to select IO burst func Min Hu (Connor)
` (11 more replies)
0 siblings, 12 replies; 44+ messages in thread
From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
This series add five features according to the 21.05 roadmap, and
also two cleanups added.
Chengchang Tang (1):
net/hns3: support for outer UDP cksum
Chengwen Feng (2):
net/hns3: support runtime config to select IO burst func
net/hns3: support Tx push quick doorbell to improve perf
Hongbo Zheng (4):
net/hns3: adjust the format of RAS related structures
net/hns3: delete redundant xstats RAS statistics
net/hns3: support query Tx descriptor status
net/hns3: support query Rx descriptor status
Min Hu (Connor) (2):
net/hns3: support imissed stats for PF/VF
net/hns3: support oerrors stats in PF
doc/guides/nics/features/hns3.ini | 2 +
doc/guides/nics/features/hns3_vf.ini | 2 +
doc/guides/rel_notes/release_21_05.rst | 5 +
drivers/net/hns3/hns3_cmd.c | 3 +
drivers/net/hns3/hns3_cmd.h | 14 +
drivers/net/hns3/hns3_ethdev.c | 87 +-
drivers/net/hns3/hns3_ethdev.h | 73 +-
drivers/net/hns3/hns3_ethdev_vf.c | 19 +-
drivers/net/hns3/hns3_intr.c | 2127 ++++++++++++++++++--------------
drivers/net/hns3/hns3_regs.h | 2 +
drivers/net/hns3/hns3_rxtx.c | 288 ++++-
drivers/net/hns3/hns3_rxtx.h | 30 +-
drivers/net/hns3/hns3_rxtx_vec_neon.h | 2 +-
drivers/net/hns3/hns3_rxtx_vec_sve.c | 7 +-
drivers/net/hns3/hns3_stats.c | 388 +++---
drivers/net/hns3/hns3_stats.h | 2 +-
16 files changed, 1923 insertions(+), 1128 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 44+ messages in thread* [dpdk-dev] [PATCH 1/9] net/hns3: support runtime config to select IO burst func 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 2/9] net/hns3: support Tx push quick doorbell to improve perf Min Hu (Connor) ` (10 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengwen Feng <fengchengwen@huawei.com> Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration. Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function. This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common. The driver will use the following rules to select io burst func: a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function. b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function. c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function. d. if hint equal common then use the common function. e. if hint not set then: e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function. e.3. else use the common function. Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE). In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 74 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 12 ++++++ drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 54 ++++++++++++++++++------- 5 files changed, 128 insertions(+), 14 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index dc5399f..1d85942 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 9cbcc13..e921924 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6,6 +6,7 @@ #include <rte_bus_pci.h> #include <ethdev_pci.h> #include <rte_pci.h> +#include <rte_kvargs.h> #include "hns3_ethdev.h" #include "hns3_logs.h" @@ -6505,6 +6506,78 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } +static int +hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) +{ + uint32_t hint = HNS3_IO_FUNC_HINT_NONE; + + RTE_SET_USED(key); + + if (strcmp(value, "vec") == 0) + hint = HNS3_IO_FUNC_HINT_VEC; + else if (strcmp(value, "sve") == 0) + hint = HNS3_IO_FUNC_HINT_SVE; + else if (strcmp(value, "simple") == 0) + hint = HNS3_IO_FUNC_HINT_SIMPLE; + else if (strcmp(value, "common") == 0) + hint = HNS3_IO_FUNC_HINT_COMMON; + + /* If the hint is valid then update output parameters */ + if (hint != HNS3_IO_FUNC_HINT_NONE) + *(uint32_t *)extra_args = hint; + + return 0; +} + +static const char * +hns3_get_io_hint_func_name(uint32_t hint) +{ + switch (hint) { + case HNS3_IO_FUNC_HINT_VEC: + return "vec"; + case HNS3_IO_FUNC_HINT_SVE: + return "sve"; + case HNS3_IO_FUNC_HINT_SIMPLE: + return "simple"; + case HNS3_IO_FUNC_HINT_COMMON: + return "common"; + default: + return "none"; + } +} + +void +hns3_parse_devargs(struct rte_eth_dev *dev) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + struct hns3_hw *hw = &hns->hw; + struct rte_kvargs *kvlist; + + if (dev->device->devargs == NULL) + return; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); + if (!kvlist) + return; + + rte_kvargs_process(kvlist, "rx_func_hint", &hns3_parse_io_hint_func, + &rx_func_hint); + rte_kvargs_process(kvlist, "tx_func_hint", &hns3_parse_io_hint_func, + &tx_func_hint); + rte_kvargs_free(kvlist); + + if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed rx_func_hint = %s.", + hns3_get_io_hint_func_name(rx_func_hint)); + hns->rx_func_hint = rx_func_hint; + if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed tx_func_hint = %s.", + hns3_get_io_hint_func_name(tx_func_hint)); + hns->tx_func_hint = tx_func_hint; +} + static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, @@ -6625,6 +6698,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = false; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); /* * Set default max packet size according to the mtu diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 932600d..173848a 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -772,9 +772,20 @@ struct hns3_adapter { bool tx_simple_allowed; bool tx_vec_allowed; + uint32_t rx_func_hint; + uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 @@ -975,6 +986,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); +void hns3_parse_devargs(struct rte_eth_dev *dev); static inline bool is_reset_pending(struct hns3_adapter *hns) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index fd20c52..5dd17c2 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = true; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); ret = hns3_reset_init(hw); if (ret) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 00167c4..f5c7d71 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2689,13 +2689,26 @@ hns3_get_rx_function(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; uint64_t offloads = dev->data->dev_conf.rxmode.offloads; + bool vec_allowed, sve_allowed, simple_allowed; + + vec_allowed = hns->rx_vec_allowed && + hns3_rx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->rx_simple_allowed && !dev->data->scattered_rx && + (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; + + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_recv_pkts_vec; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_recv_pkts_vec_sve; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) + return hns3_recv_pkts; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) + return hns3_recv_scattered_pkts; - if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0) - return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve : - hns3_recv_pkts_vec; - - if (hns->rx_simple_allowed && !dev->data->scattered_rx && - (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0) + if (vec_allowed) + return hns3_recv_pkts_vec; + if (simple_allowed) return hns3_recv_pkts; return hns3_recv_scattered_pkts; @@ -3930,19 +3943,32 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) { uint64_t offloads = dev->data->dev_conf.txmode.offloads; struct hns3_adapter *hns = dev->data->dev_private; + bool vec_allowed, sve_allowed, simple_allowed; - if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) { - *prep = NULL; - return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve : - hns3_xmit_pkts_vec; - } + vec_allowed = hns->tx_vec_allowed && + hns3_tx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->tx_simple_allowed && + offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); - if (hns->tx_simple_allowed && - offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) { - *prep = NULL; + *prep = NULL; + + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_xmit_pkts_vec; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_xmit_pkts_vec_sve; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) return hns3_xmit_pkts_simple; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { + *prep = hns3_prep_pkts; + return hns3_xmit_pkts; } + if (vec_allowed) + return hns3_xmit_pkts_vec; + if (simple_allowed) + return hns3_xmit_pkts_simple; + *prep = hns3_prep_pkts; return hns3_xmit_pkts; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 2/9] net/hns3: support Tx push quick doorbell to improve perf 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 1/9] net/hns3: support runtime config to select IO burst func Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 3/9] net/hns3: support for outer UDP cksum Min Hu (Connor) ` (9 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengwen Feng <fengchengwen@huawei.com> Kunpeng 930 support Tx push mode which could improve performance, It works like below: 1. Add pcie bar45 which support driver direct write the Tx descriptor or tail reg to it. 2. Support three operations: a) direct write one Tx descriptor, b) direct write two Tx descriptors, c) direct write tail reg. 3. The original tail reg located at bar23, the above bar45 tail reg could provide better bandwidth from the hardware perspective. The hns3 driver only support direct write tail reg (also have the name of quick doorbell), the detail: 1. Considering compatibility, firmware will report Tx push capa if the hardware support it. 2. Add control macro RTE_LIBRTE_HNS3_ENABLE_TX_PUSH which was not defined default. 3. If user define macro RTE_LIBRTE_HNS3_ENABLE_TX_PUSH and hardware support, then driver will direct write bar45 tail reg to inform the hardware. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 4 +- drivers/net/hns3/hns3_ethdev_vf.c | 4 +- drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++++++++- drivers/net/hns3/hns3_rxtx.h | 24 ++++++++++ drivers/net/hns3/hns3_rxtx_vec_neon.h | 2 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 2 +- 7 files changed, 116 insertions(+), 6 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 1d85942..10f6dd0 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for Tx push qick doorbell to improve performance. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index e921924..f725f5c 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -4886,6 +4886,8 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } + hns3_tx_push_init(eth_dev); + /* * To ensure that the hardware environment is clean during * initialization, the driver actively clear the hardware environment @@ -6682,8 +6684,8 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) "process, ret = %d", ret); goto err_mp_init_secondary; } - hw->secondary_cnt++; + hns3_tx_push_init(eth_dev); return 0; } diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 5dd17c2..6a90cd5 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1841,6 +1841,8 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } + hns3_tx_push_init(eth_dev); + /* Get VF resource */ ret = hns3_query_vf_resource(hw); if (ret) @@ -2818,8 +2820,8 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) "process, ret = %d", ret); goto err_mp_init_secondary; } - hw->secondary_cnt++; + hns3_tx_push_init(eth_dev); return 0; } diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index f5c7d71..ffd8331 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2758,6 +2758,81 @@ hns3_tx_queue_conf_check(struct hns3_hw *hw, const struct rte_eth_txconf *conf, return 0; } +#ifdef RTE_LIBRTE_HNS3_ENABLE_TX_PUSH +static void * +hns3_tx_push_get_queue_tail_reg(struct rte_eth_dev *dev, uint16_t queue_id) +{ +#define HNS3_TX_PUSH_TQP_REGION_SIZE 0x10000 +#define HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET 64 +#define HNS3_TX_PUSH_PCI_BAR_INDEX 4 + + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device); + uint8_t bar_id = HNS3_TX_PUSH_PCI_BAR_INDEX; + + /* + * If device support tx push then its pcie bar45 must exist, and DPDK + * framework will mmap the bar45 default in pci probe stage. + * + * In the bar45, the first half is for roce, and the second half is for + * nic, every TQP occupy 64KB. + * + * The quick doorbell located at 64B offset in the TQP region. + */ + return (void *)((char *)pci_dev->mem_resource[bar_id].addr + + (pci_dev->mem_resource[bar_id].len >> 1) + + HNS3_TX_PUSH_TQP_REGION_SIZE * queue_id + + HNS3_TX_PUSH_QUICK_DOORBELL_OFFSET); +} +#endif + +void +hns3_tx_push_init(struct rte_eth_dev *dev) +{ +#ifdef RTE_LIBRTE_HNS3_ENABLE_TX_PUSH + struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); + volatile uint32_t *reg; + uint32_t val; + + if (!hns3_dev_tx_push_supported(hw)) + return; + + reg = (volatile uint32_t *)hns3_tx_push_get_queue_tail_reg(dev, 0); + /* + * Because the size of bar45 is about 8GB size, it may take a long time + * to do the page fault in Tx process when work with vfio-pci, so use + * one read operation to make kernel setup page table mapping for bar45 + * in the init stage. + * Note: the bar45 is readable but the result is all 1. + */ + val = *reg; + RTE_SET_USED(val); +#else + RTE_SET_USED(dev); +#endif +} + +static void +hns3_tx_push_queue_init(struct rte_eth_dev *dev, + uint16_t queue_id, + struct hns3_tx_queue *txq) +{ +#ifdef RTE_LIBRTE_HNS3_ENABLE_TX_PUSH + struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if (!hns3_dev_tx_push_supported(hw)) { + txq->tx_push_enable = false; + return; + } + + txq->io_tail_reg = (volatile void *)hns3_tx_push_get_queue_tail_reg(dev, + queue_id); + txq->tx_push_enable = true; +#else + RTE_SET_USED(dev); + RTE_SET_USED(queue_id); + txq->tx_push_enable = false; +#endif +} + int hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, unsigned int socket_id, const struct rte_eth_txconf *conf) @@ -2848,6 +2923,12 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, memset(&txq->basic_stats, 0, sizeof(struct hns3_tx_basic_stats)); memset(&txq->dfx_stats, 0, sizeof(struct hns3_tx_dfx_stats)); + /* + * Call hns3_tx_push_queue_init after assigned io_tail_reg field because + * it may overwrite the io_tail_reg field. + */ + hns3_tx_push_queue_init(dev, idx, txq); + rte_spinlock_lock(&hw->lock); dev->data->tx_queues[idx] = txq; rte_spinlock_unlock(&hw->lock); @@ -3770,7 +3851,7 @@ hns3_xmit_pkts_simple(void *tx_queue, hns3_tx_fill_hw_ring(txq, tx_pkts + nb_tx, nb_pkts - nb_tx); txq->next_to_use += nb_pkts - nb_tx; - hns3_write_reg_opt(txq->io_tail_reg, nb_pkts); + hns3_write_txq_tail_reg(txq, nb_pkts); return nb_pkts; } @@ -3887,7 +3968,7 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) end_of_tx: if (likely(nb_tx)) - hns3_write_reg_opt(txq->io_tail_reg, nb_hold); + hns3_write_txq_tail_reg(txq, nb_hold); return nb_tx; } diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 9adeb24..6ce89cc 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -406,6 +406,7 @@ struct hns3_tx_dfx_stats { struct hns3_tx_queue { void *io_base; + /* The io_tail_reg is write-only if working in tx push mode */ volatile void *io_tail_reg; struct hns3_adapter *hns; struct hns3_desc *tx_ring; @@ -471,6 +472,7 @@ struct hns3_tx_queue { uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ bool tx_deferred_start; /* don't start this queue in dev start */ + bool tx_push_enable; /* check whether the tx push is enabled */ bool configured; /* indicate if tx queue has been configured */ /* * Indicate whether add the vlan_tci of the mbuf to the inner VLAN field @@ -638,6 +640,27 @@ hns3_rx_calc_ptype(struct hns3_rx_queue *rxq, const uint32_t l234_info, ptype_tbl->l4table[l4id]; } +/* + * If enable using tx push feature and also device support it, then use qick + * doorbell (bar45) to inform the hardware. + * + * The other cases (such as: device don't support or user don't enable using) + * then use normal doorbell (bar23) to inform the hardware. + */ +static inline void +hns3_write_txq_tail_reg(struct hns3_tx_queue *txq, uint32_t value) +{ + rte_io_wmb(); +#ifdef RTE_LIBRTE_HNS3_ENABLE_TX_PUSH + if (txq->tx_push_enable) + rte_write64_relaxed(rte_cpu_to_le_32(value), txq->io_tail_reg); + else + rte_write32_relaxed(rte_cpu_to_le_32(value), txq->io_tail_reg); +#else + rte_write32_relaxed(rte_cpu_to_le_32(value), txq->io_tail_reg); +#endif +} + void hns3_dev_rx_queue_release(void *queue); void hns3_dev_tx_queue_release(void *queue); void hns3_free_all_queues(struct rte_eth_dev *dev); @@ -718,5 +741,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +void hns3_tx_push_init(struct rte_eth_dev *dev); #endif /* _HNS3_RXTX_H_ */ diff --git a/drivers/net/hns3/hns3_rxtx_vec_neon.h b/drivers/net/hns3/hns3_rxtx_vec_neon.h index 68f098f..b5047e7 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_neon.h +++ b/drivers/net/hns3/hns3_rxtx_vec_neon.h @@ -84,7 +84,7 @@ hns3_xmit_fixed_burst_vec(void *__restrict tx_queue, txq->next_to_use = next_to_use; txq->tx_bd_ready -= nb_tx; - hns3_write_reg_opt(txq->io_tail_reg, nb_tx); + hns3_write_txq_tail_reg(txq, nb_tx); return nb_tx; } diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 2a22a1a..6a20378 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -452,7 +452,7 @@ hns3_xmit_fixed_burst_vec_sve(void *__restrict tx_queue, txq->next_to_use += nb_pkts - nb_tx; txq->tx_bd_ready -= nb_pkts; - hns3_write_reg_opt(txq->io_tail_reg, nb_pkts); + hns3_write_txq_tail_reg(txq, nb_pkts); return nb_pkts; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 3/9] net/hns3: support for outer UDP cksum 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 1/9] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 2/9] net/hns3: support Tx push quick doorbell to improve perf Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 4/9] net/hns3: adjust the format of RAS related structures Min Hu (Connor) ` (8 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengchang Tang <tangchengchang@huawei.com> Kunpeng930 support outer UDP cksum, this patch add support for it. Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 10f6dd0..ba321a5 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for Tx push qick doorbell to improve performance. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 8b9f075..03f8048 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw, if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B)) + hns3_set_bit(hw->capability, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1); } static uint32_t diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index f725f5c..c15c891 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 173848a..28365e6 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -795,6 +795,7 @@ enum { #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 #define HNS3_DEV_SUPPORT_STASH_B 0x7 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -828,6 +829,9 @@ enum { #define hns3_dev_rxd_adv_layout_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 6a90cd5..b7c27f6 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index ffd8331..26127cd 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -3048,7 +3048,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ? rxm->outer_l2_len + rxm->outer_l3_len : 0; paylen = rxm->pkt_len - hdr_len; - desc->tx.paylen = rte_cpu_to_le_32(paylen); + desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); hns3_set_tso(desc, paylen, rxm); /* @@ -3285,8 +3285,10 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, { struct hns3_desc *tx_ring = txq->tx_ring; struct hns3_desc *desc = &tx_ring[tx_desc_id]; + uint64_t ol_flags = m->ol_flags; uint32_t tmp_outer = 0; uint32_t tmp_inner = 0; + uint32_t tmp_ol4cs; int ret; /* @@ -3296,7 +3298,7 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * calculations, the length of the L2 header include the outer and * inner, will be filled during the parsing of tunnel packects. */ - if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) { + if (!(ol_flags & PKT_TX_TUNNEL_MASK)) { /* * For non tunnel type the tunnel type id is 0, so no need to * assign a value to it. Only the inner(normal) L2 header length @@ -3311,7 +3313,8 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * inner l2_len. It would lead a cksum error. So driver has to * calculate the header length. */ - if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) && + if (unlikely(!(ol_flags & + (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) && m->outer_l2_len == 0)) { struct rte_net_hdr_lens hdr_len; (void)rte_net_get_ptype(m, &hdr_len, @@ -3328,6 +3331,9 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); + tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ? + BIT(HNS3_TXD_OL4CS_B) : 0; + desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); return 0; } @@ -3457,31 +3463,78 @@ hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, return false; } +static bool +hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv4_hdr *ipv4_hdr; + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags); + + return true; + } + *l4_proto = ipv4_hdr->next_proto_id; + return false; +} + +static bool +hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv6_hdr *ipv6_hdr; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + + return true; + } + *l4_proto = ipv6_hdr->proto; + return false; +} + static void hns3_outer_header_cksum_prepare(struct rte_mbuf *m) { uint64_t ol_flags = m->ol_flags; uint32_t paylen, hdr_len, l4_proto; + struct rte_udp_hdr *udp_hdr; if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6))) return; if (ol_flags & PKT_TX_OUTER_IPV4) { - struct rte_ipv4_hdr *ipv4_hdr; - ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->outer_l2_len); - l4_proto = ipv4_hdr->next_proto_id; - if (ol_flags & PKT_TX_OUTER_IP_CKSUM) - ipv4_hdr->hdr_checksum = 0; + if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto)) + return; } else { - struct rte_ipv6_hdr *ipv6_hdr; - ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, - m->outer_l2_len); - l4_proto = ipv6_hdr->proto; + if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto)) + return; } + /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */ if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) { - struct rte_udp_hdr *udp_hdr; hdr_len = m->l2_len + m->l3_len + m->l4_len; hdr_len += m->outer_l2_len + m->outer_l3_len; paylen = m->pkt_len - hdr_len; @@ -3767,7 +3820,7 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); @@ -3783,7 +3836,7 @@ hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 6ce89cc..db34ff9 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -149,6 +149,7 @@ #define HNS3_TXD_MSS_S 0 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22 #define HNS3_L2_LEN_UNIT 1UL #define HNS3_L3_LEN_UNIT 2UL #define HNS3_L4_LEN_UNIT 2UL @@ -234,7 +235,7 @@ struct hns3_desc { }; }; - uint32_t paylen; + uint32_t paylen_fd_dop_ol4cs; uint16_t tp_fe_sc_vld_ra_ri; uint16_t mss; } tx; @@ -505,6 +506,7 @@ struct hns3_queue_info { }; #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \ diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 6a20378..f8655fa 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0)); /* save offset 24~31byte of every BD */ - svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen, - offsets, svdup_n_u64(valid_bit)); + svst1_scatter_u64offset_u64(pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets, svdup_n_u64(valid_bit)); /* Increment bytes counter */ uint32_t idx; -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 4/9] net/hns3: adjust the format of RAS related structures 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (2 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 3/9] net/hns3: support for outer UDP cksum Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 5/9] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) ` (7 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Adjust the format of hns3 RAS related structures to resolve the static check warnings of reviewbot_c.This patch has no impact on function. The correspond warnings of reviewbot_c: When struct and union members are initialized, each member is initialized on a separate line. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 2563504..3f328ba 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { }; static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "egu_cge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "egu_cge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "egu_lge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "egu_lge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "cge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "lge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "lge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "cge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "lge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "egu_cge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "egu_lge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "egu_ge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "egu_cge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "egu_cge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "egu_lge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "egu_lge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "cge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "lge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "lge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "cge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "lge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "egu_cge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "egu_lge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "egu_ge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk = 0xFFFFFFFF, - .msg = "rpu_rx_pkt_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = 0xFFFFFFFF, + .msg = "rpu_rx_pkt_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk = BIT(13), - .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rcb_tx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rcb_rx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rcb_tx_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rcb_rx_ebd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rcb_tso_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rcb_tx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rcb_rx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tpu_tx_pkt_0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tpu_tx_pkt_1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "rd_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "wr_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "ooo_ecc_err_detect", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(31), - .msg = "ooo_ecc_err_multpl", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(13), + .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rcb_tx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rcb_rx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rcb_tx_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rcb_rx_ebd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rcb_tso_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rcb_tx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rcb_rx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tpu_tx_pkt_0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tpu_tx_pkt_1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "rd_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "wr_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "ooo_ecc_err_detect", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(31), + .msg = "ooo_ecc_err_multpl", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk = BIT(29), - .msg = "rx_q_search_miss", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(29), + .msg = "rx_q_search_miss", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "low_water_line_err_port", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "low_water_line_err_port", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk = BIT(0), - .msg = "tx_vlan_tag_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "rss_list_tc_unassigned_queue_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "tx_vlan_tag_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "rss_list_tc_unassigned_queue_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk = BIT(3), - .msg = "tx_rd_fbd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(4), - .msg = "rx_rd_ebd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(3), + .msg = "tx_rd_fbd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(4), + .msg = "rx_rd_ebd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk = BIT(0), - .msg = "over_8bd_no_fe", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tso_mss_cmp_min_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "tso_mss_cmp_max_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "buf_wait_timeout", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "over_8bd_no_fe", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tso_mss_cmp_min_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "tso_mss_cmp_max_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "buf_wait_timeout", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "imp_itcm0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "imp_itcm1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "imp_itcm2_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "imp_itcm3_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "imp_dtcm0_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "imp_dtcm0_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "imp_dtcm1_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "imp_dtcm1_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(17), - .msg = "imp_itcm4_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "imp_itcm0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "imp_itcm1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "imp_itcm2_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "imp_itcm3_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "imp_dtcm0_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "imp_dtcm0_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "imp_dtcm1_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "imp_dtcm1_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(17), + .msg = "imp_itcm4_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "cmdq_nic_rx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "cmdq_nic_tx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cmdq_nic_rx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "cmdq_nic_tx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "cmdq_nic_rx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "cmdq_nic_tx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "cmdq_nic_rx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "cmdq_nic_tx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "cmdq_nic_rx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "cmdq_nic_tx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cmdq_nic_rx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "cmdq_nic_tx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "cmdq_nic_rx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "cmdq_nic_tx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "cmdq_nic_rx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "cmdq_nic_tx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk = BIT(6), - .msg = "tqp_int_cfg_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "tqp_int_cfg_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(8), - .msg = "tqp_int_ctrl_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "tqp_int_ctrl_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(10), - .msg = "tx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "rx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(6), + .msg = "tqp_int_cfg_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "tqp_int_cfg_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(8), + .msg = "tqp_int_ctrl_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "tqp_int_ctrl_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(10), + .msg = "tx_que_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "rx_que_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk = BIT(0), - .msg = "imp_rd_poison_int", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "imp_rd_poison_int", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; #define HNS3_SSU_MEM_ECC_ERR(x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +} static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { HNS3_SSU_MEM_ECC_ERR(0), @@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { }; static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk = BIT(0), - .msg = "ssu_mem32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ssu_mem32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk = BIT(0), - .msg = "buf_sum_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "ppp_mb_num_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "ppp_mbid_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ppp_rlt_mac_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ppp_rlt_host_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "cks_edit_position_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "cks_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "vlan_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "vlan_num_ot_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "vlan_num_in_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "buf_sum_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "ppp_mb_num_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "ppp_mbid_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ppp_rlt_mac_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ppp_rlt_host_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "cks_edit_position_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "cks_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "vlan_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "vlan_num_ot_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "vlan_num_in_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_int[] = { - { .int_msk = BIT(0), - .msg = "igu_rx_buf0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_rx_buf1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "igu_rx_buf0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_rx_buf1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "msix_nic_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "msix_nic_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk = BIT(0), - .msg = "vf_vlan_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "umv_mcast_group_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "umv_key_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "umv_key_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "umv_key_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "umv_key_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "umv_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "rss_tc_mode_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rss_idt_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "rss_idt_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "rss_idt_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "rss_idt_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "rss_idt_mem4_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "rss_idt_mem5_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rss_idt_mem6_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rss_idt_mem7_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rss_idt_mem8_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rss_idt_mem9_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rss_idt_mem10_ecc_m1bit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rss_idt_mem11_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rss_idt_mem12_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rss_idt_mem13_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rss_idt_mem14_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rss_idt_mem15_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "port_vlan_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "mcast_linear_table_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "mcast_result_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "flow_director_ad_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "flow_director_ad_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "rx_vlan_tag_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "vf_vlan_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "umv_mcast_group_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "umv_key_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "umv_key_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "umv_key_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "umv_key_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "umv_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "rss_tc_mode_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rss_idt_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "rss_idt_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "rss_idt_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "rss_idt_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "rss_idt_mem4_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "rss_idt_mem5_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rss_idt_mem6_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rss_idt_mem7_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rss_idt_mem8_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rss_idt_mem9_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rss_idt_mem10_ecc_m1bit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rss_idt_mem11_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rss_idt_mem12_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rss_idt_mem13_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rss_idt_mem14_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rss_idt_mem15_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "port_vlan_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "mcast_linear_table_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "mcast_result_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "flow_director_ad_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "flow_director_ad_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "rx_vlan_tag_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(0), - .msg = "hfs_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rslt_descr_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tx_vlan_tag_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "FD_CN0_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "FD_CN1_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "GRO_AD_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "hfs_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rslt_descr_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tx_vlan_tag_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "FD_CN0_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "FD_CN1_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "GRO_AD_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(4), - .msg = "gro_bd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "gro_context_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_stash_cfg_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "axi_rd_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(4), + .msg = "gro_bd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "gro_context_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_stash_cfg_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "axi_rd_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk = BIT(1), - .msg = "tm_sch_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tm_sch_port_shap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tm_sch_port_shap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "tm_sch_port_shap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "tm_sch_port_shap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "tm_sch_rq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "tm_sch_rq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tm_sch_nq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tm_sch_nq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "tm_sch_roce_up_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "tm_sch_roce_up_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "tm_sch_rcb_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "tm_sch_rcb_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "tm_sch_ssu_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(31), - .msg = "tm_sch_ssu_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "tm_sch_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tm_sch_port_shap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tm_sch_port_shap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "tm_sch_port_shap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "tm_sch_port_shap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "tm_sch_rq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "tm_sch_rq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tm_sch_nq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tm_sch_nq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "tm_sch_roce_up_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "tm_sch_roce_up_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "tm_sch_rcb_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "tm_sch_rcb_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "tm_sch_ssu_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(31), + .msg = "tm_sch_ssu_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk = BIT(0), - .msg = "qcn_shap_gp0_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "qcn_shap_gp0_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "qcn_shap_gp1_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_shap_gp1_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "qcn_shap_gp2_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_shap_gp2_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "qcn_shap_gp3_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_shap_gp3_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "qcn_shap_gp0_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_shap_gp0_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "qcn_shap_gp1_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_shap_gp1_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "qcn_shap_gp2_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_gp2_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "qcn_shap_gp3_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_shap_gp3_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "qcn_byte_info_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_byte_info_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "qcn_shap_gp0_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "qcn_shap_gp0_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "qcn_shap_gp1_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_shap_gp1_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "qcn_shap_gp2_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_shap_gp2_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "qcn_shap_gp3_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_shap_gp3_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "qcn_shap_gp0_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_shap_gp0_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "qcn_shap_gp1_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_shap_gp1_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "qcn_shap_gp2_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_gp2_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "qcn_shap_gp3_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_shap_gp3_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "qcn_byte_info_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_byte_info_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "qcn_byte_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_time_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_fb_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_link_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_rate_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_tmplt_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_cfg_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "qcn_gp3_barral_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "qcn_byte_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_time_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_fb_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_link_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_rate_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_tmplt_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_cfg_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "qcn_gp3_barral_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "ncsi_tx_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "ncsi_tx_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk = BIT(0), - .msg = "ig_mac_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ig_host_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ig_roc_buf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ig_host_data_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ig_host_key_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qm_eof_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "mb_rlt_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "dup_uncopy_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "dup_cnt_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "dup_cnt_drop_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "dup_cnt_wrb_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "host_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "mac_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "host_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "mac_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "dup_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "out_queue_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "bank2_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "bank1_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "bank0_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ig_mac_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ig_host_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ig_roc_buf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ig_host_data_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ig_host_key_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qm_eof_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "mb_rlt_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "dup_uncopy_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "dup_cnt_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "dup_cnt_drop_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "dup_cnt_wrb_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "host_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "mac_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "host_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "mac_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "dup_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "out_queue_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "bank2_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "bank1_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "bank0_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk = BIT(0), - .msg = "ets_rd_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ets_wr_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ets_rd_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ets_wr_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ets_rd_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ets_wr_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ets_rd_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ets_wr_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "rx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rx_stp_fifo_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "rx_stp_fifo_underflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tx_buf_underrun", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "rx_stp_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "rx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rx_stp_fifo_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "rx_stp_fifo_underflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tx_buf_underrun", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "rx_stp_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tpu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "roc_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tpu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "igu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "roc_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tpu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "igu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "ets_rd_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "ets_wr_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ets_rd_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "ets_wr_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tpu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "roc_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tpu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "igu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "roc_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tpu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "igu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "ets_rd_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "ets_wr_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ets_rd_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "ets_wr_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "IMP_TCM_ECC_INT_STS", - .hw_err = imp_tcm_ecc_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "CMDQ_MEM_ECC_INT_STS", - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "IMP_RD_POISON_INT_STS", - .hw_err = imp_rd_poison_int }, - { .desc_offset = 0, - .data_offset = 3, - .msg = "TQP_INT_ECC_INT_STS", - .hw_err = tqp_int_ecc_int }, - { .desc_offset = 0, - .data_offset = 4, - .msg = "MSIX_ECC_INT_STS", - .hw_err = msix_ecc_int }, - { .desc_offset = 2, - .data_offset = 2, - .msg = "SSU_ECC_MULTI_BIT_INT_0", - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset = 2, - .data_offset = 3, - .msg = "SSU_ECC_MULTI_BIT_INT_1", - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset = 2, - .data_offset = 4, - .msg = "SSU_COMMON_ERR_INT", - .hw_err = ssu_common_ecc_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "IGU_INT_STS", - .hw_err = igu_int }, - { .desc_offset = 4, - .data_offset = 1, - .msg = "PPP_MPF_ABNORMAL_INT_ST1", - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset = 4, - .data_offset = 3, - .msg = "PPP_MPF_ABNORMAL_INT_ST3", - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset = 5, - .data_offset = 1, - .msg = "PPU_MPF_ABNORMAL_INT_ST1", - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset = 5, - .data_offset = 3, - .msg = "PPU_MPF_ABNORMAL_INT_ST3", - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset = 6, - .data_offset = 0, - .msg = "TM_SCH_RINT", - .hw_err = tm_sch_int }, - { .desc_offset = 7, - .data_offset = 0, - .msg = "QCN_FIFO_RINT", - .hw_err = qcn_fifo_int }, - { .desc_offset = 7, - .data_offset = 1, - .msg = "QCN_ECC_RINT", - .hw_err = qcn_ecc_int }, - { .desc_offset = 9, - .data_offset = 0, - .msg = "NCSI_ECC_INT_RPT", - .hw_err = ncsi_ecc_int }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "IMP_TCM_ECC_INT_STS", + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "CMDQ_MEM_ECC_INT_STS", + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "IMP_RD_POISON_INT_STS", + .hw_err = imp_rd_poison_int + }, { + .desc_offset = 0, + .data_offset = 3, + .msg = "TQP_INT_ECC_INT_STS", + .hw_err = tqp_int_ecc_int + }, { + .desc_offset = 0, + .data_offset = 4, + .msg = "MSIX_ECC_INT_STS", + .hw_err = msix_ecc_int + }, { + .desc_offset = 2, + .data_offset = 2, + .msg = "SSU_ECC_MULTI_BIT_INT_0", + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset = 2, + .data_offset = 3, + .msg = "SSU_ECC_MULTI_BIT_INT_1", + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset = 2, + .data_offset = 4, + .msg = "SSU_COMMON_ERR_INT", + .hw_err = ssu_common_ecc_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "IGU_INT_STS", + .hw_err = igu_int + }, { + .desc_offset = 4, + .data_offset = 1, + .msg = "PPP_MPF_ABNORMAL_INT_ST1", + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset = 4, + .data_offset = 3, + .msg = "PPP_MPF_ABNORMAL_INT_ST3", + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset = 5, + .data_offset = 1, + .msg = "PPU_MPF_ABNORMAL_INT_ST1", + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset = 5, + .data_offset = 3, + .msg = "PPU_MPF_ABNORMAL_INT_ST3", + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset = 6, + .data_offset = 0, + .msg = "TM_SCH_RINT", + .hw_err = tm_sch_int + }, { + .desc_offset = 7, + .data_offset = 0, + .msg = "QCN_FIFO_RINT", + .hw_err = qcn_fifo_int + }, { + .desc_offset = 7, + .data_offset = 1, + .msg = "QCN_ECC_RINT", + .hw_err = qcn_ecc_int + }, { + .desc_offset = 9, + .data_offset = 0, + .msg = "NCSI_ECC_INT_RPT", + .hw_err = ncsi_ecc_int + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_RAS", - .hw_err = ssu_port_based_err_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "SSU_FIFO_OVERFLOW_INT", - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "SSU_ETS_TCG_INT", - .hw_err = ssu_ets_tcg_int }, - { .desc_offset = 1, - .data_offset = 0, - .msg = "IGU_EGU_TNL_INT_STS", - .hw_err = igu_egu_tnl_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_RAS", + .hw_err = ssu_port_based_err_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "SSU_FIFO_OVERFLOW_INT", + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "SSU_ETS_TCG_INT", + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset = 1, + .data_offset = 0, + .msg = "IGU_EGU_TNL_INT_STS", + .hw_err = igu_egu_tnl_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset = 1, - .data_offset = 0, - .msg = "MAC_AFIFO_TNL_INT_R", - .hw_err = mac_afifo_tnl_int }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 1, + .data_offset = 0, + .msg = "MAC_AFIFO_TNL_INT_R", + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_MSIX", - .hw_err = ssu_port_based_pf_int }, - { .desc_offset = 2, - .data_offset = 0, - .msg = "PPP_PF_ABNORMAL_INT_ST0", - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_MSIX", + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset = 2, + .data_offset = 0, + .msg = "PPP_PF_ABNORMAL_INT_ST0", + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; enum hns3_hw_err_type { -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 5/9] net/hns3: delete redundant xstats RAS statistics 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (3 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 4/9] net/hns3: adjust the format of RAS related structures Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 6/9] net/hns3: support imissed stats for PF/VF Min Hu (Connor) ` (6 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index c15c891..db2c94a 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5770,14 +5770,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { hns3_warn(hw, "Detected IMP RD poison!"); - hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { hns3_warn(hw, "Detected IMP CMDQ error!"); - hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 28365e6..a29d6f8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -561,38 +561,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_int_cnt; - uint64_t ppu_mpf_abn_int_st2_msix_cnt; - uint64_t ssu_port_based_pf_int_cnt; - uint64_t ppp_pf_abnormal_int_cnt; - uint64_t ppu_pf_abnormal_int_msix_cnt; - - uint64_t imp_tcm_ecc_int_cnt; - uint64_t cmdq_mem_ecc_int_cnt; - uint64_t imp_rd_poison_int_cnt; - uint64_t tqp_int_ecc_int_cnt; - uint64_t msix_ecc_int_cnt; - uint64_t ssu_ecc_multi_bit_int_0_cnt; - uint64_t ssu_ecc_multi_bit_int_1_cnt; - uint64_t ssu_common_ecc_int_cnt; - uint64_t igu_int_cnt; - uint64_t ppp_mpf_abnormal_int_st1_cnt; - uint64_t ppp_mpf_abnormal_int_st3_cnt; - uint64_t ppu_mpf_abnormal_int_st1_cnt; - uint64_t ppu_mpf_abn_int_st2_ras_cnt; - uint64_t ppu_mpf_abnormal_int_st3_cnt; - uint64_t tm_sch_int_cnt; - uint64_t qcn_fifo_int_cnt; - uint64_t qcn_ecc_int_cnt; - uint64_t ncsi_ecc_int_cnt; - uint64_t ssu_port_based_err_int_cnt; - uint64_t ssu_fifo_overflow_int_cnt; - uint64_t ssu_ets_tcg_int_cnt; - uint64_t igu_egu_tnl_int_cnt; - uint64_t ppu_pf_abnormal_int_ras_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -738,9 +706,6 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 3f328ba..89d7f0d 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } - hns3_error_int_stats_add(hns, reg); } err++; } diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 941c75f..7cda36c 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -201,65 +201,6 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = { HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)} }; -static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = { - {"MAC_AFIFO_TNL_INT_R", - HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)}, - {"SSU_PORT_BASED_ERR_INT_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)}, - {"PPP_PF_ABNORMAL_INT_ST0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)}, - {"IMP_TCM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)}, - {"CMDQ_MEM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)}, - {"IMP_RD_POISON_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)}, - {"TQP_INT_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)}, - {"MSIX_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)}, - {"SSU_COMMON_ERR_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)}, - {"IGU_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)}, - {"TM_SCH_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)}, - {"QCN_FIFO_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)}, - {"QCN_ECC_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)}, - {"NCSI_ECC_INT_RPT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)}, - {"SSU_PORT_BASED_ERR_INT_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)}, - {"SSU_FIFO_OVERFLOW_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)}, - {"SSU_ETS_TCG_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)}, - {"IGU_EGU_TNL_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)}, -}; - /* The statistic of reset */ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = { {"REQ_RESET_CNT", @@ -333,9 +274,6 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) -#define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \ - sizeof(hns3_error_int_stats_strings[0])) - #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \ sizeof(hns3_reset_stats_strings[0])) @@ -363,7 +301,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -750,23 +688,6 @@ hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } -void -hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) -{ - struct hns3_pf *pf = &hns->pf; - uint16_t i; - char *addr; - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - *(uint64_t *)addr += 1; - break; - } - } -} - static void hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) @@ -932,7 +853,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; struct hns3_hw *hw = &hns->hw; struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; @@ -986,13 +906,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } } /* Get the reset stat */ @@ -1134,13 +1047,6 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_imissed_stats_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_error_int_stats_strings[i].name); - count++; - } } for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, @@ -1358,7 +1264,6 @@ int hns3_dev_xstats_reset(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; int ret; /* Clear tqp stats */ @@ -1379,9 +1284,6 @@ hns3_dev_xstats_reset(struct rte_eth_dev *dev) if (ret) return ret; - /* Clear error stats */ - memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats)); - return 0; } diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 70a9c5b..8ea69b4 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint32_t size); int hns3_stats_reset(struct rte_eth_dev *dev); -void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err); int hns3_tqp_stats_init(struct hns3_hw *hw); void hns3_tqp_stats_uninit(struct hns3_hw *hw); int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear); -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 6/9] net/hns3: support imissed stats for PF/VF 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (4 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 5/9] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 7/9] net/hns3: support oerrors stats in PF Min Hu (Connor) ` (5 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_cmd.h | 14 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 233 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 094bf7e..939bbc2 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -111,6 +111,8 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, @@ -957,6 +959,18 @@ struct hns3_query_rpu_cmd { uint32_t rsv2[2]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t ncsi_full_drop_cnt; + uint32_t ncsi_part_drop_cnt; + uint32_t oq_glb_drop_cnt; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index db2c94a..cd92b8d 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = false; @@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = true; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index a29d6f8..915f183 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -426,6 +426,9 @@ struct hns3_queue_intr { #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -544,6 +547,24 @@ struct hns3_hw { * port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + + /* + * drop_stats_mode mode. + * value range: + * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 + * + * - HNS3_PKTS_DROP_STATS_MODE1 + * This mode for kunpeng920. In this mode, port level imissed stats + * is supported. It only includes RPU drop stats. + * + * - HNS3_PKTS_DROP_STATS_MODE2 + * This mode for kunpeng930. In this mode, imissed stats and oerrors + * stats is supported. Function level imissed stats is supported. It + * includes RPU drop stats in VF, and includes both RPU drop stats + * and SSU drop stats in PF. Oerror stats is also supported in PF. + */ + uint8_t drop_stats_mode; + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index b7c27f6..25d74ba 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; @@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; @@ -1877,6 +1879,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) if (ret) goto err_get_config; + /* Hardware statistics of imissed registers cleared. */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + goto err_set_tc_queue; + } + ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); if (ret) { PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h index 0540554..e141fe1 100644 --- a/drivers/net/hns3/hns3_regs.h +++ b/drivers/net/hns3/hns3_regs.h @@ -36,6 +36,8 @@ #define HNS3_GLOBAL_RESET_REG 0x20A00 #define HNS3_FUN_RST_ING 0x20C00 #define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008 /* Vector0 register bits for reset */ diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 7cda36c..ccad477 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -269,6 +269,8 @@ static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = { static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { {"RPU_DROP_CNT", HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)}, + {"SSU_DROP_CNT", + HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)}, }; #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ @@ -301,8 +303,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ - HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -419,7 +420,7 @@ hns3_query_update_mac_stats(struct rte_eth_dev *dev) } static int -hns3_update_rpu_drop_stats(struct hns3_hw *hw) +hns3_update_port_rpu_drop_stats(struct hns3_hw *hw) { struct hns3_rx_missed_stats *stats = &hw->imissed_stats; struct hns3_query_rpu_cmd *req; @@ -449,11 +450,89 @@ hns3_update_rpu_drop_stats(struct hns3_hw *hw) return 0; } +static void +hns3_update_function_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + + stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG); +} + +static int +hns3_update_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret = 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf) + ret = hns3_update_port_rpu_drop_stats(hw); + else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2) + hns3_update_function_rpu_drop_stats(hw); + + return ret; +} + +static int +hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + int bd_num, bool is_rx) +{ + struct hns3_query_ssu_cmd *req; + int ret; + int i; + + for (i = 0; i < bd_num - 1; i++) { + hns3_cmd_setup_basic_desc(&desc[i], + HNS3_OPC_SSU_DROP_REG, true); + desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + } + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true); + req = (struct hns3_query_ssu_cmd *)desc[0].data; + req->rxtx = is_rx ? 0 : 1; + ret = hns3_cmd_send(hw, desc, bd_num); + + return ret; +} + +static int +hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + true); + if (ret) { + hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + stats->ssu_rx_drop_cnt += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); int ret; + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) { + ret = hns3_update_port_rx_ssu_drop_stats(hw); + if (ret) + return ret; + } + ret = hns3_update_rpu_drop_stats(hw); if (ret) return ret; @@ -488,19 +567,17 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) uint16_t i; int ret; - if (!hns->is_vf) { - /* Update imissed stats */ - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt; + /* Update imissed stats */ + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt + + imissed_stats->ssu_rx_drop_cnt; - /* Reads all the stats of a rxq in a loop to keep them synchronized */ + /* Get the error stats and bytes of received packets */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) @@ -556,17 +633,14 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) uint16_t i; int ret; - if (!hns->is_vf) { - /* - * Note: Reading hardware statistics of imissed registers will - * clear them. - */ - ret = hns3_update_imissed_stats(hw, true); - if (ret) { - hns3_err(hw, "clear imissed stats failed, ret = %d", - ret); - return ret; - } + /* + * Note: Reading hardware statistics of imissed registers will + * clear them. + */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + return ret; } for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { @@ -630,6 +704,22 @@ hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev) return 0; } +static int +hns3_get_imissed_stats_num(struct hns3_adapter *hns) +{ +#define NO_IMISSED_STATS_NUM 0 +#define RPU_STATS_ITEM_NUM 1 + struct hns3_hw *hw = &hns->hw; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return NO_IMISSED_STATS_NUM; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) + return HNS3_NUM_IMISSED_XSTATS; + + return RPU_STATS_ITEM_NUM; +} + /* This function calculates the number of xstats based on the current config */ static int hns3_xstats_calc_num(struct rte_eth_dev *dev) @@ -647,13 +737,17 @@ hns3_xstats_calc_num(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM; int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM; + int stats_num; + + stats_num = rx_comm_stats_num + tx_comm_stats_num; + stats_num += hns3_get_imissed_stats_num(hns); if (hns->is_vf) - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_NUM_RESET_XSTATS; + stats_num += HNS3_NUM_RESET_XSTATS; else - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_FIX_NUM_STATS; + stats_num += HNS3_FIX_NUM_STATS; + + return stats_num; } static void @@ -835,6 +929,31 @@ hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, hns3_txq_basic_stats_get(dev, xstats, count); } +static void +hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; + int imissed_stats_num; + int cnt = *count; + char *addr; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + addr = (char *)imissed_stats + + hns3_imissed_stats_strings[i].offset; + xstats[cnt].value = *(uint64_t *)addr; + xstats[cnt].id = cnt; + cnt++; + } + + *count = cnt; +} + /* * Retrieve extended(tqp | Mac) statistics of an Ethernet device. * @param dev @@ -854,7 +973,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, { struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_bd_errors_stats *rx_err_stats; @@ -890,24 +1008,17 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, xstats[count].id = count; count++; } + } - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - addr = (char *)imissed_stats + - hns3_imissed_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } - + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + hns3_imissed_stats_get(dev, xstats, &count); + /* Get the reset stat */ for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset; @@ -992,6 +1103,28 @@ hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev, } } +static void +hns3_imissed_stats_name_get(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + uint32_t *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t cnt = *count; + int imissed_stats_num; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + snprintf(xstats_names[cnt].name, + sizeof(xstats_names[cnt].name), + "%s", hns3_imissed_stats_strings[i].name); + cnt++; + } + + *count = cnt; +} + /* * Retrieve names of extended statistics of an Ethernet device. * @@ -1040,14 +1173,10 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_mac_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_imissed_stats_strings[i].name); - count++; - } } + + hns3_imissed_stats_name_get(dev, xstats_names, &count); + for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 8ea69b4..273be42 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -112,6 +112,7 @@ struct hns3_mac_stats { struct hns3_rx_missed_stats { uint64_t rpu_rx_drop_cnt; + uint64_t ssu_rx_drop_cnt; }; /* store statistics names and its offset in stats structure */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 7/9] net/hns3: support oerrors stats in PF 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (5 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 6/9] net/hns3: support imissed stats for PF/VF Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 8/9] net/hns3: support query Tx descriptor status Min Hu (Connor) ` (4 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This patch added oerrors stats for PF in kunpeng930. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 61 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 915f183..586979b 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -443,6 +443,7 @@ struct hns3_hw { /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index ccad477..e0378dd 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -518,6 +518,29 @@ hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) return 0; } +static int +hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + false); + if (ret) { + hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_glb_drop_cnt); + + hw->oerror_stats += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { @@ -543,6 +566,25 @@ hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) return 0; } +static int +hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf) + return 0; + + ret = hns3_update_port_tx_ssu_drop_stats(hw); + if (ret) + return ret; + + if (is_clear) + hw->oerror_stats = 0; + + return 0; +} + /* * Query tqp tx queue statistics ,opcode id: 0x0B03. * Query tqp rx queue statistics ,opcode id: 0x0B13. @@ -577,6 +619,14 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt + imissed_stats->ssu_rx_drop_cnt; + ret = hns3_update_oerror_stats(hw, false); + if (ret) { + hns3_err(hw, "update oerror stats failed, ret = %d", + ret); + return ret; + } + rte_stats->oerrors = hw->oerror_stats; + /* Get the error stats and bytes of received packets */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; @@ -643,6 +693,17 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) return ret; } + /* + * Note: Reading hardware statistics of oerror registers will + * clear them. + */ + ret = hns3_update_oerror_stats(hw, true); + if (ret) { + hns3_err(hw, "clear oerror stats failed, ret = %d", + ret); + return ret; + } + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 8/9] net/hns3: support query Tx descriptor status 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (6 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 7/9] net/hns3: support oerrors stats in PF Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 9/9] net/hns3: support query Rx " Min Hu (Connor) ` (3 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 3aeea8e..2c0cb89 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index c796cd5..e60b09b 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index ba321a5..619ffd1 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for Tx push qick doorbell to improve performance. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index cd92b8d..997d017 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6776,6 +6776,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; return ret; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 25d74ba..28d0e20 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2919,6 +2919,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 26127cd..4a13613 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4125,6 +4125,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; } else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; @@ -4337,6 +4338,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) return -ENOTSUP; } +int +hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + volatile struct hns3_desc *txdp; + struct hns3_tx_queue *txq; + struct rte_eth_dev *dev; + uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; + if (offset >= txq->nb_tx_desc) + return -EINVAL; + + dev = &rte_eth_devices[txq->port_id]; + if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) + return RTE_ETH_TX_DESC_UNAVAIL; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; + if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) + return RTE_ETH_TX_DESC_FULL; + else + return RTE_ETH_TX_DESC_DONE; +} + uint32_t hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index db34ff9..a824fb2 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -743,6 +743,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); void hns3_tx_push_init(struct rte_eth_dev *dev); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH 9/9] net/hns3: support query Rx descriptor status 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (7 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 8/9] net/hns3: support query Tx descriptor status Min Hu (Connor) @ 2021-03-10 6:24 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (2 subsequent siblings) 11 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-10 6:24 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 2c0cb89..3988be4 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index e60b09b..1640669 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 619ffd1..5be2bcc 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -64,6 +64,7 @@ New Features * Added support for Tx push qick doorbell to improve performance. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 997d017..fba715b 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 28d0e20..b121d7f 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 4a13613..ba30086 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4123,6 +4123,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) if (hns->hw.adapter_state == HNS3_NIC_STARTED && __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) { eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; @@ -4339,6 +4340,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) } int +hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + volatile struct hns3_desc *rxdp; + struct hns3_rx_queue *rxq; + struct rte_eth_dev *dev; + uint32_t bd_base_info; + uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; + if (offset >= rxq->nb_rx_desc) + return -EINVAL; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; + if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { + if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ + if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) + return RTE_ETH_RX_DESC_UNAVAIL; + } else { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) + return RTE_ETH_RX_DESC_AVAIL; + else + return RTE_ETH_RX_DESC_DONE; +} + +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { volatile struct hns3_desc *txdp; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index a824fb2..ab2b05a 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -743,6 +743,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); void hns3_tx_push_init(struct rte_eth_dev *dev); -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (8 preceding siblings ...) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 9/9] net/hns3: support query Rx " Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) ` (7 more replies) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) 11 siblings, 8 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This series add four features according to the 21.05 roadmap, and also two cleanups added. Chengchang Tang (1): net/hns3: support for outer UDP cksum Chengwen Feng (1): net/hns3: support runtime config to select IO burst func Hongbo Zheng (4): net/hns3: adjust the format of RAS related structures net/hns3: delete redundant xstats RAS statistics net/hns3: support query Tx descriptor status net/hns3: support query Rx descriptor status Min Hu (Connor) (2): net/hns3: support imissed stats for PF/VF net/hns3: support oerrors stats in PF doc/guides/nics/features/hns3.ini | 2 + doc/guides/nics/features/hns3_vf.ini | 2 + doc/guides/nics/hns3.rst | 20 + doc/guides/rel_notes/release_21_05.rst | 4 + drivers/net/hns3/hns3_cmd.c | 3 + drivers/net/hns3/hns3_cmd.h | 13 + drivers/net/hns3/hns3_ethdev.c | 86 +- drivers/net/hns3/hns3_ethdev.h | 76 +- drivers/net/hns3/hns3_ethdev_vf.c | 18 + drivers/net/hns3/hns3_intr.c | 2127 ++++++++++++++++++-------------- drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_rxtx.c | 203 ++- drivers/net/hns3/hns3_rxtx.h | 6 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- drivers/net/hns3/hns3_stats.c | 394 +++--- drivers/net/hns3/hns3_stats.h | 2 +- 16 files changed, 1839 insertions(+), 1124 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 1/8] net/hns3: support runtime config to select IO burst func 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) ` (6 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengwen Feng <fengchengwen@huawei.com> Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration. Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function. This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common. The driver will use the following rules to select io burst func: a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function. b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function. c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function. d. if hint equal common then use the common function. e. if hint not set then: e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function. e.3. else use the common function. Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE). In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/hns3.rst | 20 +++++++++ doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- 6 files changed, 157 insertions(+), 14 deletions(-) diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst index 84bd7a3..40d2e3b 100644 --- a/doc/guides/nics/hns3.rst +++ b/doc/guides/nics/hns3.rst @@ -46,6 +46,26 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. +Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Rx usage condition then use the neon Rx function. + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function. + When equal "common" then use the common Rx function. + +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Tx usage condition then use the neon Tx function. + When equal "sve" and meet the sve Tx usage condition then use the sve Tx function. + When equal "simple" and meet the simple Tx usage condition then use the simple Tx function. + When equal "common" then use the common Tx function. + + Driver compilation and testing ------------------------------ diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index dc5399f..1d85942 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 9cbcc13..28aa27a 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6,6 +6,7 @@ #include <rte_bus_pci.h> #include <ethdev_pci.h> #include <rte_pci.h> +#include <rte_kvargs.h> #include "hns3_ethdev.h" #include "hns3_logs.h" @@ -6505,6 +6506,78 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } +static int +hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) +{ + uint32_t hint = HNS3_IO_FUNC_HINT_NONE; + + RTE_SET_USED(key); + + if (strcmp(value, "vec") == 0) + hint = HNS3_IO_FUNC_HINT_VEC; + else if (strcmp(value, "sve") == 0) + hint = HNS3_IO_FUNC_HINT_SVE; + else if (strcmp(value, "simple") == 0) + hint = HNS3_IO_FUNC_HINT_SIMPLE; + else if (strcmp(value, "common") == 0) + hint = HNS3_IO_FUNC_HINT_COMMON; + + /* If the hint is valid then update output parameters */ + if (hint != HNS3_IO_FUNC_HINT_NONE) + *(uint32_t *)extra_args = hint; + + return 0; +} + +static const char * +hns3_get_io_hint_func_name(uint32_t hint) +{ + switch (hint) { + case HNS3_IO_FUNC_HINT_VEC: + return "vec"; + case HNS3_IO_FUNC_HINT_SVE: + return "sve"; + case HNS3_IO_FUNC_HINT_SIMPLE: + return "simple"; + case HNS3_IO_FUNC_HINT_COMMON: + return "common"; + default: + return "none"; + } +} + +void +hns3_parse_devargs(struct rte_eth_dev *dev) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + struct hns3_hw *hw = &hns->hw; + struct rte_kvargs *kvlist; + + if (dev->device->devargs == NULL) + return; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); + if (!kvlist) + return; + + rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, + &hns3_parse_io_hint_func, &rx_func_hint); + rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, + &hns3_parse_io_hint_func, &tx_func_hint); + rte_kvargs_free(kvlist); + + if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, + hns3_get_io_hint_func_name(rx_func_hint)); + hns->rx_func_hint = rx_func_hint; + if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, + hns3_get_io_hint_func_name(tx_func_hint)); + hns->tx_func_hint = tx_func_hint; +} + static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, @@ -6625,6 +6698,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = false; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); /* * Set default max packet size according to the mtu @@ -6758,5 +6832,8 @@ static struct rte_pci_driver rte_hns3_pmd = { RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 932600d..ec4b475 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -772,9 +772,23 @@ struct hns3_adapter { bool tx_simple_allowed; bool tx_vec_allowed; + uint32_t rx_func_hint; + uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" + #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 @@ -975,6 +989,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); +void hns3_parse_devargs(struct rte_eth_dev *dev); static inline bool is_reset_pending(struct hns3_adapter *hns) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index fd20c52..f3eaefb 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = true; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); ret = hns3_reset_init(hw); if (ret) @@ -2962,3 +2963,6 @@ static struct rte_pci_driver rte_hns3vf_pmd = { RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 00167c4..f5c7d71 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2689,13 +2689,26 @@ hns3_get_rx_function(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; uint64_t offloads = dev->data->dev_conf.rxmode.offloads; + bool vec_allowed, sve_allowed, simple_allowed; + + vec_allowed = hns->rx_vec_allowed && + hns3_rx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->rx_simple_allowed && !dev->data->scattered_rx && + (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; + + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_recv_pkts_vec; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_recv_pkts_vec_sve; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) + return hns3_recv_pkts; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) + return hns3_recv_scattered_pkts; - if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0) - return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve : - hns3_recv_pkts_vec; - - if (hns->rx_simple_allowed && !dev->data->scattered_rx && - (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0) + if (vec_allowed) + return hns3_recv_pkts_vec; + if (simple_allowed) return hns3_recv_pkts; return hns3_recv_scattered_pkts; @@ -3930,19 +3943,32 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) { uint64_t offloads = dev->data->dev_conf.txmode.offloads; struct hns3_adapter *hns = dev->data->dev_private; + bool vec_allowed, sve_allowed, simple_allowed; - if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) { - *prep = NULL; - return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve : - hns3_xmit_pkts_vec; - } + vec_allowed = hns->tx_vec_allowed && + hns3_tx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->tx_simple_allowed && + offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); - if (hns->tx_simple_allowed && - offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) { - *prep = NULL; + *prep = NULL; + + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_xmit_pkts_vec; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_xmit_pkts_vec_sve; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) return hns3_xmit_pkts_simple; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { + *prep = hns3_prep_pkts; + return hns3_xmit_pkts; } + if (vec_allowed) + return hns3_xmit_pkts_vec; + if (simple_allowed) + return hns3_xmit_pkts_simple; + *prep = hns3_prep_pkts; return hns3_xmit_pkts; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 2/8] net/hns3: support for outer UDP cksum 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) ` (5 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengchang Tang <tangchengchang@huawei.com> Kunpeng930 support outer UDP cksum, this patch add support for it. Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 1d85942..c3324d8 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 8b9f075..03f8048 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw, if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B)) + hns3_set_bit(hw->capability, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1); } static uint32_t diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 28aa27a..3949153 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index ec4b475..0fc0a1c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -798,6 +798,7 @@ enum { #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 #define HNS3_DEV_SUPPORT_STASH_B 0x7 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -831,6 +832,9 @@ enum { #define hns3_dev_rxd_adv_layout_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index f3eaefb..e1e41b8 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index f5c7d71..7529279 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2967,7 +2967,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ? rxm->outer_l2_len + rxm->outer_l3_len : 0; paylen = rxm->pkt_len - hdr_len; - desc->tx.paylen = rte_cpu_to_le_32(paylen); + desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); hns3_set_tso(desc, paylen, rxm); /* @@ -3204,8 +3204,10 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, { struct hns3_desc *tx_ring = txq->tx_ring; struct hns3_desc *desc = &tx_ring[tx_desc_id]; + uint64_t ol_flags = m->ol_flags; uint32_t tmp_outer = 0; uint32_t tmp_inner = 0; + uint32_t tmp_ol4cs; int ret; /* @@ -3215,7 +3217,7 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * calculations, the length of the L2 header include the outer and * inner, will be filled during the parsing of tunnel packects. */ - if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) { + if (!(ol_flags & PKT_TX_TUNNEL_MASK)) { /* * For non tunnel type the tunnel type id is 0, so no need to * assign a value to it. Only the inner(normal) L2 header length @@ -3230,7 +3232,8 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * inner l2_len. It would lead a cksum error. So driver has to * calculate the header length. */ - if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) && + if (unlikely(!(ol_flags & + (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) && m->outer_l2_len == 0)) { struct rte_net_hdr_lens hdr_len; (void)rte_net_get_ptype(m, &hdr_len, @@ -3247,6 +3250,9 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); + tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ? + BIT(HNS3_TXD_OL4CS_B) : 0; + desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); return 0; } @@ -3376,31 +3382,78 @@ hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, return false; } +static bool +hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv4_hdr *ipv4_hdr; + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags); + + return true; + } + *l4_proto = ipv4_hdr->next_proto_id; + return false; +} + +static bool +hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv6_hdr *ipv6_hdr; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + + return true; + } + *l4_proto = ipv6_hdr->proto; + return false; +} + static void hns3_outer_header_cksum_prepare(struct rte_mbuf *m) { uint64_t ol_flags = m->ol_flags; uint32_t paylen, hdr_len, l4_proto; + struct rte_udp_hdr *udp_hdr; if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6))) return; if (ol_flags & PKT_TX_OUTER_IPV4) { - struct rte_ipv4_hdr *ipv4_hdr; - ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->outer_l2_len); - l4_proto = ipv4_hdr->next_proto_id; - if (ol_flags & PKT_TX_OUTER_IP_CKSUM) - ipv4_hdr->hdr_checksum = 0; + if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto)) + return; } else { - struct rte_ipv6_hdr *ipv6_hdr; - ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, - m->outer_l2_len); - l4_proto = ipv6_hdr->proto; + if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto)) + return; } + /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */ if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) { - struct rte_udp_hdr *udp_hdr; hdr_len = m->l2_len + m->l3_len + m->l4_len; hdr_len += m->outer_l2_len + m->outer_l3_len; paylen = m->pkt_len - hdr_len; @@ -3686,7 +3739,7 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); @@ -3702,7 +3755,7 @@ hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 9adeb24..cd04200 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -149,6 +149,7 @@ #define HNS3_TXD_MSS_S 0 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22 #define HNS3_L2_LEN_UNIT 1UL #define HNS3_L3_LEN_UNIT 2UL #define HNS3_L4_LEN_UNIT 2UL @@ -234,7 +235,7 @@ struct hns3_desc { }; }; - uint32_t paylen; + uint32_t paylen_fd_dop_ol4cs; uint16_t tp_fe_sc_vld_ra_ri; uint16_t mss; } tx; @@ -503,6 +504,7 @@ struct hns3_queue_info { }; #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \ diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 2a22a1a..90e45c6 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0)); /* save offset 24~31byte of every BD */ - svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen, - offsets, svdup_n_u64(valid_bit)); + svst1_scatter_u64offset_u64(pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets, svdup_n_u64(valid_bit)); /* Increment bytes counter */ uint32_t idx; -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 3/8] net/hns3: adjust the format of RAS related structures 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) ` (4 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Adjust the format of hns3 RAS related structures to resolve the static check warnings. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 2563504..265dae8 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { }; static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "egu_cge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "egu_cge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "egu_lge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "egu_lge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "cge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "lge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "lge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "cge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "lge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "egu_cge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "egu_lge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "egu_ge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "egu_cge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "egu_cge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "egu_lge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "egu_lge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "cge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "lge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "lge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "cge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "lge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "egu_cge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "egu_lge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "egu_ge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk = 0xFFFFFFFF, - .msg = "rpu_rx_pkt_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = 0xFFFFFFFF, + .msg = "rpu_rx_pkt_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk = BIT(13), - .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rcb_tx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rcb_rx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rcb_tx_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rcb_rx_ebd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rcb_tso_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rcb_tx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rcb_rx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tpu_tx_pkt_0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tpu_tx_pkt_1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "rd_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "wr_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "ooo_ecc_err_detect", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(31), - .msg = "ooo_ecc_err_multpl", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(13), + .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rcb_tx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rcb_rx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rcb_tx_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rcb_rx_ebd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rcb_tso_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rcb_tx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rcb_rx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tpu_tx_pkt_0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tpu_tx_pkt_1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "rd_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "wr_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "ooo_ecc_err_detect", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(31), + .msg = "ooo_ecc_err_multpl", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk = BIT(29), - .msg = "rx_q_search_miss", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(29), + .msg = "rx_q_search_miss", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "low_water_line_err_port", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "low_water_line_err_port", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk = BIT(0), - .msg = "tx_vlan_tag_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "rss_list_tc_unassigned_queue_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "tx_vlan_tag_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "rss_list_tc_unassigned_queue_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk = BIT(3), - .msg = "tx_rd_fbd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(4), - .msg = "rx_rd_ebd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(3), + .msg = "tx_rd_fbd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(4), + .msg = "rx_rd_ebd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk = BIT(0), - .msg = "over_8bd_no_fe", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tso_mss_cmp_min_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "tso_mss_cmp_max_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "buf_wait_timeout", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "over_8bd_no_fe", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tso_mss_cmp_min_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "tso_mss_cmp_max_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "buf_wait_timeout", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "imp_itcm0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "imp_itcm1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "imp_itcm2_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "imp_itcm3_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "imp_dtcm0_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "imp_dtcm0_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "imp_dtcm1_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "imp_dtcm1_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(17), - .msg = "imp_itcm4_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "imp_itcm0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "imp_itcm1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "imp_itcm2_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "imp_itcm3_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "imp_dtcm0_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "imp_dtcm0_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "imp_dtcm1_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "imp_dtcm1_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(17), + .msg = "imp_itcm4_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "cmdq_nic_rx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "cmdq_nic_tx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cmdq_nic_rx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "cmdq_nic_tx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "cmdq_nic_rx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "cmdq_nic_tx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "cmdq_nic_rx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "cmdq_nic_tx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "cmdq_nic_rx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "cmdq_nic_tx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cmdq_nic_rx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "cmdq_nic_tx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "cmdq_nic_rx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "cmdq_nic_tx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "cmdq_nic_rx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "cmdq_nic_tx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk = BIT(6), - .msg = "tqp_int_cfg_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "tqp_int_cfg_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(8), - .msg = "tqp_int_ctrl_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "tqp_int_ctrl_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(10), - .msg = "tx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "rx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(6), + .msg = "tqp_int_cfg_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "tqp_int_cfg_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(8), + .msg = "tqp_int_ctrl_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "tqp_int_ctrl_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(10), + .msg = "tx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "rx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk = BIT(0), - .msg = "imp_rd_poison_int", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "imp_rd_poison_int", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; #define HNS3_SSU_MEM_ECC_ERR(x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +} static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { HNS3_SSU_MEM_ECC_ERR(0), @@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { }; static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk = BIT(0), - .msg = "ssu_mem32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ssu_mem32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk = BIT(0), - .msg = "buf_sum_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "ppp_mb_num_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "ppp_mbid_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ppp_rlt_mac_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ppp_rlt_host_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "cks_edit_position_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "cks_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "vlan_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "vlan_num_ot_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "vlan_num_in_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "buf_sum_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "ppp_mb_num_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "ppp_mbid_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ppp_rlt_mac_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ppp_rlt_host_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "cks_edit_position_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "cks_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "vlan_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "vlan_num_ot_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "vlan_num_in_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_int[] = { - { .int_msk = BIT(0), - .msg = "igu_rx_buf0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_rx_buf1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "igu_rx_buf0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_rx_buf1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "msix_nic_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "msix_nic_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk = BIT(0), - .msg = "vf_vlan_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "umv_mcast_group_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "umv_key_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "umv_key_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "umv_key_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "umv_key_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "umv_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "rss_tc_mode_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rss_idt_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "rss_idt_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "rss_idt_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "rss_idt_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "rss_idt_mem4_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "rss_idt_mem5_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rss_idt_mem6_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rss_idt_mem7_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rss_idt_mem8_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rss_idt_mem9_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rss_idt_mem10_ecc_m1bit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rss_idt_mem11_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rss_idt_mem12_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rss_idt_mem13_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rss_idt_mem14_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rss_idt_mem15_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "port_vlan_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "mcast_linear_table_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "mcast_result_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "flow_director_ad_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "flow_director_ad_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "rx_vlan_tag_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "vf_vlan_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "umv_mcast_group_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "umv_key_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "umv_key_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "umv_key_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "umv_key_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "umv_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "rss_tc_mode_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rss_idt_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "rss_idt_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "rss_idt_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "rss_idt_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "rss_idt_mem4_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "rss_idt_mem5_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rss_idt_mem6_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rss_idt_mem7_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rss_idt_mem8_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rss_idt_mem9_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rss_idt_mem10_ecc_m1bit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rss_idt_mem11_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rss_idt_mem12_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rss_idt_mem13_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rss_idt_mem14_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rss_idt_mem15_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "port_vlan_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "mcast_linear_table_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "mcast_result_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "flow_director_ad_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "flow_director_ad_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "rx_vlan_tag_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(0), - .msg = "hfs_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rslt_descr_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tx_vlan_tag_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "FD_CN0_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "FD_CN1_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "GRO_AD_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "hfs_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rslt_descr_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tx_vlan_tag_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "FD_CN0_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "FD_CN1_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "GRO_AD_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(4), - .msg = "gro_bd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "gro_context_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_stash_cfg_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "axi_rd_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(4), + .msg = "gro_bd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "gro_context_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_stash_cfg_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "axi_rd_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk = BIT(1), - .msg = "tm_sch_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tm_sch_port_shap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tm_sch_port_shap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "tm_sch_port_shap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "tm_sch_port_shap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "tm_sch_rq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "tm_sch_rq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tm_sch_nq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tm_sch_nq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "tm_sch_roce_up_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "tm_sch_roce_up_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "tm_sch_rcb_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "tm_sch_rcb_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "tm_sch_ssu_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(31), - .msg = "tm_sch_ssu_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "tm_sch_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tm_sch_port_shap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tm_sch_port_shap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "tm_sch_port_shap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "tm_sch_port_shap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "tm_sch_rq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "tm_sch_rq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tm_sch_nq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tm_sch_nq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "tm_sch_roce_up_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "tm_sch_roce_up_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "tm_sch_rcb_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "tm_sch_rcb_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "tm_sch_ssu_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(31), + .msg = "tm_sch_ssu_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk = BIT(0), - .msg = "qcn_shap_gp0_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "qcn_shap_gp0_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "qcn_shap_gp1_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_shap_gp1_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "qcn_shap_gp2_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_shap_gp2_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "qcn_shap_gp3_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_shap_gp3_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "qcn_shap_gp0_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_shap_gp0_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "qcn_shap_gp1_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_shap_gp1_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "qcn_shap_gp2_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_gp2_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "qcn_shap_gp3_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_shap_gp3_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "qcn_byte_info_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_byte_info_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "qcn_shap_gp0_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "qcn_shap_gp0_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "qcn_shap_gp1_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_shap_gp1_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "qcn_shap_gp2_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_shap_gp2_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "qcn_shap_gp3_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_shap_gp3_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "qcn_shap_gp0_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_shap_gp0_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "qcn_shap_gp1_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_shap_gp1_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "qcn_shap_gp2_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_gp2_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "qcn_shap_gp3_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_shap_gp3_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "qcn_byte_info_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_byte_info_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "qcn_byte_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_time_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_fb_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_link_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_rate_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_tmplt_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_cfg_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "qcn_gp3_barral_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "qcn_byte_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_time_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_fb_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_link_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_rate_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_tmplt_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_cfg_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "qcn_gp3_barral_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "ncsi_tx_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "ncsi_tx_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk = BIT(0), - .msg = "ig_mac_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ig_host_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ig_roc_buf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ig_host_data_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ig_host_key_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qm_eof_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "mb_rlt_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "dup_uncopy_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "dup_cnt_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "dup_cnt_drop_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "dup_cnt_wrb_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "host_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "mac_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "host_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "mac_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "dup_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "out_queue_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "bank2_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "bank1_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "bank0_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ig_mac_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ig_host_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ig_roc_buf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ig_host_data_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ig_host_key_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qm_eof_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "mb_rlt_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "dup_uncopy_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "dup_cnt_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "dup_cnt_drop_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "dup_cnt_wrb_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "host_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "mac_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "host_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "mac_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "dup_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "out_queue_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "bank2_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "bank1_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "bank0_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk = BIT(0), - .msg = "ets_rd_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ets_wr_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ets_rd_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ets_wr_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ets_rd_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ets_wr_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ets_rd_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ets_wr_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "rx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rx_stp_fifo_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "rx_stp_fifo_underflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tx_buf_underrun", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "rx_stp_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "rx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rx_stp_fifo_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "rx_stp_fifo_underflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tx_buf_underrun", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "rx_stp_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tpu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "roc_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tpu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "igu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "roc_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tpu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "igu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "ets_rd_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "ets_wr_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ets_rd_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "ets_wr_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tpu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "roc_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tpu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "igu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "roc_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tpu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "igu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "ets_rd_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "ets_wr_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ets_rd_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "ets_wr_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "IMP_TCM_ECC_INT_STS", - .hw_err = imp_tcm_ecc_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "CMDQ_MEM_ECC_INT_STS", - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "IMP_RD_POISON_INT_STS", - .hw_err = imp_rd_poison_int }, - { .desc_offset = 0, - .data_offset = 3, - .msg = "TQP_INT_ECC_INT_STS", - .hw_err = tqp_int_ecc_int }, - { .desc_offset = 0, - .data_offset = 4, - .msg = "MSIX_ECC_INT_STS", - .hw_err = msix_ecc_int }, - { .desc_offset = 2, - .data_offset = 2, - .msg = "SSU_ECC_MULTI_BIT_INT_0", - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset = 2, - .data_offset = 3, - .msg = "SSU_ECC_MULTI_BIT_INT_1", - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset = 2, - .data_offset = 4, - .msg = "SSU_COMMON_ERR_INT", - .hw_err = ssu_common_ecc_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "IGU_INT_STS", - .hw_err = igu_int }, - { .desc_offset = 4, - .data_offset = 1, - .msg = "PPP_MPF_ABNORMAL_INT_ST1", - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset = 4, - .data_offset = 3, - .msg = "PPP_MPF_ABNORMAL_INT_ST3", - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset = 5, - .data_offset = 1, - .msg = "PPU_MPF_ABNORMAL_INT_ST1", - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset = 5, - .data_offset = 3, - .msg = "PPU_MPF_ABNORMAL_INT_ST3", - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset = 6, - .data_offset = 0, - .msg = "TM_SCH_RINT", - .hw_err = tm_sch_int }, - { .desc_offset = 7, - .data_offset = 0, - .msg = "QCN_FIFO_RINT", - .hw_err = qcn_fifo_int }, - { .desc_offset = 7, - .data_offset = 1, - .msg = "QCN_ECC_RINT", - .hw_err = qcn_ecc_int }, - { .desc_offset = 9, - .data_offset = 0, - .msg = "NCSI_ECC_INT_RPT", - .hw_err = ncsi_ecc_int }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "IMP_TCM_ECC_INT_STS", + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "CMDQ_MEM_ECC_INT_STS", + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "IMP_RD_POISON_INT_STS", + .hw_err = imp_rd_poison_int + }, { + .desc_offset = 0, + .data_offset = 3, + .msg = "TQP_INT_ECC_INT_STS", + .hw_err = tqp_int_ecc_int + }, { + .desc_offset = 0, + .data_offset = 4, + .msg = "MSIX_ECC_INT_STS", + .hw_err = msix_ecc_int + }, { + .desc_offset = 2, + .data_offset = 2, + .msg = "SSU_ECC_MULTI_BIT_INT_0", + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset = 2, + .data_offset = 3, + .msg = "SSU_ECC_MULTI_BIT_INT_1", + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset = 2, + .data_offset = 4, + .msg = "SSU_COMMON_ERR_INT", + .hw_err = ssu_common_ecc_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "IGU_INT_STS", + .hw_err = igu_int + }, { + .desc_offset = 4, + .data_offset = 1, + .msg = "PPP_MPF_ABNORMAL_INT_ST1", + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset = 4, + .data_offset = 3, + .msg = "PPP_MPF_ABNORMAL_INT_ST3", + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset = 5, + .data_offset = 1, + .msg = "PPU_MPF_ABNORMAL_INT_ST1", + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset = 5, + .data_offset = 3, + .msg = "PPU_MPF_ABNORMAL_INT_ST3", + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset = 6, + .data_offset = 0, + .msg = "TM_SCH_RINT", + .hw_err = tm_sch_int + }, { + .desc_offset = 7, + .data_offset = 0, + .msg = "QCN_FIFO_RINT", + .hw_err = qcn_fifo_int + }, { + .desc_offset = 7, + .data_offset = 1, + .msg = "QCN_ECC_RINT", + .hw_err = qcn_ecc_int + }, { + .desc_offset = 9, + .data_offset = 0, + .msg = "NCSI_ECC_INT_RPT", + .hw_err = ncsi_ecc_int + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_RAS", - .hw_err = ssu_port_based_err_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "SSU_FIFO_OVERFLOW_INT", - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "SSU_ETS_TCG_INT", - .hw_err = ssu_ets_tcg_int }, - { .desc_offset = 1, - .data_offset = 0, - .msg = "IGU_EGU_TNL_INT_STS", - .hw_err = igu_egu_tnl_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_RAS", + .hw_err = ssu_port_based_err_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "SSU_FIFO_OVERFLOW_INT", + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "SSU_ETS_TCG_INT", + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset = 1, + .data_offset = 0, + .msg = "IGU_EGU_TNL_INT_STS", + .hw_err = igu_egu_tnl_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset = 1, - .data_offset = 0, - .msg = "MAC_AFIFO_TNL_INT_R", - .hw_err = mac_afifo_tnl_int }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 1, + .data_offset = 0, + .msg = "MAC_AFIFO_TNL_INT_R", + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_MSIX", - .hw_err = ssu_port_based_pf_int }, - { .desc_offset = 2, - .data_offset = 0, - .msg = "PPP_PF_ABNORMAL_INT_ST0", - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_MSIX", + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset = 2, + .data_offset = 0, + .msg = "PPP_PF_ABNORMAL_INT_ST0", + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; enum hns3_hw_err_type { -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 4/8] net/hns3: delete redundant xstats RAS statistics 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (2 preceding siblings ...) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) ` (3 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3949153..139e893 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5768,14 +5768,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { hns3_warn(hw, "Detected IMP RD poison!"); - hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { hns3_warn(hw, "Detected IMP CMDQ error!"); - hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 0fc0a1c..314916c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -561,38 +561,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_int_cnt; - uint64_t ppu_mpf_abn_int_st2_msix_cnt; - uint64_t ssu_port_based_pf_int_cnt; - uint64_t ppp_pf_abnormal_int_cnt; - uint64_t ppu_pf_abnormal_int_msix_cnt; - - uint64_t imp_tcm_ecc_int_cnt; - uint64_t cmdq_mem_ecc_int_cnt; - uint64_t imp_rd_poison_int_cnt; - uint64_t tqp_int_ecc_int_cnt; - uint64_t msix_ecc_int_cnt; - uint64_t ssu_ecc_multi_bit_int_0_cnt; - uint64_t ssu_ecc_multi_bit_int_1_cnt; - uint64_t ssu_common_ecc_int_cnt; - uint64_t igu_int_cnt; - uint64_t ppp_mpf_abnormal_int_st1_cnt; - uint64_t ppp_mpf_abnormal_int_st3_cnt; - uint64_t ppu_mpf_abnormal_int_st1_cnt; - uint64_t ppu_mpf_abn_int_st2_ras_cnt; - uint64_t ppu_mpf_abnormal_int_st3_cnt; - uint64_t tm_sch_int_cnt; - uint64_t qcn_fifo_int_cnt; - uint64_t qcn_ecc_int_cnt; - uint64_t ncsi_ecc_int_cnt; - uint64_t ssu_port_based_err_int_cnt; - uint64_t ssu_fifo_overflow_int_cnt; - uint64_t ssu_ets_tcg_int_cnt; - uint64_t igu_egu_tnl_int_cnt; - uint64_t ppu_pf_abnormal_int_ras_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -738,9 +706,6 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 265dae8..c259f2e 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } - hns3_error_int_stats_add(hns, reg); } err++; } diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 941c75f..7cda36c 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -201,65 +201,6 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = { HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)} }; -static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = { - {"MAC_AFIFO_TNL_INT_R", - HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)}, - {"SSU_PORT_BASED_ERR_INT_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)}, - {"PPP_PF_ABNORMAL_INT_ST0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)}, - {"IMP_TCM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)}, - {"CMDQ_MEM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)}, - {"IMP_RD_POISON_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)}, - {"TQP_INT_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)}, - {"MSIX_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)}, - {"SSU_COMMON_ERR_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)}, - {"IGU_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)}, - {"TM_SCH_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)}, - {"QCN_FIFO_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)}, - {"QCN_ECC_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)}, - {"NCSI_ECC_INT_RPT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)}, - {"SSU_PORT_BASED_ERR_INT_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)}, - {"SSU_FIFO_OVERFLOW_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)}, - {"SSU_ETS_TCG_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)}, - {"IGU_EGU_TNL_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)}, -}; - /* The statistic of reset */ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = { {"REQ_RESET_CNT", @@ -333,9 +274,6 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) -#define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \ - sizeof(hns3_error_int_stats_strings[0])) - #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \ sizeof(hns3_reset_stats_strings[0])) @@ -363,7 +301,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -750,23 +688,6 @@ hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } -void -hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) -{ - struct hns3_pf *pf = &hns->pf; - uint16_t i; - char *addr; - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - *(uint64_t *)addr += 1; - break; - } - } -} - static void hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) @@ -932,7 +853,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; struct hns3_hw *hw = &hns->hw; struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; @@ -986,13 +906,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } } /* Get the reset stat */ @@ -1134,13 +1047,6 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_imissed_stats_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_error_int_stats_strings[i].name); - count++; - } } for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, @@ -1358,7 +1264,6 @@ int hns3_dev_xstats_reset(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; int ret; /* Clear tqp stats */ @@ -1379,9 +1284,6 @@ hns3_dev_xstats_reset(struct rte_eth_dev *dev) if (ret) return ret; - /* Clear error stats */ - memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats)); - return 0; } diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 70a9c5b..8ea69b4 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint32_t size); int hns3_stats_reset(struct rte_eth_dev *dev); -void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err); int hns3_tqp_stats_init(struct hns3_hw *hw); void hns3_tqp_stats_uninit(struct hns3_hw *hw); int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear); -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 5/8] net/hns3: support imissed stats for PF/VF 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (3 preceding siblings ...) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) ` (2 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_cmd.h | 13 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 234 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 094bf7e..4126574 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -111,6 +111,8 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, @@ -957,6 +959,17 @@ struct hns3_query_rpu_cmd { uint32_t rsv2[2]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t oq_glb_drop_cnt; + uint32_t rev1[2]; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 139e893..82538d4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = false; @@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = true; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 314916c..6e74ec8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -426,6 +426,9 @@ struct hns3_queue_intr { #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -544,6 +547,24 @@ struct hns3_hw { * port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + + /* + * drop_stats_mode mode. + * value range: + * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 + * + * - HNS3_PKTS_DROP_STATS_MODE1 + * This mode for kunpeng920. In this mode, port level imissed stats + * is supported. It only includes RPU drop stats. + * + * - HNS3_PKTS_DROP_STATS_MODE2 + * This mode for kunpeng930. In this mode, imissed stats and oerrors + * stats is supported. Function level imissed stats is supported. It + * includes RPU drop stats in VF, and includes both RPU drop stats + * and SSU drop stats in PF. Oerror stats is also supported in PF. + */ + uint8_t drop_stats_mode; + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index e1e41b8..7ee468f 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; @@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; @@ -1875,6 +1877,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) if (ret) goto err_get_config; + /* Hardware statistics of imissed registers cleared. */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + goto err_set_tc_queue; + } + ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); if (ret) { PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h index 0540554..e141fe1 100644 --- a/drivers/net/hns3/hns3_regs.h +++ b/drivers/net/hns3/hns3_regs.h @@ -36,6 +36,8 @@ #define HNS3_GLOBAL_RESET_REG 0x20A00 #define HNS3_FUN_RST_ING 0x20C00 #define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008 /* Vector0 register bits for reset */ diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 7cda36c..76df847 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -269,6 +269,8 @@ static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = { static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { {"RPU_DROP_CNT", HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)}, + {"SSU_DROP_CNT", + HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)}, }; #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ @@ -301,8 +303,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ - HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -419,7 +420,7 @@ hns3_query_update_mac_stats(struct rte_eth_dev *dev) } static int -hns3_update_rpu_drop_stats(struct hns3_hw *hw) +hns3_update_port_rpu_drop_stats(struct hns3_hw *hw) { struct hns3_rx_missed_stats *stats = &hw->imissed_stats; struct hns3_query_rpu_cmd *req; @@ -449,11 +450,90 @@ hns3_update_rpu_drop_stats(struct hns3_hw *hw) return 0; } +static void +hns3_update_function_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + + stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG); +} + +static int +hns3_update_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret = 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf) + ret = hns3_update_port_rpu_drop_stats(hw); + else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2) + hns3_update_function_rpu_drop_stats(hw); + + return ret; +} + +static int +hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + int bd_num, bool is_rx) +{ + struct hns3_query_ssu_cmd *req; + int ret; + int i; + + for (i = 0; i < bd_num - 1; i++) { + hns3_cmd_setup_basic_desc(&desc[i], + HNS3_OPC_SSU_DROP_REG, true); + desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + } + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true); + req = (struct hns3_query_ssu_cmd *)desc[0].data; + req->rxtx = is_rx ? 0 : 1; + ret = hns3_cmd_send(hw, desc, bd_num); + + return ret; +} + +static int +hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + true); + if (ret) { + hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_glb_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + stats->ssu_rx_drop_cnt += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); int ret; + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) { + ret = hns3_update_port_rx_ssu_drop_stats(hw); + if (ret) + return ret; + } + ret = hns3_update_rpu_drop_stats(hw); if (ret) return ret; @@ -488,19 +568,17 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) uint16_t i; int ret; - if (!hns->is_vf) { - /* Update imissed stats */ - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt; + /* Update imissed stats */ + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt + + imissed_stats->ssu_rx_drop_cnt; - /* Reads all the stats of a rxq in a loop to keep them synchronized */ + /* Get the error stats and bytes of received packets */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) @@ -556,17 +634,14 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) uint16_t i; int ret; - if (!hns->is_vf) { - /* - * Note: Reading hardware statistics of imissed registers will - * clear them. - */ - ret = hns3_update_imissed_stats(hw, true); - if (ret) { - hns3_err(hw, "clear imissed stats failed, ret = %d", - ret); - return ret; - } + /* + * Note: Reading hardware statistics of imissed registers will + * clear them. + */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + return ret; } for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { @@ -630,6 +705,22 @@ hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev) return 0; } +static int +hns3_get_imissed_stats_num(struct hns3_adapter *hns) +{ +#define NO_IMISSED_STATS_NUM 0 +#define RPU_STATS_ITEM_NUM 1 + struct hns3_hw *hw = &hns->hw; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return NO_IMISSED_STATS_NUM; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) + return HNS3_NUM_IMISSED_XSTATS; + + return RPU_STATS_ITEM_NUM; +} + /* This function calculates the number of xstats based on the current config */ static int hns3_xstats_calc_num(struct rte_eth_dev *dev) @@ -647,13 +738,17 @@ hns3_xstats_calc_num(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM; int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM; + int stats_num; + + stats_num = rx_comm_stats_num + tx_comm_stats_num; + stats_num += hns3_get_imissed_stats_num(hns); if (hns->is_vf) - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_NUM_RESET_XSTATS; + stats_num += HNS3_NUM_RESET_XSTATS; else - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_FIX_NUM_STATS; + stats_num += HNS3_FIX_NUM_STATS; + + return stats_num; } static void @@ -835,6 +930,31 @@ hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, hns3_txq_basic_stats_get(dev, xstats, count); } +static void +hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; + int imissed_stats_num; + int cnt = *count; + char *addr; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + addr = (char *)imissed_stats + + hns3_imissed_stats_strings[i].offset; + xstats[cnt].value = *(uint64_t *)addr; + xstats[cnt].id = cnt; + cnt++; + } + + *count = cnt; +} + /* * Retrieve extended(tqp | Mac) statistics of an Ethernet device. * @param dev @@ -854,7 +974,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, { struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_bd_errors_stats *rx_err_stats; @@ -890,24 +1009,17 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, xstats[count].id = count; count++; } + } - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - addr = (char *)imissed_stats + - hns3_imissed_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } - + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + hns3_imissed_stats_get(dev, xstats, &count); + /* Get the reset stat */ for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset; @@ -992,6 +1104,28 @@ hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev, } } +static void +hns3_imissed_stats_name_get(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + uint32_t *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t cnt = *count; + int imissed_stats_num; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + snprintf(xstats_names[cnt].name, + sizeof(xstats_names[cnt].name), + "%s", hns3_imissed_stats_strings[i].name); + cnt++; + } + + *count = cnt; +} + /* * Retrieve names of extended statistics of an Ethernet device. * @@ -1040,14 +1174,10 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_mac_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_imissed_stats_strings[i].name); - count++; - } } + + hns3_imissed_stats_name_get(dev, xstats_names, &count); + for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 8ea69b4..273be42 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -112,6 +112,7 @@ struct hns3_mac_stats { struct hns3_rx_missed_stats { uint64_t rpu_rx_drop_cnt; + uint64_t ssu_rx_drop_cnt; }; /* store statistics names and its offset in stats structure */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 6/8] net/hns3: support oerrors stats in PF 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (4 preceding siblings ...) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 8/8] net/hns3: support query Rx " Min Hu (Connor) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This patch added oerrors stats for PF in kunpeng930. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 64 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 6e74ec8..f69e2d8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -443,6 +443,7 @@ struct hns3_hw { /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 76df847..9243f9c 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -519,6 +519,31 @@ hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) return 0; } +static int +hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + false); + if (ret) { + hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_glb_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + hw->oerror_stats += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { @@ -544,6 +569,25 @@ hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) return 0; } +static int +hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf) + return 0; + + ret = hns3_update_port_tx_ssu_drop_stats(hw); + if (ret) + return ret; + + if (is_clear) + hw->oerror_stats = 0; + + return 0; +} + /* * Query tqp tx queue statistics ,opcode id: 0x0B03. * Query tqp rx queue statistics ,opcode id: 0x0B13. @@ -608,7 +652,14 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) rte_stats->obytes += txq->basic_stats.bytes; } - rte_stats->oerrors = 0; + ret = hns3_update_oerror_stats(hw, false); + if (ret) { + hns3_err(hw, "update oerror stats failed, ret = %d", + ret); + return ret; + } + rte_stats->oerrors = hw->oerror_stats; + /* * If HW statistics are reset by stats_reset, but a lot of residual * packets exist in the hardware queue and these packets are error @@ -644,6 +695,17 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) return ret; } + /* + * Note: Reading hardware statistics of oerror registers will + * clear them. + */ + ret = hns3_update_oerror_stats(hw, true); + if (ret) { + hns3_err(hw, "clear oerror stats failed, ret = %d", + ret); + return ret; + } + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 7/8] net/hns3: support query Tx descriptor status 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (5 preceding siblings ...) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 8/8] net/hns3: support query Rx " Min Hu (Connor) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 3aeea8e..2c0cb89 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index c796cd5..e60b09b 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index c3324d8..e8b0c6e 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 82538d4..8c65be4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; return ret; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 7ee468f..4412da3 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 7529279..a84da15 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4044,6 +4044,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; } else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; @@ -4256,6 +4257,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) return -ENOTSUP; } +int +hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + volatile struct hns3_desc *txdp; + struct hns3_tx_queue *txq; + struct rte_eth_dev *dev; + uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; + if (offset >= txq->nb_tx_desc) + return -EINVAL; + + dev = &rte_eth_devices[txq->port_id]; + if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) + return RTE_ETH_TX_DESC_UNAVAIL; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; + if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) + return RTE_ETH_TX_DESC_FULL; + else + return RTE_ETH_TX_DESC_DONE; +} + uint32_t hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index cd04200..82d5aa0 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,5 +720,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v4 8/8] net/hns3: support query Rx descriptor status 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (6 preceding siblings ...) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) @ 2021-03-17 9:50 ` Min Hu (Connor) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-17 9:50 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 2c0cb89..3988be4 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index e60b09b..1640669 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index e8b0c6e..6e1fc81 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 8c65be4..b7bfac8 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6772,6 +6772,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 4412da3..34a6927 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2915,6 +2915,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index a84da15..feeb702 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4042,6 +4042,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) if (hns->hw.adapter_state == HNS3_NIC_STARTED && __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) { eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; @@ -4258,6 +4259,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) } int +hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + volatile struct hns3_desc *rxdp; + struct hns3_rx_queue *rxq; + struct rte_eth_dev *dev; + uint32_t bd_base_info; + uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; + if (offset >= rxq->nb_rx_desc) + return -EINVAL; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; + if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { + if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ + if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) + return RTE_ETH_RX_DESC_UNAVAIL; + } else { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) + return RTE_ETH_RX_DESC_AVAIL; + else + return RTE_ETH_RX_DESC_DONE; +} + +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { volatile struct hns3_desc *txdp; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 82d5aa0..f9b3048 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,6 +720,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (9 preceding siblings ...) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) ` (7 more replies) 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) 11 siblings, 8 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This series add four features according to the 21.05 roadmap, and also two cleanups added. Chengchang Tang (1): net/hns3: support for outer UDP cksum Chengwen Feng (1): net/hns3: support runtime config to select IO burst func Hongbo Zheng (4): net/hns3: adjust the format of RAS related structures net/hns3: delete redundant xstats RAS statistics net/hns3: support query Tx descriptor status net/hns3: support query Rx descriptor status Min Hu (Connor) (2): net/hns3: support imissed stats for PF/VF net/hns3: support oerrors stats in PF doc/guides/nics/features/hns3.ini | 2 + doc/guides/nics/features/hns3_vf.ini | 2 + doc/guides/nics/hns3.rst | 19 + doc/guides/rel_notes/release_21_05.rst | 4 + drivers/net/hns3/hns3_cmd.c | 3 + drivers/net/hns3/hns3_cmd.h | 13 + drivers/net/hns3/hns3_ethdev.c | 86 +- drivers/net/hns3/hns3_ethdev.h | 76 +- drivers/net/hns3/hns3_ethdev_vf.c | 18 + drivers/net/hns3/hns3_intr.c | 2127 ++++++++++++++++++-------------- drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_rxtx.c | 203 ++- drivers/net/hns3/hns3_rxtx.h | 6 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- drivers/net/hns3/hns3_stats.c | 394 +++--- drivers/net/hns3/hns3_stats.h | 2 +- 16 files changed, 1838 insertions(+), 1124 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-22 13:58 ` Ferruh Yigit 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) ` (6 subsequent siblings) 7 siblings, 1 reply; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengwen Feng <fengchengwen@huawei.com> Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration. Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function. This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common. The driver will use the following rules to select io burst func: a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function. b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function. c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function. d. if hint equal common then use the common function. e. if hint not set then: e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function. e.3. else use the common function. Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE). In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- v6: - document hns3.rst about description of vec, common and simple. --- doc/guides/nics/hns3.rst | 19 +++++++++ doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- 6 files changed, 156 insertions(+), 14 deletions(-) diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst index 84bd7a3..8f48240 100644 --- a/doc/guides/nics/hns3.rst +++ b/doc/guides/nics/hns3.rst @@ -46,6 +46,25 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. +Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Rx usage condition then use the default vector Rx implementation, 'neon' for Kunpeng Arm platform. + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function which indicates the Scalar algorithm obtained from rte_eth_rx_burst_mode_get. + When equal "common" then use the common Rx function which indicates the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. + +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are "vec", "sve", "simple", "common". + When equal "vec" and meet the vector Tx usage condition then use the default vector Tx implementation, 'neon' for Kunpeng Arm platform. + When equal "sve" and meet the sve Tx usage condition then use the sve Tx function. + When equal "simple" and meet the simple Tx usage condition then use the simple Tx function which indicates the Scalar Simple algorithm obtained from rte_eth_tx_burst_mode_get. + When equal "common" then use the common Tx function which indicated the Scalar algorithm obtained from rte_eth_tx_burst_mode_get. + Driver compilation and testing ------------------------------ diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index dc5399f..1d85942 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 9cbcc13..28aa27a 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6,6 +6,7 @@ #include <rte_bus_pci.h> #include <ethdev_pci.h> #include <rte_pci.h> +#include <rte_kvargs.h> #include "hns3_ethdev.h" #include "hns3_logs.h" @@ -6505,6 +6506,78 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } +static int +hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) +{ + uint32_t hint = HNS3_IO_FUNC_HINT_NONE; + + RTE_SET_USED(key); + + if (strcmp(value, "vec") == 0) + hint = HNS3_IO_FUNC_HINT_VEC; + else if (strcmp(value, "sve") == 0) + hint = HNS3_IO_FUNC_HINT_SVE; + else if (strcmp(value, "simple") == 0) + hint = HNS3_IO_FUNC_HINT_SIMPLE; + else if (strcmp(value, "common") == 0) + hint = HNS3_IO_FUNC_HINT_COMMON; + + /* If the hint is valid then update output parameters */ + if (hint != HNS3_IO_FUNC_HINT_NONE) + *(uint32_t *)extra_args = hint; + + return 0; +} + +static const char * +hns3_get_io_hint_func_name(uint32_t hint) +{ + switch (hint) { + case HNS3_IO_FUNC_HINT_VEC: + return "vec"; + case HNS3_IO_FUNC_HINT_SVE: + return "sve"; + case HNS3_IO_FUNC_HINT_SIMPLE: + return "simple"; + case HNS3_IO_FUNC_HINT_COMMON: + return "common"; + default: + return "none"; + } +} + +void +hns3_parse_devargs(struct rte_eth_dev *dev) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + struct hns3_hw *hw = &hns->hw; + struct rte_kvargs *kvlist; + + if (dev->device->devargs == NULL) + return; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); + if (!kvlist) + return; + + rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, + &hns3_parse_io_hint_func, &rx_func_hint); + rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, + &hns3_parse_io_hint_func, &tx_func_hint); + rte_kvargs_free(kvlist); + + if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, + hns3_get_io_hint_func_name(rx_func_hint)); + hns->rx_func_hint = rx_func_hint; + if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, + hns3_get_io_hint_func_name(tx_func_hint)); + hns->tx_func_hint = tx_func_hint; +} + static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, @@ -6625,6 +6698,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = false; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); /* * Set default max packet size according to the mtu @@ -6758,5 +6832,8 @@ static struct rte_pci_driver rte_hns3_pmd = { RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 932600d..ec4b475 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -772,9 +772,23 @@ struct hns3_adapter { bool tx_simple_allowed; bool tx_vec_allowed; + uint32_t rx_func_hint; + uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" + #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 @@ -975,6 +989,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); +void hns3_parse_devargs(struct rte_eth_dev *dev); static inline bool is_reset_pending(struct hns3_adapter *hns) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index fd20c52..f3eaefb 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = true; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); ret = hns3_reset_init(hw); if (ret) @@ -2962,3 +2963,6 @@ static struct rte_pci_driver rte_hns3vf_pmd = { RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 00167c4..f5c7d71 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2689,13 +2689,26 @@ hns3_get_rx_function(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; uint64_t offloads = dev->data->dev_conf.rxmode.offloads; + bool vec_allowed, sve_allowed, simple_allowed; + + vec_allowed = hns->rx_vec_allowed && + hns3_rx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->rx_simple_allowed && !dev->data->scattered_rx && + (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; + + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_recv_pkts_vec; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_recv_pkts_vec_sve; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) + return hns3_recv_pkts; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) + return hns3_recv_scattered_pkts; - if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0) - return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve : - hns3_recv_pkts_vec; - - if (hns->rx_simple_allowed && !dev->data->scattered_rx && - (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0) + if (vec_allowed) + return hns3_recv_pkts_vec; + if (simple_allowed) return hns3_recv_pkts; return hns3_recv_scattered_pkts; @@ -3930,19 +3943,32 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) { uint64_t offloads = dev->data->dev_conf.txmode.offloads; struct hns3_adapter *hns = dev->data->dev_private; + bool vec_allowed, sve_allowed, simple_allowed; - if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) { - *prep = NULL; - return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve : - hns3_xmit_pkts_vec; - } + vec_allowed = hns->tx_vec_allowed && + hns3_tx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->tx_simple_allowed && + offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); - if (hns->tx_simple_allowed && - offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) { - *prep = NULL; + *prep = NULL; + + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_xmit_pkts_vec; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_xmit_pkts_vec_sve; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) return hns3_xmit_pkts_simple; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { + *prep = hns3_prep_pkts; + return hns3_xmit_pkts; } + if (vec_allowed) + return hns3_xmit_pkts_vec; + if (simple_allowed) + return hns3_xmit_pkts_simple; + *prep = hns3_prep_pkts; return hns3_xmit_pkts; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) @ 2021-03-22 13:58 ` Ferruh Yigit 2021-03-22 14:03 ` Ferruh Yigit ` (2 more replies) 0 siblings, 3 replies; 44+ messages in thread From: Ferruh Yigit @ 2021-03-22 13:58 UTC (permalink / raw) To: Min Hu (Connor), dev On 3/19/2021 1:07 AM, Min Hu (Connor) wrote: > From: Chengwen Feng <fengchengwen@huawei.com> > > Currently, the driver support multiple IO burst function and auto > selection of the most appropriate function based on offload > configuration. > > Most applications such as l2fwd/l3fwd don't provide the means to > change offload configuration, so it will use the auto selection's io > burst function. > > This patch support runtime config to select io burst function, which > add two config: rx_func_hint and tx_func_hint, both could assign > vec/sve/simple/common. > > The driver will use the following rules to select io burst func: > a. if hint equal vec and meet the vec Rx/Tx usage condition then use > the neon function. > b. if hint equal sve and meet the sve Rx/Tx usage condition then use > the sve function. > c. if hint equal simple and meet the simple Rx/Tx usage condition then > use the simple function. > d. if hint equal common then use the common function. > e. if hint not set then: > e.1. if meet the vec Rx/Tx usage condition then use the neon function. > e.2. if meet the simple Rx/Tx usage condition then use the simple > function. > e.3. else use the common function. > > Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage > condition and runtime environment (which must support SVE). > > In the previous versions, driver will preferred use the sve function > when meet the sve Rx/Tx usage condition, but in this case driver could > get better performance if use the neon function. > Is this saying 'neon' is giving better performance even if 'sve' is supported? > Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> > Signed-off-by: Min Hu (Connor) <humin29@huawei.com> > --- > v6: > - document hns3.rst about description of vec, common and simple. > --- > doc/guides/nics/hns3.rst | 19 +++++++++ > doc/guides/rel_notes/release_21_05.rst | 1 + > drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ > drivers/net/hns3/hns3_ethdev.h | 15 +++++++ > drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ > drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- > 6 files changed, 156 insertions(+), 14 deletions(-) > > diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst > index 84bd7a3..8f48240 100644 > --- a/doc/guides/nics/hns3.rst > +++ b/doc/guides/nics/hns3.rst > @@ -46,6 +46,25 @@ Prerequisites > - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. > > > +Runtime Config Options > +---------------------- > + > +- ``rx_func_hint`` (default ``none``) > + > + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". ``vec``, ``sve``, ``simple`` and ``common``. ?? > + When equal "vec" and meet the vector Rx usage condition then use the default vector Rx implementation, 'neon' for Kunpeng Arm platform. > + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. > + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function which indicates the Scalar algorithm obtained from rte_eth_rx_burst_mode_get. > + When equal "common" then use the common Rx function which indicates the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. > + A few comments on the documentation, - What about using `` to highlight the parameter, like ``vec``, on all occurrences. - What about adding bullet points for each parameter - I think you can drop "When equal" start from all - You can drop "obtained from rte_eth_rx_burst_mode_get" part, the function name is not needed here, something like gives same information: - Can "and meet the vector Rx usage condition" be simplified, overall what about something like: * ``simple``, if supported use the ``simple`` Rx function which indicates the scalar algorithm. - It is not clear what happens when provided parameter is not supported, like when I set 'vec' but if PMD doesn't support it, which function will be supported? - Can you please try to limit the line length aroung 80 columns. - No need to start words with uppercase for 'Scalar' & 'Scalar Scattered' - Same for below Tx ones. ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-22 13:58 ` Ferruh Yigit @ 2021-03-22 14:03 ` Ferruh Yigit 2021-03-23 3:31 ` fengchengwen 2021-03-23 3:37 ` fengchengwen 2 siblings, 0 replies; 44+ messages in thread From: Ferruh Yigit @ 2021-03-22 14:03 UTC (permalink / raw) To: Min Hu (Connor), dev On 3/22/2021 1:58 PM, Ferruh Yigit wrote: > On 3/19/2021 1:07 AM, Min Hu (Connor) wrote: >> From: Chengwen Feng <fengchengwen@huawei.com> >> >> Currently, the driver support multiple IO burst function and auto >> selection of the most appropriate function based on offload >> configuration. >> >> Most applications such as l2fwd/l3fwd don't provide the means to >> change offload configuration, so it will use the auto selection's io >> burst function. >> >> This patch support runtime config to select io burst function, which >> add two config: rx_func_hint and tx_func_hint, both could assign >> vec/sve/simple/common. >> >> The driver will use the following rules to select io burst func: >> a. if hint equal vec and meet the vec Rx/Tx usage condition then use >> the neon function. >> b. if hint equal sve and meet the sve Rx/Tx usage condition then use >> the sve function. >> c. if hint equal simple and meet the simple Rx/Tx usage condition then >> use the simple function. >> d. if hint equal common then use the common function. >> e. if hint not set then: >> e.1. if meet the vec Rx/Tx usage condition then use the neon function. >> e.2. if meet the simple Rx/Tx usage condition then use the simple >> function. >> e.3. else use the common function. >> >> Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage >> condition and runtime environment (which must support SVE). >> >> In the previous versions, driver will preferred use the sve function >> when meet the sve Rx/Tx usage condition, but in this case driver could >> get better performance if use the neon function. >> > > Is this saying 'neon' is giving better performance even if 'sve' is supported? > >> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> >> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> >> --- >> v6: >> - document hns3.rst about description of vec, common and simple. >> --- >> doc/guides/nics/hns3.rst | 19 +++++++++ >> doc/guides/rel_notes/release_21_05.rst | 1 + >> drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ >> drivers/net/hns3/hns3_ethdev.h | 15 +++++++ >> drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ >> drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- >> 6 files changed, 156 insertions(+), 14 deletions(-) >> >> diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst >> index 84bd7a3..8f48240 100644 >> --- a/doc/guides/nics/hns3.rst >> +++ b/doc/guides/nics/hns3.rst >> @@ -46,6 +46,25 @@ Prerequisites >> - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to >> setup the basic DPDK environment. >> +Runtime Config Options >> +---------------------- >> + >> +- ``rx_func_hint`` (default ``none``) >> + >> + Used to select Rx burst function, supported value are "vec", "sve", >> "simple", "common". > > ``vec``, ``sve``, ``simple`` and ``common``. ?? > >> + When equal "vec" and meet the vector Rx usage condition then use the >> default vector Rx implementation, 'neon' for Kunpeng Arm platform. >> + When equal "sve" and meet the sve Rx usage condition then use the sve Rx >> function. >> + When equal "simple" and meet the simple Rx usage condition then use the >> simple Rx function which indicates the Scalar algorithm obtained from >> rte_eth_rx_burst_mode_get. >> + When equal "common" then use the common Rx function which indicates the >> Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. >> + > > A few comments on the documentation, > > - What about using `` to highlight the parameter, like ``vec``, on all occurrences. > > - What about adding bullet points for each parameter > > - I think you can drop "When equal" start from all > > - You can drop "obtained from rte_eth_rx_burst_mode_get" part, the function name > is not needed here, something like gives same information: > > - Can "and meet the vector Rx usage condition" be simplified, overall what about > something like: > * ``simple``, if supported use the ``simple`` Rx function which indicates the > scalar algorithm. > > - It is not clear what happens when provided parameter is not supported, like > when I set 'vec' but if PMD doesn't support it, which function will be supported? > > - Can you please try to limit the line length aroung 80 columns. > > - No need to start words with uppercase for 'Scalar' & 'Scalar Scattered' > > - Same for below Tx ones. Can you also put a separate line to document the Rx function selection order if the ``rx_func_hint`` is not provided. Same for Tx. ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-22 13:58 ` Ferruh Yigit 2021-03-22 14:03 ` Ferruh Yigit @ 2021-03-23 3:31 ` fengchengwen 2021-03-23 10:31 ` Ferruh Yigit 2021-03-23 3:37 ` fengchengwen 2 siblings, 1 reply; 44+ messages in thread From: fengchengwen @ 2021-03-23 3:31 UTC (permalink / raw) To: dev, humin29 On 2021/3/22 21:58, Ferruh Yigit wrote: > On 3/19/2021 1:07 AM, Min Hu (Connor) wrote: >> From: Chengwen Feng <fengchengwen@huawei.com> >> >> Currently, the driver support multiple IO burst function and auto >> selection of the most appropriate function based on offload >> configuration. >> >> Most applications such as l2fwd/l3fwd don't provide the means to >> change offload configuration, so it will use the auto selection's io >> burst function. >> >> This patch support runtime config to select io burst function, which >> add two config: rx_func_hint and tx_func_hint, both could assign >> vec/sve/simple/common. >> >> The driver will use the following rules to select io burst func: >> a. if hint equal vec and meet the vec Rx/Tx usage condition then use >> the neon function. >> b. if hint equal sve and meet the sve Rx/Tx usage condition then use >> the sve function. >> c. if hint equal simple and meet the simple Rx/Tx usage condition then >> use the simple function. >> d. if hint equal common then use the common function. >> e. if hint not set then: >> e.1. if meet the vec Rx/Tx usage condition then use the neon function. >> e.2. if meet the simple Rx/Tx usage condition then use the simple >> function. >> e.3. else use the common function. >> >> Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage >> condition and runtime environment (which must support SVE). >> >> In the previous versions, driver will preferred use the sve function >> when meet the sve Rx/Tx usage condition, but in this case driver could >> get better performance if use the neon function. >> > > Is this saying 'neon' is giving better performance even if 'sve' is supported? I'm sorry to confuse you, let me explain the hns3 sve function history: 1. The sve instruction only support on our latest processor Kunpeng930, and the sve Rx/Tx function is being gradually optimized. 2. We define a macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE which equal n default in the original scheme, so driver will not select sve Rx/Tx function unless user config CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE=y. 3. We plan to switch CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE equal y when the sve Rx/Tx function is fully optimized. 4. The makefile is switched to meson build in 20.11, and it's not recommended to define the marco such as above, so the upload scheme is adjusted which delete the macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE, this leads to driver select sve Rx/Tx function when meeting sve conditions (which are gcc support compile sve and the host cpu&os support sve), but it doesn't fit out plan, so here we modify it. > >> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> >> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> >> --- >> v6: >> - document hns3.rst about description of vec, common and simple. >> --- >> doc/guides/nics/hns3.rst | 19 +++++++++ >> doc/guides/rel_notes/release_21_05.rst | 1 + >> drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ >> drivers/net/hns3/hns3_ethdev.h | 15 +++++++ >> drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ >> drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- >> 6 files changed, 156 insertions(+), 14 deletions(-) >> >> diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst >> index 84bd7a3..8f48240 100644 >> --- a/doc/guides/nics/hns3.rst >> +++ b/doc/guides/nics/hns3.rst >> @@ -46,6 +46,25 @@ Prerequisites >> - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. >> +Runtime Config Options >> +---------------------- >> + >> +- ``rx_func_hint`` (default ``none``) >> + >> + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". > > ``vec``, ``sve``, ``simple`` and ``common``. ?? > >> + When equal "vec" and meet the vector Rx usage condition then use the default vector Rx implementation, 'neon' for Kunpeng Arm platform. >> + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. >> + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function which indicates the Scalar algorithm obtained from rte_eth_rx_burst_mode_get. >> + When equal "common" then use the common Rx function which indicates the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. >> + > > A few comments on the documentation, > > - What about using `` to highlight the parameter, like ``vec``, on all occurrences. > > - What about adding bullet points for each parameter > > - I think you can drop "When equal" start from all > > - You can drop "obtained from rte_eth_rx_burst_mode_get" part, the function name is not needed here, something like gives same information: > > - Can "and meet the vector Rx usage condition" be simplified, overall what about something like: > * ``simple``, if supported use the ``simple`` Rx function which indicates the scalar algorithm. > > - It is not clear what happens when provided parameter is not supported, like when I set 'vec' but if PMD doesn't support it, which function will be supported? > > - Can you please try to limit the line length aroung 80 columns. > > - No need to start words with uppercase for 'Scalar' & 'Scalar Scattered' > > - Same for below Tx ones. > > . OK, will fix in later patch ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-23 3:31 ` fengchengwen @ 2021-03-23 10:31 ` Ferruh Yigit 2021-03-23 11:22 ` Min Hu (Connor) 0 siblings, 1 reply; 44+ messages in thread From: Ferruh Yigit @ 2021-03-23 10:31 UTC (permalink / raw) To: fengchengwen, dev, humin29 On 3/23/2021 3:31 AM, fengchengwen wrote: > > > On 2021/3/22 21:58, Ferruh Yigit wrote: >> On 3/19/2021 1:07 AM, Min Hu (Connor) wrote: >>> From: Chengwen Feng <fengchengwen@huawei.com> >>> >>> Currently, the driver support multiple IO burst function and auto >>> selection of the most appropriate function based on offload >>> configuration. >>> >>> Most applications such as l2fwd/l3fwd don't provide the means to >>> change offload configuration, so it will use the auto selection's io >>> burst function. >>> >>> This patch support runtime config to select io burst function, which >>> add two config: rx_func_hint and tx_func_hint, both could assign >>> vec/sve/simple/common. >>> >>> The driver will use the following rules to select io burst func: >>> a. if hint equal vec and meet the vec Rx/Tx usage condition then use >>> the neon function. >>> b. if hint equal sve and meet the sve Rx/Tx usage condition then use >>> the sve function. >>> c. if hint equal simple and meet the simple Rx/Tx usage condition then >>> use the simple function. >>> d. if hint equal common then use the common function. >>> e. if hint not set then: >>> e.1. if meet the vec Rx/Tx usage condition then use the neon function. >>> e.2. if meet the simple Rx/Tx usage condition then use the simple >>> function. >>> e.3. else use the common function. >>> >>> Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage >>> condition and runtime environment (which must support SVE). >>> >>> In the previous versions, driver will preferred use the sve function >>> when meet the sve Rx/Tx usage condition, but in this case driver could >>> get better performance if use the neon function. >>> >> >> Is this saying 'neon' is giving better performance even if 'sve' is supported? > > I'm sorry to confuse you, let me explain the hns3 sve function history: > 1. The sve instruction only support on our latest processor Kunpeng930, and > the sve Rx/Tx function is being gradually optimized. > 2. We define a macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE which equal n > default in the original scheme, so driver will not select sve Rx/Tx function > unless user config CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE=y. > 3. We plan to switch CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE equal y when the > sve Rx/Tx function is fully optimized. > 4. The makefile is switched to meson build in 20.11, and it's not recommended > to define the marco such as above, so the upload scheme is adjusted which > delete the macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE, this leads to driver > select sve Rx/Tx function when meeting sve conditions (which are gcc support > compile sve and the host cpu&os support sve), but it doesn't fit out plan, so > here we modify it. > Got it, so you want keep the 'neon' path default until 'sve' path is more optimized, thanks for clarification. >> >>> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> >>> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> >>> --- >>> v6: >>> - document hns3.rst about description of vec, common and simple. >>> --- >>> doc/guides/nics/hns3.rst | 19 +++++++++ >>> doc/guides/rel_notes/release_21_05.rst | 1 + >>> drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ >>> drivers/net/hns3/hns3_ethdev.h | 15 +++++++ >>> drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ >>> drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- >>> 6 files changed, 156 insertions(+), 14 deletions(-) >>> >>> diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst >>> index 84bd7a3..8f48240 100644 >>> --- a/doc/guides/nics/hns3.rst >>> +++ b/doc/guides/nics/hns3.rst >>> @@ -46,6 +46,25 @@ Prerequisites >>> - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. >>> +Runtime Config Options >>> +---------------------- >>> + >>> +- ``rx_func_hint`` (default ``none``) >>> + >>> + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". >> >> ``vec``, ``sve``, ``simple`` and ``common``. ?? >> >>> + When equal "vec" and meet the vector Rx usage condition then use the default vector Rx implementation, 'neon' for Kunpeng Arm platform. >>> + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. >>> + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function which indicates the Scalar algorithm obtained from rte_eth_rx_burst_mode_get. >>> + When equal "common" then use the common Rx function which indicates the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. >>> + >> >> A few comments on the documentation, >> >> - What about using `` to highlight the parameter, like ``vec``, on all occurrences. >> >> - What about adding bullet points for each parameter >> >> - I think you can drop "When equal" start from all >> >> - You can drop "obtained from rte_eth_rx_burst_mode_get" part, the function name is not needed here, something like gives same information: >> >> - Can "and meet the vector Rx usage condition" be simplified, overall what about something like: >> * ``simple``, if supported use the ``simple`` Rx function which indicates the scalar algorithm. >> >> - It is not clear what happens when provided parameter is not supported, like when I set 'vec' but if PMD doesn't support it, which function will be supported? >> >> - Can you please try to limit the line length aroung 80 columns. >> >> - No need to start words with uppercase for 'Scalar' & 'Scalar Scattered' >> >> - Same for below Tx ones. >> >> . > > OK, will fix in later patch > ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-23 10:31 ` Ferruh Yigit @ 2021-03-23 11:22 ` Min Hu (Connor) 0 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:22 UTC (permalink / raw) To: Ferruh Yigit, fengchengwen, dev 在 2021/3/23 18:31, Ferruh Yigit 写道: > On 3/23/2021 3:31 AM, fengchengwen wrote: >> >> >> On 2021/3/22 21:58, Ferruh Yigit wrote: >>> On 3/19/2021 1:07 AM, Min Hu (Connor) wrote: >>>> From: Chengwen Feng <fengchengwen@huawei.com> >>>> >>>> Currently, the driver support multiple IO burst function and auto >>>> selection of the most appropriate function based on offload >>>> configuration. >>>> >>>> Most applications such as l2fwd/l3fwd don't provide the means to >>>> change offload configuration, so it will use the auto selection's io >>>> burst function. >>>> >>>> This patch support runtime config to select io burst function, which >>>> add two config: rx_func_hint and tx_func_hint, both could assign >>>> vec/sve/simple/common. >>>> >>>> The driver will use the following rules to select io burst func: >>>> a. if hint equal vec and meet the vec Rx/Tx usage condition then use >>>> the neon function. >>>> b. if hint equal sve and meet the sve Rx/Tx usage condition then use >>>> the sve function. >>>> c. if hint equal simple and meet the simple Rx/Tx usage condition then >>>> use the simple function. >>>> d. if hint equal common then use the common function. >>>> e. if hint not set then: >>>> e.1. if meet the vec Rx/Tx usage condition then use the neon function. >>>> e.2. if meet the simple Rx/Tx usage condition then use the simple >>>> function. >>>> e.3. else use the common function. >>>> >>>> Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage >>>> condition and runtime environment (which must support SVE). >>>> >>>> In the previous versions, driver will preferred use the sve function >>>> when meet the sve Rx/Tx usage condition, but in this case driver could >>>> get better performance if use the neon function. >>>> >>> >>> Is this saying 'neon' is giving better performance even if 'sve' is >>> supported? >> >> I'm sorry to confuse you, let me explain the hns3 sve function history: >> 1. The sve instruction only support on our latest processor >> Kunpeng930, and >> the sve Rx/Tx function is being gradually optimized. >> 2. We define a macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE which equal n >> default in the original scheme, so driver will not select sve Rx/Tx >> function >> unless user config CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE=y. >> 3. We plan to switch CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE equal y >> when the >> sve Rx/Tx function is fully optimized. >> 4. The makefile is switched to meson build in 20.11, and it's not >> recommended >> to define the marco such as above, so the upload scheme is adjusted which >> delete the macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE, this leads to >> driver >> select sve Rx/Tx function when meeting sve conditions (which are gcc >> support >> compile sve and the host cpu&os support sve), but it doesn't fit out >> plan, so >> here we modify it. >> > > Got it, so you want keep the 'neon' path default until 'sve' path is > more optimized, thanks for clarification. OK, v6 has been sent, which fixed all the bugs, please check it, thanks. > >>> >>>> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> >>>> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> >>>> --- >>>> v6: >>>> - document hns3.rst about description of vec, common and simple. >>>> --- >>>> doc/guides/nics/hns3.rst | 19 +++++++++ >>>> doc/guides/rel_notes/release_21_05.rst | 1 + >>>> drivers/net/hns3/hns3_ethdev.c | 77 >>>> ++++++++++++++++++++++++++++++++++ >>>> drivers/net/hns3/hns3_ethdev.h | 15 +++++++ >>>> drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ >>>> drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- >>>> 6 files changed, 156 insertions(+), 14 deletions(-) >>>> >>>> diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst >>>> index 84bd7a3..8f48240 100644 >>>> --- a/doc/guides/nics/hns3.rst >>>> +++ b/doc/guides/nics/hns3.rst >>>> @@ -46,6 +46,25 @@ Prerequisites >>>> - Follow the DPDK :ref:`Getting Started Guide for Linux >>>> <linux_gsg>` to setup the basic DPDK environment. >>>> +Runtime Config Options >>>> +---------------------- >>>> + >>>> +- ``rx_func_hint`` (default ``none``) >>>> + >>>> + Used to select Rx burst function, supported value are "vec", >>>> "sve", "simple", "common". >>> >>> ``vec``, ``sve``, ``simple`` and ``common``. ?? >>> >>>> + When equal "vec" and meet the vector Rx usage condition then use >>>> the default vector Rx implementation, 'neon' for Kunpeng Arm platform. >>>> + When equal "sve" and meet the sve Rx usage condition then use the >>>> sve Rx function. >>>> + When equal "simple" and meet the simple Rx usage condition then >>>> use the simple Rx function which indicates the Scalar algorithm >>>> obtained from rte_eth_rx_burst_mode_get. >>>> + When equal "common" then use the common Rx function which >>>> indicates the Scalar Scattered algorithm obtained from >>>> rte_eth_rx_burst_mode_get. >>>> + >>> >>> A few comments on the documentation, >>> >>> - What about using `` to highlight the parameter, like ``vec``, on >>> all occurrences. >>> >>> - What about adding bullet points for each parameter >>> >>> - I think you can drop "When equal" start from all >>> >>> - You can drop "obtained from rte_eth_rx_burst_mode_get" part, the >>> function name is not needed here, something like gives same information: >>> >>> - Can "and meet the vector Rx usage condition" be simplified, overall >>> what about something like: >>> * ``simple``, if supported use the ``simple`` Rx function which >>> indicates the scalar algorithm. >>> >>> - It is not clear what happens when provided parameter is not >>> supported, like when I set 'vec' but if PMD doesn't support it, which >>> function will be supported? >>> >>> - Can you please try to limit the line length aroung 80 columns. >>> >>> - No need to start words with uppercase for 'Scalar' & 'Scalar >>> Scattered' >>> >>> - Same for below Tx ones. >>> >>> . >> >> OK, will fix in later patch >> > > . ^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func 2021-03-22 13:58 ` Ferruh Yigit 2021-03-22 14:03 ` Ferruh Yigit 2021-03-23 3:31 ` fengchengwen @ 2021-03-23 3:37 ` fengchengwen 2 siblings, 0 replies; 44+ messages in thread From: fengchengwen @ 2021-03-23 3:37 UTC (permalink / raw) To: ferruh.yigit, dev; +Cc: humin29 sorry to send again: +to Ferruh On 2021/3/22 21:58, Ferruh Yigit wrote: > On 3/19/2021 1:07 AM, Min Hu (Connor) wrote: >> From: Chengwen Feng <fengchengwen@huawei.com> >> >> Currently, the driver support multiple IO burst function and auto >> selection of the most appropriate function based on offload >> configuration. >> >> Most applications such as l2fwd/l3fwd don't provide the means to >> change offload configuration, so it will use the auto selection's io >> burst function. >> >> This patch support runtime config to select io burst function, which >> add two config: rx_func_hint and tx_func_hint, both could assign >> vec/sve/simple/common. >> >> The driver will use the following rules to select io burst func: >> a. if hint equal vec and meet the vec Rx/Tx usage condition then use >> the neon function. >> b. if hint equal sve and meet the sve Rx/Tx usage condition then use >> the sve function. >> c. if hint equal simple and meet the simple Rx/Tx usage condition then >> use the simple function. >> d. if hint equal common then use the common function. >> e. if hint not set then: >> e.1. if meet the vec Rx/Tx usage condition then use the neon function. >> e.2. if meet the simple Rx/Tx usage condition then use the simple >> function. >> e.3. else use the common function. >> >> Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage >> condition and runtime environment (which must support SVE). >> >> In the previous versions, driver will preferred use the sve function >> when meet the sve Rx/Tx usage condition, but in this case driver could >> get better performance if use the neon function. >> > > Is this saying 'neon' is giving better performance even if 'sve' is supported? I'm sorry to confuse you, let me explain the hns3 sve function history: 1. The sve instruction only support on our latest processor Kunpeng930, and the sve Rx/Tx function is being gradually optimized. 2. We define a macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE which equal n default in the original scheme, so driver will not select sve Rx/Tx function unless user config CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE=y. 3. We plan to switch CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE equal y when the sve Rx/Tx function is fully optimized. 4. The makefile is switched to meson build in 20.11, and it's not recommended to define the marco such as above, so the upload scheme is adjusted which delete the macro CONFIG_RTE_LIBRTE_HNS3_INC_VECTOR_SVE, this leads to driver select sve Rx/Tx function when meeting sve conditions (which are gcc support compile sve and the host cpu&os support sve), but it doesn't fit out plan, so here we modify it. > >> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> >> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> >> --- >> v6: >> - document hns3.rst about description of vec, common and simple. >> --- >> doc/guides/nics/hns3.rst | 19 +++++++++ >> doc/guides/rel_notes/release_21_05.rst | 1 + >> drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ >> drivers/net/hns3/hns3_ethdev.h | 15 +++++++ >> drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ >> drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- >> 6 files changed, 156 insertions(+), 14 deletions(-) >> >> diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst >> index 84bd7a3..8f48240 100644 >> --- a/doc/guides/nics/hns3.rst >> +++ b/doc/guides/nics/hns3.rst >> @@ -46,6 +46,25 @@ Prerequisites >> - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. >> +Runtime Config Options >> +---------------------- >> + >> +- ``rx_func_hint`` (default ``none``) >> + >> + Used to select Rx burst function, supported value are "vec", "sve", "simple", "common". > > ``vec``, ``sve``, ``simple`` and ``common``. ?? > >> + When equal "vec" and meet the vector Rx usage condition then use the default vector Rx implementation, 'neon' for Kunpeng Arm platform. >> + When equal "sve" and meet the sve Rx usage condition then use the sve Rx function. >> + When equal "simple" and meet the simple Rx usage condition then use the simple Rx function which indicates the Scalar algorithm obtained from rte_eth_rx_burst_mode_get. >> + When equal "common" then use the common Rx function which indicates the Scalar Scattered algorithm obtained from rte_eth_rx_burst_mode_get. >> + > > A few comments on the documentation, > > - What about using `` to highlight the parameter, like ``vec``, on all occurrences. > > - What about adding bullet points for each parameter > > - I think you can drop "When equal" start from all > > - You can drop "obtained from rte_eth_rx_burst_mode_get" part, the function name is not needed here, something like gives same information: > > - Can "and meet the vector Rx usage condition" be simplified, overall what about something like: > * ``simple``, if supported use the ``simple`` Rx function which indicates the scalar algorithm. > > - It is not clear what happens when provided parameter is not supported, like when I set 'vec' but if PMD doesn't support it, which function will be supported? > > - Can you please try to limit the line length aroung 80 columns. > > - No need to start words with uppercase for 'Scalar' & 'Scalar Scattered' > > - Same for below Tx ones. > > . OK, will fix in later patch ^ permalink raw reply [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 2/8] net/hns3: support for outer UDP cksum 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) ` (5 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Chengchang Tang <tangchengchang@huawei.com> Kunpeng930 support outer UDP cksum, this patch add support for it. Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 1d85942..c3324d8 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 8b9f075..03f8048 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw, if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B)) + hns3_set_bit(hw->capability, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1); } static uint32_t diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 28aa27a..3949153 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index ec4b475..0fc0a1c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -798,6 +798,7 @@ enum { #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 #define HNS3_DEV_SUPPORT_STASH_B 0x7 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -831,6 +832,9 @@ enum { #define hns3_dev_rxd_adv_layout_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index f3eaefb..e1e41b8 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index f5c7d71..7529279 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2967,7 +2967,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ? rxm->outer_l2_len + rxm->outer_l3_len : 0; paylen = rxm->pkt_len - hdr_len; - desc->tx.paylen = rte_cpu_to_le_32(paylen); + desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); hns3_set_tso(desc, paylen, rxm); /* @@ -3204,8 +3204,10 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, { struct hns3_desc *tx_ring = txq->tx_ring; struct hns3_desc *desc = &tx_ring[tx_desc_id]; + uint64_t ol_flags = m->ol_flags; uint32_t tmp_outer = 0; uint32_t tmp_inner = 0; + uint32_t tmp_ol4cs; int ret; /* @@ -3215,7 +3217,7 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * calculations, the length of the L2 header include the outer and * inner, will be filled during the parsing of tunnel packects. */ - if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) { + if (!(ol_flags & PKT_TX_TUNNEL_MASK)) { /* * For non tunnel type the tunnel type id is 0, so no need to * assign a value to it. Only the inner(normal) L2 header length @@ -3230,7 +3232,8 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * inner l2_len. It would lead a cksum error. So driver has to * calculate the header length. */ - if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) && + if (unlikely(!(ol_flags & + (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) && m->outer_l2_len == 0)) { struct rte_net_hdr_lens hdr_len; (void)rte_net_get_ptype(m, &hdr_len, @@ -3247,6 +3250,9 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); + tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ? + BIT(HNS3_TXD_OL4CS_B) : 0; + desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); return 0; } @@ -3376,31 +3382,78 @@ hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, return false; } +static bool +hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv4_hdr *ipv4_hdr; + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags); + + return true; + } + *l4_proto = ipv4_hdr->next_proto_id; + return false; +} + +static bool +hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv6_hdr *ipv6_hdr; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + + return true; + } + *l4_proto = ipv6_hdr->proto; + return false; +} + static void hns3_outer_header_cksum_prepare(struct rte_mbuf *m) { uint64_t ol_flags = m->ol_flags; uint32_t paylen, hdr_len, l4_proto; + struct rte_udp_hdr *udp_hdr; if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6))) return; if (ol_flags & PKT_TX_OUTER_IPV4) { - struct rte_ipv4_hdr *ipv4_hdr; - ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->outer_l2_len); - l4_proto = ipv4_hdr->next_proto_id; - if (ol_flags & PKT_TX_OUTER_IP_CKSUM) - ipv4_hdr->hdr_checksum = 0; + if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto)) + return; } else { - struct rte_ipv6_hdr *ipv6_hdr; - ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, - m->outer_l2_len); - l4_proto = ipv6_hdr->proto; + if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto)) + return; } + /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */ if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) { - struct rte_udp_hdr *udp_hdr; hdr_len = m->l2_len + m->l3_len + m->l4_len; hdr_len += m->outer_l2_len + m->outer_l3_len; paylen = m->pkt_len - hdr_len; @@ -3686,7 +3739,7 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); @@ -3702,7 +3755,7 @@ hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 9adeb24..cd04200 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -149,6 +149,7 @@ #define HNS3_TXD_MSS_S 0 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22 #define HNS3_L2_LEN_UNIT 1UL #define HNS3_L3_LEN_UNIT 2UL #define HNS3_L4_LEN_UNIT 2UL @@ -234,7 +235,7 @@ struct hns3_desc { }; }; - uint32_t paylen; + uint32_t paylen_fd_dop_ol4cs; uint16_t tp_fe_sc_vld_ra_ri; uint16_t mss; } tx; @@ -503,6 +504,7 @@ struct hns3_queue_info { }; #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \ diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 2a22a1a..90e45c6 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0)); /* save offset 24~31byte of every BD */ - svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen, - offsets, svdup_n_u64(valid_bit)); + svst1_scatter_u64offset_u64(pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets, svdup_n_u64(valid_bit)); /* Increment bytes counter */ uint32_t idx; -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 3/8] net/hns3: adjust the format of RAS related structures 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) ` (4 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Adjust the format of hns3 RAS related structures to resolve the static check warnings. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- v3: - change code styles. --- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 2563504..265dae8 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { }; static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "egu_cge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "egu_cge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "egu_lge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "egu_lge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "cge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "lge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "lge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "cge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "lge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "egu_cge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "egu_lge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "egu_ge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "egu_cge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "egu_cge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "egu_lge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "egu_lge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "cge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "lge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "lge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "cge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "lge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "egu_cge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "egu_lge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "egu_ge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk = 0xFFFFFFFF, - .msg = "rpu_rx_pkt_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = 0xFFFFFFFF, + .msg = "rpu_rx_pkt_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk = BIT(13), - .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rcb_tx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rcb_rx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rcb_tx_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rcb_rx_ebd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rcb_tso_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rcb_tx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rcb_rx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tpu_tx_pkt_0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tpu_tx_pkt_1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "rd_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "wr_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "ooo_ecc_err_detect", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(31), - .msg = "ooo_ecc_err_multpl", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(13), + .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rcb_tx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rcb_rx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rcb_tx_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rcb_rx_ebd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rcb_tso_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rcb_tx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rcb_rx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tpu_tx_pkt_0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tpu_tx_pkt_1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "rd_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "wr_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "ooo_ecc_err_detect", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(31), + .msg = "ooo_ecc_err_multpl", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk = BIT(29), - .msg = "rx_q_search_miss", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(29), + .msg = "rx_q_search_miss", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "low_water_line_err_port", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "low_water_line_err_port", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk = BIT(0), - .msg = "tx_vlan_tag_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "rss_list_tc_unassigned_queue_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "tx_vlan_tag_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "rss_list_tc_unassigned_queue_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk = BIT(3), - .msg = "tx_rd_fbd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(4), - .msg = "rx_rd_ebd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(3), + .msg = "tx_rd_fbd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(4), + .msg = "rx_rd_ebd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk = BIT(0), - .msg = "over_8bd_no_fe", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tso_mss_cmp_min_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "tso_mss_cmp_max_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "buf_wait_timeout", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "over_8bd_no_fe", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tso_mss_cmp_min_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "tso_mss_cmp_max_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "buf_wait_timeout", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "imp_itcm0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "imp_itcm1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "imp_itcm2_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "imp_itcm3_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "imp_dtcm0_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "imp_dtcm0_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "imp_dtcm1_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "imp_dtcm1_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(17), - .msg = "imp_itcm4_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "imp_itcm0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "imp_itcm1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "imp_itcm2_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "imp_itcm3_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "imp_dtcm0_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "imp_dtcm0_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "imp_dtcm1_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "imp_dtcm1_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(17), + .msg = "imp_itcm4_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "cmdq_nic_rx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "cmdq_nic_tx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cmdq_nic_rx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "cmdq_nic_tx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "cmdq_nic_rx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "cmdq_nic_tx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "cmdq_nic_rx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "cmdq_nic_tx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "cmdq_nic_rx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "cmdq_nic_tx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cmdq_nic_rx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "cmdq_nic_tx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "cmdq_nic_rx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "cmdq_nic_tx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "cmdq_nic_rx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "cmdq_nic_tx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk = BIT(6), - .msg = "tqp_int_cfg_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "tqp_int_cfg_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(8), - .msg = "tqp_int_ctrl_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "tqp_int_ctrl_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(10), - .msg = "tx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "rx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(6), + .msg = "tqp_int_cfg_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "tqp_int_cfg_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(8), + .msg = "tqp_int_ctrl_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "tqp_int_ctrl_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(10), + .msg = "tx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "rx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk = BIT(0), - .msg = "imp_rd_poison_int", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "imp_rd_poison_int", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; #define HNS3_SSU_MEM_ECC_ERR(x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +} static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { HNS3_SSU_MEM_ECC_ERR(0), @@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { }; static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk = BIT(0), - .msg = "ssu_mem32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ssu_mem32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk = BIT(0), - .msg = "buf_sum_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "ppp_mb_num_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "ppp_mbid_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ppp_rlt_mac_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ppp_rlt_host_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "cks_edit_position_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "cks_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "vlan_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "vlan_num_ot_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "vlan_num_in_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "buf_sum_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "ppp_mb_num_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "ppp_mbid_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ppp_rlt_mac_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ppp_rlt_host_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "cks_edit_position_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "cks_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "vlan_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "vlan_num_ot_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "vlan_num_in_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_int[] = { - { .int_msk = BIT(0), - .msg = "igu_rx_buf0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_rx_buf1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "igu_rx_buf0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_rx_buf1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "msix_nic_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "msix_nic_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk = BIT(0), - .msg = "vf_vlan_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "umv_mcast_group_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "umv_key_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "umv_key_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "umv_key_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "umv_key_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "umv_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "rss_tc_mode_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rss_idt_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "rss_idt_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "rss_idt_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "rss_idt_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "rss_idt_mem4_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "rss_idt_mem5_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rss_idt_mem6_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rss_idt_mem7_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rss_idt_mem8_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rss_idt_mem9_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rss_idt_mem10_ecc_m1bit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rss_idt_mem11_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rss_idt_mem12_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rss_idt_mem13_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rss_idt_mem14_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rss_idt_mem15_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "port_vlan_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "mcast_linear_table_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "mcast_result_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "flow_director_ad_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "flow_director_ad_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "rx_vlan_tag_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "vf_vlan_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "umv_mcast_group_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "umv_key_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "umv_key_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "umv_key_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "umv_key_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "umv_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "rss_tc_mode_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rss_idt_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "rss_idt_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "rss_idt_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "rss_idt_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "rss_idt_mem4_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "rss_idt_mem5_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rss_idt_mem6_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rss_idt_mem7_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rss_idt_mem8_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rss_idt_mem9_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rss_idt_mem10_ecc_m1bit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rss_idt_mem11_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rss_idt_mem12_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rss_idt_mem13_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rss_idt_mem14_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rss_idt_mem15_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "port_vlan_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "mcast_linear_table_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "mcast_result_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "flow_director_ad_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "flow_director_ad_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "rx_vlan_tag_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(0), - .msg = "hfs_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rslt_descr_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tx_vlan_tag_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "FD_CN0_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "FD_CN1_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "GRO_AD_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "hfs_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rslt_descr_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tx_vlan_tag_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "FD_CN0_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "FD_CN1_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "GRO_AD_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(4), - .msg = "gro_bd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "gro_context_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_stash_cfg_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "axi_rd_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(4), + .msg = "gro_bd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "gro_context_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_stash_cfg_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "axi_rd_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk = BIT(1), - .msg = "tm_sch_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tm_sch_port_shap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tm_sch_port_shap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "tm_sch_port_shap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "tm_sch_port_shap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "tm_sch_rq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "tm_sch_rq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tm_sch_nq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tm_sch_nq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "tm_sch_roce_up_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "tm_sch_roce_up_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "tm_sch_rcb_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "tm_sch_rcb_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "tm_sch_ssu_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(31), - .msg = "tm_sch_ssu_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "tm_sch_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tm_sch_port_shap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tm_sch_port_shap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "tm_sch_port_shap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "tm_sch_port_shap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "tm_sch_rq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "tm_sch_rq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tm_sch_nq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tm_sch_nq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "tm_sch_roce_up_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "tm_sch_roce_up_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "tm_sch_rcb_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "tm_sch_rcb_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "tm_sch_ssu_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(31), + .msg = "tm_sch_ssu_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk = BIT(0), - .msg = "qcn_shap_gp0_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "qcn_shap_gp0_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "qcn_shap_gp1_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_shap_gp1_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "qcn_shap_gp2_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_shap_gp2_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "qcn_shap_gp3_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_shap_gp3_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "qcn_shap_gp0_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_shap_gp0_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "qcn_shap_gp1_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_shap_gp1_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "qcn_shap_gp2_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_gp2_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "qcn_shap_gp3_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_shap_gp3_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "qcn_byte_info_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_byte_info_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "qcn_shap_gp0_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "qcn_shap_gp0_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "qcn_shap_gp1_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_shap_gp1_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "qcn_shap_gp2_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_shap_gp2_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "qcn_shap_gp3_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_shap_gp3_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "qcn_shap_gp0_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_shap_gp0_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "qcn_shap_gp1_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_shap_gp1_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "qcn_shap_gp2_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_gp2_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "qcn_shap_gp3_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_shap_gp3_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "qcn_byte_info_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_byte_info_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "qcn_byte_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_time_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_fb_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_link_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_rate_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_tmplt_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_cfg_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "qcn_gp3_barral_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "qcn_byte_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_time_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_fb_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_link_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_rate_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_tmplt_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_cfg_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "qcn_gp3_barral_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "ncsi_tx_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "ncsi_tx_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk = BIT(0), - .msg = "ig_mac_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ig_host_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ig_roc_buf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ig_host_data_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ig_host_key_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qm_eof_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "mb_rlt_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "dup_uncopy_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "dup_cnt_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "dup_cnt_drop_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "dup_cnt_wrb_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "host_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "mac_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "host_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "mac_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "dup_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "out_queue_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "bank2_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "bank1_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "bank0_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ig_mac_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ig_host_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ig_roc_buf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ig_host_data_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ig_host_key_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qm_eof_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "mb_rlt_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "dup_uncopy_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "dup_cnt_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "dup_cnt_drop_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "dup_cnt_wrb_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "host_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "mac_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "host_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "mac_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "dup_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "out_queue_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "bank2_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "bank1_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "bank0_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk = BIT(0), - .msg = "ets_rd_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ets_wr_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ets_rd_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ets_wr_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ets_rd_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ets_wr_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ets_rd_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ets_wr_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "rx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rx_stp_fifo_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "rx_stp_fifo_underflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tx_buf_underrun", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "rx_stp_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "rx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rx_stp_fifo_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "rx_stp_fifo_underflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tx_buf_underrun", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "rx_stp_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tpu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "roc_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tpu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "igu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "roc_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tpu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "igu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "ets_rd_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "ets_wr_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ets_rd_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "ets_wr_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tpu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "roc_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tpu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "igu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "roc_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tpu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "igu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "ets_rd_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "ets_wr_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ets_rd_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "ets_wr_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "IMP_TCM_ECC_INT_STS", - .hw_err = imp_tcm_ecc_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "CMDQ_MEM_ECC_INT_STS", - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "IMP_RD_POISON_INT_STS", - .hw_err = imp_rd_poison_int }, - { .desc_offset = 0, - .data_offset = 3, - .msg = "TQP_INT_ECC_INT_STS", - .hw_err = tqp_int_ecc_int }, - { .desc_offset = 0, - .data_offset = 4, - .msg = "MSIX_ECC_INT_STS", - .hw_err = msix_ecc_int }, - { .desc_offset = 2, - .data_offset = 2, - .msg = "SSU_ECC_MULTI_BIT_INT_0", - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset = 2, - .data_offset = 3, - .msg = "SSU_ECC_MULTI_BIT_INT_1", - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset = 2, - .data_offset = 4, - .msg = "SSU_COMMON_ERR_INT", - .hw_err = ssu_common_ecc_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "IGU_INT_STS", - .hw_err = igu_int }, - { .desc_offset = 4, - .data_offset = 1, - .msg = "PPP_MPF_ABNORMAL_INT_ST1", - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset = 4, - .data_offset = 3, - .msg = "PPP_MPF_ABNORMAL_INT_ST3", - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset = 5, - .data_offset = 1, - .msg = "PPU_MPF_ABNORMAL_INT_ST1", - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset = 5, - .data_offset = 3, - .msg = "PPU_MPF_ABNORMAL_INT_ST3", - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset = 6, - .data_offset = 0, - .msg = "TM_SCH_RINT", - .hw_err = tm_sch_int }, - { .desc_offset = 7, - .data_offset = 0, - .msg = "QCN_FIFO_RINT", - .hw_err = qcn_fifo_int }, - { .desc_offset = 7, - .data_offset = 1, - .msg = "QCN_ECC_RINT", - .hw_err = qcn_ecc_int }, - { .desc_offset = 9, - .data_offset = 0, - .msg = "NCSI_ECC_INT_RPT", - .hw_err = ncsi_ecc_int }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "IMP_TCM_ECC_INT_STS", + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "CMDQ_MEM_ECC_INT_STS", + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "IMP_RD_POISON_INT_STS", + .hw_err = imp_rd_poison_int + }, { + .desc_offset = 0, + .data_offset = 3, + .msg = "TQP_INT_ECC_INT_STS", + .hw_err = tqp_int_ecc_int + }, { + .desc_offset = 0, + .data_offset = 4, + .msg = "MSIX_ECC_INT_STS", + .hw_err = msix_ecc_int + }, { + .desc_offset = 2, + .data_offset = 2, + .msg = "SSU_ECC_MULTI_BIT_INT_0", + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset = 2, + .data_offset = 3, + .msg = "SSU_ECC_MULTI_BIT_INT_1", + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset = 2, + .data_offset = 4, + .msg = "SSU_COMMON_ERR_INT", + .hw_err = ssu_common_ecc_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "IGU_INT_STS", + .hw_err = igu_int + }, { + .desc_offset = 4, + .data_offset = 1, + .msg = "PPP_MPF_ABNORMAL_INT_ST1", + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset = 4, + .data_offset = 3, + .msg = "PPP_MPF_ABNORMAL_INT_ST3", + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset = 5, + .data_offset = 1, + .msg = "PPU_MPF_ABNORMAL_INT_ST1", + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset = 5, + .data_offset = 3, + .msg = "PPU_MPF_ABNORMAL_INT_ST3", + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset = 6, + .data_offset = 0, + .msg = "TM_SCH_RINT", + .hw_err = tm_sch_int + }, { + .desc_offset = 7, + .data_offset = 0, + .msg = "QCN_FIFO_RINT", + .hw_err = qcn_fifo_int + }, { + .desc_offset = 7, + .data_offset = 1, + .msg = "QCN_ECC_RINT", + .hw_err = qcn_ecc_int + }, { + .desc_offset = 9, + .data_offset = 0, + .msg = "NCSI_ECC_INT_RPT", + .hw_err = ncsi_ecc_int + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_RAS", - .hw_err = ssu_port_based_err_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "SSU_FIFO_OVERFLOW_INT", - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "SSU_ETS_TCG_INT", - .hw_err = ssu_ets_tcg_int }, - { .desc_offset = 1, - .data_offset = 0, - .msg = "IGU_EGU_TNL_INT_STS", - .hw_err = igu_egu_tnl_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_RAS", + .hw_err = ssu_port_based_err_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "SSU_FIFO_OVERFLOW_INT", + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "SSU_ETS_TCG_INT", + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset = 1, + .data_offset = 0, + .msg = "IGU_EGU_TNL_INT_STS", + .hw_err = igu_egu_tnl_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset = 1, - .data_offset = 0, - .msg = "MAC_AFIFO_TNL_INT_R", - .hw_err = mac_afifo_tnl_int }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 1, + .data_offset = 0, + .msg = "MAC_AFIFO_TNL_INT_R", + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_MSIX", - .hw_err = ssu_port_based_pf_int }, - { .desc_offset = 2, - .data_offset = 0, - .msg = "PPP_PF_ABNORMAL_INT_ST0", - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_MSIX", + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset = 2, + .data_offset = 0, + .msg = "PPP_PF_ABNORMAL_INT_ST0", + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; enum hns3_hw_err_type { -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 4/8] net/hns3: delete redundant xstats RAS statistics 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (2 preceding siblings ...) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) ` (3 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3949153..139e893 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5768,14 +5768,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { hns3_warn(hw, "Detected IMP RD poison!"); - hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { hns3_warn(hw, "Detected IMP CMDQ error!"); - hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 0fc0a1c..314916c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -561,38 +561,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_int_cnt; - uint64_t ppu_mpf_abn_int_st2_msix_cnt; - uint64_t ssu_port_based_pf_int_cnt; - uint64_t ppp_pf_abnormal_int_cnt; - uint64_t ppu_pf_abnormal_int_msix_cnt; - - uint64_t imp_tcm_ecc_int_cnt; - uint64_t cmdq_mem_ecc_int_cnt; - uint64_t imp_rd_poison_int_cnt; - uint64_t tqp_int_ecc_int_cnt; - uint64_t msix_ecc_int_cnt; - uint64_t ssu_ecc_multi_bit_int_0_cnt; - uint64_t ssu_ecc_multi_bit_int_1_cnt; - uint64_t ssu_common_ecc_int_cnt; - uint64_t igu_int_cnt; - uint64_t ppp_mpf_abnormal_int_st1_cnt; - uint64_t ppp_mpf_abnormal_int_st3_cnt; - uint64_t ppu_mpf_abnormal_int_st1_cnt; - uint64_t ppu_mpf_abn_int_st2_ras_cnt; - uint64_t ppu_mpf_abnormal_int_st3_cnt; - uint64_t tm_sch_int_cnt; - uint64_t qcn_fifo_int_cnt; - uint64_t qcn_ecc_int_cnt; - uint64_t ncsi_ecc_int_cnt; - uint64_t ssu_port_based_err_int_cnt; - uint64_t ssu_fifo_overflow_int_cnt; - uint64_t ssu_ets_tcg_int_cnt; - uint64_t igu_egu_tnl_int_cnt; - uint64_t ppu_pf_abnormal_int_ras_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -738,9 +706,6 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 265dae8..c259f2e 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } - hns3_error_int_stats_add(hns, reg); } err++; } diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 941c75f..7cda36c 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -201,65 +201,6 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = { HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)} }; -static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = { - {"MAC_AFIFO_TNL_INT_R", - HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)}, - {"SSU_PORT_BASED_ERR_INT_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)}, - {"PPP_PF_ABNORMAL_INT_ST0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)}, - {"IMP_TCM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)}, - {"CMDQ_MEM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)}, - {"IMP_RD_POISON_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)}, - {"TQP_INT_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)}, - {"MSIX_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)}, - {"SSU_COMMON_ERR_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)}, - {"IGU_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)}, - {"TM_SCH_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)}, - {"QCN_FIFO_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)}, - {"QCN_ECC_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)}, - {"NCSI_ECC_INT_RPT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)}, - {"SSU_PORT_BASED_ERR_INT_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)}, - {"SSU_FIFO_OVERFLOW_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)}, - {"SSU_ETS_TCG_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)}, - {"IGU_EGU_TNL_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)}, -}; - /* The statistic of reset */ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = { {"REQ_RESET_CNT", @@ -333,9 +274,6 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) -#define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \ - sizeof(hns3_error_int_stats_strings[0])) - #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \ sizeof(hns3_reset_stats_strings[0])) @@ -363,7 +301,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -750,23 +688,6 @@ hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } -void -hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) -{ - struct hns3_pf *pf = &hns->pf; - uint16_t i; - char *addr; - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - *(uint64_t *)addr += 1; - break; - } - } -} - static void hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) @@ -932,7 +853,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; struct hns3_hw *hw = &hns->hw; struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; @@ -986,13 +906,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } } /* Get the reset stat */ @@ -1134,13 +1047,6 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_imissed_stats_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_error_int_stats_strings[i].name); - count++; - } } for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, @@ -1358,7 +1264,6 @@ int hns3_dev_xstats_reset(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; int ret; /* Clear tqp stats */ @@ -1379,9 +1284,6 @@ hns3_dev_xstats_reset(struct rte_eth_dev *dev) if (ret) return ret; - /* Clear error stats */ - memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats)); - return 0; } diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 70a9c5b..8ea69b4 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint32_t size); int hns3_stats_reset(struct rte_eth_dev *dev); -void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err); int hns3_tqp_stats_init(struct hns3_hw *hw); void hns3_tqp_stats_uninit(struct hns3_hw *hw); int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear); -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 5/8] net/hns3: support imissed stats for PF/VF 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (3 preceding siblings ...) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) ` (2 subsequent siblings) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- v4: - rename variable name oq_glb_drop_cnt to oq_drop_cnt. --- drivers/net/hns3/hns3_cmd.h | 13 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 234 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 094bf7e..e704d0c 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -111,6 +111,8 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, @@ -957,6 +959,17 @@ struct hns3_query_rpu_cmd { uint32_t rsv2[2]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t oq_drop_cnt; + uint32_t rev1[2]; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 139e893..82538d4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = false; @@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = true; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 314916c..6e74ec8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -426,6 +426,9 @@ struct hns3_queue_intr { #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -544,6 +547,24 @@ struct hns3_hw { * port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + + /* + * drop_stats_mode mode. + * value range: + * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 + * + * - HNS3_PKTS_DROP_STATS_MODE1 + * This mode for kunpeng920. In this mode, port level imissed stats + * is supported. It only includes RPU drop stats. + * + * - HNS3_PKTS_DROP_STATS_MODE2 + * This mode for kunpeng930. In this mode, imissed stats and oerrors + * stats is supported. Function level imissed stats is supported. It + * includes RPU drop stats in VF, and includes both RPU drop stats + * and SSU drop stats in PF. Oerror stats is also supported in PF. + */ + uint8_t drop_stats_mode; + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index e1e41b8..7ee468f 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; @@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; @@ -1875,6 +1877,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) if (ret) goto err_get_config; + /* Hardware statistics of imissed registers cleared. */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + goto err_set_tc_queue; + } + ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); if (ret) { PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h index 0540554..e141fe1 100644 --- a/drivers/net/hns3/hns3_regs.h +++ b/drivers/net/hns3/hns3_regs.h @@ -36,6 +36,8 @@ #define HNS3_GLOBAL_RESET_REG 0x20A00 #define HNS3_FUN_RST_ING 0x20C00 #define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008 /* Vector0 register bits for reset */ diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 7cda36c..e802c0b 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -269,6 +269,8 @@ static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = { static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { {"RPU_DROP_CNT", HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)}, + {"SSU_DROP_CNT", + HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)}, }; #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ @@ -301,8 +303,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ - HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -419,7 +420,7 @@ hns3_query_update_mac_stats(struct rte_eth_dev *dev) } static int -hns3_update_rpu_drop_stats(struct hns3_hw *hw) +hns3_update_port_rpu_drop_stats(struct hns3_hw *hw) { struct hns3_rx_missed_stats *stats = &hw->imissed_stats; struct hns3_query_rpu_cmd *req; @@ -449,11 +450,90 @@ hns3_update_rpu_drop_stats(struct hns3_hw *hw) return 0; } +static void +hns3_update_function_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + + stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG); +} + +static int +hns3_update_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret = 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf) + ret = hns3_update_port_rpu_drop_stats(hw); + else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2) + hns3_update_function_rpu_drop_stats(hw); + + return ret; +} + +static int +hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + int bd_num, bool is_rx) +{ + struct hns3_query_ssu_cmd *req; + int ret; + int i; + + for (i = 0; i < bd_num - 1; i++) { + hns3_cmd_setup_basic_desc(&desc[i], + HNS3_OPC_SSU_DROP_REG, true); + desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + } + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true); + req = (struct hns3_query_ssu_cmd *)desc[0].data; + req->rxtx = is_rx ? 0 : 1; + ret = hns3_cmd_send(hw, desc, bd_num); + + return ret; +} + +static int +hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + true); + if (ret) { + hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + stats->ssu_rx_drop_cnt += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); int ret; + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) { + ret = hns3_update_port_rx_ssu_drop_stats(hw); + if (ret) + return ret; + } + ret = hns3_update_rpu_drop_stats(hw); if (ret) return ret; @@ -488,19 +568,17 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) uint16_t i; int ret; - if (!hns->is_vf) { - /* Update imissed stats */ - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt; + /* Update imissed stats */ + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt + + imissed_stats->ssu_rx_drop_cnt; - /* Reads all the stats of a rxq in a loop to keep them synchronized */ + /* Get the error stats and bytes of received packets */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) @@ -556,17 +634,14 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) uint16_t i; int ret; - if (!hns->is_vf) { - /* - * Note: Reading hardware statistics of imissed registers will - * clear them. - */ - ret = hns3_update_imissed_stats(hw, true); - if (ret) { - hns3_err(hw, "clear imissed stats failed, ret = %d", - ret); - return ret; - } + /* + * Note: Reading hardware statistics of imissed registers will + * clear them. + */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + return ret; } for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { @@ -630,6 +705,22 @@ hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev) return 0; } +static int +hns3_get_imissed_stats_num(struct hns3_adapter *hns) +{ +#define NO_IMISSED_STATS_NUM 0 +#define RPU_STATS_ITEM_NUM 1 + struct hns3_hw *hw = &hns->hw; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return NO_IMISSED_STATS_NUM; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) + return HNS3_NUM_IMISSED_XSTATS; + + return RPU_STATS_ITEM_NUM; +} + /* This function calculates the number of xstats based on the current config */ static int hns3_xstats_calc_num(struct rte_eth_dev *dev) @@ -647,13 +738,17 @@ hns3_xstats_calc_num(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM; int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM; + int stats_num; + + stats_num = rx_comm_stats_num + tx_comm_stats_num; + stats_num += hns3_get_imissed_stats_num(hns); if (hns->is_vf) - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_NUM_RESET_XSTATS; + stats_num += HNS3_NUM_RESET_XSTATS; else - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_FIX_NUM_STATS; + stats_num += HNS3_FIX_NUM_STATS; + + return stats_num; } static void @@ -835,6 +930,31 @@ hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, hns3_txq_basic_stats_get(dev, xstats, count); } +static void +hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; + int imissed_stats_num; + int cnt = *count; + char *addr; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + addr = (char *)imissed_stats + + hns3_imissed_stats_strings[i].offset; + xstats[cnt].value = *(uint64_t *)addr; + xstats[cnt].id = cnt; + cnt++; + } + + *count = cnt; +} + /* * Retrieve extended(tqp | Mac) statistics of an Ethernet device. * @param dev @@ -854,7 +974,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, { struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_bd_errors_stats *rx_err_stats; @@ -890,24 +1009,17 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, xstats[count].id = count; count++; } + } - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - addr = (char *)imissed_stats + - hns3_imissed_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } - + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + hns3_imissed_stats_get(dev, xstats, &count); + /* Get the reset stat */ for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset; @@ -992,6 +1104,28 @@ hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev, } } +static void +hns3_imissed_stats_name_get(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + uint32_t *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t cnt = *count; + int imissed_stats_num; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + snprintf(xstats_names[cnt].name, + sizeof(xstats_names[cnt].name), + "%s", hns3_imissed_stats_strings[i].name); + cnt++; + } + + *count = cnt; +} + /* * Retrieve names of extended statistics of an Ethernet device. * @@ -1040,14 +1174,10 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_mac_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_imissed_stats_strings[i].name); - count++; - } } + + hns3_imissed_stats_name_get(dev, xstats_names, &count); + for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 8ea69b4..273be42 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -112,6 +112,7 @@ struct hns3_mac_stats { struct hns3_rx_missed_stats { uint64_t rpu_rx_drop_cnt; + uint64_t ssu_rx_drop_cnt; }; /* store statistics names and its offset in stats structure */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 6/8] net/hns3: support oerrors stats in PF 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (4 preceding siblings ...) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 8/8] net/hns3: support query Rx " Min Hu (Connor) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit This patch added oerrors stats for PF in kunpeng930. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- v4: - rename variable name oq_glb_drop_cnt to oq_drop_cnt. --- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 64 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 6e74ec8..f69e2d8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -443,6 +443,7 @@ struct hns3_hw { /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index e802c0b..1af689f 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -519,6 +519,31 @@ hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) return 0; } +static int +hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + false); + if (ret) { + hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + hw->oerror_stats += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { @@ -544,6 +569,25 @@ hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) return 0; } +static int +hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf) + return 0; + + ret = hns3_update_port_tx_ssu_drop_stats(hw); + if (ret) + return ret; + + if (is_clear) + hw->oerror_stats = 0; + + return 0; +} + /* * Query tqp tx queue statistics ,opcode id: 0x0B03. * Query tqp rx queue statistics ,opcode id: 0x0B13. @@ -608,7 +652,14 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) rte_stats->obytes += txq->basic_stats.bytes; } - rte_stats->oerrors = 0; + ret = hns3_update_oerror_stats(hw, false); + if (ret) { + hns3_err(hw, "update oerror stats failed, ret = %d", + ret); + return ret; + } + rte_stats->oerrors = hw->oerror_stats; + /* * If HW statistics are reset by stats_reset, but a lot of residual * packets exist in the hardware queue and these packets are error @@ -644,6 +695,17 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) return ret; } + /* + * Note: Reading hardware statistics of oerror registers will + * clear them. + */ + ret = hns3_update_oerror_stats(hw, true); + if (ret) { + hns3_err(hw, "clear oerror stats failed, ret = %d", + ret); + return ret; + } + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 7/8] net/hns3: support query Tx descriptor status 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (5 preceding siblings ...) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 8/8] net/hns3: support query Rx " Min Hu (Connor) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 3aeea8e..2c0cb89 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index c796cd5..e60b09b 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index c3324d8..e8b0c6e 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 82538d4..8c65be4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; return ret; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 7ee468f..4412da3 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 7529279..a84da15 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4044,6 +4044,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; } else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; @@ -4256,6 +4257,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) return -ENOTSUP; } +int +hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + volatile struct hns3_desc *txdp; + struct hns3_tx_queue *txq; + struct rte_eth_dev *dev; + uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; + if (offset >= txq->nb_tx_desc) + return -EINVAL; + + dev = &rte_eth_devices[txq->port_id]; + if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) + return RTE_ETH_TX_DESC_UNAVAIL; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; + if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) + return RTE_ETH_TX_DESC_FULL; + else + return RTE_ETH_TX_DESC_DONE; +} + uint32_t hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index cd04200..82d5aa0 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,5 +720,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v5 8/8] net/hns3: support query Rx descriptor status 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (6 preceding siblings ...) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) @ 2021-03-19 1:07 ` Min Hu (Connor) 7 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-19 1:07 UTC (permalink / raw) To: dev; +Cc: ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 2c0cb89..3988be4 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index e60b09b..1640669 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index e8b0c6e..6e1fc81 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 8c65be4..b7bfac8 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6772,6 +6772,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 4412da3..34a6927 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2915,6 +2915,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index a84da15..feeb702 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4042,6 +4042,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) if (hns->hw.adapter_state == HNS3_NIC_STARTED && __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) { eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; @@ -4258,6 +4259,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) } int +hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + volatile struct hns3_desc *rxdp; + struct hns3_rx_queue *rxq; + struct rte_eth_dev *dev; + uint32_t bd_base_info; + uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; + if (offset >= rxq->nb_rx_desc) + return -EINVAL; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; + if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { + if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ + if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) + return RTE_ETH_RX_DESC_UNAVAIL; + } else { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) + return RTE_ETH_RX_DESC_AVAIL; + else + return RTE_ETH_RX_DESC_DONE; +} + +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { volatile struct hns3_desc *txdp; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 82d5aa0..f9b3048 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,6 +720,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) ` (10 preceding siblings ...) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) @ 2021-03-23 11:20 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) ` (8 more replies) 11 siblings, 9 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:20 UTC (permalink / raw) To: dev, ferruh.yigit This series add four features according to the 21.05 roadmap, and also two cleanups added. v6: * Adjust the styles of hns3.rst about runtime config options. v5: * Document hns3.rst about description of vec, common and simple. v4: * Rename variable name oq_glb_drop_cnt to oq_drop_cnt. v3: * Change code styles. v2: * Fixed commit information about patch set. Chengchang Tang (1): net/hns3: support for outer UDP cksum Chengwen Feng (1): net/hns3: support runtime config to select IO burst func Hongbo Zheng (4): net/hns3: adjust the format of RAS related structures net/hns3: delete redundant xstats RAS statistics net/hns3: support query Tx descriptor status net/hns3: support query Rx descriptor status Min Hu (Connor) (2): net/hns3: support imissed stats for PF/VF net/hns3: support oerrors stats in PF doc/guides/nics/features/hns3.ini | 2 + doc/guides/nics/features/hns3_vf.ini | 2 + doc/guides/nics/hns3.rst | 37 + doc/guides/rel_notes/release_21_05.rst | 4 + drivers/net/hns3/hns3_cmd.c | 3 + drivers/net/hns3/hns3_cmd.h | 13 + drivers/net/hns3/hns3_ethdev.c | 86 +- drivers/net/hns3/hns3_ethdev.h | 76 +- drivers/net/hns3/hns3_ethdev_vf.c | 18 + drivers/net/hns3/hns3_intr.c | 2127 ++++++++++++++++++-------------- drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_rxtx.c | 203 ++- drivers/net/hns3/hns3_rxtx.h | 6 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- drivers/net/hns3/hns3_stats.c | 394 +++--- drivers/net/hns3/hns3_stats.h | 2 +- 16 files changed, 1856 insertions(+), 1124 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 1/8] net/hns3: support runtime config to select IO burst func 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) ` (7 subsequent siblings) 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit From: Chengwen Feng <fengchengwen@huawei.com> Currently, the driver support multiple IO burst function and auto selection of the most appropriate function based on offload configuration. Most applications such as l2fwd/l3fwd don't provide the means to change offload configuration, so it will use the auto selection's io burst function. This patch support runtime config to select io burst function, which add two config: rx_func_hint and tx_func_hint, both could assign vec/sve/simple/common. The driver will use the following rules to select io burst func: a. if hint equal vec and meet the vec Rx/Tx usage condition then use the neon function. b. if hint equal sve and meet the sve Rx/Tx usage condition then use the sve function. c. if hint equal simple and meet the simple Rx/Tx usage condition then use the simple function. d. if hint equal common then use the common function. e. if hint not set then: e.1. if meet the vec Rx/Tx usage condition then use the neon function. e.2. if meet the simple Rx/Tx usage condition then use the simple function. e.3. else use the common function. Note: the sve Rx/Tx usage condition based on the vec Rx/Tx usage condition and runtime environment (which must support SVE). In the previous versions, driver will preferred use the sve function when meet the sve Rx/Tx usage condition, but in this case driver could get better performance if use the neon function. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/hns3.rst | 37 ++++++++++++++++ doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 77 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.h | 15 +++++++ drivers/net/hns3/hns3_ethdev_vf.c | 4 ++ drivers/net/hns3/hns3_rxtx.c | 54 +++++++++++++++++------- 6 files changed, 174 insertions(+), 14 deletions(-) diff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst index 84bd7a3..ccd2f6f 100644 --- a/doc/guides/nics/hns3.rst +++ b/doc/guides/nics/hns3.rst @@ -46,6 +46,43 @@ Prerequisites - Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. +Runtime Config Options +---------------------- + +- ``rx_func_hint`` (default ``none``) + + Used to select Rx burst function, supported value are ``vec``, ``sve``, + ``simple``, ``common``. + ``vec``, if supported use the ``vec`` Rx function which indicates the + default vector algorithm, neon for Kunpeng Arm platform. + ``sve``, if supported use the ``sve`` Rx function which indicates the + sve algorithm. + ``simple``, if supported use the ``simple`` Rx function which indicates + the scalar algorithm. + ``common``, if supported use the ``common`` Rx function which indicates + the scalar scattered algorithm. + + When provided parameter is not supported, ``vec`` usage condition will + be first checked, if meets, use the ``vec``. Then, ``simple``, at last + ``common``. + +- ``tx_func_hint`` (default ``none``) + + Used to select Tx burst function, supported value are ``vec``, ``sve``, + ``simple``, ``common``. + ``vec``, if supported use the ``vec`` Tx function which indicates the + default vector algorithm, neon for Kunpeng Arm platform. + ``sve``, if supported use the ``sve`` Tx function which indicates the + sve algorithm. + ``simple``, if supported use the ``simple`` Tx function which indicates + the scalar simple algorithm. + ``common``, if supported use the ``common`` Tx function which indicates + the scalar algorithm. + + When provided parameter is not supported, ``vec`` usage condition will + be first checked, if meets, use the ``vec``. Then, ``simple``, at last + ``common``. + Driver compilation and testing ------------------------------ diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index dc5399f..1d85942 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -60,6 +60,7 @@ New Features * Added support for module EEPROM dumping. * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. + * Added support for runtime config to select IO burst function. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 9cbcc13..28aa27a 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6,6 +6,7 @@ #include <rte_bus_pci.h> #include <ethdev_pci.h> #include <rte_pci.h> +#include <rte_kvargs.h> #include "hns3_ethdev.h" #include "hns3_logs.h" @@ -6505,6 +6506,78 @@ hns3_get_module_info(struct rte_eth_dev *dev, return 0; } +static int +hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) +{ + uint32_t hint = HNS3_IO_FUNC_HINT_NONE; + + RTE_SET_USED(key); + + if (strcmp(value, "vec") == 0) + hint = HNS3_IO_FUNC_HINT_VEC; + else if (strcmp(value, "sve") == 0) + hint = HNS3_IO_FUNC_HINT_SVE; + else if (strcmp(value, "simple") == 0) + hint = HNS3_IO_FUNC_HINT_SIMPLE; + else if (strcmp(value, "common") == 0) + hint = HNS3_IO_FUNC_HINT_COMMON; + + /* If the hint is valid then update output parameters */ + if (hint != HNS3_IO_FUNC_HINT_NONE) + *(uint32_t *)extra_args = hint; + + return 0; +} + +static const char * +hns3_get_io_hint_func_name(uint32_t hint) +{ + switch (hint) { + case HNS3_IO_FUNC_HINT_VEC: + return "vec"; + case HNS3_IO_FUNC_HINT_SVE: + return "sve"; + case HNS3_IO_FUNC_HINT_SIMPLE: + return "simple"; + case HNS3_IO_FUNC_HINT_COMMON: + return "common"; + default: + return "none"; + } +} + +void +hns3_parse_devargs(struct rte_eth_dev *dev) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; + uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; + struct hns3_hw *hw = &hns->hw; + struct rte_kvargs *kvlist; + + if (dev->device->devargs == NULL) + return; + + kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); + if (!kvlist) + return; + + rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, + &hns3_parse_io_hint_func, &rx_func_hint); + rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, + &hns3_parse_io_hint_func, &tx_func_hint); + rte_kvargs_free(kvlist); + + if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, + hns3_get_io_hint_func_name(rx_func_hint)); + hns->rx_func_hint = rx_func_hint; + if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) + hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, + hns3_get_io_hint_func_name(tx_func_hint)); + hns->tx_func_hint = tx_func_hint; +} + static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_configure = hns3_dev_configure, .dev_start = hns3_dev_start, @@ -6625,6 +6698,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = false; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); /* * Set default max packet size according to the mtu @@ -6758,5 +6832,8 @@ static struct rte_pci_driver rte_hns3_pmd = { RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 932600d..ec4b475 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -772,9 +772,23 @@ struct hns3_adapter { bool tx_simple_allowed; bool tx_vec_allowed; + uint32_t rx_func_hint; + uint32_t tx_func_hint; + struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned; }; +enum { + HNS3_IO_FUNC_HINT_NONE = 0, + HNS3_IO_FUNC_HINT_VEC, + HNS3_IO_FUNC_HINT_SVE, + HNS3_IO_FUNC_HINT_SIMPLE, + HNS3_IO_FUNC_HINT_COMMON +}; + +#define HNS3_DEVARG_RX_FUNC_HINT "rx_func_hint" +#define HNS3_DEVARG_TX_FUNC_HINT "tx_func_hint" + #define HNS3_DEV_SUPPORT_DCB_B 0x0 #define HNS3_DEV_SUPPORT_COPPER_B 0x1 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2 @@ -975,6 +989,7 @@ int hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info); void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status, uint32_t link_speed, uint8_t link_duplex); +void hns3_parse_devargs(struct rte_eth_dev *dev); static inline bool is_reset_pending(struct hns3_adapter *hns) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index fd20c52..f3eaefb 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2834,6 +2834,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) hw->adapter_state = HNS3_NIC_UNINITIALIZED; hns->is_vf = true; hw->data = eth_dev->data; + hns3_parse_devargs(eth_dev); ret = hns3_reset_init(hw); if (ret) @@ -2962,3 +2963,6 @@ static struct rte_pci_driver rte_hns3vf_pmd = { RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map); RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf, + HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " + HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "); diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 00167c4..f5c7d71 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2689,13 +2689,26 @@ hns3_get_rx_function(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; uint64_t offloads = dev->data->dev_conf.rxmode.offloads; + bool vec_allowed, sve_allowed, simple_allowed; + + vec_allowed = hns->rx_vec_allowed && + hns3_rx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->rx_simple_allowed && !dev->data->scattered_rx && + (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0; + + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_recv_pkts_vec; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_recv_pkts_vec_sve; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) + return hns3_recv_pkts; + if (hns->rx_func_hint == HNS3_IO_FUNC_HINT_COMMON) + return hns3_recv_scattered_pkts; - if (hns->rx_vec_allowed && hns3_rx_check_vec_support(dev) == 0) - return hns3_check_sve_support() ? hns3_recv_pkts_vec_sve : - hns3_recv_pkts_vec; - - if (hns->rx_simple_allowed && !dev->data->scattered_rx && - (offloads & DEV_RX_OFFLOAD_TCP_LRO) == 0) + if (vec_allowed) + return hns3_recv_pkts_vec; + if (simple_allowed) return hns3_recv_pkts; return hns3_recv_scattered_pkts; @@ -3930,19 +3943,32 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep) { uint64_t offloads = dev->data->dev_conf.txmode.offloads; struct hns3_adapter *hns = dev->data->dev_private; + bool vec_allowed, sve_allowed, simple_allowed; - if (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) { - *prep = NULL; - return hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve : - hns3_xmit_pkts_vec; - } + vec_allowed = hns->tx_vec_allowed && + hns3_tx_check_vec_support(dev) == 0; + sve_allowed = vec_allowed && hns3_check_sve_support(); + simple_allowed = hns->tx_simple_allowed && + offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE); - if (hns->tx_simple_allowed && - offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) { - *prep = NULL; + *prep = NULL; + + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_VEC && vec_allowed) + return hns3_xmit_pkts_vec; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SVE && sve_allowed) + return hns3_xmit_pkts_vec_sve; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_SIMPLE && simple_allowed) return hns3_xmit_pkts_simple; + if (hns->tx_func_hint == HNS3_IO_FUNC_HINT_COMMON) { + *prep = hns3_prep_pkts; + return hns3_xmit_pkts; } + if (vec_allowed) + return hns3_xmit_pkts_vec; + if (simple_allowed) + return hns3_xmit_pkts_simple; + *prep = hns3_prep_pkts; return hns3_xmit_pkts; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 2/8] net/hns3: support for outer UDP cksum 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) ` (6 subsequent siblings) 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit From: Chengchang Tang <tangchengchang@huawei.com> Kunpeng930 support outer UDP cksum, this patch add support for it. Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_cmd.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 3 ++ drivers/net/hns3/hns3_ethdev.h | 4 ++ drivers/net/hns3/hns3_ethdev_vf.c | 3 ++ drivers/net/hns3/hns3_rxtx.c | 85 +++++++++++++++++++++++++++------- drivers/net/hns3/hns3_rxtx.h | 4 +- drivers/net/hns3/hns3_rxtx_vec_sve.c | 5 +- 8 files changed, 89 insertions(+), 19 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 1d85942..c3324d8 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -61,6 +61,7 @@ New Features * Added support for freeing Tx mbuf on demand. * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. + * Added support for outer UDP checksum in Kunpeng930. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 8b9f075..03f8048 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -433,6 +433,9 @@ hns3_parse_capability(struct hns3_hw *hw, if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_UDP_TUNNEL_CSUM_B)) + hns3_set_bit(hw->capability, + HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1); } static uint32_t diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 28aa27a..3949153 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2620,6 +2620,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index ec4b475..0fc0a1c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -798,6 +798,7 @@ enum { #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6 #define HNS3_DEV_SUPPORT_STASH_B 0x7 #define HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B 0x9 +#define HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B 0xA #define hns3_dev_dcb_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B) @@ -831,6 +832,9 @@ enum { #define hns3_dev_rxd_adv_layout_supported(hw) \ hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B) +#define hns3_dev_outer_udp_cksum_supported(hw) \ + hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B) + #define HNS3_DEV_PRIVATE_TO_HW(adapter) \ (&((struct hns3_adapter *)adapter)->hw) #define HNS3_DEV_PRIVATE_TO_PF(adapter) \ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index f3eaefb..e1e41b8 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -988,6 +988,9 @@ hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) DEV_TX_OFFLOAD_MBUF_FAST_FREE | hns3_txvlan_cap_get(hw)); + if (hns3_dev_outer_udp_cksum_supported(hw)) + info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; + if (hns3_dev_indep_txrx_supported(hw)) info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index f5c7d71..7529279 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2967,7 +2967,7 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc, hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ? rxm->outer_l2_len + rxm->outer_l3_len : 0; paylen = rxm->pkt_len - hdr_len; - desc->tx.paylen = rte_cpu_to_le_32(paylen); + desc->tx.paylen_fd_dop_ol4cs |= rte_cpu_to_le_32(paylen); hns3_set_tso(desc, paylen, rxm); /* @@ -3204,8 +3204,10 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, { struct hns3_desc *tx_ring = txq->tx_ring; struct hns3_desc *desc = &tx_ring[tx_desc_id]; + uint64_t ol_flags = m->ol_flags; uint32_t tmp_outer = 0; uint32_t tmp_inner = 0; + uint32_t tmp_ol4cs; int ret; /* @@ -3215,7 +3217,7 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * calculations, the length of the L2 header include the outer and * inner, will be filled during the parsing of tunnel packects. */ - if (!(m->ol_flags & PKT_TX_TUNNEL_MASK)) { + if (!(ol_flags & PKT_TX_TUNNEL_MASK)) { /* * For non tunnel type the tunnel type id is 0, so no need to * assign a value to it. Only the inner(normal) L2 header length @@ -3230,7 +3232,8 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, * inner l2_len. It would lead a cksum error. So driver has to * calculate the header length. */ - if (unlikely(!(m->ol_flags & PKT_TX_OUTER_IP_CKSUM) && + if (unlikely(!(ol_flags & + (PKT_TX_OUTER_IP_CKSUM | PKT_TX_OUTER_UDP_CKSUM)) && m->outer_l2_len == 0)) { struct rte_net_hdr_lens hdr_len; (void)rte_net_get_ptype(m, &hdr_len, @@ -3247,6 +3250,9 @@ hns3_parse_tunneling_params(struct hns3_tx_queue *txq, struct rte_mbuf *m, desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp_outer); desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp_inner); + tmp_ol4cs = ol_flags & PKT_TX_OUTER_UDP_CKSUM ? + BIT(HNS3_TXD_OL4CS_B) : 0; + desc->tx.paylen_fd_dop_ol4cs = rte_cpu_to_le_32(tmp_ol4cs); return 0; } @@ -3376,31 +3382,78 @@ hns3_pkt_need_linearized(struct rte_mbuf *tx_pkts, uint32_t bd_num, return false; } +static bool +hns3_outer_ipv4_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv4_hdr *ipv4_hdr; + ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) + ipv4_hdr->hdr_checksum = 0; + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv4_phdr_cksum(ipv4_hdr, ol_flags); + + return true; + } + *l4_proto = ipv4_hdr->next_proto_id; + return false; +} + +static bool +hns3_outer_ipv6_cksum_prepared(struct rte_mbuf *m, uint64_t ol_flags, + uint32_t *l4_proto) +{ + struct rte_ipv6_hdr *ipv6_hdr; + ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, + m->outer_l2_len); + if (ol_flags & PKT_TX_OUTER_UDP_CKSUM) { + struct rte_udp_hdr *udp_hdr; + /* + * If OUTER_UDP_CKSUM is support, HW can caclulate the pseudo + * header for TSO packets + */ + if (ol_flags & PKT_TX_TCP_SEG) + return true; + udp_hdr = rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *, + m->outer_l2_len + m->outer_l3_len); + udp_hdr->dgram_cksum = rte_ipv6_phdr_cksum(ipv6_hdr, ol_flags); + + return true; + } + *l4_proto = ipv6_hdr->proto; + return false; +} + static void hns3_outer_header_cksum_prepare(struct rte_mbuf *m) { uint64_t ol_flags = m->ol_flags; uint32_t paylen, hdr_len, l4_proto; + struct rte_udp_hdr *udp_hdr; if (!(ol_flags & (PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IPV6))) return; if (ol_flags & PKT_TX_OUTER_IPV4) { - struct rte_ipv4_hdr *ipv4_hdr; - ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, - m->outer_l2_len); - l4_proto = ipv4_hdr->next_proto_id; - if (ol_flags & PKT_TX_OUTER_IP_CKSUM) - ipv4_hdr->hdr_checksum = 0; + if (hns3_outer_ipv4_cksum_prepared(m, ol_flags, &l4_proto)) + return; } else { - struct rte_ipv6_hdr *ipv6_hdr; - ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *, - m->outer_l2_len); - l4_proto = ipv6_hdr->proto; + if (hns3_outer_ipv6_cksum_prepared(m, ol_flags, &l4_proto)) + return; } + /* driver should ensure the outer udp cksum is 0 for TUNNEL TSO */ if (l4_proto == IPPROTO_UDP && (ol_flags & PKT_TX_TCP_SEG)) { - struct rte_udp_hdr *udp_hdr; hdr_len = m->l2_len + m->l3_len + m->l4_len; hdr_len += m->outer_l2_len + m->outer_l3_len; paylen = m->pkt_len - hdr_len; @@ -3686,7 +3739,7 @@ hns3_tx_setup_4bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); @@ -3702,7 +3755,7 @@ hns3_tx_setup_1bd(struct hns3_desc *txdp, struct rte_mbuf **pkts) dma_addr = rte_mbuf_data_iova(*pkts); txdp->addr = rte_cpu_to_le_64(dma_addr); txdp->tx.send_size = rte_cpu_to_le_16((*pkts)->data_len); - txdp->tx.paylen = 0; + txdp->tx.paylen_fd_dop_ol4cs = 0; txdp->tx.type_cs_vlan_tso_len = 0; txdp->tx.ol_type_vlan_len_msec = 0; txdp->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(bd_flag); diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 9adeb24..cd04200 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -149,6 +149,7 @@ #define HNS3_TXD_MSS_S 0 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) +#define HNS3_TXD_OL4CS_B 22 #define HNS3_L2_LEN_UNIT 1UL #define HNS3_L3_LEN_UNIT 2UL #define HNS3_L4_LEN_UNIT 2UL @@ -234,7 +235,7 @@ struct hns3_desc { }; }; - uint32_t paylen; + uint32_t paylen_fd_dop_ol4cs; uint16_t tp_fe_sc_vld_ra_ri; uint16_t mss; } tx; @@ -503,6 +504,7 @@ struct hns3_queue_info { }; #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_OUTER_UDP_CKSUM | \ PKT_TX_OUTER_IP_CKSUM | \ PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \ diff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c index 2a22a1a..90e45c6 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_sve.c +++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c @@ -408,8 +408,9 @@ hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq, (uint64_t *)&txdp->tx.outer_vlan_tag, offsets, svdup_n_u64(0)); /* save offset 24~31byte of every BD */ - svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen, - offsets, svdup_n_u64(valid_bit)); + svst1_scatter_u64offset_u64(pg, + (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs, + offsets, svdup_n_u64(valid_bit)); /* Increment bytes counter */ uint32_t idx; -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 3/8] net/hns3: adjust the format of RAS related structures 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) ` (5 subsequent siblings) 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Adjust the format of hns3 RAS related structures to resolve the static check warnings. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_intr.c | 2126 ++++++++++++++++++++++++------------------ 1 file changed, 1224 insertions(+), 902 deletions(-) diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 2563504..265dae8 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -28,282 +28,375 @@ static const char *reset_string[HNS3_MAX_RESET] = { }; static const struct hns3_hw_error mac_afifo_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "egu_cge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "egu_cge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "egu_lge_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "egu_lge_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "cge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "lge_igu_afifo_ecc_1bit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "lge_igu_afifo_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "cge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "lge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "egu_cge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "egu_lge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "egu_ge_afifo_underrun_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ge_igu_afifo_overflow_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "egu_cge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "egu_cge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "egu_lge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "egu_lge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "cge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "lge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "lge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "cge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "lge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "egu_cge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "egu_lge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "egu_ge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { - { .int_msk = 0xFFFFFFFF, - .msg = "rpu_rx_pkt_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = 0xFFFFFFFF, + .msg = "rpu_rx_pkt_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { - { .int_msk = BIT(13), - .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rcb_tx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rcb_rx_ring_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rcb_tx_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rcb_rx_ebd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rcb_tso_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rcb_tx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rcb_rx_int_info_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tpu_tx_pkt_0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tpu_tx_pkt_1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "rd_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "wr_bus_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "ooo_ecc_err_detect", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(31), - .msg = "ooo_ecc_err_multpl", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(13), + .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rcb_tx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rcb_rx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rcb_tx_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rcb_rx_ebd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rcb_tso_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rcb_tx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rcb_rx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tpu_tx_pkt_0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tpu_tx_pkt_1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "rd_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "wr_bus_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "ooo_ecc_err_detect", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(31), + .msg = "ooo_ecc_err_multpl", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { - { .int_msk = BIT(29), - .msg = "rx_q_search_miss", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(29), + .msg = "rx_q_search_miss", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_pf_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "low_water_line_err_port", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "low_water_line_err_port", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_pf_abnormal_int[] = { - { .int_msk = BIT(0), - .msg = "tx_vlan_tag_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "rss_list_tc_unassigned_queue_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "tx_vlan_tag_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "rss_list_tc_unassigned_queue_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { - { .int_msk = BIT(3), - .msg = "tx_rd_fbd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(4), - .msg = "rx_rd_ebd_poison", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(3), + .msg = "tx_rd_fbd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(4), + .msg = "rx_rd_ebd_poison", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { - { .int_msk = BIT(0), - .msg = "over_8bd_no_fe", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tso_mss_cmp_min_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "tso_mss_cmp_max_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "buf_wait_timeout", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "over_8bd_no_fe", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tso_mss_cmp_min_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "tso_mss_cmp_max_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "buf_wait_timeout", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_tcm_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "imp_itcm0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "imp_itcm1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "imp_itcm2_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "imp_itcm3_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "imp_dtcm0_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "imp_dtcm0_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "imp_dtcm1_mem0_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "imp_dtcm1_mem1_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(17), - .msg = "imp_itcm4_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "imp_itcm0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "imp_itcm1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "imp_itcm2_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "imp_itcm3_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "imp_dtcm0_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "imp_dtcm0_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "imp_dtcm1_mem0_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "imp_dtcm1_mem1_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(17), + .msg = "imp_itcm4_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error cmdq_mem_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "cmdq_nic_rx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(3), - .msg = "cmdq_nic_tx_depth_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(5), - .msg = "cmdq_nic_rx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "cmdq_nic_tx_tail_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "cmdq_nic_rx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "cmdq_nic_tx_head_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(13), - .msg = "cmdq_nic_rx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(15), - .msg = "cmdq_nic_tx_addr_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "cmdq_nic_rx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(3), + .msg = "cmdq_nic_tx_depth_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(5), + .msg = "cmdq_nic_rx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "cmdq_nic_tx_tail_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "cmdq_nic_rx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "cmdq_nic_tx_head_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(13), + .msg = "cmdq_nic_rx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(15), + .msg = "cmdq_nic_tx_addr_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tqp_int_ecc_int[] = { - { .int_msk = BIT(6), - .msg = "tqp_int_cfg_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(7), - .msg = "tqp_int_cfg_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(8), - .msg = "tqp_int_ctrl_even_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(9), - .msg = "tqp_int_ctrl_odd_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(10), - .msg = "tx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(11), - .msg = "rx_queue_scan_int_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(6), + .msg = "tqp_int_cfg_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(7), + .msg = "tqp_int_cfg_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(8), + .msg = "tqp_int_ctrl_even_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(9), + .msg = "tqp_int_ctrl_odd_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(10), + .msg = "tx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(11), + .msg = "rx_queue_scan_int_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error imp_rd_poison_int[] = { - { .int_msk = BIT(0), - .msg = "imp_rd_poison_int", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "imp_rd_poison_int", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; #define HNS3_SSU_MEM_ECC_ERR(x) \ - { .int_msk = BIT(x), \ - .msg = "ssu_mem" #x "_ecc_mbit_err", \ - .reset_level = HNS3_GLOBAL_RESET } +{ \ + .int_msk = BIT(x), \ + .msg = "ssu_mem" #x "_ecc_mbit_err", \ + .reset_level = HNS3_GLOBAL_RESET \ +} static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { HNS3_SSU_MEM_ECC_ERR(0), @@ -344,722 +437,951 @@ static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { }; static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { - { .int_msk = BIT(0), - .msg = "ssu_mem32_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ssu_mem32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_common_ecc_int[] = { - { .int_msk = BIT(0), - .msg = "buf_sum_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(1), - .msg = "ppp_mb_num_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = BIT(2), - .msg = "ppp_mbid_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ppp_rlt_mac_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ppp_rlt_host_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "cks_edit_position_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "cks_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "vlan_edit_condition_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "vlan_num_ot_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "vlan_num_in_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "buf_sum_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(1), + .msg = "ppp_mb_num_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = BIT(2), + .msg = "ppp_mbid_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ppp_rlt_mac_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ppp_rlt_host_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "cks_edit_position_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "cks_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "vlan_edit_condition_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "vlan_num_ot_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "vlan_num_in_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_int[] = { - { .int_msk = BIT(0), - .msg = "igu_rx_buf0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_rx_buf1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "igu_rx_buf0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_rx_buf1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error msix_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "msix_nic_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "msix_nic_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { - { .int_msk = BIT(0), - .msg = "vf_vlan_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "umv_mcast_group_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "umv_key_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "umv_key_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "umv_key_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "umv_key_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "umv_ad_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "rss_tc_mode_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rss_idt_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "rss_idt_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "rss_idt_mem2_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "rss_idt_mem3_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "rss_idt_mem4_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "rss_idt_mem5_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "rss_idt_mem6_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "rss_idt_mem7_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "rss_idt_mem8_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "rss_idt_mem9_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "rss_idt_mem10_ecc_m1bit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "rss_idt_mem11_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "rss_idt_mem12_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "rss_idt_mem13_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "rss_idt_mem14_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "rss_idt_mem15_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "port_vlan_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "mcast_linear_table_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "mcast_result_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "flow_director_ad_mem0_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "flow_director_ad_mem1_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "rx_vlan_tag_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "vf_vlan_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "umv_mcast_group_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "umv_key_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "umv_key_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "umv_key_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "umv_key_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "umv_ad_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "rss_tc_mode_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rss_idt_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "rss_idt_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "rss_idt_mem2_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "rss_idt_mem3_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "rss_idt_mem4_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "rss_idt_mem5_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "rss_idt_mem6_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "rss_idt_mem7_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "rss_idt_mem8_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "rss_idt_mem9_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "rss_idt_mem10_ecc_m1bit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "rss_idt_mem11_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "rss_idt_mem12_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "rss_idt_mem13_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "rss_idt_mem14_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "rss_idt_mem15_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "port_vlan_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "mcast_linear_table_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "mcast_result_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "flow_director_ad_mem0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "flow_director_ad_mem1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "rx_vlan_tag_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(0), - .msg = "hfs_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rslt_descr_fifo_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tx_vlan_tag_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "FD_CN0_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "FD_CN1_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "GRO_AD_memory_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "hfs_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rslt_descr_fifo_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tx_vlan_tag_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "FD_CN0_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "FD_CN1_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "GRO_AD_memory_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { - { .int_msk = BIT(4), - .msg = "gro_bd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "gro_context_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_stash_cfg_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "axi_rd_fbd_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(4), + .msg = "gro_bd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "gro_context_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_stash_cfg_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "axi_rd_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error tm_sch_int[] = { - { .int_msk = BIT(1), - .msg = "tm_sch_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "tm_sch_port_shap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tm_sch_port_shap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "tm_sch_port_shap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "tm_sch_port_shap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "tm_sch_rq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "tm_sch_rq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(24), - .msg = "tm_sch_nq_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(25), - .msg = "tm_sch_nq_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(26), - .msg = "tm_sch_roce_up_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(27), - .msg = "tm_sch_roce_up_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(28), - .msg = "tm_sch_rcb_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(29), - .msg = "tm_sch_rcb_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(30), - .msg = "tm_sch_ssu_byte_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(31), - .msg = "tm_sch_ssu_byte_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "tm_sch_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "tm_sch_port_shap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tm_sch_port_shap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "tm_sch_port_shap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "tm_sch_port_shap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "tm_sch_rq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "tm_sch_rq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(24), + .msg = "tm_sch_nq_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(25), + .msg = "tm_sch_nq_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(26), + .msg = "tm_sch_roce_up_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(27), + .msg = "tm_sch_roce_up_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(28), + .msg = "tm_sch_rcb_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(29), + .msg = "tm_sch_rcb_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(30), + .msg = "tm_sch_ssu_byte_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(31), + .msg = "tm_sch_ssu_byte_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_fifo_int[] = { - { .int_msk = BIT(0), - .msg = "qcn_shap_gp0_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "qcn_shap_gp0_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "qcn_shap_gp1_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_shap_gp1_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "qcn_shap_gp2_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_shap_gp2_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "qcn_shap_gp3_sch_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_shap_gp3_sch_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "qcn_shap_gp0_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_shap_gp0_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "qcn_shap_gp1_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_shap_gp1_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "qcn_shap_gp2_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_gp2_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "qcn_shap_gp3_offset_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_shap_gp3_offset_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "qcn_byte_info_fifo_rd_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_byte_info_fifo_wr_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "qcn_shap_gp0_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "qcn_shap_gp0_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "qcn_shap_gp1_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_shap_gp1_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "qcn_shap_gp2_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_shap_gp2_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "qcn_shap_gp3_sch_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_shap_gp3_sch_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "qcn_shap_gp0_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_shap_gp0_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "qcn_shap_gp1_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_shap_gp1_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "qcn_shap_gp2_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_gp2_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "qcn_shap_gp3_offset_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_shap_gp3_offset_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "qcn_byte_info_fifo_rd_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_byte_info_fifo_wr_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error qcn_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "qcn_byte_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "qcn_time_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "qcn_fb_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "qcn_link_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qcn_rate_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "qcn_tmplt_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "qcn_shap_cfg_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "qcn_gp3_barral_mem_ecc_mbit_err", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "qcn_byte_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "qcn_time_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "qcn_fb_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "qcn_link_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qcn_rate_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "qcn_tmplt_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "qcn_shap_cfg_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "qcn_gp3_barral_mem_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ncsi_ecc_int[] = { - { .int_msk = BIT(1), - .msg = "ncsi_tx_ecc_mbit_err", - .reset_level = HNS3_NONE_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(1), + .msg = "ncsi_tx_ecc_mbit_err", + .reset_level = HNS3_NONE_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_fifo_overflow_int[] = { - { .int_msk = BIT(0), - .msg = "ig_mac_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ig_host_inf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ig_roc_buf_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ig_host_data_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "ig_host_key_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "tx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "rx_qcn_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "rx_pf_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(9), - .msg = "qm_eof_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(10), - .msg = "mb_rlt_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "dup_uncopy_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "dup_cnt_rd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "dup_cnt_drop_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "dup_cnt_wrb_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(15), - .msg = "host_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(16), - .msg = "mac_cmd_fifo_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(17), - .msg = "host_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(18), - .msg = "mac_cmd_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(19), - .msg = "dup_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(20), - .msg = "out_queue_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(21), - .msg = "bank2_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(22), - .msg = "bank1_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(23), - .msg = "bank0_bitmap_empty_int", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ig_mac_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ig_host_inf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ig_roc_buf_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ig_host_data_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "ig_host_key_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "tx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "rx_qcn_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "rx_pf_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(9), + .msg = "qm_eof_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(10), + .msg = "mb_rlt_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "dup_uncopy_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "dup_cnt_rd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "dup_cnt_drop_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "dup_cnt_wrb_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(15), + .msg = "host_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(16), + .msg = "mac_cmd_fifo_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(17), + .msg = "host_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(18), + .msg = "mac_cmd_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(19), + .msg = "dup_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(20), + .msg = "out_queue_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(21), + .msg = "bank2_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(22), + .msg = "bank1_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(23), + .msg = "bank0_bitmap_empty_int", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_ets_tcg_int[] = { - { .int_msk = BIT(0), - .msg = "ets_rd_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "ets_wr_int_rx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "ets_rd_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "ets_wr_int_tx_tcg", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "ets_rd_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "ets_wr_int_rx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "ets_rd_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "ets_wr_int_tx_tcg", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error igu_egu_tnl_int[] = { - { .int_msk = BIT(0), - .msg = "rx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(1), - .msg = "rx_stp_fifo_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "rx_stp_fifo_underflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "tx_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tx_buf_underrun", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "rx_stp_buf_overflow", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "rx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(1), + .msg = "rx_stp_fifo_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "rx_stp_fifo_underflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "tx_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tx_buf_underrun", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "rx_stp_buf_overflow", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error ssu_port_based_err_int[] = { - { .int_msk = BIT(0), - .msg = "roc_pkt_without_key_port", - .reset_level = HNS3_FUNC_RESET }, - { .int_msk = BIT(1), - .msg = "tpu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(2), - .msg = "igu_pkt_without_key_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(3), - .msg = "roc_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(4), - .msg = "tpu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(5), - .msg = "igu_eof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(6), - .msg = "roc_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(7), - .msg = "tpu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(8), - .msg = "igu_sof_mis_match_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(11), - .msg = "ets_rd_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(12), - .msg = "ets_wr_int_rx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(13), - .msg = "ets_rd_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = BIT(14), - .msg = "ets_wr_int_tx_port", - .reset_level = HNS3_GLOBAL_RESET }, - { .int_msk = 0, - .msg = NULL, - .reset_level = HNS3_NONE_RESET} + { + .int_msk = BIT(0), + .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_FUNC_RESET + }, { + .int_msk = BIT(1), + .msg = "tpu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(2), + .msg = "igu_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(3), + .msg = "roc_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(4), + .msg = "tpu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(5), + .msg = "igu_eof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(6), + .msg = "roc_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(7), + .msg = "tpu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(8), + .msg = "igu_sof_mis_match_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(11), + .msg = "ets_rd_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(12), + .msg = "ets_wr_int_rx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(13), + .msg = "ets_rd_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = BIT(14), + .msg = "ets_wr_int_tx_port", + .reset_level = HNS3_GLOBAL_RESET + }, { + .int_msk = 0, + .msg = NULL, + .reset_level = HNS3_NONE_RESET + } }; static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "IMP_TCM_ECC_INT_STS", - .hw_err = imp_tcm_ecc_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "CMDQ_MEM_ECC_INT_STS", - .hw_err = cmdq_mem_ecc_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "IMP_RD_POISON_INT_STS", - .hw_err = imp_rd_poison_int }, - { .desc_offset = 0, - .data_offset = 3, - .msg = "TQP_INT_ECC_INT_STS", - .hw_err = tqp_int_ecc_int }, - { .desc_offset = 0, - .data_offset = 4, - .msg = "MSIX_ECC_INT_STS", - .hw_err = msix_ecc_int }, - { .desc_offset = 2, - .data_offset = 2, - .msg = "SSU_ECC_MULTI_BIT_INT_0", - .hw_err = ssu_ecc_multi_bit_int_0 }, - { .desc_offset = 2, - .data_offset = 3, - .msg = "SSU_ECC_MULTI_BIT_INT_1", - .hw_err = ssu_ecc_multi_bit_int_1 }, - { .desc_offset = 2, - .data_offset = 4, - .msg = "SSU_COMMON_ERR_INT", - .hw_err = ssu_common_ecc_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "IGU_INT_STS", - .hw_err = igu_int }, - { .desc_offset = 4, - .data_offset = 1, - .msg = "PPP_MPF_ABNORMAL_INT_ST1", - .hw_err = ppp_mpf_abnormal_int_st1 }, - { .desc_offset = 4, - .data_offset = 3, - .msg = "PPP_MPF_ABNORMAL_INT_ST3", - .hw_err = ppp_mpf_abnormal_int_st3 }, - { .desc_offset = 5, - .data_offset = 1, - .msg = "PPU_MPF_ABNORMAL_INT_ST1", - .hw_err = ppu_mpf_abnormal_int_st1 }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", - .hw_err = ppu_mpf_abnormal_int_st2_ras }, - { .desc_offset = 5, - .data_offset = 3, - .msg = "PPU_MPF_ABNORMAL_INT_ST3", - .hw_err = ppu_mpf_abnormal_int_st3 }, - { .desc_offset = 6, - .data_offset = 0, - .msg = "TM_SCH_RINT", - .hw_err = tm_sch_int }, - { .desc_offset = 7, - .data_offset = 0, - .msg = "QCN_FIFO_RINT", - .hw_err = qcn_fifo_int }, - { .desc_offset = 7, - .data_offset = 1, - .msg = "QCN_ECC_RINT", - .hw_err = qcn_ecc_int }, - { .desc_offset = 9, - .data_offset = 0, - .msg = "NCSI_ECC_INT_RPT", - .hw_err = ncsi_ecc_int }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "IMP_TCM_ECC_INT_STS", + .hw_err = imp_tcm_ecc_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "CMDQ_MEM_ECC_INT_STS", + .hw_err = cmdq_mem_ecc_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "IMP_RD_POISON_INT_STS", + .hw_err = imp_rd_poison_int + }, { + .desc_offset = 0, + .data_offset = 3, + .msg = "TQP_INT_ECC_INT_STS", + .hw_err = tqp_int_ecc_int + }, { + .desc_offset = 0, + .data_offset = 4, + .msg = "MSIX_ECC_INT_STS", + .hw_err = msix_ecc_int + }, { + .desc_offset = 2, + .data_offset = 2, + .msg = "SSU_ECC_MULTI_BIT_INT_0", + .hw_err = ssu_ecc_multi_bit_int_0 + }, { + .desc_offset = 2, + .data_offset = 3, + .msg = "SSU_ECC_MULTI_BIT_INT_1", + .hw_err = ssu_ecc_multi_bit_int_1 + }, { + .desc_offset = 2, + .data_offset = 4, + .msg = "SSU_COMMON_ERR_INT", + .hw_err = ssu_common_ecc_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "IGU_INT_STS", + .hw_err = igu_int + }, { + .desc_offset = 4, + .data_offset = 1, + .msg = "PPP_MPF_ABNORMAL_INT_ST1", + .hw_err = ppp_mpf_abnormal_int_st1 + }, { + .desc_offset = 4, + .data_offset = 3, + .msg = "PPP_MPF_ABNORMAL_INT_ST3", + .hw_err = ppp_mpf_abnormal_int_st3 + }, { + .desc_offset = 5, + .data_offset = 1, + .msg = "PPU_MPF_ABNORMAL_INT_ST1", + .hw_err = ppu_mpf_abnormal_int_st1 + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", + .hw_err = ppu_mpf_abnormal_int_st2_ras + }, { + .desc_offset = 5, + .data_offset = 3, + .msg = "PPU_MPF_ABNORMAL_INT_ST3", + .hw_err = ppu_mpf_abnormal_int_st3 + }, { + .desc_offset = 6, + .data_offset = 0, + .msg = "TM_SCH_RINT", + .hw_err = tm_sch_int + }, { + .desc_offset = 7, + .data_offset = 0, + .msg = "QCN_FIFO_RINT", + .hw_err = qcn_fifo_int + }, { + .desc_offset = 7, + .data_offset = 1, + .msg = "QCN_ECC_RINT", + .hw_err = qcn_ecc_int + }, { + .desc_offset = 9, + .data_offset = 0, + .msg = "NCSI_ECC_INT_RPT", + .hw_err = ncsi_ecc_int + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_RAS", - .hw_err = ssu_port_based_err_int }, - { .desc_offset = 0, - .data_offset = 1, - .msg = "SSU_FIFO_OVERFLOW_INT", - .hw_err = ssu_fifo_overflow_int }, - { .desc_offset = 0, - .data_offset = 2, - .msg = "SSU_ETS_TCG_INT", - .hw_err = ssu_ets_tcg_int }, - { .desc_offset = 1, - .data_offset = 0, - .msg = "IGU_EGU_TNL_INT_STS", - .hw_err = igu_egu_tnl_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", - .hw_err = ppu_pf_abnormal_int_ras }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_RAS", + .hw_err = ssu_port_based_err_int + }, { + .desc_offset = 0, + .data_offset = 1, + .msg = "SSU_FIFO_OVERFLOW_INT", + .hw_err = ssu_fifo_overflow_int + }, { + .desc_offset = 0, + .data_offset = 2, + .msg = "SSU_ETS_TCG_INT", + .hw_err = ssu_ets_tcg_int + }, { + .desc_offset = 1, + .data_offset = 0, + .msg = "IGU_EGU_TNL_INT_STS", + .hw_err = igu_egu_tnl_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", + .hw_err = ppu_pf_abnormal_int_ras + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { - { .desc_offset = 1, - .data_offset = 0, - .msg = "MAC_AFIFO_TNL_INT_R", - .hw_err = mac_afifo_tnl_int }, - { .desc_offset = 5, - .data_offset = 2, - .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", - .hw_err = ppu_mpf_abnormal_int_st2_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 1, + .data_offset = 0, + .msg = "MAC_AFIFO_TNL_INT_R", + .hw_err = mac_afifo_tnl_int + }, { + .desc_offset = 5, + .data_offset = 2, + .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", + .hw_err = ppu_mpf_abnormal_int_st2_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { - { .desc_offset = 0, - .data_offset = 0, - .msg = "SSU_PORT_BASED_ERR_INT_MSIX", - .hw_err = ssu_port_based_pf_int }, - { .desc_offset = 2, - .data_offset = 0, - .msg = "PPP_PF_ABNORMAL_INT_ST0", - .hw_err = ppp_pf_abnormal_int }, - { .desc_offset = 3, - .data_offset = 0, - .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", - .hw_err = ppu_pf_abnormal_int_msix }, - { .desc_offset = 0, - .data_offset = 0, - .msg = NULL, - .hw_err = NULL } + { + .desc_offset = 0, + .data_offset = 0, + .msg = "SSU_PORT_BASED_ERR_INT_MSIX", + .hw_err = ssu_port_based_pf_int + }, { + .desc_offset = 2, + .data_offset = 0, + .msg = "PPP_PF_ABNORMAL_INT_ST0", + .hw_err = ppp_pf_abnormal_int + }, { + .desc_offset = 3, + .data_offset = 0, + .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", + .hw_err = ppu_pf_abnormal_int_msix + }, { + .desc_offset = 0, + .data_offset = 0, + .msg = NULL, + .hw_err = NULL + } }; enum hns3_hw_err_type { -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 4/8] net/hns3: delete redundant xstats RAS statistics 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (2 preceding siblings ...) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) ` (4 subsequent siblings) 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> The current RAS code stores the reported RAS statistics in xstats. This part of statistics is of little use in practice, and because of the change of RAS scheme on Kunpeng930, the driver can not obtain the RAS information any more, so this patch delete these redundant RAS statistics. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.c | 2 - drivers/net/hns3/hns3_ethdev.h | 35 --------------- drivers/net/hns3/hns3_intr.c | 1 - drivers/net/hns3/hns3_stats.c | 100 +---------------------------------------- drivers/net/hns3/hns3_stats.h | 1 - 5 files changed, 1 insertion(+), 138 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3949153..139e893 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5768,14 +5768,12 @@ hns3_record_imp_error(struct hns3_adapter *hns) reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { hns3_warn(hw, "Detected IMP RD poison!"); - hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { hns3_warn(hw, "Detected IMP CMDQ error!"); - hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 0fc0a1c..314916c 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -561,38 +561,6 @@ struct hns3_hw { #define HNS3_FLAG_TC_BASE_SCH_MODE 1 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2 -struct hns3_err_msix_intr_stats { - uint64_t mac_afifo_tnl_int_cnt; - uint64_t ppu_mpf_abn_int_st2_msix_cnt; - uint64_t ssu_port_based_pf_int_cnt; - uint64_t ppp_pf_abnormal_int_cnt; - uint64_t ppu_pf_abnormal_int_msix_cnt; - - uint64_t imp_tcm_ecc_int_cnt; - uint64_t cmdq_mem_ecc_int_cnt; - uint64_t imp_rd_poison_int_cnt; - uint64_t tqp_int_ecc_int_cnt; - uint64_t msix_ecc_int_cnt; - uint64_t ssu_ecc_multi_bit_int_0_cnt; - uint64_t ssu_ecc_multi_bit_int_1_cnt; - uint64_t ssu_common_ecc_int_cnt; - uint64_t igu_int_cnt; - uint64_t ppp_mpf_abnormal_int_st1_cnt; - uint64_t ppp_mpf_abnormal_int_st3_cnt; - uint64_t ppu_mpf_abnormal_int_st1_cnt; - uint64_t ppu_mpf_abn_int_st2_ras_cnt; - uint64_t ppu_mpf_abnormal_int_st3_cnt; - uint64_t tm_sch_int_cnt; - uint64_t qcn_fifo_int_cnt; - uint64_t qcn_ecc_int_cnt; - uint64_t ncsi_ecc_int_cnt; - uint64_t ssu_port_based_err_int_cnt; - uint64_t ssu_fifo_overflow_int_cnt; - uint64_t ssu_ets_tcg_int_cnt; - uint64_t igu_egu_tnl_int_cnt; - uint64_t ppu_pf_abnormal_int_ras_cnt; -}; - /* vlan entry information. */ struct hns3_user_vlan_table { LIST_ENTRY(hns3_user_vlan_table) next; @@ -738,9 +706,6 @@ struct hns3_pf { uint16_t max_umv_size; uint16_t used_umv_size; - /* Statistics information for abnormal interrupt */ - struct hns3_err_msix_intr_stats abn_int_stats; - bool support_sfp_query; uint32_t fec_mode; /* current FEC mode for ethdev */ diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 265dae8..c259f2e 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -1838,7 +1838,6 @@ hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, reset_level = err->reset_level; need_reset = true; } - hns3_error_int_stats_add(hns, reg); } err++; } diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 941c75f..7cda36c 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -201,65 +201,6 @@ static const struct hns3_xstats_name_offset hns3_mac_strings[] = { HNS3_MAC_STATS_OFFSET(mac_rx_send_app_bad_pkt_num)} }; -static const struct hns3_xstats_name_offset hns3_error_int_stats_strings[] = { - {"MAC_AFIFO_TNL_INT_R", - HNS3_ERR_INT_STATS_FIELD_OFFSET(mac_afifo_tnl_int_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_msix_cnt)}, - {"SSU_PORT_BASED_ERR_INT_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_pf_int_cnt)}, - {"PPP_PF_ABNORMAL_INT_ST0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_pf_abnormal_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_MSIX", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_msix_cnt)}, - {"IMP_TCM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_tcm_ecc_int_cnt)}, - {"CMDQ_MEM_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(cmdq_mem_ecc_int_cnt)}, - {"IMP_RD_POISON_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(imp_rd_poison_int_cnt)}, - {"TQP_INT_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tqp_int_ecc_int_cnt)}, - {"MSIX_ECC_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(msix_ecc_int_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_0", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_0_cnt)}, - {"SSU_ECC_MULTI_BIT_INT_1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ecc_multi_bit_int_1_cnt)}, - {"SSU_COMMON_ERR_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_common_ecc_int_cnt)}, - {"IGU_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_int_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st1_cnt)}, - {"PPP_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppp_mpf_abnormal_int_st3_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST1", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st1_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST2_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abn_int_st2_ras_cnt)}, - {"PPU_MPF_ABNORMAL_INT_ST3", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_mpf_abnormal_int_st3_cnt)}, - {"TM_SCH_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(tm_sch_int_cnt)}, - {"QCN_FIFO_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_fifo_int_cnt)}, - {"QCN_ECC_RINT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(qcn_ecc_int_cnt)}, - {"NCSI_ECC_INT_RPT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ncsi_ecc_int_cnt)}, - {"SSU_PORT_BASED_ERR_INT_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_port_based_err_int_cnt)}, - {"SSU_FIFO_OVERFLOW_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_fifo_overflow_int_cnt)}, - {"SSU_ETS_TCG_INT", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ssu_ets_tcg_int_cnt)}, - {"IGU_EGU_TNL_INT_STS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(igu_egu_tnl_int_cnt)}, - {"PPU_PF_ABNORMAL_INT_ST_RAS", - HNS3_ERR_INT_STATS_FIELD_OFFSET(ppu_pf_abnormal_int_ras_cnt)}, -}; - /* The statistic of reset */ static const struct hns3_xstats_name_offset hns3_reset_stats_strings[] = { {"REQ_RESET_CNT", @@ -333,9 +274,6 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) -#define HNS3_NUM_ERROR_INT_XSTATS (sizeof(hns3_error_int_stats_strings) / \ - sizeof(hns3_error_int_stats_strings[0])) - #define HNS3_NUM_RESET_XSTATS (sizeof(hns3_reset_stats_strings) / \ sizeof(hns3_reset_stats_strings[0])) @@ -363,7 +301,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -750,23 +688,6 @@ hns3_queue_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } -void -hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err) -{ - struct hns3_pf *pf = &hns->pf; - uint16_t i; - char *addr; - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - if (strcmp(hns3_error_int_stats_strings[i].name, err) == 0) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - *(uint64_t *)addr += 1; - break; - } - } -} - static void hns3_rxq_dfx_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, int *count) @@ -932,7 +853,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, unsigned int n) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; struct hns3_hw *hw = &hns->hw; struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; @@ -986,13 +906,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, count++; } - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - addr = (char *)&pf->abn_int_stats + - hns3_error_int_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } } /* Get the reset stat */ @@ -1134,13 +1047,6 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_imissed_stats_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_ERROR_INT_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_error_int_stats_strings[i].name); - count++; - } } for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, @@ -1358,7 +1264,6 @@ int hns3_dev_xstats_reset(struct rte_eth_dev *dev) { struct hns3_adapter *hns = dev->data->dev_private; - struct hns3_pf *pf = &hns->pf; int ret; /* Clear tqp stats */ @@ -1379,9 +1284,6 @@ hns3_dev_xstats_reset(struct rte_eth_dev *dev) if (ret) return ret; - /* Clear error stats */ - memset(&pf->abn_int_stats, 0, sizeof(struct hns3_err_msix_intr_stats)); - return 0; } diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 70a9c5b..8ea69b4 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -164,7 +164,6 @@ int hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, const uint64_t *ids, uint32_t size); int hns3_stats_reset(struct rte_eth_dev *dev); -void hns3_error_int_stats_add(struct hns3_adapter *hns, const char *err); int hns3_tqp_stats_init(struct hns3_hw *hw); void hns3_tqp_stats_uninit(struct hns3_hw *hw); int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear); -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 5/8] net/hns3: support imissed stats for PF/VF 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (3 preceding siblings ...) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) ` (3 subsequent siblings) 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit This patch added function level imissed stats for PF and VF. In kunpeng920, imissed is supported, only including RPU drop stats in PF. In kunpeng930, imissed is supported,including RPU drop stats and SSU drop stats in PF. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_cmd.h | 13 +++ drivers/net/hns3/hns3_ethdev.c | 2 + drivers/net/hns3/hns3_ethdev.h | 21 ++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 ++ drivers/net/hns3/hns3_regs.h | 2 + drivers/net/hns3/hns3_stats.c | 234 +++++++++++++++++++++++++++++--------- drivers/net/hns3/hns3_stats.h | 1 + 7 files changed, 230 insertions(+), 52 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 094bf7e..e704d0c 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -111,6 +111,8 @@ enum hns3_opcode_type { HNS3_OPC_QUERY_DEV_SPECS = 0x0050, + HNS3_OPC_SSU_DROP_REG = 0x0065, + /* MAC command */ HNS3_OPC_CONFIG_MAC_MODE = 0x0301, HNS3_OPC_QUERY_LINK_STATUS = 0x0307, @@ -957,6 +959,17 @@ struct hns3_query_rpu_cmd { uint32_t rsv2[2]; }; +#define HNS3_OPC_SSU_DROP_REG_NUM 2 + +struct hns3_query_ssu_cmd { + uint8_t rxtx; + uint8_t rsv[3]; + uint32_t full_drop_cnt; + uint32_t part_drop_cnt; + uint32_t oq_drop_cnt; + uint32_t rev1[2]; +}; + #define HNS3_MAX_TQP_NUM_HIP08_PF 64 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 139e893..82538d4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -3122,6 +3122,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = false; @@ -3140,6 +3141,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; hw->rss_info.ipv6_sctp_offload_supported = true; diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 314916c..6e74ec8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -426,6 +426,9 @@ struct hns3_queue_intr { #define HNS3_TSO_SW_CAL_PSEUDO_H_CSUM 0 #define HNS3_TSO_HW_CAL_PSEUDO_H_CSUM 1 +#define HNS3_PKTS_DROP_STATS_MODE1 0 +#define HNS3_PKTS_DROP_STATS_MODE2 1 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -544,6 +547,24 @@ struct hns3_hw { * port won't be copied to the function which has set promisc mode. */ uint8_t promisc_mode; + + /* + * drop_stats_mode mode. + * value range: + * HNS3_PKTS_DROP_STATS_MODE1/HNS3_PKTS_DROP_STATS_MODE2 + * + * - HNS3_PKTS_DROP_STATS_MODE1 + * This mode for kunpeng920. In this mode, port level imissed stats + * is supported. It only includes RPU drop stats. + * + * - HNS3_PKTS_DROP_STATS_MODE2 + * This mode for kunpeng930. In this mode, imissed stats and oerrors + * stats is supported. Function level imissed stats is supported. It + * includes RPU drop stats in VF, and includes both RPU drop stats + * and SSU drop stats in PF. Oerror stats is also supported in PF. + */ + uint8_t drop_stats_mode; + uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */ struct hns3_port_base_vlan_config port_base_vlan_cfg; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index e1e41b8..7ee468f 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1221,6 +1221,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; @@ -1238,6 +1239,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; + hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; @@ -1875,6 +1877,13 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) if (ret) goto err_get_config; + /* Hardware statistics of imissed registers cleared. */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + goto err_set_tc_queue; + } + ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num); if (ret) { PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret); diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h index 0540554..e141fe1 100644 --- a/drivers/net/hns3/hns3_regs.h +++ b/drivers/net/hns3/hns3_regs.h @@ -36,6 +36,8 @@ #define HNS3_GLOBAL_RESET_REG 0x20A00 #define HNS3_FUN_RST_ING 0x20C00 #define HNS3_GRO_EN_REG 0x28000 + +#define HNS3_RPU_DROP_CNT_REG 0x28004 #define HNS3_RXD_ADV_LAYOUT_EN_REG 0x28008 /* Vector0 register bits for reset */ diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index 7cda36c..e802c0b 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -269,6 +269,8 @@ static const struct hns3_xstats_name_offset hns3_tx_queue_strings[] = { static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { {"RPU_DROP_CNT", HNS3_IMISSED_STATS_FIELD_OFFSET(rpu_rx_drop_cnt)}, + {"SSU_DROP_CNT", + HNS3_IMISSED_STATS_FIELD_OFFSET(ssu_rx_drop_cnt)}, }; #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ @@ -301,8 +303,7 @@ static const struct hns3_xstats_name_offset hns3_imissed_stats_strings[] = { #define HNS3_NUM_IMISSED_XSTATS (sizeof(hns3_imissed_stats_strings) / \ sizeof(hns3_imissed_stats_strings[0])) -#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + \ - HNS3_NUM_RESET_XSTATS + HNS3_NUM_IMISSED_XSTATS) +#define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_RESET_XSTATS) static void hns3_tqp_stats_clear(struct hns3_hw *hw); @@ -419,7 +420,7 @@ hns3_query_update_mac_stats(struct rte_eth_dev *dev) } static int -hns3_update_rpu_drop_stats(struct hns3_hw *hw) +hns3_update_port_rpu_drop_stats(struct hns3_hw *hw) { struct hns3_rx_missed_stats *stats = &hw->imissed_stats; struct hns3_query_rpu_cmd *req; @@ -449,11 +450,90 @@ hns3_update_rpu_drop_stats(struct hns3_hw *hw) return 0; } +static void +hns3_update_function_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + + stats->rpu_rx_drop_cnt += hns3_read_dev(hw, HNS3_RPU_DROP_CNT_REG); +} + +static int +hns3_update_rpu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret = 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && !hns->is_vf) + ret = hns3_update_port_rpu_drop_stats(hw); + else if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2) + hns3_update_function_rpu_drop_stats(hw); + + return ret; +} + +static int +hns3_get_ssu_drop_stats(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + int bd_num, bool is_rx) +{ + struct hns3_query_ssu_cmd *req; + int ret; + int i; + + for (i = 0; i < bd_num - 1; i++) { + hns3_cmd_setup_basic_desc(&desc[i], + HNS3_OPC_SSU_DROP_REG, true); + desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + } + hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_SSU_DROP_REG, true); + req = (struct hns3_query_ssu_cmd *)desc[0].data; + req->rxtx = is_rx ? 0 : 1; + ret = hns3_cmd_send(hw, desc, bd_num); + + return ret; +} + +static int +hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_rx_missed_stats *stats = &hw->imissed_stats; + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + true); + if (ret) { + hns3_err(hw, "failed to get Rx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + stats->ssu_rx_drop_cnt += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); int ret; + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return 0; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) { + ret = hns3_update_port_rx_ssu_drop_stats(hw); + if (ret) + return ret; + } + ret = hns3_update_rpu_drop_stats(hw); if (ret) return ret; @@ -488,19 +568,17 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) uint16_t i; int ret; - if (!hns->is_vf) { - /* Update imissed stats */ - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt; + /* Update imissed stats */ + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + rte_stats->imissed = imissed_stats->rpu_rx_drop_cnt + + imissed_stats->ssu_rx_drop_cnt; - /* Reads all the stats of a rxq in a loop to keep them synchronized */ + /* Get the error stats and bytes of received packets */ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) @@ -556,17 +634,14 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) uint16_t i; int ret; - if (!hns->is_vf) { - /* - * Note: Reading hardware statistics of imissed registers will - * clear them. - */ - ret = hns3_update_imissed_stats(hw, true); - if (ret) { - hns3_err(hw, "clear imissed stats failed, ret = %d", - ret); - return ret; - } + /* + * Note: Reading hardware statistics of imissed registers will + * clear them. + */ + ret = hns3_update_imissed_stats(hw, true); + if (ret) { + hns3_err(hw, "clear imissed stats failed, ret = %d", ret); + return ret; } for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { @@ -630,6 +705,22 @@ hns3_mac_stats_reset(__rte_unused struct rte_eth_dev *dev) return 0; } +static int +hns3_get_imissed_stats_num(struct hns3_adapter *hns) +{ +#define NO_IMISSED_STATS_NUM 0 +#define RPU_STATS_ITEM_NUM 1 + struct hns3_hw *hw = &hns->hw; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 && hns->is_vf) + return NO_IMISSED_STATS_NUM; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE2 && !hns->is_vf) + return HNS3_NUM_IMISSED_XSTATS; + + return RPU_STATS_ITEM_NUM; +} + /* This function calculates the number of xstats based on the current config */ static int hns3_xstats_calc_num(struct rte_eth_dev *dev) @@ -647,13 +738,17 @@ hns3_xstats_calc_num(struct rte_eth_dev *dev) uint16_t nb_tx_q = dev->data->nb_tx_queues; int rx_comm_stats_num = nb_rx_q * HNS3_PF_VF_RX_COMM_STATS_NUM; int tx_comm_stats_num = nb_tx_q * HNS3_PF_VF_TX_COMM_STATS_NUM; + int stats_num; + + stats_num = rx_comm_stats_num + tx_comm_stats_num; + stats_num += hns3_get_imissed_stats_num(hns); if (hns->is_vf) - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_NUM_RESET_XSTATS; + stats_num += HNS3_NUM_RESET_XSTATS; else - return rx_comm_stats_num + tx_comm_stats_num + - HNS3_FIX_NUM_STATS; + stats_num += HNS3_FIX_NUM_STATS; + + return stats_num; } static void @@ -835,6 +930,31 @@ hns3_tqp_basic_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, hns3_txq_basic_stats_get(dev, xstats, count); } +static void +hns3_imissed_stats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, + int *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; + int imissed_stats_num; + int cnt = *count; + char *addr; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + addr = (char *)imissed_stats + + hns3_imissed_stats_strings[i].offset; + xstats[cnt].value = *(uint64_t *)addr; + xstats[cnt].id = cnt; + cnt++; + } + + *count = cnt; +} + /* * Retrieve extended(tqp | Mac) statistics of an Ethernet device. * @param dev @@ -854,7 +974,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, { struct hns3_adapter *hns = dev->data->dev_private; struct hns3_hw *hw = &hns->hw; - struct hns3_rx_missed_stats *imissed_stats = &hw->imissed_stats; struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_bd_errors_stats *rx_err_stats; @@ -890,24 +1009,17 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, xstats[count].id = count; count++; } + } - ret = hns3_update_imissed_stats(hw, false); - if (ret) { - hns3_err(hw, "update imissed stats failed, ret = %d", - ret); - return ret; - } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - addr = (char *)imissed_stats + - hns3_imissed_stats_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } - + ret = hns3_update_imissed_stats(hw, false); + if (ret) { + hns3_err(hw, "update imissed stats failed, ret = %d", + ret); + return ret; } + hns3_imissed_stats_get(dev, xstats, &count); + /* Get the reset stat */ for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { addr = (char *)reset_stats + hns3_reset_stats_strings[i].offset; @@ -992,6 +1104,28 @@ hns3_tqp_dfx_stats_name_get(struct rte_eth_dev *dev, } } +static void +hns3_imissed_stats_name_get(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + uint32_t *count) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t cnt = *count; + int imissed_stats_num; + uint16_t i; + + imissed_stats_num = hns3_get_imissed_stats_num(hns); + + for (i = 0; i < imissed_stats_num; i++) { + snprintf(xstats_names[cnt].name, + sizeof(xstats_names[cnt].name), + "%s", hns3_imissed_stats_strings[i].name); + cnt++; + } + + *count = cnt; +} + /* * Retrieve names of extended statistics of an Ethernet device. * @@ -1040,14 +1174,10 @@ hns3_dev_xstats_get_names(struct rte_eth_dev *dev, "%s", hns3_mac_strings[i].name); count++; } - - for (i = 0; i < HNS3_NUM_IMISSED_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "%s", hns3_imissed_stats_strings[i].name); - count++; - } } + + hns3_imissed_stats_name_get(dev, xstats_names, &count); + for (i = 0; i < HNS3_NUM_RESET_XSTATS; i++) { snprintf(xstats_names[count].name, sizeof(xstats_names[count].name), diff --git a/drivers/net/hns3/hns3_stats.h b/drivers/net/hns3/hns3_stats.h index 8ea69b4..273be42 100644 --- a/drivers/net/hns3/hns3_stats.h +++ b/drivers/net/hns3/hns3_stats.h @@ -112,6 +112,7 @@ struct hns3_mac_stats { struct hns3_rx_missed_stats { uint64_t rpu_rx_drop_cnt; + uint64_t ssu_rx_drop_cnt; }; /* store statistics names and its offset in stats structure */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 6/8] net/hns3: support oerrors stats in PF 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (4 preceding siblings ...) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) ` (2 subsequent siblings) 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit This patch added oerrors stats for PF in kunpeng930. Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_stats.c | 64 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 6e74ec8..f69e2d8 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -443,6 +443,7 @@ struct hns3_hw { /* Include Mac stats | Rx stats | Tx stats */ struct hns3_mac_stats mac_stats; struct hns3_rx_missed_stats imissed_stats; + uint64_t oerror_stats; uint32_t fw_version; uint16_t num_msi; diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index e802c0b..1af689f 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -519,6 +519,31 @@ hns3_update_port_rx_ssu_drop_stats(struct hns3_hw *hw) return 0; } +static int +hns3_update_port_tx_ssu_drop_stats(struct hns3_hw *hw) +{ + struct hns3_cmd_desc desc[HNS3_OPC_SSU_DROP_REG_NUM]; + struct hns3_query_ssu_cmd *req; + uint64_t cnt; + int ret; + + ret = hns3_get_ssu_drop_stats(hw, desc, HNS3_OPC_SSU_DROP_REG_NUM, + false); + if (ret) { + hns3_err(hw, "failed to get Tx SSU drop stats, ret = %d", ret); + return ret; + } + + req = (struct hns3_query_ssu_cmd *)desc[0].data; + cnt = rte_le_to_cpu_32(req->oq_drop_cnt) + + rte_le_to_cpu_32(req->full_drop_cnt) + + rte_le_to_cpu_32(req->part_drop_cnt); + + hw->oerror_stats += cnt; + + return 0; +} + int hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) { @@ -544,6 +569,25 @@ hns3_update_imissed_stats(struct hns3_hw *hw, bool is_clear) return 0; } +static int +hns3_update_oerror_stats(struct hns3_hw *hw, bool is_clear) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + int ret; + + if (hw->drop_stats_mode == HNS3_PKTS_DROP_STATS_MODE1 || hns->is_vf) + return 0; + + ret = hns3_update_port_tx_ssu_drop_stats(hw); + if (ret) + return ret; + + if (is_clear) + hw->oerror_stats = 0; + + return 0; +} + /* * Query tqp tx queue statistics ,opcode id: 0x0B03. * Query tqp rx queue statistics ,opcode id: 0x0B13. @@ -608,7 +652,14 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) rte_stats->obytes += txq->basic_stats.bytes; } - rte_stats->oerrors = 0; + ret = hns3_update_oerror_stats(hw, false); + if (ret) { + hns3_err(hw, "update oerror stats failed, ret = %d", + ret); + return ret; + } + rte_stats->oerrors = hw->oerror_stats; + /* * If HW statistics are reset by stats_reset, but a lot of residual * packets exist in the hardware queue and these packets are error @@ -644,6 +695,17 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) return ret; } + /* + * Note: Reading hardware statistics of oerror registers will + * clear them. + */ + ret = hns3_update_oerror_stats(hw, true); + if (ret) { + hns3_err(hw, "clear oerror stats failed, ret = %d", + ret); + return ret; + } + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { rxq = eth_dev->data->rx_queues[i]; if (rxq == NULL) -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 7/8] net/hns3: support query Tx descriptor status 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (5 preceding siblings ...) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 8/8] net/hns3: support query Rx " Min Hu (Connor) 2021-03-23 12:49 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Ferruh Yigit 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Tx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 28 ++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 34 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 3aeea8e..2c0cb89 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index c796cd5..e60b09b 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -32,6 +32,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Tx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index c3324d8..e8b0c6e 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -62,6 +62,7 @@ New Features * Added support for copper port in Kunpeng930. * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. + * Added support for query Tx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 82538d4..8c65be4 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6774,6 +6774,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; return ret; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 7ee468f..4412da3 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2917,6 +2917,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; + eth_dev->tx_descriptor_status = NULL; rte_free(eth_dev->process_private); eth_dev->process_private = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 7529279..a84da15 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4044,6 +4044,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; + eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; } else { eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst; eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst; @@ -4256,6 +4257,33 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) return -ENOTSUP; } +int +hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + volatile struct hns3_desc *txdp; + struct hns3_tx_queue *txq; + struct rte_eth_dev *dev; + uint16_t desc_id; + + txq = (struct hns3_tx_queue *)tx_queue; + if (offset >= txq->nb_tx_desc) + return -EINVAL; + + dev = &rte_eth_devices[txq->port_id]; + if (dev->tx_pkt_burst != hns3_xmit_pkts_simple && + dev->tx_pkt_burst != hns3_xmit_pkts && + dev->tx_pkt_burst != hns3_xmit_pkts_vec_sve && + dev->tx_pkt_burst != hns3_xmit_pkts_vec) + return RTE_ETH_TX_DESC_UNAVAIL; + + desc_id = (txq->next_to_use + offset) % txq->nb_tx_desc; + txdp = &txq->tx_ring[desc_id]; + if (txdp->tx.tp_fe_sc_vld_ra_ri & rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B))) + return RTE_ETH_TX_DESC_FULL; + else + return RTE_ETH_TX_DESC_DONE; +} + uint32_t hns3_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index cd04200..82d5aa0 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,5 +720,6 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* [dpdk-dev] [PATCH v6 8/8] net/hns3: support query Rx descriptor status 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (6 preceding siblings ...) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) @ 2021-03-23 11:21 ` Min Hu (Connor) 2021-03-23 12:49 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Ferruh Yigit 8 siblings, 0 replies; 44+ messages in thread From: Min Hu (Connor) @ 2021-03-23 11:21 UTC (permalink / raw) To: dev, ferruh.yigit From: Hongbo Zheng <zhenghongbo3@huawei.com> Add support for query Rx descriptor status in hns3 driver. Check the descriptor specified and provide the status information of the corresponding descriptor. Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> --- doc/guides/nics/features/hns3.ini | 1 + doc/guides/nics/features/hns3_vf.ini | 1 + doc/guides/rel_notes/release_21_05.rst | 1 + drivers/net/hns3/hns3_ethdev.c | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 1 + drivers/net/hns3/hns3_rxtx.c | 36 ++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_rxtx.h | 1 + 7 files changed, 42 insertions(+) diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini index 2c0cb89..3988be4 100644 --- a/doc/guides/nics/features/hns3.ini +++ b/doc/guides/nics/features/hns3.ini @@ -35,6 +35,7 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Rx descriptor status = Y Tx descriptor status = Y Basic stats = Y Extended stats = Y diff --git a/doc/guides/nics/features/hns3_vf.ini b/doc/guides/nics/features/hns3_vf.ini index e60b09b..1640669 100644 --- a/doc/guides/nics/features/hns3_vf.ini +++ b/doc/guides/nics/features/hns3_vf.ini @@ -33,6 +33,7 @@ Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y Tx descriptor status = Y +Rx descriptor status = Y Basic stats = Y Extended stats = Y Stats per queue = Y diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index e8b0c6e..6e1fc81 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -63,6 +63,7 @@ New Features * Added support for runtime config to select IO burst function. * Added support for outer UDP checksum in Kunpeng930. * Added support for query Tx descriptor status. + * Added support for query Rx descriptor status. * **Updated NXP DPAA2 driver.** diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 8c65be4..b7bfac8 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -6772,6 +6772,7 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 4412da3..34a6927 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -2915,6 +2915,7 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev) err_mp_init_secondary: eth_dev->dev_ops = NULL; eth_dev->rx_pkt_burst = NULL; + eth_dev->rx_descriptor_status = NULL; eth_dev->tx_pkt_burst = NULL; eth_dev->tx_pkt_prepare = NULL; eth_dev->tx_descriptor_status = NULL; diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index a84da15..feeb702 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -4042,6 +4042,7 @@ void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev) if (hns->hw.adapter_state == HNS3_NIC_STARTED && __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) { eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev); + eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status; eth_dev->tx_pkt_burst = hns3_get_tx_function(eth_dev, &prep); eth_dev->tx_pkt_prepare = prep; eth_dev->tx_descriptor_status = hns3_dev_tx_descriptor_status; @@ -4258,6 +4259,41 @@ hns3_tx_done_cleanup(void *txq, uint32_t free_cnt) } int +hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + volatile struct hns3_desc *rxdp; + struct hns3_rx_queue *rxq; + struct rte_eth_dev *dev; + uint32_t bd_base_info; + uint16_t desc_id; + + rxq = (struct hns3_rx_queue *)rx_queue; + if (offset >= rxq->nb_rx_desc) + return -EINVAL; + + desc_id = (rxq->next_to_use + offset) % rxq->nb_rx_desc; + rxdp = &rxq->rx_ring[desc_id]; + bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info); + dev = &rte_eth_devices[rxq->port_id]; + if (dev->rx_pkt_burst == hns3_recv_pkts || + dev->rx_pkt_burst == hns3_recv_scattered_pkts) { + if (offset >= rxq->nb_rx_desc - rxq->rx_free_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + } else if (dev->rx_pkt_burst == hns3_recv_pkts_vec || + dev->rx_pkt_burst == hns3_recv_pkts_vec_sve){ + if (offset >= rxq->nb_rx_desc - rxq->rx_rearm_nb) + return RTE_ETH_RX_DESC_UNAVAIL; + } else { + return RTE_ETH_RX_DESC_UNAVAIL; + } + + if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) + return RTE_ETH_RX_DESC_AVAIL; + else + return RTE_ETH_RX_DESC_DONE; +} + +int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { volatile struct hns3_desc *txdp; diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 82d5aa0..f9b3048 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -720,6 +720,7 @@ void hns3_stop_all_txqs(struct rte_eth_dev *dev); void hns3_restore_tqp_enable_state(struct hns3_hw *hw); int hns3_tx_done_cleanup(void *txq, uint32_t free_cnt); void hns3_enable_rxd_adv_layout(struct hns3_hw *hw); +int hns3_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); int hns3_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); #endif /* _HNS3_RXTX_H_ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) ` (7 preceding siblings ...) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 8/8] net/hns3: support query Rx " Min Hu (Connor) @ 2021-03-23 12:49 ` Ferruh Yigit 8 siblings, 0 replies; 44+ messages in thread From: Ferruh Yigit @ 2021-03-23 12:49 UTC (permalink / raw) To: Min Hu (Connor), dev On 3/23/2021 11:20 AM, Min Hu (Connor) wrote: > This series add four features according to the 21.05 roadmap, and > also two cleanups added. > > v6: > * Adjust the styles of hns3.rst about runtime config options. > > v5: > * Document hns3.rst about description of vec, common and simple. > > v4: > * Rename variable name oq_glb_drop_cnt to oq_drop_cnt. > > v3: > * Change code styles. > > v2: > * Fixed commit information about patch set. > > Chengchang Tang (1): > net/hns3: support for outer UDP cksum > > Chengwen Feng (1): > net/hns3: support runtime config to select IO burst func > > Hongbo Zheng (4): > net/hns3: adjust the format of RAS related structures > net/hns3: delete redundant xstats RAS statistics > net/hns3: support query Tx descriptor status > net/hns3: support query Rx descriptor status > > Min Hu (Connor) (2): > net/hns3: support imissed stats for PF/VF > net/hns3: support oerrors stats in PF > Series applied to dpdk-next-net/main, thanks. ^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2021-03-23 12:49 UTC | newest] Thread overview: 44+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-10 6:24 [dpdk-dev] [PATCH 0/9] features and bugfixes for hns3 Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 1/9] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 2/9] net/hns3: support Tx push quick doorbell to improve perf Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 3/9] net/hns3: support for outer UDP cksum Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 4/9] net/hns3: adjust the format of RAS related structures Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 5/9] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 6/9] net/hns3: support imissed stats for PF/VF Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 7/9] net/hns3: support oerrors stats in PF Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 8/9] net/hns3: support query Tx descriptor status Min Hu (Connor) 2021-03-10 6:24 ` [dpdk-dev] [PATCH 9/9] net/hns3: support query Rx " Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) 2021-03-17 9:50 ` [dpdk-dev] [PATCH v4 8/8] net/hns3: support query Rx " Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-22 13:58 ` Ferruh Yigit 2021-03-22 14:03 ` Ferruh Yigit 2021-03-23 3:31 ` fengchengwen 2021-03-23 10:31 ` Ferruh Yigit 2021-03-23 11:22 ` Min Hu (Connor) 2021-03-23 3:37 ` fengchengwen 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) 2021-03-19 1:07 ` [dpdk-dev] [PATCH v5 8/8] net/hns3: support query Rx " Min Hu (Connor) 2021-03-23 11:20 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 1/8] net/hns3: support runtime config to select IO burst func Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 2/8] net/hns3: support for outer UDP cksum Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 3/8] net/hns3: adjust the format of RAS related structures Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 4/8] net/hns3: delete redundant xstats RAS statistics Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 5/8] net/hns3: support imissed stats for PF/VF Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 6/8] net/hns3: support oerrors stats in PF Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 7/8] net/hns3: support query Tx descriptor status Min Hu (Connor) 2021-03-23 11:21 ` [dpdk-dev] [PATCH v6 8/8] net/hns3: support query Rx " Min Hu (Connor) 2021-03-23 12:49 ` [dpdk-dev] [PATCH v6 0/8] features and bugfixes for hns3 Ferruh Yigit
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